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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-06-18 19:49:08 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-19 19:46:05 -0400
commit34a661a1fe02840b6fc8de0a616464dd4899782f (patch)
treefd992a4d4cba9eaed72bdab0b123216b5ee09127 /drivers/spi/spi_mpc83xx.c
parentaef79d827657fce5a3038ba07f11ce6dcd0421d0 (diff)
spi_mpc83xx: rename spi_83xx.c to spi_8xxx.c
The driver handles MPC83xx, MPC85xx and MPC86xx SPI controllers, so rename the file for clarity. Suggested-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Cc: Kumar Gala <galak@gate.crashing.org> Cc: David Brownell <david-b@pacbell.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/spi/spi_mpc83xx.c')
-rw-r--r--drivers/spi/spi_mpc83xx.c945
1 files changed, 0 insertions, 945 deletions
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
deleted file mode 100644
index c5cb98f65454..000000000000
--- a/drivers/spi/spi_mpc83xx.c
+++ /dev/null
@@ -1,945 +0,0 @@
1/*
2 * MPC83xx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/bug.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/completion.h>
22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/irq.h>
25#include <linux/device.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/spi_bitbang.h>
28#include <linux/platform_device.h>
29#include <linux/fsl_devices.h>
30#include <linux/of.h>
31#include <linux/of_platform.h>
32#include <linux/gpio.h>
33#include <linux/of_gpio.h>
34#include <linux/of_spi.h>
35
36#include <sysdev/fsl_soc.h>
37#include <asm/irq.h>
38
39/* SPI Controller registers */
40struct mpc83xx_spi_reg {
41 u8 res1[0x20];
42 __be32 mode;
43 __be32 event;
44 __be32 mask;
45 __be32 command;
46 __be32 transmit;
47 __be32 receive;
48};
49
50/* SPI Controller mode register definitions */
51#define SPMODE_LOOP (1 << 30)
52#define SPMODE_CI_INACTIVEHIGH (1 << 29)
53#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
54#define SPMODE_DIV16 (1 << 27)
55#define SPMODE_REV (1 << 26)
56#define SPMODE_MS (1 << 25)
57#define SPMODE_ENABLE (1 << 24)
58#define SPMODE_LEN(x) ((x) << 20)
59#define SPMODE_PM(x) ((x) << 16)
60#define SPMODE_OP (1 << 14)
61#define SPMODE_CG(x) ((x) << 7)
62
63/*
64 * Default for SPI Mode:
65 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
66 */
67#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
68 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
69
70/* SPIE register values */
71#define SPIE_NE 0x00000200 /* Not empty */
72#define SPIE_NF 0x00000100 /* Not full */
73
74/* SPIM register values */
75#define SPIM_NE 0x00000200 /* Not empty */
76#define SPIM_NF 0x00000100 /* Not full */
77
78/* SPI Controller driver's private data. */
79struct mpc83xx_spi {
80 struct mpc83xx_spi_reg __iomem *base;
81
82 /* rx & tx bufs from the spi_transfer */
83 const void *tx;
84 void *rx;
85
86 /* functions to deal with different sized buffers */
87 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
88 u32(*get_tx) (struct mpc83xx_spi *);
89
90 unsigned int count;
91 unsigned int irq;
92
93 unsigned nsecs; /* (clock cycle time)/2 */
94
95 u32 spibrg; /* SPIBRG input clock */
96 u32 rx_shift; /* RX data reg shift when in qe mode */
97 u32 tx_shift; /* TX data reg shift when in qe mode */
98
99 bool qe_mode;
100
101 struct workqueue_struct *workqueue;
102 struct work_struct work;
103
104 struct list_head queue;
105 spinlock_t lock;
106
107 struct completion done;
108};
109
110struct spi_mpc83xx_cs {
111 /* functions to deal with different sized buffers */
112 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
113 u32 (*get_tx) (struct mpc83xx_spi *);
114 u32 rx_shift; /* RX data reg shift when in qe mode */
115 u32 tx_shift; /* TX data reg shift when in qe mode */
116 u32 hw_mode; /* Holds HW mode register settings */
117};
118
119static inline void mpc83xx_spi_write_reg(__be32 __iomem *reg, u32 val)
120{
121 out_be32(reg, val);
122}
123
124static inline u32 mpc83xx_spi_read_reg(__be32 __iomem *reg)
125{
126 return in_be32(reg);
127}
128
129#define MPC83XX_SPI_RX_BUF(type) \
130static \
131void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
132{ \
133 type *rx = mpc83xx_spi->rx; \
134 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
135 mpc83xx_spi->rx = rx; \
136}
137
138#define MPC83XX_SPI_TX_BUF(type) \
139static \
140u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
141{ \
142 u32 data; \
143 const type *tx = mpc83xx_spi->tx; \
144 if (!tx) \
145 return 0; \
146 data = *tx++ << mpc83xx_spi->tx_shift; \
147 mpc83xx_spi->tx = tx; \
148 return data; \
149}
150
151MPC83XX_SPI_RX_BUF(u8)
152MPC83XX_SPI_RX_BUF(u16)
153MPC83XX_SPI_RX_BUF(u32)
154MPC83XX_SPI_TX_BUF(u8)
155MPC83XX_SPI_TX_BUF(u16)
156MPC83XX_SPI_TX_BUF(u32)
157
158static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
159{
160 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
161 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
162 bool pol = spi->mode & SPI_CS_HIGH;
163 struct spi_mpc83xx_cs *cs = spi->controller_state;
164
165 if (value == BITBANG_CS_INACTIVE) {
166 if (pdata->cs_control)
167 pdata->cs_control(spi, !pol);
168 }
169
170 if (value == BITBANG_CS_ACTIVE) {
171 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
172
173 mpc83xx_spi->rx_shift = cs->rx_shift;
174 mpc83xx_spi->tx_shift = cs->tx_shift;
175 mpc83xx_spi->get_rx = cs->get_rx;
176 mpc83xx_spi->get_tx = cs->get_tx;
177
178 if (cs->hw_mode != regval) {
179 unsigned long flags;
180 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
181
182 regval = cs->hw_mode;
183 /* Turn off IRQs locally to minimize time that
184 * SPI is disabled
185 */
186 local_irq_save(flags);
187 /* Turn off SPI unit prior changing mode */
188 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
189 mpc83xx_spi_write_reg(mode, regval);
190 local_irq_restore(flags);
191 }
192 if (pdata->cs_control)
193 pdata->cs_control(spi, pol);
194 }
195}
196
197static
198int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
199{
200 struct mpc83xx_spi *mpc83xx_spi;
201 u32 regval;
202 u8 bits_per_word, pm;
203 u32 hz;
204 struct spi_mpc83xx_cs *cs = spi->controller_state;
205
206 mpc83xx_spi = spi_master_get_devdata(spi->master);
207
208 if (t) {
209 bits_per_word = t->bits_per_word;
210 hz = t->speed_hz;
211 } else {
212 bits_per_word = 0;
213 hz = 0;
214 }
215
216 /* spi_transfer level calls that work per-word */
217 if (!bits_per_word)
218 bits_per_word = spi->bits_per_word;
219
220 /* Make sure its a bit width we support [4..16, 32] */
221 if ((bits_per_word < 4)
222 || ((bits_per_word > 16) && (bits_per_word != 32)))
223 return -EINVAL;
224
225 if (!hz)
226 hz = spi->max_speed_hz;
227
228 cs->rx_shift = 0;
229 cs->tx_shift = 0;
230 if (bits_per_word <= 8) {
231 cs->get_rx = mpc83xx_spi_rx_buf_u8;
232 cs->get_tx = mpc83xx_spi_tx_buf_u8;
233 if (mpc83xx_spi->qe_mode) {
234 cs->rx_shift = 16;
235 cs->tx_shift = 24;
236 }
237 } else if (bits_per_word <= 16) {
238 cs->get_rx = mpc83xx_spi_rx_buf_u16;
239 cs->get_tx = mpc83xx_spi_tx_buf_u16;
240 if (mpc83xx_spi->qe_mode) {
241 cs->rx_shift = 16;
242 cs->tx_shift = 16;
243 }
244 } else if (bits_per_word <= 32) {
245 cs->get_rx = mpc83xx_spi_rx_buf_u32;
246 cs->get_tx = mpc83xx_spi_tx_buf_u32;
247 } else
248 return -EINVAL;
249
250 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
251 cs->tx_shift = 0;
252 if (bits_per_word <= 8)
253 cs->rx_shift = 8;
254 else
255 cs->rx_shift = 0;
256 }
257
258 mpc83xx_spi->rx_shift = cs->rx_shift;
259 mpc83xx_spi->tx_shift = cs->tx_shift;
260 mpc83xx_spi->get_rx = cs->get_rx;
261 mpc83xx_spi->get_tx = cs->get_tx;
262
263 if (bits_per_word == 32)
264 bits_per_word = 0;
265 else
266 bits_per_word = bits_per_word - 1;
267
268 /* mask out bits we are going to set */
269 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
270 | SPMODE_PM(0xF));
271
272 cs->hw_mode |= SPMODE_LEN(bits_per_word);
273
274 if ((mpc83xx_spi->spibrg / hz) > 64) {
275 cs->hw_mode |= SPMODE_DIV16;
276 pm = mpc83xx_spi->spibrg / (hz * 64);
277
278 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
279 "Will use %d Hz instead.\n", dev_name(&spi->dev),
280 hz, mpc83xx_spi->spibrg / 1024);
281 if (pm > 16)
282 pm = 16;
283 } else
284 pm = mpc83xx_spi->spibrg / (hz * 4);
285 if (pm)
286 pm--;
287
288 cs->hw_mode |= SPMODE_PM(pm);
289 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
290 if (cs->hw_mode != regval) {
291 unsigned long flags;
292 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
293
294 regval = cs->hw_mode;
295 /* Turn off IRQs locally to minimize time
296 * that SPI is disabled
297 */
298 local_irq_save(flags);
299 /* Turn off SPI unit prior changing mode */
300 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
301 mpc83xx_spi_write_reg(mode, regval);
302 local_irq_restore(flags);
303 }
304 return 0;
305}
306
307static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
308{
309 struct mpc83xx_spi *mpc83xx_spi;
310 u32 word, len, bits_per_word;
311
312 mpc83xx_spi = spi_master_get_devdata(spi->master);
313
314 mpc83xx_spi->tx = t->tx_buf;
315 mpc83xx_spi->rx = t->rx_buf;
316 bits_per_word = spi->bits_per_word;
317 if (t->bits_per_word)
318 bits_per_word = t->bits_per_word;
319 len = t->len;
320 if (bits_per_word > 8) {
321 /* invalid length? */
322 if (len & 1)
323 return -EINVAL;
324 len /= 2;
325 }
326 if (bits_per_word > 16) {
327 /* invalid length? */
328 if (len & 1)
329 return -EINVAL;
330 len /= 2;
331 }
332 mpc83xx_spi->count = len;
333
334 INIT_COMPLETION(mpc83xx_spi->done);
335
336 /* enable rx ints */
337 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
338
339 /* transmit word */
340 word = mpc83xx_spi->get_tx(mpc83xx_spi);
341 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
342
343 wait_for_completion(&mpc83xx_spi->done);
344
345 /* disable rx ints */
346 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
347
348 return mpc83xx_spi->count;
349}
350
351static void mpc83xx_spi_do_one_msg(struct spi_message *m)
352{
353 struct spi_device *spi = m->spi;
354 struct spi_transfer *t;
355 unsigned int cs_change;
356 const int nsecs = 50;
357 int status;
358
359 cs_change = 1;
360 status = 0;
361 list_for_each_entry(t, &m->transfers, transfer_list) {
362 if (t->bits_per_word || t->speed_hz) {
363 /* Don't allow changes if CS is active */
364 status = -EINVAL;
365
366 if (cs_change)
367 status = mpc83xx_spi_setup_transfer(spi, t);
368 if (status < 0)
369 break;
370 }
371
372 if (cs_change) {
373 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
374 ndelay(nsecs);
375 }
376 cs_change = t->cs_change;
377 if (t->len)
378 status = mpc83xx_spi_bufs(spi, t);
379 if (status) {
380 status = -EMSGSIZE;
381 break;
382 }
383 m->actual_length += t->len;
384
385 if (t->delay_usecs)
386 udelay(t->delay_usecs);
387
388 if (cs_change) {
389 ndelay(nsecs);
390 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
391 ndelay(nsecs);
392 }
393 }
394
395 m->status = status;
396 m->complete(m->context);
397
398 if (status || !cs_change) {
399 ndelay(nsecs);
400 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
401 }
402
403 mpc83xx_spi_setup_transfer(spi, NULL);
404}
405
406static void mpc83xx_spi_work(struct work_struct *work)
407{
408 struct mpc83xx_spi *mpc83xx_spi = container_of(work, struct mpc83xx_spi,
409 work);
410
411 spin_lock_irq(&mpc83xx_spi->lock);
412 while (!list_empty(&mpc83xx_spi->queue)) {
413 struct spi_message *m = container_of(mpc83xx_spi->queue.next,
414 struct spi_message, queue);
415
416 list_del_init(&m->queue);
417 spin_unlock_irq(&mpc83xx_spi->lock);
418
419 mpc83xx_spi_do_one_msg(m);
420
421 spin_lock_irq(&mpc83xx_spi->lock);
422 }
423 spin_unlock_irq(&mpc83xx_spi->lock);
424}
425
426static int mpc83xx_spi_setup(struct spi_device *spi)
427{
428 struct mpc83xx_spi *mpc83xx_spi;
429 int retval;
430 u32 hw_mode;
431 struct spi_mpc83xx_cs *cs = spi->controller_state;
432
433 if (!spi->max_speed_hz)
434 return -EINVAL;
435
436 if (!cs) {
437 cs = kzalloc(sizeof *cs, GFP_KERNEL);
438 if (!cs)
439 return -ENOMEM;
440 spi->controller_state = cs;
441 }
442 mpc83xx_spi = spi_master_get_devdata(spi->master);
443
444 hw_mode = cs->hw_mode; /* Save orginal settings */
445 cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
446 /* mask out bits we are going to set */
447 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
448 | SPMODE_REV | SPMODE_LOOP);
449
450 if (spi->mode & SPI_CPHA)
451 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
452 if (spi->mode & SPI_CPOL)
453 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
454 if (!(spi->mode & SPI_LSB_FIRST))
455 cs->hw_mode |= SPMODE_REV;
456 if (spi->mode & SPI_LOOP)
457 cs->hw_mode |= SPMODE_LOOP;
458
459 retval = mpc83xx_spi_setup_transfer(spi, NULL);
460 if (retval < 0) {
461 cs->hw_mode = hw_mode; /* Restore settings */
462 return retval;
463 }
464 return 0;
465}
466
467static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
468{
469 struct mpc83xx_spi *mpc83xx_spi = context_data;
470 u32 event;
471 irqreturn_t ret = IRQ_NONE;
472
473 /* Get interrupt events(tx/rx) */
474 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
475
476 /* We need handle RX first */
477 if (event & SPIE_NE) {
478 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
479
480 if (mpc83xx_spi->rx)
481 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
482
483 ret = IRQ_HANDLED;
484 }
485
486 if ((event & SPIE_NF) == 0)
487 /* spin until TX is done */
488 while (((event =
489 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
490 SPIE_NF) == 0)
491 cpu_relax();
492
493 mpc83xx_spi->count -= 1;
494 if (mpc83xx_spi->count) {
495 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
496 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
497 } else {
498 complete(&mpc83xx_spi->done);
499 }
500
501 /* Clear the events */
502 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
503
504 return ret;
505}
506static int mpc83xx_spi_transfer(struct spi_device *spi,
507 struct spi_message *m)
508{
509 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
510 unsigned long flags;
511
512 m->actual_length = 0;
513 m->status = -EINPROGRESS;
514
515 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
516 list_add_tail(&m->queue, &mpc83xx_spi->queue);
517 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
518 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
519
520 return 0;
521}
522
523
524static void mpc83xx_spi_cleanup(struct spi_device *spi)
525{
526 kfree(spi->controller_state);
527}
528
529static struct spi_master * __devinit
530mpc83xx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
531{
532 struct fsl_spi_platform_data *pdata = dev->platform_data;
533 struct spi_master *master;
534 struct mpc83xx_spi *mpc83xx_spi;
535 u32 regval;
536 int ret = 0;
537
538 master = spi_alloc_master(dev, sizeof(struct mpc83xx_spi));
539 if (master == NULL) {
540 ret = -ENOMEM;
541 goto err;
542 }
543
544 dev_set_drvdata(dev, master);
545
546 /* the spi->mode bits understood by this driver: */
547 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
548 | SPI_LSB_FIRST | SPI_LOOP;
549
550 master->setup = mpc83xx_spi_setup;
551 master->transfer = mpc83xx_spi_transfer;
552 master->cleanup = mpc83xx_spi_cleanup;
553
554 mpc83xx_spi = spi_master_get_devdata(master);
555 mpc83xx_spi->qe_mode = pdata->qe_mode;
556 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
557 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
558 mpc83xx_spi->spibrg = pdata->sysclk;
559
560 mpc83xx_spi->rx_shift = 0;
561 mpc83xx_spi->tx_shift = 0;
562 if (mpc83xx_spi->qe_mode) {
563 mpc83xx_spi->rx_shift = 16;
564 mpc83xx_spi->tx_shift = 24;
565 }
566
567 init_completion(&mpc83xx_spi->done);
568
569 mpc83xx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
570 if (mpc83xx_spi->base == NULL) {
571 ret = -ENOMEM;
572 goto put_master;
573 }
574
575 mpc83xx_spi->irq = irq;
576
577 /* Register for SPI Interrupt */
578 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
579 0, "mpc83xx_spi", mpc83xx_spi);
580
581 if (ret != 0)
582 goto unmap_io;
583
584 master->bus_num = pdata->bus_num;
585 master->num_chipselect = pdata->max_chipselect;
586
587 /* SPI controller initializations */
588 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
589 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
590 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
591 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
592
593 /* Enable SPI interface */
594 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
595 if (pdata->qe_mode)
596 regval |= SPMODE_OP;
597
598 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
599 spin_lock_init(&mpc83xx_spi->lock);
600 init_completion(&mpc83xx_spi->done);
601 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
602 INIT_LIST_HEAD(&mpc83xx_spi->queue);
603
604 mpc83xx_spi->workqueue = create_singlethread_workqueue(
605 dev_name(master->dev.parent));
606 if (mpc83xx_spi->workqueue == NULL) {
607 ret = -EBUSY;
608 goto free_irq;
609 }
610
611 ret = spi_register_master(master);
612 if (ret < 0)
613 goto unreg_master;
614
615 printk(KERN_INFO
616 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
617 dev_name(dev), mpc83xx_spi->base, mpc83xx_spi->irq);
618
619 return master;
620
621unreg_master:
622 destroy_workqueue(mpc83xx_spi->workqueue);
623free_irq:
624 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
625unmap_io:
626 iounmap(mpc83xx_spi->base);
627put_master:
628 spi_master_put(master);
629err:
630 return ERR_PTR(ret);
631}
632
633static int __devexit mpc83xx_spi_remove(struct device *dev)
634{
635 struct mpc83xx_spi *mpc83xx_spi;
636 struct spi_master *master;
637
638 master = dev_get_drvdata(dev);
639 mpc83xx_spi = spi_master_get_devdata(master);
640
641 flush_workqueue(mpc83xx_spi->workqueue);
642 destroy_workqueue(mpc83xx_spi->workqueue);
643 spi_unregister_master(master);
644
645 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
646 iounmap(mpc83xx_spi->base);
647
648 return 0;
649}
650
651struct mpc83xx_spi_probe_info {
652 struct fsl_spi_platform_data pdata;
653 int *gpios;
654 bool *alow_flags;
655};
656
657static struct mpc83xx_spi_probe_info *
658to_of_pinfo(struct fsl_spi_platform_data *pdata)
659{
660 return container_of(pdata, struct mpc83xx_spi_probe_info, pdata);
661}
662
663static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
664{
665 struct device *dev = spi->dev.parent;
666 struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
667 u16 cs = spi->chip_select;
668 int gpio = pinfo->gpios[cs];
669 bool alow = pinfo->alow_flags[cs];
670
671 gpio_set_value(gpio, on ^ alow);
672}
673
674static int of_mpc83xx_spi_get_chipselects(struct device *dev)
675{
676 struct device_node *np = dev_archdata_get_node(&dev->archdata);
677 struct fsl_spi_platform_data *pdata = dev->platform_data;
678 struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata);
679 unsigned int ngpios;
680 int i = 0;
681 int ret;
682
683 ngpios = of_gpio_count(np);
684 if (!ngpios) {
685 /*
686 * SPI w/o chip-select line. One SPI device is still permitted
687 * though.
688 */
689 pdata->max_chipselect = 1;
690 return 0;
691 }
692
693 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
694 if (!pinfo->gpios)
695 return -ENOMEM;
696 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
697
698 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
699 GFP_KERNEL);
700 if (!pinfo->alow_flags) {
701 ret = -ENOMEM;
702 goto err_alloc_flags;
703 }
704
705 for (; i < ngpios; i++) {
706 int gpio;
707 enum of_gpio_flags flags;
708
709 gpio = of_get_gpio_flags(np, i, &flags);
710 if (!gpio_is_valid(gpio)) {
711 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
712 goto err_loop;
713 }
714
715 ret = gpio_request(gpio, dev_name(dev));
716 if (ret) {
717 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
718 goto err_loop;
719 }
720
721 pinfo->gpios[i] = gpio;
722 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
723
724 ret = gpio_direction_output(pinfo->gpios[i],
725 pinfo->alow_flags[i]);
726 if (ret) {
727 dev_err(dev, "can't set output direction for gpio "
728 "#%d: %d\n", i, ret);
729 goto err_loop;
730 }
731 }
732
733 pdata->max_chipselect = ngpios;
734 pdata->cs_control = mpc83xx_spi_cs_control;
735
736 return 0;
737
738err_loop:
739 while (i >= 0) {
740 if (gpio_is_valid(pinfo->gpios[i]))
741 gpio_free(pinfo->gpios[i]);
742 i--;
743 }
744
745 kfree(pinfo->alow_flags);
746 pinfo->alow_flags = NULL;
747err_alloc_flags:
748 kfree(pinfo->gpios);
749 pinfo->gpios = NULL;
750 return ret;
751}
752
753static int of_mpc83xx_spi_free_chipselects(struct device *dev)
754{
755 struct fsl_spi_platform_data *pdata = dev->platform_data;
756 struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata);
757 int i;
758
759 if (!pinfo->gpios)
760 return 0;
761
762 for (i = 0; i < pdata->max_chipselect; i++) {
763 if (gpio_is_valid(pinfo->gpios[i]))
764 gpio_free(pinfo->gpios[i]);
765 }
766
767 kfree(pinfo->gpios);
768 kfree(pinfo->alow_flags);
769 return 0;
770}
771
772static int __devinit of_mpc83xx_spi_probe(struct of_device *ofdev,
773 const struct of_device_id *ofid)
774{
775 struct device *dev = &ofdev->dev;
776 struct device_node *np = ofdev->node;
777 struct mpc83xx_spi_probe_info *pinfo;
778 struct fsl_spi_platform_data *pdata;
779 struct spi_master *master;
780 struct resource mem;
781 struct resource irq;
782 const void *prop;
783 int ret = -ENOMEM;
784
785 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
786 if (!pinfo)
787 return -ENOMEM;
788
789 pdata = &pinfo->pdata;
790 dev->platform_data = pdata;
791
792 /* Allocate bus num dynamically. */
793 pdata->bus_num = -1;
794
795 /* SPI controller is either clocked from QE or SoC clock. */
796 pdata->sysclk = get_brgfreq();
797 if (pdata->sysclk == -1) {
798 pdata->sysclk = fsl_get_sys_freq();
799 if (pdata->sysclk == -1) {
800 ret = -ENODEV;
801 goto err_clk;
802 }
803 }
804
805 prop = of_get_property(np, "mode", NULL);
806 if (prop && !strcmp(prop, "cpu-qe"))
807 pdata->qe_mode = 1;
808
809 ret = of_mpc83xx_spi_get_chipselects(dev);
810 if (ret)
811 goto err;
812
813 ret = of_address_to_resource(np, 0, &mem);
814 if (ret)
815 goto err;
816
817 ret = of_irq_to_resource(np, 0, &irq);
818 if (!ret) {
819 ret = -EINVAL;
820 goto err;
821 }
822
823 master = mpc83xx_spi_probe(dev, &mem, irq.start);
824 if (IS_ERR(master)) {
825 ret = PTR_ERR(master);
826 goto err;
827 }
828
829 of_register_spi_devices(master, np);
830
831 return 0;
832
833err:
834 of_mpc83xx_spi_free_chipselects(dev);
835err_clk:
836 kfree(pinfo);
837 return ret;
838}
839
840static int __devexit of_mpc83xx_spi_remove(struct of_device *ofdev)
841{
842 int ret;
843
844 ret = mpc83xx_spi_remove(&ofdev->dev);
845 if (ret)
846 return ret;
847 of_mpc83xx_spi_free_chipselects(&ofdev->dev);
848 return 0;
849}
850
851static const struct of_device_id of_mpc83xx_spi_match[] = {
852 { .compatible = "fsl,spi" },
853 {},
854};
855MODULE_DEVICE_TABLE(of, of_mpc83xx_spi_match);
856
857static struct of_platform_driver of_mpc83xx_spi_driver = {
858 .name = "mpc83xx_spi",
859 .match_table = of_mpc83xx_spi_match,
860 .probe = of_mpc83xx_spi_probe,
861 .remove = __devexit_p(of_mpc83xx_spi_remove),
862};
863
864#ifdef CONFIG_MPC832x_RDB
865/*
866 * XXX XXX XXX
867 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
868 * only. The driver should go away soon, since newer MPC8323E-RDB's device
869 * tree can work with OpenFirmware driver. But for now we support old trees
870 * as well.
871 */
872static int __devinit plat_mpc83xx_spi_probe(struct platform_device *pdev)
873{
874 struct resource *mem;
875 unsigned int irq;
876 struct spi_master *master;
877
878 if (!pdev->dev.platform_data)
879 return -EINVAL;
880
881 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
882 if (!mem)
883 return -EINVAL;
884
885 irq = platform_get_irq(pdev, 0);
886 if (!irq)
887 return -EINVAL;
888
889 master = mpc83xx_spi_probe(&pdev->dev, mem, irq);
890 if (IS_ERR(master))
891 return PTR_ERR(master);
892 return 0;
893}
894
895static int __devexit plat_mpc83xx_spi_remove(struct platform_device *pdev)
896{
897 return mpc83xx_spi_remove(&pdev->dev);
898}
899
900MODULE_ALIAS("platform:mpc83xx_spi");
901static struct platform_driver mpc83xx_spi_driver = {
902 .probe = plat_mpc83xx_spi_probe,
903 .remove = __exit_p(plat_mpc83xx_spi_remove),
904 .driver = {
905 .name = "mpc83xx_spi",
906 .owner = THIS_MODULE,
907 },
908};
909
910static bool legacy_driver_failed;
911
912static void __init legacy_driver_register(void)
913{
914 legacy_driver_failed = platform_driver_register(&mpc83xx_spi_driver);
915}
916
917static void __exit legacy_driver_unregister(void)
918{
919 if (legacy_driver_failed)
920 return;
921 platform_driver_unregister(&mpc83xx_spi_driver);
922}
923#else
924static void __init legacy_driver_register(void) {}
925static void __exit legacy_driver_unregister(void) {}
926#endif /* CONFIG_MPC832x_RDB */
927
928static int __init mpc83xx_spi_init(void)
929{
930 legacy_driver_register();
931 return of_register_platform_driver(&of_mpc83xx_spi_driver);
932}
933
934static void __exit mpc83xx_spi_exit(void)
935{
936 of_unregister_platform_driver(&of_mpc83xx_spi_driver);
937 legacy_driver_unregister();
938}
939
940module_init(mpc83xx_spi_init);
941module_exit(mpc83xx_spi_exit);
942
943MODULE_AUTHOR("Kumar Gala");
944MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
945MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 15:56:29 -0500