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authorhartleys <hartleys@visionengravers.com>2010-05-06 16:51:04 -0400
committerGrant Likely <grant.likely@secretlab.ca>2010-05-25 02:23:17 -0400
commit41c4221ca6b9db8ea63d2c2323c0e7a8865eba6e (patch)
tree31e12f709964805f9d73cf834297950b9ad09000 /drivers/spi/spi_bitbang_txrx.h
parent6e27388f1bd60b55e0b1a83d14233e6c7ad33700 (diff)
spi: move bitbang txrx utility functions to private header
A number of files in drivers/spi fail checkincludes.pl due to the double include of <linux/spi/spi_bitbang.h>. The first include is needed to get the struct spi_bitbang definition and the spi_bitbang_* function prototypes. The second include happens after defining EXPAND_BITBANG_TXRX to get the inlined bitbang_txrx_* utility functions. The <linux/spi/spi_bitbang.h> header is also included by a number of other spi drivers, as well as some arch/ code, in order to use struct spi_bitbang and the associated functions. To fix the double include, and remove any potential confusion about it, move the inlined bitbang_txrx_* functions to a new private header in drivers/spi and also remove the need to define EXPAND_BITBANG_TXRX. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi/spi_bitbang_txrx.h')
-rw-r--r--drivers/spi/spi_bitbang_txrx.h93
1 files changed, 93 insertions, 0 deletions
diff --git a/drivers/spi/spi_bitbang_txrx.h b/drivers/spi/spi_bitbang_txrx.h
new file mode 100644
index 000000000000..fc033bbf9180
--- /dev/null
+++ b/drivers/spi/spi_bitbang_txrx.h
@@ -0,0 +1,93 @@
1/*
2 * Mix this utility code with some glue code to get one of several types of
3 * simple SPI master driver. Two do polled word-at-a-time I/O:
4 *
5 * - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
6 * expanding the per-word routines from the inline templates below.
7 *
8 * - Drivers for controllers resembling bare shift registers. Provide
9 * chipselect() and txrx_word[](), with custom setup()/cleanup() methods
10 * that use your controller's clock and chipselect registers.
11 *
12 * Some hardware works well with requests at spi_transfer scope:
13 *
14 * - Drivers leveraging smarter hardware, with fifos or DMA; or for half
15 * duplex (MicroWire) controllers. Provide chipselect() and txrx_bufs(),
16 * and custom setup()/cleanup() methods.
17 */
18
19/*
20 * The code that knows what GPIO pins do what should have declared four
21 * functions, ideally as inlines, before including this header:
22 *
23 * void setsck(struct spi_device *, int is_on);
24 * void setmosi(struct spi_device *, int is_on);
25 * int getmiso(struct spi_device *);
26 * void spidelay(unsigned);
27 *
28 * setsck()'s is_on parameter is a zero/nonzero boolean.
29 *
30 * setmosi()'s is_on parameter is a zero/nonzero boolean.
31 *
32 * getmiso() is required to return 0 or 1 only. Any other value is invalid
33 * and will result in improper operation.
34 *
35 * A non-inlined routine would call bitbang_txrx_*() routines. The
36 * main loop could easily compile down to a handful of instructions,
37 * especially if the delay is a NOP (to run at peak speed).
38 *
39 * Since this is software, the timings may not be exactly what your board's
40 * chips need ... there may be several reasons you'd need to tweak timings
41 * in these routines, not just make to make it faster or slower to match a
42 * particular CPU clock rate.
43 */
44
45static inline u32
46bitbang_txrx_be_cpha0(struct spi_device *spi,
47 unsigned nsecs, unsigned cpol,
48 u32 word, u8 bits)
49{
50 /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
51
52 /* clock starts at inactive polarity */
53 for (word <<= (32 - bits); likely(bits); bits--) {
54
55 /* setup MSB (to slave) on trailing edge */
56 setmosi(spi, word & (1 << 31));
57 spidelay(nsecs); /* T(setup) */
58
59 setsck(spi, !cpol);
60 spidelay(nsecs);
61
62 /* sample MSB (from slave) on leading edge */
63 word <<= 1;
64 word |= getmiso(spi);
65 setsck(spi, cpol);
66 }
67 return word;
68}
69
70static inline u32
71bitbang_txrx_be_cpha1(struct spi_device *spi,
72 unsigned nsecs, unsigned cpol,
73 u32 word, u8 bits)
74{
75 /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
76
77 /* clock starts at inactive polarity */
78 for (word <<= (32 - bits); likely(bits); bits--) {
79
80 /* setup MSB (to slave) on leading edge */
81 setsck(spi, !cpol);
82 setmosi(spi, word & (1 << 31));
83 spidelay(nsecs); /* T(setup) */
84
85 setsck(spi, cpol);
86 spidelay(nsecs);
87
88 /* sample MSB (from slave) on trailing edge */
89 word <<= 1;
90 word |= getmiso(spi);
91 }
92 return word;
93}