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authorMike Frysinger <vapier@gentoo.org>2009-12-18 13:00:10 -0500
committerMike Frysinger <vapier@gentoo.org>2010-10-18 02:49:39 -0400
commit5e8592dca303fb429d1641c205fe509f4b781ca2 (patch)
tree14bbd03eeec15e99bb9ea1aefcb1a953be31159e /drivers/spi/spi_bfin5xx.c
parent5b47bcd48b3bd53c86040321de0d348aadebed87 (diff)
spi/bfin_spi: combine duplicate SPI_CTL read/write logic
While combining things, also switch to the proper SPI bit define names. This lets us punt the rarely used SPI defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'drivers/spi/spi_bfin5xx.c')
-rw-r--r--drivers/spi/spi_bfin5xx.c40
1 files changed, 18 insertions, 22 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index 376f2f09e34c..b3450b78cc50 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -560,8 +560,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
560 struct spi_transfer *previous = NULL; 560 struct spi_transfer *previous = NULL;
561 struct slave_data *chip = NULL; 561 struct slave_data *chip = NULL;
562 unsigned int bits_per_word; 562 unsigned int bits_per_word;
563 u8 width; 563 u16 cr, cr_width, dma_width, dma_config;
564 u16 cr, dma_width, dma_config;
565 u32 tranf_success = 1; 564 u32 tranf_success = 1;
566 u8 full_duplex = 0; 565 u8 full_duplex = 0;
567 566
@@ -642,22 +641,19 @@ static void bfin_spi_pump_transfers(unsigned long data)
642 bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; 641 bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
643 if (bits_per_word == 8) { 642 if (bits_per_word == 8) {
644 drv_data->n_bytes = 1; 643 drv_data->n_bytes = 1;
645 width = CFG_SPI_WORDSIZE8; 644 drv_data->len = transfer->len;
645 cr_width = 0;
646 drv_data->ops = &bfin_transfer_ops_u8; 646 drv_data->ops = &bfin_transfer_ops_u8;
647 } else { 647 } else {
648 drv_data->n_bytes = 2; 648 drv_data->n_bytes = 2;
649 width = CFG_SPI_WORDSIZE16; 649 drv_data->len = (transfer->len) >> 1;
650 cr_width = BIT_CTL_WORDSIZE;
650 drv_data->ops = &bfin_transfer_ops_u16; 651 drv_data->ops = &bfin_transfer_ops_u16;
651 } 652 }
652 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); 653 cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
653 cr |= (width << 8); 654 cr |= cr_width;
654 write_CTRL(drv_data, cr); 655 write_CTRL(drv_data, cr);
655 656
656 if (width == CFG_SPI_WORDSIZE16) {
657 drv_data->len = (transfer->len) >> 1;
658 } else {
659 drv_data->len = transfer->len;
660 }
661 dev_dbg(&drv_data->pdev->dev, 657 dev_dbg(&drv_data->pdev->dev,
662 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", 658 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
663 drv_data->ops, chip->ops, &bfin_transfer_ops_u8); 659 drv_data->ops, chip->ops, &bfin_transfer_ops_u8);
@@ -672,13 +668,12 @@ static void bfin_spi_pump_transfers(unsigned long data)
672 write_BAUD(drv_data, chip->baud); 668 write_BAUD(drv_data, chip->baud);
673 669
674 write_STAT(drv_data, BIT_STAT_CLR); 670 write_STAT(drv_data, BIT_STAT_CLR);
675 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
676 if (drv_data->cs_change) 671 if (drv_data->cs_change)
677 bfin_spi_cs_active(drv_data, chip); 672 bfin_spi_cs_active(drv_data, chip);
678 673
679 dev_dbg(&drv_data->pdev->dev, 674 dev_dbg(&drv_data->pdev->dev,
680 "now pumping a transfer: width is %d, len is %d\n", 675 "now pumping a transfer: width is %d, len is %d\n",
681 width, transfer->len); 676 cr_width, transfer->len);
682 677
683 /* 678 /*
684 * Try to map dma buffer and do a dma transfer. If successful use, 679 * Try to map dma buffer and do a dma transfer. If successful use,
@@ -697,7 +692,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
697 /* config dma channel */ 692 /* config dma channel */
698 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); 693 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
699 set_dma_x_count(drv_data->dma_channel, drv_data->len); 694 set_dma_x_count(drv_data->dma_channel, drv_data->len);
700 if (width == CFG_SPI_WORDSIZE16) { 695 if (cr_width == BIT_CTL_WORDSIZE) {
701 set_dma_x_modify(drv_data->dma_channel, 2); 696 set_dma_x_modify(drv_data->dma_channel, 2);
702 dma_width = WDSIZE_16; 697 dma_width = WDSIZE_16;
703 } else { 698 } else {
@@ -786,10 +781,16 @@ static void bfin_spi_pump_transfers(unsigned long data)
786 return; 781 return;
787 } 782 }
788 783
784 /*
785 * We always use SPI_WRITE mode (transfer starts with TDBR write).
786 * SPI_READ mode (transfer starts with RDBR read) seems to have
787 * problems with setting up the output value in TDBR prior to the
788 * start of the transfer.
789 */
790 write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
791
789 if (chip->pio_interrupt) { 792 if (chip->pio_interrupt) {
790 /* use write mode. spi irq should have been disabled */ 793 /* SPI irq should have been disabled by now */
791 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
792 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
793 794
794 /* discard old RX data and clear RXS */ 795 /* discard old RX data and clear RXS */
795 bfin_spi_dummy_read(drv_data); 796 bfin_spi_dummy_read(drv_data);
@@ -813,11 +814,6 @@ static void bfin_spi_pump_transfers(unsigned long data)
813 /* IO mode */ 814 /* IO mode */
814 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); 815 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
815 816
816 /* we always use SPI_WRITE mode. SPI_READ mode
817 seems to have problems with setting up the
818 output value in TDBR prior to the transfer. */
819 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
820
821 if (full_duplex) { 817 if (full_duplex) {
822 /* full duplex mode */ 818 /* full duplex mode */
823 BUG_ON((drv_data->tx_end - drv_data->tx) != 819 BUG_ON((drv_data->tx_end - drv_data->tx) !=