diff options
author | Mike Frysinger <vapier@gentoo.org> | 2009-12-18 12:38:04 -0500 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-18 02:49:38 -0400 |
commit | 033f44bd0ebca1809e8274237a64263d909f01a7 (patch) | |
tree | 04ba3e37c926c07809e934b0adf39ec6310f7114 /drivers/spi/spi_bfin5xx.c | |
parent | 7370ed6b91c37d7022a89a820b0fcd3156fa87fc (diff) |
spi/bfin_spi: push all size checks into the transfer function
This reduces duplication between the setup/transfer functions and keeps
values cached during setup from overriding values changed on a transfer
basis (like bits_per_word).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'drivers/spi/spi_bfin5xx.c')
-rw-r--r-- | drivers/spi/spi_bfin5xx.c | 57 |
1 files changed, 14 insertions, 43 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c index d446524aa894..830c7055f151 100644 --- a/drivers/spi/spi_bfin5xx.c +++ b/drivers/spi/spi_bfin5xx.c | |||
@@ -114,10 +114,7 @@ struct slave_data { | |||
114 | u16 flag; | 114 | u16 flag; |
115 | 115 | ||
116 | u8 chip_select_num; | 116 | u8 chip_select_num; |
117 | u8 n_bytes; | ||
118 | u8 width; /* 0 or 1 */ | ||
119 | u8 enable_dma; | 117 | u8 enable_dma; |
120 | u8 bits_per_word; /* 8 or 16 */ | ||
121 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ | 118 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
122 | u32 cs_gpio; | 119 | u32 cs_gpio; |
123 | u16 idle_tx_val; | 120 | u16 idle_tx_val; |
@@ -562,6 +559,7 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
562 | struct spi_transfer *transfer = NULL; | 559 | struct spi_transfer *transfer = NULL; |
563 | struct spi_transfer *previous = NULL; | 560 | struct spi_transfer *previous = NULL; |
564 | struct slave_data *chip = NULL; | 561 | struct slave_data *chip = NULL; |
562 | unsigned int bits_per_word; | ||
565 | u8 width; | 563 | u8 width; |
566 | u16 cr, dma_width, dma_config; | 564 | u16 cr, dma_width, dma_config; |
567 | u32 tranf_success = 1; | 565 | u32 tranf_success = 1; |
@@ -641,26 +639,15 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
641 | drv_data->cs_change = transfer->cs_change; | 639 | drv_data->cs_change = transfer->cs_change; |
642 | 640 | ||
643 | /* Bits per word setup */ | 641 | /* Bits per word setup */ |
644 | switch (transfer->bits_per_word) { | 642 | bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; |
645 | case 8: | 643 | if (bits_per_word == 8) { |
646 | drv_data->n_bytes = 1; | 644 | drv_data->n_bytes = 1; |
647 | width = CFG_SPI_WORDSIZE8; | 645 | width = CFG_SPI_WORDSIZE8; |
648 | drv_data->ops = &bfin_transfer_ops_u8; | 646 | drv_data->ops = &bfin_transfer_ops_u8; |
649 | break; | 647 | } else { |
650 | |||
651 | case 16: | ||
652 | drv_data->n_bytes = 2; | 648 | drv_data->n_bytes = 2; |
653 | width = CFG_SPI_WORDSIZE16; | 649 | width = CFG_SPI_WORDSIZE16; |
654 | drv_data->ops = &bfin_transfer_ops_u16; | 650 | drv_data->ops = &bfin_transfer_ops_u16; |
655 | break; | ||
656 | |||
657 | default: | ||
658 | /* No change, the same as default setting */ | ||
659 | transfer->bits_per_word = chip->bits_per_word; | ||
660 | drv_data->n_bytes = chip->n_bytes; | ||
661 | width = chip->width; | ||
662 | drv_data->ops = chip->ops; | ||
663 | break; | ||
664 | } | 651 | } |
665 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | 652 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); |
666 | cr |= (width << 8); | 653 | cr |= (width << 8); |
@@ -811,9 +798,9 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
811 | if (drv_data->tx == NULL) | 798 | if (drv_data->tx == NULL) |
812 | write_TDBR(drv_data, chip->idle_tx_val); | 799 | write_TDBR(drv_data, chip->idle_tx_val); |
813 | else { | 800 | else { |
814 | if (transfer->bits_per_word == 8) | 801 | if (bits_per_word == 8) |
815 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | 802 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
816 | else if (transfer->bits_per_word == 16) | 803 | else |
817 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | 804 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
818 | drv_data->tx += drv_data->n_bytes; | 805 | drv_data->tx += drv_data->n_bytes; |
819 | } | 806 | } |
@@ -987,9 +974,6 @@ static int bfin_spi_setup(struct spi_device *spi) | |||
987 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | 974 | struct master_data *drv_data = spi_master_get_devdata(spi->master); |
988 | int ret = -EINVAL; | 975 | int ret = -EINVAL; |
989 | 976 | ||
990 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | ||
991 | goto error; | ||
992 | |||
993 | /* Only alloc (or use chip_info) on first setup */ | 977 | /* Only alloc (or use chip_info) on first setup */ |
994 | chip_info = NULL; | 978 | chip_info = NULL; |
995 | chip = spi_get_ctldata(spi); | 979 | chip = spi_get_ctldata(spi); |
@@ -1023,10 +1007,16 @@ static int bfin_spi_setup(struct spi_device *spi) | |||
1023 | chip->enable_dma = chip_info->enable_dma != 0 | 1007 | chip->enable_dma = chip_info->enable_dma != 0 |
1024 | && drv_data->master_info->enable_dma; | 1008 | && drv_data->master_info->enable_dma; |
1025 | chip->ctl_reg = chip_info->ctl_reg; | 1009 | chip->ctl_reg = chip_info->ctl_reg; |
1026 | chip->bits_per_word = chip_info->bits_per_word; | ||
1027 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | 1010 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
1028 | chip->idle_tx_val = chip_info->idle_tx_val; | 1011 | chip->idle_tx_val = chip_info->idle_tx_val; |
1029 | chip->pio_interrupt = chip_info->pio_interrupt; | 1012 | chip->pio_interrupt = chip_info->pio_interrupt; |
1013 | spi->bits_per_word = chip_info->bits_per_word; | ||
1014 | } | ||
1015 | |||
1016 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) { | ||
1017 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | ||
1018 | spi->bits_per_word); | ||
1019 | goto error; | ||
1030 | } | 1020 | } |
1031 | 1021 | ||
1032 | /* translate common spi framework into our register */ | 1022 | /* translate common spi framework into our register */ |
@@ -1050,25 +1040,6 @@ static int bfin_spi_setup(struct spi_device *spi) | |||
1050 | else | 1040 | else |
1051 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; | 1041 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; |
1052 | 1042 | ||
1053 | switch (chip->bits_per_word) { | ||
1054 | case 8: | ||
1055 | chip->n_bytes = 1; | ||
1056 | chip->width = CFG_SPI_WORDSIZE8; | ||
1057 | chip->ops = &bfin_transfer_ops_u8; | ||
1058 | break; | ||
1059 | |||
1060 | case 16: | ||
1061 | chip->n_bytes = 2; | ||
1062 | chip->width = CFG_SPI_WORDSIZE16; | ||
1063 | chip->ops = &bfin_transfer_ops_u16; | ||
1064 | break; | ||
1065 | |||
1066 | default: | ||
1067 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | ||
1068 | chip->bits_per_word); | ||
1069 | goto error; | ||
1070 | } | ||
1071 | |||
1072 | if (chip->enable_dma && chip->pio_interrupt) { | 1043 | if (chip->enable_dma && chip->pio_interrupt) { |
1073 | dev_err(&spi->dev, "enable_dma is set, " | 1044 | dev_err(&spi->dev, "enable_dma is set, " |
1074 | "do not set pio_interrupt\n"); | 1045 | "do not set pio_interrupt\n"); |
@@ -1119,7 +1090,7 @@ static int bfin_spi_setup(struct spi_device *spi) | |||
1119 | } | 1090 | } |
1120 | 1091 | ||
1121 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", | 1092 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
1122 | spi->modalias, chip->width, chip->enable_dma); | 1093 | spi->modalias, spi->bits_per_word, chip->enable_dma); |
1123 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", | 1094 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
1124 | chip->ctl_reg, chip->flag); | 1095 | chip->ctl_reg, chip->flag); |
1125 | 1096 | ||