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authorStephen Warren <swarren@nvidia.com>2013-11-06 18:31:24 -0500
committerStephen Warren <swarren@nvidia.com>2013-12-11 18:44:17 -0500
commitff2251e3de37b002e2e91e4917119f5776e210e3 (patch)
treeb08a8d09129d099d018c3d1e618f1ffdd689943f /drivers/spi/spi-tegra20-slink.c
parentc0df5bf5369ec5d12d781491c95e3207ec5ee2b7 (diff)
spi: tegra: use reset framework
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/spi/spi-tegra20-slink.c')
-rw-r--r--drivers/spi/spi-tegra20-slink.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index e66715ba37ed..1305b8f933ba 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -33,8 +33,8 @@
33#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
34#include <linux/of.h> 34#include <linux/of.h>
35#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/reset.h>
36#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
37#include <linux/clk/tegra.h>
38 38
39#define SLINK_COMMAND 0x000 39#define SLINK_COMMAND 0x000
40#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 40#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
@@ -167,6 +167,7 @@ struct tegra_slink_data {
167 spinlock_t lock; 167 spinlock_t lock;
168 168
169 struct clk *clk; 169 struct clk *clk;
170 struct reset_control *rst;
170 void __iomem *base; 171 void __iomem *base;
171 phys_addr_t phys; 172 phys_addr_t phys;
172 unsigned irq; 173 unsigned irq;
@@ -884,9 +885,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
884 dev_err(tspi->dev, 885 dev_err(tspi->dev,
885 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 886 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
886 tspi->command2_reg, tspi->dma_control_reg); 887 tspi->command2_reg, tspi->dma_control_reg);
887 tegra_periph_reset_assert(tspi->clk); 888 reset_control_assert(tspi->rst);
888 udelay(2); 889 udelay(2);
889 tegra_periph_reset_deassert(tspi->clk); 890 reset_control_deassert(tspi->rst);
890 complete(&tspi->xfer_completion); 891 complete(&tspi->xfer_completion);
891 goto exit; 892 goto exit;
892 } 893 }
@@ -957,9 +958,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
957 dev_err(tspi->dev, 958 dev_err(tspi->dev,
958 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 959 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
959 tspi->command2_reg, tspi->dma_control_reg); 960 tspi->command2_reg, tspi->dma_control_reg);
960 tegra_periph_reset_assert(tspi->clk); 961 reset_control_assert(tspi->rst);
961 udelay(2); 962 udelay(2);
962 tegra_periph_reset_deassert(tspi->clk); 963 reset_control_assert(tspi->rst);
963 complete(&tspi->xfer_completion); 964 complete(&tspi->xfer_completion);
964 spin_unlock_irqrestore(&tspi->lock, flags); 965 spin_unlock_irqrestore(&tspi->lock, flags);
965 return IRQ_HANDLED; 966 return IRQ_HANDLED;
@@ -1118,6 +1119,13 @@ static int tegra_slink_probe(struct platform_device *pdev)
1118 goto exit_free_irq; 1119 goto exit_free_irq;
1119 } 1120 }
1120 1121
1122 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1123 if (IS_ERR(tspi->rst)) {
1124 dev_err(&pdev->dev, "can not get reset\n");
1125 ret = PTR_ERR(tspi->rst);
1126 goto exit_free_irq;
1127 }
1128
1121 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1129 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1122 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1130 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1123 1131