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authorMark Brown <broonie@linaro.org>2013-09-27 14:56:31 -0400
committerMark Brown <broonie@linaro.org>2013-09-30 07:53:38 -0400
commit8c09daa1c963e2ab58029520dd2f3d54184d7258 (patch)
tree9ae4dddb29279dc42d1dcaf908dd46c862f9a781 /drivers/spi/spi-s3c64xx.c
parentdd97e26849c16f484191f056b6e080cc30ebe98b (diff)
spi/s3c64xx: Factor transfer start out of enable/disable_cs()
The hardware level /CS handling is tied to the start of the data path so is rolled into the same function as we use to manipulate GPIO /CS. In order to support factoring out the /CS handling into the core separate the two and explicitly start transfers separately to the /CS handling. Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/spi/spi-s3c64xx.c')
-rw-r--r--drivers/spi/spi-s3c64xx.c19
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 43caeee8641a..2ab96fb28d22 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -570,9 +570,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
570 570
571 if (spi->cs_gpio >= 0) 571 if (spi->cs_gpio >= 0)
572 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 1 : 0); 572 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 1 : 0);
573
574 /* Start the signals */
575 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
576} 573}
577 574
578static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 575static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
@@ -702,9 +699,6 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
702 699
703 if (spi->cs_gpio >= 0) 700 if (spi->cs_gpio >= 0)
704 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); 701 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
705
706 /* Quiese the signals */
707 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
708} 702}
709 703
710static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 704static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
@@ -930,6 +924,9 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
930 /* Slave Select */ 924 /* Slave Select */
931 enable_cs(sdd, spi); 925 enable_cs(sdd, spi);
932 926
927 /* Start the signals */
928 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
929
933 spin_unlock_irqrestore(&sdd->lock, flags); 930 spin_unlock_irqrestore(&sdd->lock, flags);
934 931
935 status = wait_for_xfer(sdd, xfer, use_dma); 932 status = wait_for_xfer(sdd, xfer, use_dma);
@@ -970,10 +967,14 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
970 } 967 }
971 968
972out: 969out:
973 if (!cs_toggle || status) 970 if (!cs_toggle || status) {
971 /* Quiese the signals */
972 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
973 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
974 disable_cs(sdd, spi); 974 disable_cs(sdd, spi);
975 else 975 } else {
976 sdd->tgl_spi = spi; 976 sdd->tgl_spi = spi;
977 }
977 978
978 s3c64xx_spi_unmap_mssg(sdd, msg); 979 s3c64xx_spi_unmap_mssg(sdd, msg);
979 980
@@ -1112,11 +1113,13 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
1112 } 1113 }
1113 1114
1114 pm_runtime_put(&sdd->pdev->dev); 1115 pm_runtime_put(&sdd->pdev->dev);
1116 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1115 disable_cs(sdd, spi); 1117 disable_cs(sdd, spi);
1116 return 0; 1118 return 0;
1117 1119
1118setup_exit: 1120setup_exit:
1119 /* setup() returns with device de-selected */ 1121 /* setup() returns with device de-selected */
1122 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1120 disable_cs(sdd, spi); 1123 disable_cs(sdd, spi);
1121 1124
1122 gpio_free(cs->line); 1125 gpio_free(cs->line);