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authorBenoit Cousson <b-cousson@ti.com>2012-03-26 06:02:33 -0400
committerGrant Likely <grant.likely@secretlab.ca>2012-04-10 16:10:35 -0400
commit1bd897f84964c2ce3a28d11f7eb7c4e0a8d3ca3c (patch)
treeed96f4986d79d35d5f04c54ea0f494139f424288 /drivers/spi/spi-omap2-mcspi.c
parentaae730dfe239f1a5122ba873b54dffc20a516775 (diff)
spi/omap: Remove bus_num usage for instance index
bus_num was used to reference the mcspi controller instance in a fixed array. Remove this array and store this information directly inside drvdata structure. bus_num is now just set if the pdev->id is present or with -1 for dynamic allocation by SPI core, but the driver does not access it anymore. Clean some bad comments format, and remove un-needed space. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [Cleanup the OMAP2_MCSPI_MAX_CTRL macro as it is not needed anymore] Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Diffstat (limited to 'drivers/spi/spi-omap2-mcspi.c')
-rw-r--r--drivers/spi/spi-omap2-mcspi.c75
1 files changed, 34 insertions, 41 deletions
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 33f54cd07fe0..1907ed2e2958 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -45,9 +45,6 @@
45 45
46#define OMAP2_MCSPI_MAX_FREQ 48000000 46#define OMAP2_MCSPI_MAX_FREQ 48000000
47 47
48/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
49#define OMAP2_MCSPI_MAX_CTRL 4
50
51#define OMAP2_MCSPI_REVISION 0x00 48#define OMAP2_MCSPI_REVISION 0x00
52#define OMAP2_MCSPI_SYSSTATUS 0x14 49#define OMAP2_MCSPI_SYSSTATUS 0x14
53#define OMAP2_MCSPI_IRQSTATUS 0x18 50#define OMAP2_MCSPI_IRQSTATUS 0x18
@@ -111,6 +108,16 @@ struct omap2_mcspi_dma {
111#define DMA_MIN_BYTES 160 108#define DMA_MIN_BYTES 160
112 109
113 110
111/*
112 * Used for context save and restore, structure members to be updated whenever
113 * corresponding registers are modified.
114 */
115struct omap2_mcspi_regs {
116 u32 modulctrl;
117 u32 wakeupenable;
118 struct list_head cs;
119};
120
114struct omap2_mcspi { 121struct omap2_mcspi {
115 struct work_struct work; 122 struct work_struct work;
116 /* lock protects queue and registers */ 123 /* lock protects queue and registers */
@@ -122,8 +129,9 @@ struct omap2_mcspi {
122 unsigned long phys; 129 unsigned long phys;
123 /* SPI1 has 4 channels, while SPI2 has 2 */ 130 /* SPI1 has 4 channels, while SPI2 has 2 */
124 struct omap2_mcspi_dma *dma_channels; 131 struct omap2_mcspi_dma *dma_channels;
125 struct device *dev; 132 struct device *dev;
126 struct workqueue_struct *wq; 133 struct workqueue_struct *wq;
134 struct omap2_mcspi_regs ctx;
127}; 135};
128 136
129struct omap2_mcspi_cs { 137struct omap2_mcspi_cs {
@@ -135,17 +143,6 @@ struct omap2_mcspi_cs {
135 u32 chconf0; 143 u32 chconf0;
136}; 144};
137 145
138/* used for context save and restore, structure members to be updated whenever
139 * corresponding registers are modified.
140 */
141struct omap2_mcspi_regs {
142 u32 modulctrl;
143 u32 wakeupenable;
144 struct list_head cs;
145};
146
147static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
148
149#define MOD_REG_BIT(val, mask, set) do { \ 146#define MOD_REG_BIT(val, mask, set) do { \
150 if (set) \ 147 if (set) \
151 val |= mask; \ 148 val |= mask; \
@@ -236,9 +233,12 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
236 233
237static void omap2_mcspi_set_master_mode(struct spi_master *master) 234static void omap2_mcspi_set_master_mode(struct spi_master *master)
238{ 235{
236 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
237 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
239 u32 l; 238 u32 l;
240 239
241 /* setup when switching from (reset default) slave mode 240 /*
241 * Setup when switching from (reset default) slave mode
242 * to single-channel master mode 242 * to single-channel master mode
243 */ 243 */
244 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 244 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
@@ -247,24 +247,20 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master)
247 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); 247 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
248 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 248 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
249 249
250 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l; 250 ctx->modulctrl = l;
251} 251}
252 252
253static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) 253static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
254{ 254{
255 struct spi_master *spi_cntrl; 255 struct spi_master *spi_cntrl = mcspi->master;
256 struct omap2_mcspi_cs *cs; 256 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
257 spi_cntrl = mcspi->master; 257 struct omap2_mcspi_cs *cs;
258 258
259 /* McSPI: context restore */ 259 /* McSPI: context restore */
260 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, 260 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
261 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); 261 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
262 262
263 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, 263 list_for_each_entry(cs, &ctx->cs, node)
264 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
265
266 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
267 node)
268 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 264 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
269} 265}
270static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) 266static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
@@ -777,7 +773,8 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
777static int omap2_mcspi_setup(struct spi_device *spi) 773static int omap2_mcspi_setup(struct spi_device *spi)
778{ 774{
779 int ret; 775 int ret;
780 struct omap2_mcspi *mcspi; 776 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
777 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
781 struct omap2_mcspi_dma *mcspi_dma; 778 struct omap2_mcspi_dma *mcspi_dma;
782 struct omap2_mcspi_cs *cs = spi->controller_state; 779 struct omap2_mcspi_cs *cs = spi->controller_state;
783 780
@@ -787,7 +784,6 @@ static int omap2_mcspi_setup(struct spi_device *spi)
787 return -EINVAL; 784 return -EINVAL;
788 } 785 }
789 786
790 mcspi = spi_master_get_devdata(spi->master);
791 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 787 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
792 788
793 if (!cs) { 789 if (!cs) {
@@ -799,8 +795,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
799 cs->chconf0 = 0; 795 cs->chconf0 = 0;
800 spi->controller_state = cs; 796 spi->controller_state = cs;
801 /* Link this to context save list */ 797 /* Link this to context save list */
802 list_add_tail(&cs->node, 798 list_add_tail(&cs->node, &ctx->cs);
803 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
804 } 799 }
805 800
806 if (mcspi_dma->dma_rx_channel == -1 801 if (mcspi_dma->dma_rx_channel == -1
@@ -1052,8 +1047,9 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
1052static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1047static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1053{ 1048{
1054 struct spi_master *master = mcspi->master; 1049 struct spi_master *master = mcspi->master;
1050 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1055 u32 tmp; 1051 u32 tmp;
1056 int ret = 0; 1052 int ret = 0;
1057 1053
1058 ret = omap2_mcspi_enable_clocks(mcspi); 1054 ret = omap2_mcspi_enable_clocks(mcspi);
1059 if (ret < 0) 1055 if (ret < 0)
@@ -1061,7 +1057,7 @@ static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1061 1057
1062 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1058 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1063 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); 1059 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1064 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp; 1060 ctx->wakeupenable = tmp;
1065 1061
1066 omap2_mcspi_set_master_mode(master); 1062 omap2_mcspi_set_master_mode(master);
1067 omap2_mcspi_disable_clocks(mcspi); 1063 omap2_mcspi_disable_clocks(mcspi);
@@ -1108,7 +1104,6 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1108 struct omap2_mcspi *mcspi; 1104 struct omap2_mcspi *mcspi;
1109 struct resource *r; 1105 struct resource *r;
1110 int status = 0, i; 1106 int status = 0, i;
1111 char wq_name[20];
1112 u32 regs_offset = 0; 1107 u32 regs_offset = 0;
1113 static int bus_num = 1; 1108 static int bus_num = 1;
1114 struct device_node *node = pdev->dev.of_node; 1109 struct device_node *node = pdev->dev.of_node;
@@ -1149,8 +1144,7 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1149 mcspi = spi_master_get_devdata(master); 1144 mcspi = spi_master_get_devdata(master);
1150 mcspi->master = master; 1145 mcspi->master = master;
1151 1146
1152 sprintf(wq_name, "omap2_mcspi/%d", master->bus_num); 1147 mcspi->wq = alloc_workqueue(dev_name(&pdev->dev), WQ_MEM_RECLAIM, 1);
1153 mcspi->wq = alloc_workqueue(wq_name, WQ_MEM_RECLAIM, 1);
1154 if (mcspi->wq == NULL) { 1148 if (mcspi->wq == NULL) {
1155 status = -ENOMEM; 1149 status = -ENOMEM;
1156 goto free_master; 1150 goto free_master;
@@ -1178,7 +1172,7 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1178 1172
1179 spin_lock_init(&mcspi->lock); 1173 spin_lock_init(&mcspi->lock);
1180 INIT_LIST_HEAD(&mcspi->msg_queue); 1174 INIT_LIST_HEAD(&mcspi->msg_queue);
1181 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); 1175 INIT_LIST_HEAD(&mcspi->ctx.cs);
1182 1176
1183 mcspi->dma_channels = kcalloc(master->num_chipselect, 1177 mcspi->dma_channels = kcalloc(master->num_chipselect,
1184 sizeof(struct omap2_mcspi_dma), 1178 sizeof(struct omap2_mcspi_dma),
@@ -1275,13 +1269,12 @@ static int omap2_mcspi_resume(struct device *dev)
1275{ 1269{
1276 struct spi_master *master = dev_get_drvdata(dev); 1270 struct spi_master *master = dev_get_drvdata(dev);
1277 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1271 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1278 struct omap2_mcspi_cs *cs; 1272 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1273 struct omap2_mcspi_cs *cs;
1279 1274
1280 omap2_mcspi_enable_clocks(mcspi); 1275 omap2_mcspi_enable_clocks(mcspi);
1281 list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs, 1276 list_for_each_entry(cs, &ctx->cs, node) {
1282 node) {
1283 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1277 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1284
1285 /* 1278 /*
1286 * We need to toggle CS state for OMAP take this 1279 * We need to toggle CS state for OMAP take this
1287 * change in account. 1280 * change in account.