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authorDaniel Mack <zonque@gmail.com>2012-10-07 12:19:44 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-10-17 03:26:51 -0400
commit0384e90b853357d24935c65ba0e1bdd27faa6e58 (patch)
tree4ee58ec411a372761b15e9316ca6f827c613308f /drivers/spi/spi-omap2-mcspi.c
parentddffeb8c4d0331609ef2581d84de4d763607bd37 (diff)
spi/mcspi: allow configuration of pin directions
Allow D0 to be an input and D1 to be an output, configurable via platform data and a new DT property. Based on a patch from Matus Ujhelyi <matus.ujhelyi@streamunlimited.com> Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/spi/spi-omap2-mcspi.c')
-rw-r--r--drivers/spi/spi-omap2-mcspi.c25
1 files changed, 18 insertions, 7 deletions
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 3542fdc664b1..51046332677c 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -130,6 +130,7 @@ struct omap2_mcspi {
130 struct omap2_mcspi_dma *dma_channels; 130 struct omap2_mcspi_dma *dma_channels;
131 struct device *dev; 131 struct device *dev;
132 struct omap2_mcspi_regs ctx; 132 struct omap2_mcspi_regs ctx;
133 unsigned int pin_dir:1;
133}; 134};
134 135
135struct omap2_mcspi_cs { 136struct omap2_mcspi_cs {
@@ -765,8 +766,15 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
765 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 766 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
766 * REVISIT: this controller could support SPI_3WIRE mode. 767 * REVISIT: this controller could support SPI_3WIRE mode.
767 */ 768 */
768 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); 769 if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) {
769 l |= OMAP2_MCSPI_CHCONF_DPE0; 770 l &= ~OMAP2_MCSPI_CHCONF_IS;
771 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
772 l |= OMAP2_MCSPI_CHCONF_DPE0;
773 } else {
774 l |= OMAP2_MCSPI_CHCONF_IS;
775 l |= OMAP2_MCSPI_CHCONF_DPE1;
776 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
777 }
770 778
771 /* wordlength */ 779 /* wordlength */
772 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 780 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
@@ -1167,6 +1175,11 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1167 master->cleanup = omap2_mcspi_cleanup; 1175 master->cleanup = omap2_mcspi_cleanup;
1168 master->dev.of_node = node; 1176 master->dev.of_node = node;
1169 1177
1178 dev_set_drvdata(&pdev->dev, master);
1179
1180 mcspi = spi_master_get_devdata(master);
1181 mcspi->master = master;
1182
1170 match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1183 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1171 if (match) { 1184 if (match) {
1172 u32 num_cs = 1; /* default number of chipselect */ 1185 u32 num_cs = 1; /* default number of chipselect */
@@ -1175,19 +1188,17 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1175 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1188 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1176 master->num_chipselect = num_cs; 1189 master->num_chipselect = num_cs;
1177 master->bus_num = bus_num++; 1190 master->bus_num = bus_num++;
1191 if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL))
1192 mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
1178 } else { 1193 } else {
1179 pdata = pdev->dev.platform_data; 1194 pdata = pdev->dev.platform_data;
1180 master->num_chipselect = pdata->num_cs; 1195 master->num_chipselect = pdata->num_cs;
1181 if (pdev->id != -1) 1196 if (pdev->id != -1)
1182 master->bus_num = pdev->id; 1197 master->bus_num = pdev->id;
1198 mcspi->pin_dir = pdata->pin_dir;
1183 } 1199 }
1184 regs_offset = pdata->regs_offset; 1200 regs_offset = pdata->regs_offset;
1185 1201
1186 dev_set_drvdata(&pdev->dev, master);
1187
1188 mcspi = spi_master_get_devdata(master);
1189 mcspi->master = master;
1190
1191 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1202 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1192 if (r == NULL) { 1203 if (r == NULL) {
1193 status = -ENODEV; 1204 status = -ENODEV;