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authorIngo Molnar <mingo@elte.hu>2008-11-26 02:22:50 -0500
committerIngo Molnar <mingo@elte.hu>2008-11-26 02:22:50 -0500
commit7fbb8759eff9a348efa5f352ffaa51c364837c4b (patch)
treed40cd3f47b9f667ba94d9613270132080dcb6a1a /drivers/spi/pxa2xx_spi.c
parent6003ab0bad4cc56f3c4fadf62a0d23a967b9c53b (diff)
parent13d428afc007fcfcd6deeb215618f54cf9c0cae6 (diff)
Merge commit 'v2.6.28-rc6' into core/debug
Diffstat (limited to 'drivers/spi/pxa2xx_spi.c')
-rw-r--r--drivers/spi/pxa2xx_spi.c194
1 files changed, 134 insertions, 60 deletions
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index 34c7c9875681..cf12f2d84be2 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -47,9 +47,14 @@ MODULE_ALIAS("platform:pxa2xx-spi");
47 47
48#define MAX_BUSES 3 48#define MAX_BUSES 3
49 49
50#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) 50#define RX_THRESH_DFLT 8
51#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) 51#define TX_THRESH_DFLT 8
52#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) 52#define TIMOUT_DFLT 1000
53
54#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
55#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
56#define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
57#define MAX_DMA_LEN 8191
53 58
54/* 59/*
55 * for testing SSCR1 changes that require SSP restart, basically 60 * for testing SSCR1 changes that require SSP restart, basically
@@ -144,7 +149,6 @@ struct driver_data {
144 size_t tx_map_len; 149 size_t tx_map_len;
145 u8 n_bytes; 150 u8 n_bytes;
146 u32 dma_width; 151 u32 dma_width;
147 int cs_change;
148 int (*write)(struct driver_data *drv_data); 152 int (*write)(struct driver_data *drv_data);
149 int (*read)(struct driver_data *drv_data); 153 int (*read)(struct driver_data *drv_data);
150 irqreturn_t (*transfer_handler)(struct driver_data *drv_data); 154 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
@@ -348,21 +352,21 @@ static int map_dma_buffers(struct driver_data *drv_data)
348 } else 352 } else
349 drv_data->tx_map_len = drv_data->len; 353 drv_data->tx_map_len = drv_data->len;
350 354
351 /* Stream map the rx buffer */ 355 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
352 drv_data->rx_dma = dma_map_single(dev, drv_data->rx, 356 * so we flush the cache *before* invalidating it, in case
353 drv_data->rx_map_len, 357 * the tx and rx buffers overlap.
354 DMA_FROM_DEVICE); 358 */
355 if (dma_mapping_error(dev, drv_data->rx_dma))
356 return 0;
357
358 /* Stream map the tx buffer */
359 drv_data->tx_dma = dma_map_single(dev, drv_data->tx, 359 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
360 drv_data->tx_map_len, 360 drv_data->tx_map_len, DMA_TO_DEVICE);
361 DMA_TO_DEVICE); 361 if (dma_mapping_error(dev, drv_data->tx_dma))
362 return 0;
362 363
363 if (dma_mapping_error(dev, drv_data->tx_dma)) { 364 /* Stream map the rx buffer */
364 dma_unmap_single(dev, drv_data->rx_dma, 365 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
365 drv_data->rx_map_len, DMA_FROM_DEVICE); 366 drv_data->rx_map_len, DMA_FROM_DEVICE);
367 if (dma_mapping_error(dev, drv_data->rx_dma)) {
368 dma_unmap_single(dev, drv_data->tx_dma,
369 drv_data->tx_map_len, DMA_TO_DEVICE);
366 return 0; 370 return 0;
367 } 371 }
368 372
@@ -406,8 +410,45 @@ static void giveback(struct driver_data *drv_data)
406 struct spi_transfer, 410 struct spi_transfer,
407 transfer_list); 411 transfer_list);
408 412
413 /* Delay if requested before any change in chip select */
414 if (last_transfer->delay_usecs)
415 udelay(last_transfer->delay_usecs);
416
417 /* Drop chip select UNLESS cs_change is true or we are returning
418 * a message with an error, or next message is for another chip
419 */
409 if (!last_transfer->cs_change) 420 if (!last_transfer->cs_change)
410 drv_data->cs_control(PXA2XX_CS_DEASSERT); 421 drv_data->cs_control(PXA2XX_CS_DEASSERT);
422 else {
423 struct spi_message *next_msg;
424
425 /* Holding of cs was hinted, but we need to make sure
426 * the next message is for the same chip. Don't waste
427 * time with the following tests unless this was hinted.
428 *
429 * We cannot postpone this until pump_messages, because
430 * after calling msg->complete (below) the driver that
431 * sent the current message could be unloaded, which
432 * could invalidate the cs_control() callback...
433 */
434
435 /* get a pointer to the next message, if any */
436 spin_lock_irqsave(&drv_data->lock, flags);
437 if (list_empty(&drv_data->queue))
438 next_msg = NULL;
439 else
440 next_msg = list_entry(drv_data->queue.next,
441 struct spi_message, queue);
442 spin_unlock_irqrestore(&drv_data->lock, flags);
443
444 /* see if the next and current messages point
445 * to the same chip
446 */
447 if (next_msg && next_msg->spi != msg->spi)
448 next_msg = NULL;
449 if (!next_msg || msg->state == ERROR_STATE)
450 drv_data->cs_control(PXA2XX_CS_DEASSERT);
451 }
411 452
412 msg->state = NULL; 453 msg->state = NULL;
413 if (msg->complete) 454 if (msg->complete)
@@ -490,10 +531,9 @@ static void dma_transfer_complete(struct driver_data *drv_data)
490 msg->actual_length += drv_data->len - 531 msg->actual_length += drv_data->len -
491 (drv_data->rx_end - drv_data->rx); 532 (drv_data->rx_end - drv_data->rx);
492 533
493 /* Release chip select if requested, transfer delays are 534 /* Transfer delays and chip select release are
494 * handled in pump_transfers */ 535 * handled in pump_transfers or giveback
495 if (drv_data->cs_change) 536 */
496 drv_data->cs_control(PXA2XX_CS_DEASSERT);
497 537
498 /* Move to next transfer */ 538 /* Move to next transfer */
499 msg->state = next_transfer(drv_data); 539 msg->state = next_transfer(drv_data);
@@ -602,10 +642,9 @@ static void int_transfer_complete(struct driver_data *drv_data)
602 drv_data->cur_msg->actual_length += drv_data->len - 642 drv_data->cur_msg->actual_length += drv_data->len -
603 (drv_data->rx_end - drv_data->rx); 643 (drv_data->rx_end - drv_data->rx);
604 644
605 /* Release chip select if requested, transfer delays are 645 /* Transfer delays and chip select release are
606 * handled in pump_transfers */ 646 * handled in pump_transfers or giveback
607 if (drv_data->cs_change) 647 */
608 drv_data->cs_control(PXA2XX_CS_DEASSERT);
609 648
610 /* Move to next transfer */ 649 /* Move to next transfer */
611 drv_data->cur_msg->state = next_transfer(drv_data); 650 drv_data->cur_msg->state = next_transfer(drv_data);
@@ -840,23 +879,40 @@ static void pump_transfers(unsigned long data)
840 return; 879 return;
841 } 880 }
842 881
843 /* Delay if requested at end of transfer*/ 882 /* Delay if requested at end of transfer before CS change */
844 if (message->state == RUNNING_STATE) { 883 if (message->state == RUNNING_STATE) {
845 previous = list_entry(transfer->transfer_list.prev, 884 previous = list_entry(transfer->transfer_list.prev,
846 struct spi_transfer, 885 struct spi_transfer,
847 transfer_list); 886 transfer_list);
848 if (previous->delay_usecs) 887 if (previous->delay_usecs)
849 udelay(previous->delay_usecs); 888 udelay(previous->delay_usecs);
889
890 /* Drop chip select only if cs_change is requested */
891 if (previous->cs_change)
892 drv_data->cs_control(PXA2XX_CS_DEASSERT);
850 } 893 }
851 894
852 /* Check transfer length */ 895 /* Check for transfers that need multiple DMA segments */
853 if (transfer->len > 8191) 896 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
854 { 897
855 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer " 898 /* reject already-mapped transfers; PIO won't always work */
856 "length greater than 8191\n"); 899 if (message->is_dma_mapped
857 message->status = -EINVAL; 900 || transfer->rx_dma || transfer->tx_dma) {
858 giveback(drv_data); 901 dev_err(&drv_data->pdev->dev,
859 return; 902 "pump_transfers: mapped transfer length "
903 "of %u is greater than %d\n",
904 transfer->len, MAX_DMA_LEN);
905 message->status = -EINVAL;
906 giveback(drv_data);
907 return;
908 }
909
910 /* warn ... we force this to PIO mode */
911 if (printk_ratelimit())
912 dev_warn(&message->spi->dev, "pump_transfers: "
913 "DMA disabled for transfer length %ld "
914 "greater than %d\n",
915 (long)drv_data->len, MAX_DMA_LEN);
860 } 916 }
861 917
862 /* Setup the transfer state based on the type of transfer */ 918 /* Setup the transfer state based on the type of transfer */
@@ -878,7 +934,6 @@ static void pump_transfers(unsigned long data)
878 drv_data->len = transfer->len & DCMD_LENGTH; 934 drv_data->len = transfer->len & DCMD_LENGTH;
879 drv_data->write = drv_data->tx ? chip->write : null_writer; 935 drv_data->write = drv_data->tx ? chip->write : null_writer;
880 drv_data->read = drv_data->rx ? chip->read : null_reader; 936 drv_data->read = drv_data->rx ? chip->read : null_reader;
881 drv_data->cs_change = transfer->cs_change;
882 937
883 /* Change speed and bit per word on a per transfer */ 938 /* Change speed and bit per word on a per transfer */
884 cr0 = chip->cr0; 939 cr0 = chip->cr0;
@@ -925,7 +980,7 @@ static void pump_transfers(unsigned long data)
925 &dma_thresh)) 980 &dma_thresh))
926 if (printk_ratelimit()) 981 if (printk_ratelimit())
927 dev_warn(&message->spi->dev, 982 dev_warn(&message->spi->dev,
928 "pump_transfer: " 983 "pump_transfers: "
929 "DMA burst size reduced to " 984 "DMA burst size reduced to "
930 "match bits_per_word\n"); 985 "match bits_per_word\n");
931 } 986 }
@@ -939,8 +994,23 @@ static void pump_transfers(unsigned long data)
939 994
940 message->state = RUNNING_STATE; 995 message->state = RUNNING_STATE;
941 996
942 /* Try to map dma buffer and do a dma transfer if successful */ 997 /* Try to map dma buffer and do a dma transfer if successful, but
943 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) { 998 * only if the length is non-zero and less than MAX_DMA_LEN.
999 *
1000 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1001 * of PIO instead. Care is needed above because the transfer may
1002 * have have been passed with buffers that are already dma mapped.
1003 * A zero-length transfer in PIO mode will not try to write/read
1004 * to/from the buffers
1005 *
1006 * REVISIT large transfers are exactly where we most want to be
1007 * using DMA. If this happens much, split those transfers into
1008 * multiple DMA segments rather than forcing PIO.
1009 */
1010 drv_data->dma_mapped = 0;
1011 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1012 drv_data->dma_mapped = map_dma_buffers(drv_data);
1013 if (drv_data->dma_mapped) {
944 1014
945 /* Ensure we have the correct interrupt handler */ 1015 /* Ensure we have the correct interrupt handler */
946 drv_data->transfer_handler = dma_transfer; 1016 drv_data->transfer_handler = dma_transfer;
@@ -1105,6 +1175,8 @@ static int setup(struct spi_device *spi)
1105 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1175 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1106 struct ssp_device *ssp = drv_data->ssp; 1176 struct ssp_device *ssp = drv_data->ssp;
1107 unsigned int clk_div; 1177 unsigned int clk_div;
1178 uint tx_thres = TX_THRESH_DFLT;
1179 uint rx_thres = RX_THRESH_DFLT;
1108 1180
1109 if (!spi->bits_per_word) 1181 if (!spi->bits_per_word)
1110 spi->bits_per_word = 8; 1182 spi->bits_per_word = 8;
@@ -1143,8 +1215,7 @@ static int setup(struct spi_device *spi)
1143 1215
1144 chip->cs_control = null_cs_control; 1216 chip->cs_control = null_cs_control;
1145 chip->enable_dma = 0; 1217 chip->enable_dma = 0;
1146 chip->timeout = 1000; 1218 chip->timeout = TIMOUT_DFLT;
1147 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1148 chip->dma_burst_size = drv_data->master_info->enable_dma ? 1219 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1149 DCMD_BURST8 : 0; 1220 DCMD_BURST8 : 0;
1150 } 1221 }
@@ -1158,22 +1229,21 @@ static int setup(struct spi_device *spi)
1158 if (chip_info) { 1229 if (chip_info) {
1159 if (chip_info->cs_control) 1230 if (chip_info->cs_control)
1160 chip->cs_control = chip_info->cs_control; 1231 chip->cs_control = chip_info->cs_control;
1161 1232 if (chip_info->timeout)
1162 chip->timeout = chip_info->timeout; 1233 chip->timeout = chip_info->timeout;
1163 1234 if (chip_info->tx_threshold)
1164 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) & 1235 tx_thres = chip_info->tx_threshold;
1165 SSCR1_RFT) | 1236 if (chip_info->rx_threshold)
1166 (SSCR1_TxTresh(chip_info->tx_threshold) & 1237 rx_thres = chip_info->rx_threshold;
1167 SSCR1_TFT); 1238 chip->enable_dma = drv_data->master_info->enable_dma;
1168
1169 chip->enable_dma = chip_info->dma_burst_size != 0
1170 && drv_data->master_info->enable_dma;
1171 chip->dma_threshold = 0; 1239 chip->dma_threshold = 0;
1172
1173 if (chip_info->enable_loopback) 1240 if (chip_info->enable_loopback)
1174 chip->cr1 = SSCR1_LBM; 1241 chip->cr1 = SSCR1_LBM;
1175 } 1242 }
1176 1243
1244 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1245 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1246
1177 /* set dma burst and threshold outside of chip_info path so that if 1247 /* set dma burst and threshold outside of chip_info path so that if
1178 * chip_info goes away after setting chip->enable_dma, the 1248 * chip_info goes away after setting chip->enable_dma, the
1179 * burst and threshold can still respond to changes in bits_per_word */ 1249 * burst and threshold can still respond to changes in bits_per_word */
@@ -1202,17 +1272,19 @@ static int setup(struct spi_device *spi)
1202 1272
1203 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1273 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1204 if (drv_data->ssp_type != PXA25x_SSP) 1274 if (drv_data->ssp_type != PXA25x_SSP)
1205 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", 1275 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n",
1206 spi->bits_per_word, 1276 spi->bits_per_word,
1207 clk_get_rate(ssp->clk) 1277 clk_get_rate(ssp->clk)
1208 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), 1278 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1209 spi->mode & 0x3); 1279 spi->mode & 0x3,
1280 chip->enable_dma ? "DMA" : "PIO");
1210 else 1281 else
1211 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", 1282 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n",
1212 spi->bits_per_word, 1283 spi->bits_per_word,
1213 clk_get_rate(ssp->clk) 1284 clk_get_rate(ssp->clk) / 2
1214 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), 1285 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1215 spi->mode & 0x3); 1286 spi->mode & 0x3,
1287 chip->enable_dma ? "DMA" : "PIO");
1216 1288
1217 if (spi->bits_per_word <= 8) { 1289 if (spi->bits_per_word <= 8) {
1218 chip->n_bytes = 1; 1290 chip->n_bytes = 1;
@@ -1341,9 +1413,9 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1341 struct device *dev = &pdev->dev; 1413 struct device *dev = &pdev->dev;
1342 struct pxa2xx_spi_master *platform_info; 1414 struct pxa2xx_spi_master *platform_info;
1343 struct spi_master *master; 1415 struct spi_master *master;
1344 struct driver_data *drv_data = NULL; 1416 struct driver_data *drv_data;
1345 struct ssp_device *ssp; 1417 struct ssp_device *ssp;
1346 int status = 0; 1418 int status;
1347 1419
1348 platform_info = dev->platform_data; 1420 platform_info = dev->platform_data;
1349 1421
@@ -1356,7 +1428,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1356 /* Allocate master with space for drv_data and null dma buffer */ 1428 /* Allocate master with space for drv_data and null dma buffer */
1357 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1429 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1358 if (!master) { 1430 if (!master) {
1359 dev_err(&pdev->dev, "can not alloc spi_master\n"); 1431 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1360 ssp_free(ssp); 1432 ssp_free(ssp);
1361 return -ENOMEM; 1433 return -ENOMEM;
1362 } 1434 }
@@ -1392,7 +1464,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1392 1464
1393 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data); 1465 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
1394 if (status < 0) { 1466 if (status < 0) {
1395 dev_err(&pdev->dev, "can not get IRQ\n"); 1467 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1396 goto out_error_master_alloc; 1468 goto out_error_master_alloc;
1397 } 1469 }
1398 1470
@@ -1432,7 +1504,9 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1432 1504
1433 /* Load default SSP configuration */ 1505 /* Load default SSP configuration */
1434 write_SSCR0(0, drv_data->ioaddr); 1506 write_SSCR0(0, drv_data->ioaddr);
1435 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr); 1507 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1508 SSCR1_TxTresh(TX_THRESH_DFLT),
1509 drv_data->ioaddr);
1436 write_SSCR0(SSCR0_SerClkDiv(2) 1510 write_SSCR0(SSCR0_SerClkDiv(2)
1437 | SSCR0_Motorola 1511 | SSCR0_Motorola
1438 | SSCR0_DataSize(8), 1512 | SSCR0_DataSize(8),