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authorFelipe Balbi <felipe.balbi@nokia.com>2010-09-29 04:31:29 -0400
committerGrant Likely <grant.likely@secretlab.ca>2010-09-29 04:31:29 -0400
commit079a176d87a4da4cb18864c54d3932131e11e229 (patch)
tree8e4b0c96174840ab831994d424783ddd55661988 /drivers/spi/omap2_mcspi.c
parent899611ee7d373e5eeda08e9a8632684e1ebbbf00 (diff)
spi: omap2_mcspi: make use of dev_vdbg()
dev_vdbg() is only compiled when VERBOSE is defined, so there's no need to wrap dev_dbg() on #ifdef VERBOSE .. #endif as we can use dev_vdbg() directly. Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi/omap2_mcspi.c')
-rw-r--r--drivers/spi/omap2_mcspi.c36
1 files changed, 9 insertions, 27 deletions
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index b3a94ca0a75a..d70392795055 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -489,10 +489,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
489 dev_err(&spi->dev, "TXS timed out\n"); 489 dev_err(&spi->dev, "TXS timed out\n");
490 goto out; 490 goto out;
491 } 491 }
492#ifdef VERBOSE 492 dev_vdbg(&spi->dev, "write-%d %02x\n",
493 dev_dbg(&spi->dev, "write-%d %02x\n",
494 word_len, *tx); 493 word_len, *tx);
495#endif
496 __raw_writel(*tx++, tx_reg); 494 __raw_writel(*tx++, tx_reg);
497 } 495 }
498 if (rx != NULL) { 496 if (rx != NULL) {
@@ -506,10 +504,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
506 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 504 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
507 omap2_mcspi_set_enable(spi, 0); 505 omap2_mcspi_set_enable(spi, 0);
508 *rx++ = __raw_readl(rx_reg); 506 *rx++ = __raw_readl(rx_reg);
509#ifdef VERBOSE 507 dev_vdbg(&spi->dev, "read-%d %02x\n",
510 dev_dbg(&spi->dev, "read-%d %02x\n",
511 word_len, *(rx - 1)); 508 word_len, *(rx - 1));
512#endif
513 if (mcspi_wait_for_reg_bit(chstat_reg, 509 if (mcspi_wait_for_reg_bit(chstat_reg,
514 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 510 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
515 dev_err(&spi->dev, 511 dev_err(&spi->dev,
@@ -522,10 +518,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
522 } 518 }
523 519
524 *rx++ = __raw_readl(rx_reg); 520 *rx++ = __raw_readl(rx_reg);
525#ifdef VERBOSE 521 dev_vdbg(&spi->dev, "read-%d %02x\n",
526 dev_dbg(&spi->dev, "read-%d %02x\n",
527 word_len, *(rx - 1)); 522 word_len, *(rx - 1));
528#endif
529 } 523 }
530 } while (c); 524 } while (c);
531 } else if (word_len <= 16) { 525 } else if (word_len <= 16) {
@@ -542,10 +536,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
542 dev_err(&spi->dev, "TXS timed out\n"); 536 dev_err(&spi->dev, "TXS timed out\n");
543 goto out; 537 goto out;
544 } 538 }
545#ifdef VERBOSE 539 dev_vdbg(&spi->dev, "write-%d %04x\n",
546 dev_dbg(&spi->dev, "write-%d %04x\n",
547 word_len, *tx); 540 word_len, *tx);
548#endif
549 __raw_writel(*tx++, tx_reg); 541 __raw_writel(*tx++, tx_reg);
550 } 542 }
551 if (rx != NULL) { 543 if (rx != NULL) {
@@ -559,10 +551,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
559 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 551 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
560 omap2_mcspi_set_enable(spi, 0); 552 omap2_mcspi_set_enable(spi, 0);
561 *rx++ = __raw_readl(rx_reg); 553 *rx++ = __raw_readl(rx_reg);
562#ifdef VERBOSE 554 dev_vdbg(&spi->dev, "read-%d %04x\n",
563 dev_dbg(&spi->dev, "read-%d %04x\n",
564 word_len, *(rx - 1)); 555 word_len, *(rx - 1));
565#endif
566 if (mcspi_wait_for_reg_bit(chstat_reg, 556 if (mcspi_wait_for_reg_bit(chstat_reg,
567 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 557 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
568 dev_err(&spi->dev, 558 dev_err(&spi->dev,
@@ -575,10 +565,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
575 } 565 }
576 566
577 *rx++ = __raw_readl(rx_reg); 567 *rx++ = __raw_readl(rx_reg);
578#ifdef VERBOSE 568 dev_vdbg(&spi->dev, "read-%d %04x\n",
579 dev_dbg(&spi->dev, "read-%d %04x\n",
580 word_len, *(rx - 1)); 569 word_len, *(rx - 1));
581#endif
582 } 570 }
583 } while (c); 571 } while (c);
584 } else if (word_len <= 32) { 572 } else if (word_len <= 32) {
@@ -595,10 +583,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
595 dev_err(&spi->dev, "TXS timed out\n"); 583 dev_err(&spi->dev, "TXS timed out\n");
596 goto out; 584 goto out;
597 } 585 }
598#ifdef VERBOSE 586 dev_vdbg(&spi->dev, "write-%d %08x\n",
599 dev_dbg(&spi->dev, "write-%d %08x\n",
600 word_len, *tx); 587 word_len, *tx);
601#endif
602 __raw_writel(*tx++, tx_reg); 588 __raw_writel(*tx++, tx_reg);
603 } 589 }
604 if (rx != NULL) { 590 if (rx != NULL) {
@@ -612,10 +598,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
612 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 598 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
613 omap2_mcspi_set_enable(spi, 0); 599 omap2_mcspi_set_enable(spi, 0);
614 *rx++ = __raw_readl(rx_reg); 600 *rx++ = __raw_readl(rx_reg);
615#ifdef VERBOSE 601 dev_vdbg(&spi->dev, "read-%d %08x\n",
616 dev_dbg(&spi->dev, "read-%d %08x\n",
617 word_len, *(rx - 1)); 602 word_len, *(rx - 1));
618#endif
619 if (mcspi_wait_for_reg_bit(chstat_reg, 603 if (mcspi_wait_for_reg_bit(chstat_reg,
620 OMAP2_MCSPI_CHSTAT_RXS) < 0) { 604 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
621 dev_err(&spi->dev, 605 dev_err(&spi->dev,
@@ -628,10 +612,8 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
628 } 612 }
629 613
630 *rx++ = __raw_readl(rx_reg); 614 *rx++ = __raw_readl(rx_reg);
631#ifdef VERBOSE 615 dev_vdbg(&spi->dev, "read-%d %08x\n",
632 dev_dbg(&spi->dev, "read-%d %08x\n",
633 word_len, *(rx - 1)); 616 word_len, *(rx - 1));
634#endif
635 } 617 }
636 } while (c); 618 } while (c);
637 } 619 }