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authorGrant Likely <grant.likely@secretlab.ca>2008-10-08 11:02:11 -0400
committerGrant Likely <grant.likely@secretlab.ca>2008-10-08 11:02:11 -0400
commita897ea13f7a801e6baba8d4985f459042712244c (patch)
tree580ce1aee753c3e1e7963e252beaf10ac8d87df6 /drivers/spi/mpc52xx_psc_spi.c
parent7c12d906f4ef690c65e60111375856640f63a545 (diff)
powerpc/mpc5200: fix build warnings on mpc52xx_psc_spi driver
The register definitions have been changed for the mpc5200 PSC ports to cover some of the changes in the mpc5200b. One change is that the ccr register is now a u32 instead of a u16. However, for the purposes of this driver we want to continue to use 16 bit access to avoid changing the existing (working) behaviour. This patch allows the driver to continue to do 16 bit accesses without the compiler complaining about it. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi/mpc52xx_psc_spi.c')
-rw-r--r--drivers/spi/mpc52xx_psc_spi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
index 25eda71f4bf4..cdb3d3191719 100644
--- a/drivers/spi/mpc52xx_psc_spi.c
+++ b/drivers/spi/mpc52xx_psc_spi.c
@@ -108,13 +108,13 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
108 * Because psc->ccr is defined as 16bit register instead of 32bit 108 * Because psc->ccr is defined as 16bit register instead of 32bit
109 * just set the lower byte of BitClkDiv 109 * just set the lower byte of BitClkDiv
110 */ 110 */
111 ccr = in_be16(&psc->ccr); 111 ccr = in_be16((u16 __iomem *)&psc->ccr);
112 ccr &= 0xFF00; 112 ccr &= 0xFF00;
113 if (cs->speed_hz) 113 if (cs->speed_hz)
114 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; 114 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
115 else /* by default SPI Clk 1MHz */ 115 else /* by default SPI Clk 1MHz */
116 ccr |= (MCLK / 1000000 - 1) & 0xFF; 116 ccr |= (MCLK / 1000000 - 1) & 0xFF;
117 out_be16(&psc->ccr, ccr); 117 out_be16((u16 __iomem *)&psc->ccr, ccr);
118 mps->bits_per_word = cs->bits_per_word; 118 mps->bits_per_word = cs->bits_per_word;
119 119
120 if (mps->activate_cs) 120 if (mps->activate_cs)
@@ -347,7 +347,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
347 /* Configure 8bit codec mode as a SPI master and use EOF flags */ 347 /* Configure 8bit codec mode as a SPI master and use EOF flags */
348 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ 348 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
349 out_be32(&psc->sicr, 0x0180C800); 349 out_be32(&psc->sicr, 0x0180C800);
350 out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */ 350 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
351 351
352 /* Set 2ms DTL delay */ 352 /* Set 2ms DTL delay */
353 out_8(&psc->ctur, 0x00); 353 out_8(&psc->ctur, 0x00);