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authorJan Nikitenko <jan.nikitenko@gmail.com>2007-05-08 03:32:25 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-08 14:15:16 -0400
commit63bd23591e6c3891d34e4c6dba7c6aa41b05caad (patch)
tree7251bee620c2ad802148502305496d5b63090c19 /drivers/spi/au1550_spi.c
parent33e34dc6ee2cb2cf2d50e65c5b825d9ebb8b9e66 (diff)
au1550 SPI controller driver
Here is a driver for the Alchemy au1550 PSC (Programmable Serial Controller) in SPI master mode. It supports dma transfers using the Alchemy descriptor based dma controller for 4-8 bits per word SPI transfers. For 9-24 bits per word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550; this may also work on other MIPS Alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI; this handles 8.1MHz SPI clock transfers using dma without any problem (the highest SPI clock freq possible with au1550 running on 324MHz). The driver supports sharing of SPI bus by multiple devices. All features of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per word in 4-24 range). As the SPI clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 SPI controller driver contains mainclk_hz attribute to define the input clock rate. From this value, dividers of the controller for SPI clock are set up for required frequency. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Whitespace and section fixups. Remove partial workaround for platform setup bug in dma_mask setup; it couldn't work with multiple controllers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/spi/au1550_spi.c')
-rw-r--r--drivers/spi/au1550_spi.c974
1 files changed, 974 insertions, 0 deletions
diff --git a/drivers/spi/au1550_spi.c b/drivers/spi/au1550_spi.c
new file mode 100644
index 000000000000..ae2b1af0dba4
--- /dev/null
+++ b/drivers/spi/au1550_spi.c
@@ -0,0 +1,974 @@
1/*
2 * au1550_spi.c - au1550 psc spi controller driver
3 * may work also with au1200, au1210, au1250
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
5 *
6 * Copyright (c) 2006 ATRON electronic GmbH
7 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/errno.h>
27#include <linux/device.h>
28#include <linux/platform_device.h>
29#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h>
31#include <linux/dma-mapping.h>
32#include <linux/completion.h>
33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-au1x00/au1xxx_psc.h>
35#include <asm/mach-au1x00/au1xxx_dbdma.h>
36
37#include <asm/mach-au1x00/au1550_spi.h>
38
39static unsigned usedma = 1;
40module_param(usedma, uint, 0644);
41
42/*
43#define AU1550_SPI_DEBUG_LOOPBACK
44*/
45
46
47#define AU1550_SPI_DBDMA_DESCRIPTORS 1
48#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
49
50struct au1550_spi {
51 struct spi_bitbang bitbang;
52
53 volatile psc_spi_t __iomem *regs;
54 int irq;
55 unsigned freq_max;
56 unsigned freq_min;
57
58 unsigned len;
59 unsigned tx_count;
60 unsigned rx_count;
61 const u8 *tx;
62 u8 *rx;
63
64 void (*rx_word)(struct au1550_spi *hw);
65 void (*tx_word)(struct au1550_spi *hw);
66 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
67 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
68
69 struct completion master_done;
70
71 unsigned usedma;
72 u32 dma_tx_id;
73 u32 dma_rx_id;
74 u32 dma_tx_ch;
75 u32 dma_rx_ch;
76
77 u8 *dma_rx_tmpbuf;
78 unsigned dma_rx_tmpbuf_size;
79 u32 dma_rx_tmpbuf_addr;
80
81 struct spi_master *master;
82 struct device *dev;
83 struct au1550_spi_info *pdata;
84};
85
86
87/* we use an 8-bit memory device for dma transfers to/from spi fifo */
88static dbdev_tab_t au1550_spi_mem_dbdev =
89{
90 .dev_id = DBDMA_MEM_CHAN,
91 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
92 .dev_tsize = 0,
93 .dev_devwidth = 8,
94 .dev_physaddr = 0x00000000,
95 .dev_intlevel = 0,
96 .dev_intpolarity = 0
97};
98
99static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
100
101
102/**
103 * compute BRG and DIV bits to setup spi clock based on main input clock rate
104 * that was specified in platform data structure
105 * according to au1550 datasheet:
106 * psc_tempclk = psc_mainclk / (2 << DIV)
107 * spiclk = psc_tempclk / (2 * (BRG + 1))
108 * BRG valid range is 4..63
109 * DIV valid range is 0..3
110 */
111static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
112{
113 u32 mainclk_hz = hw->pdata->mainclk_hz;
114 u32 div, brg;
115
116 for (div = 0; div < 4; div++) {
117 brg = mainclk_hz / speed_hz / (4 << div);
118 /* now we have BRG+1 in brg, so count with that */
119 if (brg < (4 + 1)) {
120 brg = (4 + 1); /* speed_hz too big */
121 break; /* set lowest brg (div is == 0) */
122 }
123 if (brg <= (63 + 1))
124 break; /* we have valid brg and div */
125 }
126 if (div == 4) {
127 div = 3; /* speed_hz too small */
128 brg = (63 + 1); /* set highest brg and div */
129 }
130 brg--;
131 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
132}
133
134static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
135{
136 hw->regs->psc_spimsk =
137 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
138 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
139 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
140 au_sync();
141
142 hw->regs->psc_spievent =
143 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
144 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
145 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
146 au_sync();
147}
148
149static void au1550_spi_reset_fifos(struct au1550_spi *hw)
150{
151 u32 pcr;
152
153 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
154 au_sync();
155 do {
156 pcr = hw->regs->psc_spipcr;
157 au_sync();
158 } while (pcr != 0);
159}
160
161/*
162 * dma transfers are used for the most common spi word size of 8-bits
163 * we cannot easily change already set up dma channels' width, so if we wanted
164 * dma support for more than 8-bit words (up to 24 bits), we would need to
165 * setup dma channels from scratch on each spi transfer, based on bits_per_word
166 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
167 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
168 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
169 */
170static void au1550_spi_chipsel(struct spi_device *spi, int value)
171{
172 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
173 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
174 u32 cfg, stat;
175
176 switch (value) {
177 case BITBANG_CS_INACTIVE:
178 if (hw->pdata->deactivate_cs)
179 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
180 cspol);
181 break;
182
183 case BITBANG_CS_ACTIVE:
184 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
185
186 cfg = hw->regs->psc_spicfg;
187 au_sync();
188 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
189 au_sync();
190
191 if (spi->mode & SPI_CPOL)
192 cfg |= PSC_SPICFG_BI;
193 else
194 cfg &= ~PSC_SPICFG_BI;
195 if (spi->mode & SPI_CPHA)
196 cfg &= ~PSC_SPICFG_CDE;
197 else
198 cfg |= PSC_SPICFG_CDE;
199
200 if (spi->mode & SPI_LSB_FIRST)
201 cfg |= PSC_SPICFG_MLF;
202 else
203 cfg &= ~PSC_SPICFG_MLF;
204
205 if (hw->usedma && spi->bits_per_word <= 8)
206 cfg &= ~PSC_SPICFG_DD_DISABLE;
207 else
208 cfg |= PSC_SPICFG_DD_DISABLE;
209 cfg = PSC_SPICFG_CLR_LEN(cfg);
210 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
211
212 cfg = PSC_SPICFG_CLR_BAUD(cfg);
213 cfg &= ~PSC_SPICFG_SET_DIV(3);
214 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
215
216 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
217 au_sync();
218 do {
219 stat = hw->regs->psc_spistat;
220 au_sync();
221 } while ((stat & PSC_SPISTAT_DR) == 0);
222
223 if (hw->pdata->activate_cs)
224 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
225 cspol);
226 break;
227 }
228}
229
230static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
231{
232 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
233 unsigned bpw, hz;
234 u32 cfg, stat;
235
236 bpw = t ? t->bits_per_word : spi->bits_per_word;
237 hz = t ? t->speed_hz : spi->max_speed_hz;
238
239 if (bpw < 4 || bpw > 24) {
240 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
241 bpw);
242 return -EINVAL;
243 }
244 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
245 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
246 hz);
247 return -EINVAL;
248 }
249
250 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
251
252 cfg = hw->regs->psc_spicfg;
253 au_sync();
254 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
255 au_sync();
256
257 if (hw->usedma && bpw <= 8)
258 cfg &= ~PSC_SPICFG_DD_DISABLE;
259 else
260 cfg |= PSC_SPICFG_DD_DISABLE;
261 cfg = PSC_SPICFG_CLR_LEN(cfg);
262 cfg |= PSC_SPICFG_SET_LEN(bpw);
263
264 cfg = PSC_SPICFG_CLR_BAUD(cfg);
265 cfg &= ~PSC_SPICFG_SET_DIV(3);
266 cfg |= au1550_spi_baudcfg(hw, hz);
267
268 hw->regs->psc_spicfg = cfg;
269 au_sync();
270
271 if (cfg & PSC_SPICFG_DE_ENABLE) {
272 do {
273 stat = hw->regs->psc_spistat;
274 au_sync();
275 } while ((stat & PSC_SPISTAT_DR) == 0);
276 }
277
278 au1550_spi_reset_fifos(hw);
279 au1550_spi_mask_ack_all(hw);
280 return 0;
281}
282
283static int au1550_spi_setup(struct spi_device *spi)
284{
285 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
286
287 if (spi->bits_per_word == 0)
288 spi->bits_per_word = 8;
289 if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
290 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
291 spi->bits_per_word);
292 return -EINVAL;
293 }
294
295 if (spi->max_speed_hz == 0)
296 spi->max_speed_hz = hw->freq_max;
297 if (spi->max_speed_hz > hw->freq_max
298 || spi->max_speed_hz < hw->freq_min)
299 return -EINVAL;
300 /*
301 * NOTE: cannot change speed and other hw settings immediately,
302 * otherwise sharing of spi bus is not possible,
303 * so do not call setupxfer(spi, NULL) here
304 */
305 return 0;
306}
307
308/*
309 * for dma spi transfers, we have to setup rx channel, otherwise there is
310 * no reliable way how to recognize that spi transfer is done
311 * dma complete callbacks are called before real spi transfer is finished
312 * and if only tx dma channel is set up (and rx fifo overflow event masked)
313 * spi master done event irq is not generated unless rx fifo is empty (emptied)
314 * so we need rx tmp buffer to use for rx dma if user does not provide one
315 */
316static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
317{
318 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
319 if (!hw->dma_rx_tmpbuf)
320 return -ENOMEM;
321 hw->dma_rx_tmpbuf_size = size;
322 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
323 size, DMA_FROM_DEVICE);
324 if (dma_mapping_error(hw->dma_rx_tmpbuf_addr)) {
325 kfree(hw->dma_rx_tmpbuf);
326 hw->dma_rx_tmpbuf = 0;
327 hw->dma_rx_tmpbuf_size = 0;
328 return -EFAULT;
329 }
330 return 0;
331}
332
333static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
334{
335 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
336 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
337 kfree(hw->dma_rx_tmpbuf);
338 hw->dma_rx_tmpbuf = 0;
339 hw->dma_rx_tmpbuf_size = 0;
340}
341
342static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
343{
344 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
345 dma_addr_t dma_tx_addr;
346 dma_addr_t dma_rx_addr;
347 u32 res;
348
349 hw->len = t->len;
350 hw->tx_count = 0;
351 hw->rx_count = 0;
352
353 hw->tx = t->tx_buf;
354 hw->rx = t->rx_buf;
355 dma_tx_addr = t->tx_dma;
356 dma_rx_addr = t->rx_dma;
357
358 /*
359 * check if buffers are already dma mapped, map them otherwise
360 * use rx buffer in place of tx if tx buffer was not provided
361 * use temp rx buffer (preallocated or realloc to fit) for rx dma
362 */
363 if (t->rx_buf) {
364 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
365 dma_rx_addr = dma_map_single(hw->dev,
366 (void *)t->rx_buf,
367 t->len, DMA_FROM_DEVICE);
368 if (dma_mapping_error(dma_rx_addr))
369 dev_err(hw->dev, "rx dma map error\n");
370 }
371 } else {
372 if (t->len > hw->dma_rx_tmpbuf_size) {
373 int ret;
374
375 au1550_spi_dma_rxtmp_free(hw);
376 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
377 AU1550_SPI_DMA_RXTMP_MINSIZE));
378 if (ret < 0)
379 return ret;
380 }
381 hw->rx = hw->dma_rx_tmpbuf;
382 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
383 dma_sync_single_for_device(hw->dev, dma_rx_addr,
384 t->len, DMA_FROM_DEVICE);
385 }
386 if (t->tx_buf) {
387 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
388 dma_tx_addr = dma_map_single(hw->dev,
389 (void *)t->tx_buf,
390 t->len, DMA_TO_DEVICE);
391 if (dma_mapping_error(dma_tx_addr))
392 dev_err(hw->dev, "tx dma map error\n");
393 }
394 } else {
395 dma_sync_single_for_device(hw->dev, dma_rx_addr,
396 t->len, DMA_BIDIRECTIONAL);
397 hw->tx = hw->rx;
398 }
399
400 /* put buffers on the ring */
401 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
402 if (!res)
403 dev_err(hw->dev, "rx dma put dest error\n");
404
405 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
406 if (!res)
407 dev_err(hw->dev, "tx dma put source error\n");
408
409 au1xxx_dbdma_start(hw->dma_rx_ch);
410 au1xxx_dbdma_start(hw->dma_tx_ch);
411
412 /* by default enable nearly all events interrupt */
413 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
414 au_sync();
415
416 /* start the transfer */
417 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
418 au_sync();
419
420 wait_for_completion(&hw->master_done);
421
422 au1xxx_dbdma_stop(hw->dma_tx_ch);
423 au1xxx_dbdma_stop(hw->dma_rx_ch);
424
425 if (!t->rx_buf) {
426 /* using the temporal preallocated and premapped buffer */
427 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
428 DMA_FROM_DEVICE);
429 }
430 /* unmap buffers if mapped above */
431 if (t->rx_buf && t->rx_dma == 0 )
432 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
433 DMA_FROM_DEVICE);
434 if (t->tx_buf && t->tx_dma == 0 )
435 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
436 DMA_TO_DEVICE);
437
438 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
439}
440
441static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
442{
443 u32 stat, evnt;
444
445 stat = hw->regs->psc_spistat;
446 evnt = hw->regs->psc_spievent;
447 au_sync();
448 if ((stat & PSC_SPISTAT_DI) == 0) {
449 dev_err(hw->dev, "Unexpected IRQ!\n");
450 return IRQ_NONE;
451 }
452
453 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
454 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
455 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
456 != 0) {
457 /*
458 * due to an spi error we consider transfer as done,
459 * so mask all events until before next transfer start
460 * and stop the possibly running dma immediatelly
461 */
462 au1550_spi_mask_ack_all(hw);
463 au1xxx_dbdma_stop(hw->dma_rx_ch);
464 au1xxx_dbdma_stop(hw->dma_tx_ch);
465
466 /* get number of transfered bytes */
467 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
468 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
469
470 au1xxx_dbdma_reset(hw->dma_rx_ch);
471 au1xxx_dbdma_reset(hw->dma_tx_ch);
472 au1550_spi_reset_fifos(hw);
473
474 dev_err(hw->dev,
475 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
476 evnt, stat);
477
478 complete(&hw->master_done);
479 return IRQ_HANDLED;
480 }
481
482 if ((evnt & PSC_SPIEVNT_MD) != 0) {
483 /* transfer completed successfully */
484 au1550_spi_mask_ack_all(hw);
485 hw->rx_count = hw->len;
486 hw->tx_count = hw->len;
487 complete(&hw->master_done);
488 }
489 return IRQ_HANDLED;
490}
491
492
493/* routines to handle different word sizes in pio mode */
494#define AU1550_SPI_RX_WORD(size, mask) \
495static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
496{ \
497 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
498 au_sync(); \
499 if (hw->rx) { \
500 *(u##size *)hw->rx = (u##size)fifoword; \
501 hw->rx += (size) / 8; \
502 } \
503 hw->rx_count += (size) / 8; \
504}
505
506#define AU1550_SPI_TX_WORD(size, mask) \
507static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
508{ \
509 u32 fifoword = 0; \
510 if (hw->tx) { \
511 fifoword = *(u##size *)hw->tx & (u32)(mask); \
512 hw->tx += (size) / 8; \
513 } \
514 hw->tx_count += (size) / 8; \
515 if (hw->tx_count >= hw->len) \
516 fifoword |= PSC_SPITXRX_LC; \
517 hw->regs->psc_spitxrx = fifoword; \
518 au_sync(); \
519}
520
521AU1550_SPI_RX_WORD(8,0xff)
522AU1550_SPI_RX_WORD(16,0xffff)
523AU1550_SPI_RX_WORD(32,0xffffff)
524AU1550_SPI_TX_WORD(8,0xff)
525AU1550_SPI_TX_WORD(16,0xffff)
526AU1550_SPI_TX_WORD(32,0xffffff)
527
528static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
529{
530 u32 stat, mask;
531 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
532
533 hw->tx = t->tx_buf;
534 hw->rx = t->rx_buf;
535 hw->len = t->len;
536 hw->tx_count = 0;
537 hw->rx_count = 0;
538
539 /* by default enable nearly all events after filling tx fifo */
540 mask = PSC_SPIMSK_SD;
541
542 /* fill the transmit FIFO */
543 while (hw->tx_count < hw->len) {
544
545 hw->tx_word(hw);
546
547 if (hw->tx_count >= hw->len) {
548 /* mask tx fifo request interrupt as we are done */
549 mask |= PSC_SPIMSK_TR;
550 }
551
552 stat = hw->regs->psc_spistat;
553 au_sync();
554 if (stat & PSC_SPISTAT_TF)
555 break;
556 }
557
558 /* enable event interrupts */
559 hw->regs->psc_spimsk = mask;
560 au_sync();
561
562 /* start the transfer */
563 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
564 au_sync();
565
566 wait_for_completion(&hw->master_done);
567
568 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
569}
570
571static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
572{
573 int busy;
574 u32 stat, evnt;
575
576 stat = hw->regs->psc_spistat;
577 evnt = hw->regs->psc_spievent;
578 au_sync();
579 if ((stat & PSC_SPISTAT_DI) == 0) {
580 dev_err(hw->dev, "Unexpected IRQ!\n");
581 return IRQ_NONE;
582 }
583
584 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
585 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
586 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
587 != 0) {
588 dev_err(hw->dev,
589 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
590 evnt, stat);
591 /*
592 * due to an error we consider transfer as done,
593 * so mask all events until before next transfer start
594 */
595 au1550_spi_mask_ack_all(hw);
596 au1550_spi_reset_fifos(hw);
597 complete(&hw->master_done);
598 return IRQ_HANDLED;
599 }
600
601 /*
602 * while there is something to read from rx fifo
603 * or there is a space to write to tx fifo:
604 */
605 do {
606 busy = 0;
607 stat = hw->regs->psc_spistat;
608 au_sync();
609
610 if ((stat & PSC_SPISTAT_RE) == 0 && hw->rx_count < hw->len) {
611 hw->rx_word(hw);
612 /* ack the receive request event */
613 hw->regs->psc_spievent = PSC_SPIEVNT_RR;
614 au_sync();
615 busy = 1;
616 }
617
618 if ((stat & PSC_SPISTAT_TF) == 0 && hw->tx_count < hw->len) {
619 hw->tx_word(hw);
620 /* ack the transmit request event */
621 hw->regs->psc_spievent = PSC_SPIEVNT_TR;
622 au_sync();
623 busy = 1;
624 }
625 } while (busy);
626
627 evnt = hw->regs->psc_spievent;
628 au_sync();
629
630 if (hw->rx_count >= hw->len || (evnt & PSC_SPIEVNT_MD) != 0) {
631 /* transfer completed successfully */
632 au1550_spi_mask_ack_all(hw);
633 complete(&hw->master_done);
634 }
635 return IRQ_HANDLED;
636}
637
638static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
639{
640 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
641 return hw->txrx_bufs(spi, t);
642}
643
644static irqreturn_t au1550_spi_irq(int irq, void *dev, struct pt_regs *regs)
645{
646 struct au1550_spi *hw = dev;
647 return hw->irq_callback(hw);
648}
649
650static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
651{
652 if (bpw <= 8) {
653 if (hw->usedma) {
654 hw->txrx_bufs = &au1550_spi_dma_txrxb;
655 hw->irq_callback = &au1550_spi_dma_irq_callback;
656 } else {
657 hw->rx_word = &au1550_spi_rx_word_8;
658 hw->tx_word = &au1550_spi_tx_word_8;
659 hw->txrx_bufs = &au1550_spi_pio_txrxb;
660 hw->irq_callback = &au1550_spi_pio_irq_callback;
661 }
662 } else if (bpw <= 16) {
663 hw->rx_word = &au1550_spi_rx_word_16;
664 hw->tx_word = &au1550_spi_tx_word_16;
665 hw->txrx_bufs = &au1550_spi_pio_txrxb;
666 hw->irq_callback = &au1550_spi_pio_irq_callback;
667 } else {
668 hw->rx_word = &au1550_spi_rx_word_32;
669 hw->tx_word = &au1550_spi_tx_word_32;
670 hw->txrx_bufs = &au1550_spi_pio_txrxb;
671 hw->irq_callback = &au1550_spi_pio_irq_callback;
672 }
673}
674
675static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
676{
677 u32 stat, cfg;
678
679 /* set up the PSC for SPI mode */
680 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
681 au_sync();
682 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
683 au_sync();
684
685 hw->regs->psc_spicfg = 0;
686 au_sync();
687
688 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
689 au_sync();
690
691 do {
692 stat = hw->regs->psc_spistat;
693 au_sync();
694 } while ((stat & PSC_SPISTAT_SR) == 0);
695
696
697 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
698 cfg |= PSC_SPICFG_SET_LEN(8);
699 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
700 /* use minimal allowed brg and div values as initial setting: */
701 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
702
703#ifdef AU1550_SPI_DEBUG_LOOPBACK
704 cfg |= PSC_SPICFG_LB;
705#endif
706
707 hw->regs->psc_spicfg = cfg;
708 au_sync();
709
710 au1550_spi_mask_ack_all(hw);
711
712 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
713 au_sync();
714
715 do {
716 stat = hw->regs->psc_spistat;
717 au_sync();
718 } while ((stat & PSC_SPISTAT_DR) == 0);
719}
720
721
722static int __init au1550_spi_probe(struct platform_device *pdev)
723{
724 struct au1550_spi *hw;
725 struct spi_master *master;
726 int err = 0;
727
728 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
729 if (master == NULL) {
730 dev_err(&pdev->dev, "No memory for spi_master\n");
731 err = -ENOMEM;
732 goto err_nomem;
733 }
734
735 hw = spi_master_get_devdata(master);
736
737 hw->master = spi_master_get(master);
738 hw->pdata = pdev->dev.platform_data;
739 hw->dev = &pdev->dev;
740
741 if (hw->pdata == NULL) {
742 dev_err(&pdev->dev, "No platform data supplied\n");
743 err = -ENOENT;
744 goto err_no_pdata;
745 }
746
747 platform_set_drvdata(pdev, hw);
748
749 init_completion(&hw->master_done);
750
751 hw->bitbang.master = hw->master;
752 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
753 hw->bitbang.chipselect = au1550_spi_chipsel;
754 hw->bitbang.master->setup = au1550_spi_setup;
755 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
756
757 switch (hw->pdata->bus_num) {
758 case 0:
759 hw->irq = AU1550_PSC0_INT;
760 hw->regs = (volatile psc_spi_t *)PSC0_BASE_ADDR;
761 hw->dma_rx_id = DSCR_CMD0_PSC0_RX;
762 hw->dma_tx_id = DSCR_CMD0_PSC0_TX;
763 break;
764 case 1:
765 hw->irq = AU1550_PSC1_INT;
766 hw->regs = (volatile psc_spi_t *)PSC1_BASE_ADDR;
767 hw->dma_rx_id = DSCR_CMD0_PSC1_RX;
768 hw->dma_tx_id = DSCR_CMD0_PSC1_TX;
769 break;
770 case 2:
771 hw->irq = AU1550_PSC2_INT;
772 hw->regs = (volatile psc_spi_t *)PSC2_BASE_ADDR;
773 hw->dma_rx_id = DSCR_CMD0_PSC2_RX;
774 hw->dma_tx_id = DSCR_CMD0_PSC2_TX;
775 break;
776 case 3:
777 hw->irq = AU1550_PSC3_INT;
778 hw->regs = (volatile psc_spi_t *)PSC3_BASE_ADDR;
779 hw->dma_rx_id = DSCR_CMD0_PSC3_RX;
780 hw->dma_tx_id = DSCR_CMD0_PSC3_TX;
781 break;
782 default:
783 dev_err(&pdev->dev, "Wrong bus_num of SPI\n");
784 err = -ENOENT;
785 goto err_no_pdata;
786 }
787
788 if (request_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t),
789 pdev->name) == NULL) {
790 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
791 err = -ENXIO;
792 goto err_no_iores;
793 }
794
795
796 if (usedma) {
797 if (pdev->dev.dma_mask == NULL)
798 dev_warn(&pdev->dev, "no dma mask\n");
799 else
800 hw->usedma = 1;
801 }
802
803 if (hw->usedma) {
804 /*
805 * create memory device with 8 bits dev_devwidth
806 * needed for proper byte ordering to spi fifo
807 */
808 int memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
809 if (!memid) {
810 dev_err(&pdev->dev,
811 "Cannot create dma 8 bit mem device\n");
812 err = -ENXIO;
813 goto err_dma_add_dev;
814 }
815
816 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(memid,
817 hw->dma_tx_id, NULL, (void *)hw);
818 if (hw->dma_tx_ch == 0) {
819 dev_err(&pdev->dev,
820 "Cannot allocate tx dma channel\n");
821 err = -ENXIO;
822 goto err_no_txdma;
823 }
824 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
825 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
826 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
827 dev_err(&pdev->dev,
828 "Cannot allocate tx dma descriptors\n");
829 err = -ENXIO;
830 goto err_no_txdma_descr;
831 }
832
833
834 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
835 memid, NULL, (void *)hw);
836 if (hw->dma_rx_ch == 0) {
837 dev_err(&pdev->dev,
838 "Cannot allocate rx dma channel\n");
839 err = -ENXIO;
840 goto err_no_rxdma;
841 }
842 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
843 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
844 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
845 dev_err(&pdev->dev,
846 "Cannot allocate rx dma descriptors\n");
847 err = -ENXIO;
848 goto err_no_rxdma_descr;
849 }
850
851 err = au1550_spi_dma_rxtmp_alloc(hw,
852 AU1550_SPI_DMA_RXTMP_MINSIZE);
853 if (err < 0) {
854 dev_err(&pdev->dev,
855 "Cannot allocate initial rx dma tmp buffer\n");
856 goto err_dma_rxtmp_alloc;
857 }
858 }
859
860 au1550_spi_bits_handlers_set(hw, 8);
861
862 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
863 if (err) {
864 dev_err(&pdev->dev, "Cannot claim IRQ\n");
865 goto err_no_irq;
866 }
867
868 master->bus_num = hw->pdata->bus_num;
869 master->num_chipselect = hw->pdata->num_chipselect;
870
871 /*
872 * precompute valid range for spi freq - from au1550 datasheet:
873 * psc_tempclk = psc_mainclk / (2 << DIV)
874 * spiclk = psc_tempclk / (2 * (BRG + 1))
875 * BRG valid range is 4..63
876 * DIV valid range is 0..3
877 * round the min and max frequencies to values that would still
878 * produce valid brg and div
879 */
880 {
881 int min_div = (2 << 0) * (2 * (4 + 1));
882 int max_div = (2 << 3) * (2 * (63 + 1));
883 hw->freq_max = hw->pdata->mainclk_hz / min_div;
884 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
885 }
886
887 au1550_spi_setup_psc_as_spi(hw);
888
889 err = spi_bitbang_start(&hw->bitbang);
890 if (err) {
891 dev_err(&pdev->dev, "Failed to register SPI master\n");
892 goto err_register;
893 }
894
895 dev_info(&pdev->dev,
896 "spi master registered: bus_num=%d num_chipselect=%d\n",
897 master->bus_num, master->num_chipselect);
898
899 return 0;
900
901err_register:
902 free_irq(hw->irq, hw);
903
904err_no_irq:
905 au1550_spi_dma_rxtmp_free(hw);
906
907err_dma_rxtmp_alloc:
908err_no_rxdma_descr:
909 if (hw->usedma)
910 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
911
912err_no_rxdma:
913err_no_txdma_descr:
914 if (hw->usedma)
915 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
916
917err_no_txdma:
918err_dma_add_dev:
919 release_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t));
920
921err_no_iores:
922err_no_pdata:
923 spi_master_put(hw->master);
924
925err_nomem:
926 return err;
927}
928
929static int __exit au1550_spi_remove(struct platform_device *pdev)
930{
931 struct au1550_spi *hw = platform_get_drvdata(pdev);
932
933 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
934 hw->master->bus_num);
935
936 spi_bitbang_stop(&hw->bitbang);
937 free_irq(hw->irq, hw);
938 release_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t));
939
940 if (hw->usedma) {
941 au1550_spi_dma_rxtmp_free(hw);
942 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
943 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
944 }
945
946 platform_set_drvdata(pdev, NULL);
947
948 spi_master_put(hw->master);
949 return 0;
950}
951
952static struct platform_driver au1550_spi_drv = {
953 .remove = __exit_p(au1550_spi_remove),
954 .driver = {
955 .name = "au1550-spi",
956 .owner = THIS_MODULE,
957 },
958};
959
960static int __init au1550_spi_init(void)
961{
962 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
963}
964module_init(au1550_spi_init);
965
966static void __exit au1550_spi_exit(void)
967{
968 platform_driver_unregister(&au1550_spi_drv);
969}
970module_exit(au1550_spi_exit);
971
972MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
973MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
974MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 19:56:04 -0500