[PATCH] spi: add spi_bitbang driver

This adds a bitbanging spi master, hooking up to board/adapter-specific glue
code which knows how to set and read the signals (gpios etc).

This code kicks in after the glue code creates a platform_device with the
right platform_data.  That data includes I/O loops, which will usually
come from expanding an inline function (provided in the header).  One goal
is that the I/O loops should be easily optimized down to a few GPIO register
accesses, in common cases, for speed and minimized overhead.

This understands all the currently defined protocol tweaking options in the
SPI framework, and might eventually serve as as reference implementation.

  - different word sizes (1..32 bits)
  - differing clock rates
  - SPI modes differing by CPOL (affecting chip select and I/O loops)
  - SPI modes differing by CPHA (affecting I/O loops)
  - delays (usecs) after transfers
  - temporarily deselecting chips in mid-transfer

A lot of hardware could work with this framework, though common types of
controller can't reach peak performance without switching to a driver
structure that supports pipelining of transfers (e.g.  DMA queues) and maybe
controllers (e.g.  IRQ driven).

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d3105104a297..9b21c5d77b4a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -51,6 +51,19 @@ config SPI_MASTER
 comment "SPI Master Controller Drivers"
         depends on SPI_MASTER
 
+config SPI_BITBANG
+        tristate "Bitbanging SPI master"
+        depends on SPI_MASTER && EXPERIMENTAL
+        help
+          With a few GPIO pins, your system can bitbang the SPI protocol.
+          Select this to get SPI support through I/O pins (GPIO, parallel
+          port, etc).  Or, some systems' SPI master controller drivers use
+          this code to manage the per-word or per-transfer accesses to the
+          hardware shift registers.
+
+          This is library code, and is automatically selected by drivers that
+          need it.  You only need to select this explicitly to support driver
+          modules that aren't part of this kernel tree.
 
 #
 # Add new SPI master controllers in alphabetical order above this line