diff options
author | Magnus Damm <damm@opensource.se> | 2012-02-29 08:16:21 -0500 |
---|---|---|
committer | Rafael J. Wysocki <rjw@sisk.pl> | 2012-03-12 17:19:07 -0400 |
commit | a0ec360f6b83146fa4ba1a681bdd751382f9f90e (patch) | |
tree | bf947a9164af84fd588aed4dd74e3b9d983281c9 /drivers/sh | |
parent | e34828298ec542294f4b798606ee73e462d322f5 (diff) |
sh: convert cpg code to sh_clk_ops
Convert the CPG code to use sh_clk_ops.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/clk/cpg.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 92d314a73f69..91b6d52f74eb 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c | |||
@@ -26,7 +26,7 @@ static void sh_clk_mstp32_disable(struct clk *clk) | |||
26 | clk->mapped_reg); | 26 | clk->mapped_reg); |
27 | } | 27 | } |
28 | 28 | ||
29 | static struct clk_ops sh_clk_mstp32_clk_ops = { | 29 | static struct sh_clk_ops sh_clk_mstp32_clk_ops = { |
30 | .enable = sh_clk_mstp32_enable, | 30 | .enable = sh_clk_mstp32_enable, |
31 | .disable = sh_clk_mstp32_disable, | 31 | .disable = sh_clk_mstp32_disable, |
32 | .recalc = followparent_recalc, | 32 | .recalc = followparent_recalc, |
@@ -150,7 +150,7 @@ static void sh_clk_div6_disable(struct clk *clk) | |||
150 | iowrite32(value, clk->mapped_reg); | 150 | iowrite32(value, clk->mapped_reg); |
151 | } | 151 | } |
152 | 152 | ||
153 | static struct clk_ops sh_clk_div6_clk_ops = { | 153 | static struct sh_clk_ops sh_clk_div6_clk_ops = { |
154 | .recalc = sh_clk_div6_recalc, | 154 | .recalc = sh_clk_div6_recalc, |
155 | .round_rate = sh_clk_div_round_rate, | 155 | .round_rate = sh_clk_div_round_rate, |
156 | .set_rate = sh_clk_div6_set_rate, | 156 | .set_rate = sh_clk_div6_set_rate, |
@@ -158,7 +158,7 @@ static struct clk_ops sh_clk_div6_clk_ops = { | |||
158 | .disable = sh_clk_div6_disable, | 158 | .disable = sh_clk_div6_disable, |
159 | }; | 159 | }; |
160 | 160 | ||
161 | static struct clk_ops sh_clk_div6_reparent_clk_ops = { | 161 | static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { |
162 | .recalc = sh_clk_div6_recalc, | 162 | .recalc = sh_clk_div6_recalc, |
163 | .round_rate = sh_clk_div_round_rate, | 163 | .round_rate = sh_clk_div_round_rate, |
164 | .set_rate = sh_clk_div6_set_rate, | 164 | .set_rate = sh_clk_div6_set_rate, |
@@ -200,7 +200,7 @@ static int __init sh_clk_init_parent(struct clk *clk) | |||
200 | } | 200 | } |
201 | 201 | ||
202 | static int __init sh_clk_div6_register_ops(struct clk *clks, int nr, | 202 | static int __init sh_clk_div6_register_ops(struct clk *clks, int nr, |
203 | struct clk_ops *ops) | 203 | struct sh_clk_ops *ops) |
204 | { | 204 | { |
205 | struct clk *clkp; | 205 | struct clk *clkp; |
206 | void *freq_table; | 206 | void *freq_table; |
@@ -317,13 +317,13 @@ static void sh_clk_div4_disable(struct clk *clk) | |||
317 | iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg); | 317 | iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg); |
318 | } | 318 | } |
319 | 319 | ||
320 | static struct clk_ops sh_clk_div4_clk_ops = { | 320 | static struct sh_clk_ops sh_clk_div4_clk_ops = { |
321 | .recalc = sh_clk_div4_recalc, | 321 | .recalc = sh_clk_div4_recalc, |
322 | .set_rate = sh_clk_div4_set_rate, | 322 | .set_rate = sh_clk_div4_set_rate, |
323 | .round_rate = sh_clk_div_round_rate, | 323 | .round_rate = sh_clk_div_round_rate, |
324 | }; | 324 | }; |
325 | 325 | ||
326 | static struct clk_ops sh_clk_div4_enable_clk_ops = { | 326 | static struct sh_clk_ops sh_clk_div4_enable_clk_ops = { |
327 | .recalc = sh_clk_div4_recalc, | 327 | .recalc = sh_clk_div4_recalc, |
328 | .set_rate = sh_clk_div4_set_rate, | 328 | .set_rate = sh_clk_div4_set_rate, |
329 | .round_rate = sh_clk_div_round_rate, | 329 | .round_rate = sh_clk_div_round_rate, |
@@ -331,7 +331,7 @@ static struct clk_ops sh_clk_div4_enable_clk_ops = { | |||
331 | .disable = sh_clk_div4_disable, | 331 | .disable = sh_clk_div4_disable, |
332 | }; | 332 | }; |
333 | 333 | ||
334 | static struct clk_ops sh_clk_div4_reparent_clk_ops = { | 334 | static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { |
335 | .recalc = sh_clk_div4_recalc, | 335 | .recalc = sh_clk_div4_recalc, |
336 | .set_rate = sh_clk_div4_set_rate, | 336 | .set_rate = sh_clk_div4_set_rate, |
337 | .round_rate = sh_clk_div_round_rate, | 337 | .round_rate = sh_clk_div_round_rate, |
@@ -341,7 +341,7 @@ static struct clk_ops sh_clk_div4_reparent_clk_ops = { | |||
341 | }; | 341 | }; |
342 | 342 | ||
343 | static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, | 343 | static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, |
344 | struct clk_div4_table *table, struct clk_ops *ops) | 344 | struct clk_div4_table *table, struct sh_clk_ops *ops) |
345 | { | 345 | { |
346 | struct clk *clkp; | 346 | struct clk *clkp; |
347 | void *freq_table; | 347 | void *freq_table; |