diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-03-08 15:21:04 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-03-08 15:21:04 -0500 |
commit | 988addf82e4c03739375279de73929580a2d4a6a (patch) | |
tree | 989ae1cd4e264bbad80c65f04480486246e7b9f3 /drivers/sh | |
parent | 004c1c7096659d352b83047a7593e91d8a30e3c5 (diff) | |
parent | 25cf84cf377c0aae5dbcf937ea89bc7893db5176 (diff) |
Merge branch 'origin' into devel-stable
Conflicts:
arch/arm/mach-mx2/devices.c
arch/arm/mach-mx2/devices.h
sound/soc/pxa/pxa-ssp.c
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/intc.c | 266 | ||||
-rw-r--r-- | drivers/sh/pfc.c | 37 |
2 files changed, 226 insertions, 77 deletions
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index 926013bece12..c2750391fd34 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c | |||
@@ -259,6 +259,43 @@ static void intc_disable(unsigned int irq) | |||
259 | } | 259 | } |
260 | } | 260 | } |
261 | 261 | ||
262 | static void (*intc_enable_noprio_fns[])(unsigned long addr, | ||
263 | unsigned long handle, | ||
264 | void (*fn)(unsigned long, | ||
265 | unsigned long, | ||
266 | unsigned long), | ||
267 | unsigned int irq) = { | ||
268 | [MODE_ENABLE_REG] = intc_mode_field, | ||
269 | [MODE_MASK_REG] = intc_mode_zero, | ||
270 | [MODE_DUAL_REG] = intc_mode_field, | ||
271 | [MODE_PRIO_REG] = intc_mode_field, | ||
272 | [MODE_PCLR_REG] = intc_mode_field, | ||
273 | }; | ||
274 | |||
275 | static void intc_enable_disable(struct intc_desc_int *d, | ||
276 | unsigned long handle, int do_enable) | ||
277 | { | ||
278 | unsigned long addr; | ||
279 | unsigned int cpu; | ||
280 | void (*fn)(unsigned long, unsigned long, | ||
281 | void (*)(unsigned long, unsigned long, unsigned long), | ||
282 | unsigned int); | ||
283 | |||
284 | if (do_enable) { | ||
285 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { | ||
286 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | ||
287 | fn = intc_enable_noprio_fns[_INTC_MODE(handle)]; | ||
288 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | ||
289 | } | ||
290 | } else { | ||
291 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { | ||
292 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | ||
293 | fn = intc_disable_fns[_INTC_MODE(handle)]; | ||
294 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | ||
295 | } | ||
296 | } | ||
297 | } | ||
298 | |||
262 | static int intc_set_wake(unsigned int irq, unsigned int on) | 299 | static int intc_set_wake(unsigned int irq, unsigned int on) |
263 | { | 300 | { |
264 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ | 301 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ |
@@ -400,11 +437,11 @@ static unsigned int __init intc_get_reg(struct intc_desc_int *d, | |||
400 | static intc_enum __init intc_grp_id(struct intc_desc *desc, | 437 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
401 | intc_enum enum_id) | 438 | intc_enum enum_id) |
402 | { | 439 | { |
403 | struct intc_group *g = desc->groups; | 440 | struct intc_group *g = desc->hw.groups; |
404 | unsigned int i, j; | 441 | unsigned int i, j; |
405 | 442 | ||
406 | for (i = 0; g && enum_id && i < desc->nr_groups; i++) { | 443 | for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) { |
407 | g = desc->groups + i; | 444 | g = desc->hw.groups + i; |
408 | 445 | ||
409 | for (j = 0; g->enum_ids[j]; j++) { | 446 | for (j = 0; g->enum_ids[j]; j++) { |
410 | if (g->enum_ids[j] != enum_id) | 447 | if (g->enum_ids[j] != enum_id) |
@@ -417,19 +454,21 @@ static intc_enum __init intc_grp_id(struct intc_desc *desc, | |||
417 | return 0; | 454 | return 0; |
418 | } | 455 | } |
419 | 456 | ||
420 | static unsigned int __init intc_mask_data(struct intc_desc *desc, | 457 | static unsigned int __init _intc_mask_data(struct intc_desc *desc, |
421 | struct intc_desc_int *d, | 458 | struct intc_desc_int *d, |
422 | intc_enum enum_id, int do_grps) | 459 | intc_enum enum_id, |
460 | unsigned int *reg_idx, | ||
461 | unsigned int *fld_idx) | ||
423 | { | 462 | { |
424 | struct intc_mask_reg *mr = desc->mask_regs; | 463 | struct intc_mask_reg *mr = desc->hw.mask_regs; |
425 | unsigned int i, j, fn, mode; | 464 | unsigned int fn, mode; |
426 | unsigned long reg_e, reg_d; | 465 | unsigned long reg_e, reg_d; |
427 | 466 | ||
428 | for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { | 467 | while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { |
429 | mr = desc->mask_regs + i; | 468 | mr = desc->hw.mask_regs + *reg_idx; |
430 | 469 | ||
431 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | 470 | for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) { |
432 | if (mr->enum_ids[j] != enum_id) | 471 | if (mr->enum_ids[*fld_idx] != enum_id) |
433 | continue; | 472 | continue; |
434 | 473 | ||
435 | if (mr->set_reg && mr->clr_reg) { | 474 | if (mr->set_reg && mr->clr_reg) { |
@@ -455,29 +494,49 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc, | |||
455 | intc_get_reg(d, reg_e), | 494 | intc_get_reg(d, reg_e), |
456 | intc_get_reg(d, reg_d), | 495 | intc_get_reg(d, reg_d), |
457 | 1, | 496 | 1, |
458 | (mr->reg_width - 1) - j); | 497 | (mr->reg_width - 1) - *fld_idx); |
459 | } | 498 | } |
499 | |||
500 | *fld_idx = 0; | ||
501 | (*reg_idx)++; | ||
460 | } | 502 | } |
461 | 503 | ||
504 | return 0; | ||
505 | } | ||
506 | |||
507 | static unsigned int __init intc_mask_data(struct intc_desc *desc, | ||
508 | struct intc_desc_int *d, | ||
509 | intc_enum enum_id, int do_grps) | ||
510 | { | ||
511 | unsigned int i = 0; | ||
512 | unsigned int j = 0; | ||
513 | unsigned int ret; | ||
514 | |||
515 | ret = _intc_mask_data(desc, d, enum_id, &i, &j); | ||
516 | if (ret) | ||
517 | return ret; | ||
518 | |||
462 | if (do_grps) | 519 | if (do_grps) |
463 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); | 520 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
464 | 521 | ||
465 | return 0; | 522 | return 0; |
466 | } | 523 | } |
467 | 524 | ||
468 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | 525 | static unsigned int __init _intc_prio_data(struct intc_desc *desc, |
469 | struct intc_desc_int *d, | 526 | struct intc_desc_int *d, |
470 | intc_enum enum_id, int do_grps) | 527 | intc_enum enum_id, |
528 | unsigned int *reg_idx, | ||
529 | unsigned int *fld_idx) | ||
471 | { | 530 | { |
472 | struct intc_prio_reg *pr = desc->prio_regs; | 531 | struct intc_prio_reg *pr = desc->hw.prio_regs; |
473 | unsigned int i, j, fn, mode, bit; | 532 | unsigned int fn, n, mode, bit; |
474 | unsigned long reg_e, reg_d; | 533 | unsigned long reg_e, reg_d; |
475 | 534 | ||
476 | for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { | 535 | while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { |
477 | pr = desc->prio_regs + i; | 536 | pr = desc->hw.prio_regs + *reg_idx; |
478 | 537 | ||
479 | for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { | 538 | for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) { |
480 | if (pr->enum_ids[j] != enum_id) | 539 | if (pr->enum_ids[*fld_idx] != enum_id) |
481 | continue; | 540 | continue; |
482 | 541 | ||
483 | if (pr->set_reg && pr->clr_reg) { | 542 | if (pr->set_reg && pr->clr_reg) { |
@@ -495,34 +554,79 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc, | |||
495 | } | 554 | } |
496 | 555 | ||
497 | fn += (pr->reg_width >> 3) - 1; | 556 | fn += (pr->reg_width >> 3) - 1; |
557 | n = *fld_idx + 1; | ||
498 | 558 | ||
499 | BUG_ON((j + 1) * pr->field_width > pr->reg_width); | 559 | BUG_ON(n * pr->field_width > pr->reg_width); |
500 | 560 | ||
501 | bit = pr->reg_width - ((j + 1) * pr->field_width); | 561 | bit = pr->reg_width - (n * pr->field_width); |
502 | 562 | ||
503 | return _INTC_MK(fn, mode, | 563 | return _INTC_MK(fn, mode, |
504 | intc_get_reg(d, reg_e), | 564 | intc_get_reg(d, reg_e), |
505 | intc_get_reg(d, reg_d), | 565 | intc_get_reg(d, reg_d), |
506 | pr->field_width, bit); | 566 | pr->field_width, bit); |
507 | } | 567 | } |
568 | |||
569 | *fld_idx = 0; | ||
570 | (*reg_idx)++; | ||
508 | } | 571 | } |
509 | 572 | ||
573 | return 0; | ||
574 | } | ||
575 | |||
576 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | ||
577 | struct intc_desc_int *d, | ||
578 | intc_enum enum_id, int do_grps) | ||
579 | { | ||
580 | unsigned int i = 0; | ||
581 | unsigned int j = 0; | ||
582 | unsigned int ret; | ||
583 | |||
584 | ret = _intc_prio_data(desc, d, enum_id, &i, &j); | ||
585 | if (ret) | ||
586 | return ret; | ||
587 | |||
510 | if (do_grps) | 588 | if (do_grps) |
511 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); | 589 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
512 | 590 | ||
513 | return 0; | 591 | return 0; |
514 | } | 592 | } |
515 | 593 | ||
594 | static void __init intc_enable_disable_enum(struct intc_desc *desc, | ||
595 | struct intc_desc_int *d, | ||
596 | intc_enum enum_id, int enable) | ||
597 | { | ||
598 | unsigned int i, j, data; | ||
599 | |||
600 | /* go through and enable/disable all mask bits */ | ||
601 | i = j = 0; | ||
602 | do { | ||
603 | data = _intc_mask_data(desc, d, enum_id, &i, &j); | ||
604 | if (data) | ||
605 | intc_enable_disable(d, data, enable); | ||
606 | j++; | ||
607 | } while (data); | ||
608 | |||
609 | /* go through and enable/disable all priority fields */ | ||
610 | i = j = 0; | ||
611 | do { | ||
612 | data = _intc_prio_data(desc, d, enum_id, &i, &j); | ||
613 | if (data) | ||
614 | intc_enable_disable(d, data, enable); | ||
615 | |||
616 | j++; | ||
617 | } while (data); | ||
618 | } | ||
619 | |||
516 | static unsigned int __init intc_ack_data(struct intc_desc *desc, | 620 | static unsigned int __init intc_ack_data(struct intc_desc *desc, |
517 | struct intc_desc_int *d, | 621 | struct intc_desc_int *d, |
518 | intc_enum enum_id) | 622 | intc_enum enum_id) |
519 | { | 623 | { |
520 | struct intc_mask_reg *mr = desc->ack_regs; | 624 | struct intc_mask_reg *mr = desc->hw.ack_regs; |
521 | unsigned int i, j, fn, mode; | 625 | unsigned int i, j, fn, mode; |
522 | unsigned long reg_e, reg_d; | 626 | unsigned long reg_e, reg_d; |
523 | 627 | ||
524 | for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { | 628 | for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) { |
525 | mr = desc->ack_regs + i; | 629 | mr = desc->hw.ack_regs + i; |
526 | 630 | ||
527 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | 631 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { |
528 | if (mr->enum_ids[j] != enum_id) | 632 | if (mr->enum_ids[j] != enum_id) |
@@ -549,11 +653,11 @@ static unsigned int __init intc_sense_data(struct intc_desc *desc, | |||
549 | struct intc_desc_int *d, | 653 | struct intc_desc_int *d, |
550 | intc_enum enum_id) | 654 | intc_enum enum_id) |
551 | { | 655 | { |
552 | struct intc_sense_reg *sr = desc->sense_regs; | 656 | struct intc_sense_reg *sr = desc->hw.sense_regs; |
553 | unsigned int i, j, fn, bit; | 657 | unsigned int i, j, fn, bit; |
554 | 658 | ||
555 | for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) { | 659 | for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) { |
556 | sr = desc->sense_regs + i; | 660 | sr = desc->hw.sense_regs + i; |
557 | 661 | ||
558 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | 662 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { |
559 | if (sr->enum_ids[j] != enum_id) | 663 | if (sr->enum_ids[j] != enum_id) |
@@ -656,7 +760,7 @@ static void __init intc_register_irq(struct intc_desc *desc, | |||
656 | /* irq should be disabled by default */ | 760 | /* irq should be disabled by default */ |
657 | d->chip.mask(irq); | 761 | d->chip.mask(irq); |
658 | 762 | ||
659 | if (desc->ack_regs) | 763 | if (desc->hw.ack_regs) |
660 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); | 764 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); |
661 | 765 | ||
662 | #ifdef CONFIG_ARM | 766 | #ifdef CONFIG_ARM |
@@ -688,6 +792,7 @@ static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) | |||
688 | void __init register_intc_controller(struct intc_desc *desc) | 792 | void __init register_intc_controller(struct intc_desc *desc) |
689 | { | 793 | { |
690 | unsigned int i, k, smp; | 794 | unsigned int i, k, smp; |
795 | struct intc_hw_desc *hw = &desc->hw; | ||
691 | struct intc_desc_int *d; | 796 | struct intc_desc_int *d; |
692 | 797 | ||
693 | d = kzalloc(sizeof(*d), GFP_NOWAIT); | 798 | d = kzalloc(sizeof(*d), GFP_NOWAIT); |
@@ -695,10 +800,10 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
695 | INIT_LIST_HEAD(&d->list); | 800 | INIT_LIST_HEAD(&d->list); |
696 | list_add(&d->list, &intc_list); | 801 | list_add(&d->list, &intc_list); |
697 | 802 | ||
698 | d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0; | 803 | d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; |
699 | d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; | 804 | d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; |
700 | d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; | 805 | d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; |
701 | d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; | 806 | d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; |
702 | 807 | ||
703 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); | 808 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); |
704 | #ifdef CONFIG_SMP | 809 | #ifdef CONFIG_SMP |
@@ -706,30 +811,31 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
706 | #endif | 811 | #endif |
707 | k = 0; | 812 | k = 0; |
708 | 813 | ||
709 | if (desc->mask_regs) { | 814 | if (hw->mask_regs) { |
710 | for (i = 0; i < desc->nr_mask_regs; i++) { | 815 | for (i = 0; i < hw->nr_mask_regs; i++) { |
711 | smp = IS_SMP(desc->mask_regs[i]); | 816 | smp = IS_SMP(hw->mask_regs[i]); |
712 | k += save_reg(d, k, desc->mask_regs[i].set_reg, smp); | 817 | k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); |
713 | k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp); | 818 | k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); |
714 | } | 819 | } |
715 | } | 820 | } |
716 | 821 | ||
717 | if (desc->prio_regs) { | 822 | if (hw->prio_regs) { |
718 | d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT); | 823 | d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), |
824 | GFP_NOWAIT); | ||
719 | 825 | ||
720 | for (i = 0; i < desc->nr_prio_regs; i++) { | 826 | for (i = 0; i < hw->nr_prio_regs; i++) { |
721 | smp = IS_SMP(desc->prio_regs[i]); | 827 | smp = IS_SMP(hw->prio_regs[i]); |
722 | k += save_reg(d, k, desc->prio_regs[i].set_reg, smp); | 828 | k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); |
723 | k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp); | 829 | k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); |
724 | } | 830 | } |
725 | } | 831 | } |
726 | 832 | ||
727 | if (desc->sense_regs) { | 833 | if (hw->sense_regs) { |
728 | d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT); | 834 | d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), |
835 | GFP_NOWAIT); | ||
729 | 836 | ||
730 | for (i = 0; i < desc->nr_sense_regs; i++) { | 837 | for (i = 0; i < hw->nr_sense_regs; i++) |
731 | k += save_reg(d, k, desc->sense_regs[i].reg, 0); | 838 | k += save_reg(d, k, hw->sense_regs[i].reg, 0); |
732 | } | ||
733 | } | 839 | } |
734 | 840 | ||
735 | d->chip.name = desc->name; | 841 | d->chip.name = desc->name; |
@@ -742,18 +848,26 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
742 | d->chip.set_type = intc_set_sense; | 848 | d->chip.set_type = intc_set_sense; |
743 | d->chip.set_wake = intc_set_wake; | 849 | d->chip.set_wake = intc_set_wake; |
744 | 850 | ||
745 | if (desc->ack_regs) { | 851 | if (hw->ack_regs) { |
746 | for (i = 0; i < desc->nr_ack_regs; i++) | 852 | for (i = 0; i < hw->nr_ack_regs; i++) |
747 | k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); | 853 | k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); |
748 | 854 | ||
749 | d->chip.mask_ack = intc_mask_ack; | 855 | d->chip.mask_ack = intc_mask_ack; |
750 | } | 856 | } |
751 | 857 | ||
858 | /* disable bits matching force_disable before registering irqs */ | ||
859 | if (desc->force_disable) | ||
860 | intc_enable_disable_enum(desc, d, desc->force_disable, 0); | ||
861 | |||
862 | /* disable bits matching force_enable before registering irqs */ | ||
863 | if (desc->force_enable) | ||
864 | intc_enable_disable_enum(desc, d, desc->force_enable, 0); | ||
865 | |||
752 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ | 866 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ |
753 | 867 | ||
754 | /* register the vectors one by one */ | 868 | /* register the vectors one by one */ |
755 | for (i = 0; i < desc->nr_vectors; i++) { | 869 | for (i = 0; i < hw->nr_vectors; i++) { |
756 | struct intc_vect *vect = desc->vectors + i; | 870 | struct intc_vect *vect = hw->vectors + i; |
757 | unsigned int irq = evt2irq(vect->vect); | 871 | unsigned int irq = evt2irq(vect->vect); |
758 | struct irq_desc *irq_desc; | 872 | struct irq_desc *irq_desc; |
759 | 873 | ||
@@ -768,8 +882,8 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
768 | 882 | ||
769 | intc_register_irq(desc, d, vect->enum_id, irq); | 883 | intc_register_irq(desc, d, vect->enum_id, irq); |
770 | 884 | ||
771 | for (k = i + 1; k < desc->nr_vectors; k++) { | 885 | for (k = i + 1; k < hw->nr_vectors; k++) { |
772 | struct intc_vect *vect2 = desc->vectors + k; | 886 | struct intc_vect *vect2 = hw->vectors + k; |
773 | unsigned int irq2 = evt2irq(vect2->vect); | 887 | unsigned int irq2 = evt2irq(vect2->vect); |
774 | 888 | ||
775 | if (vect->enum_id != vect2->enum_id) | 889 | if (vect->enum_id != vect2->enum_id) |
@@ -789,11 +903,15 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
789 | vect2->enum_id = 0; | 903 | vect2->enum_id = 0; |
790 | 904 | ||
791 | /* redirect this interrupts to the first one */ | 905 | /* redirect this interrupts to the first one */ |
792 | set_irq_chip_and_handler_name(irq2, &d->chip, | 906 | set_irq_chip(irq2, &dummy_irq_chip); |
793 | intc_redirect_irq, "redirect"); | 907 | set_irq_chained_handler(irq2, intc_redirect_irq); |
794 | set_irq_data(irq2, (void *)irq); | 908 | set_irq_data(irq2, (void *)irq); |
795 | } | 909 | } |
796 | } | 910 | } |
911 | |||
912 | /* enable bits matching force_enable after registering irqs */ | ||
913 | if (desc->force_enable) | ||
914 | intc_enable_disable_enum(desc, d, desc->force_enable, 1); | ||
797 | } | 915 | } |
798 | 916 | ||
799 | static int intc_suspend(struct sys_device *dev, pm_message_t state) | 917 | static int intc_suspend(struct sys_device *dev, pm_message_t state) |
@@ -876,7 +994,7 @@ device_initcall(register_intc_sysdevs); | |||
876 | /* | 994 | /* |
877 | * Dynamic IRQ allocation and deallocation | 995 | * Dynamic IRQ allocation and deallocation |
878 | */ | 996 | */ |
879 | static unsigned int create_irq_on_node(unsigned int irq_want, int node) | 997 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
880 | { | 998 | { |
881 | unsigned int irq = 0, new; | 999 | unsigned int irq = 0, new; |
882 | unsigned long flags; | 1000 | unsigned long flags; |
@@ -885,24 +1003,28 @@ static unsigned int create_irq_on_node(unsigned int irq_want, int node) | |||
885 | spin_lock_irqsave(&vector_lock, flags); | 1003 | spin_lock_irqsave(&vector_lock, flags); |
886 | 1004 | ||
887 | /* | 1005 | /* |
888 | * First try the wanted IRQ, then scan. | 1006 | * First try the wanted IRQ |
889 | */ | 1007 | */ |
890 | if (test_and_set_bit(irq_want, intc_irq_map)) { | 1008 | if (test_and_set_bit(irq_want, intc_irq_map) == 0) { |
1009 | new = irq_want; | ||
1010 | } else { | ||
1011 | /* .. then fall back to scanning. */ | ||
891 | new = find_first_zero_bit(intc_irq_map, nr_irqs); | 1012 | new = find_first_zero_bit(intc_irq_map, nr_irqs); |
892 | if (unlikely(new == nr_irqs)) | 1013 | if (unlikely(new == nr_irqs)) |
893 | goto out_unlock; | 1014 | goto out_unlock; |
894 | 1015 | ||
895 | desc = irq_to_desc_alloc_node(new, node); | ||
896 | if (unlikely(!desc)) { | ||
897 | pr_info("can't get irq_desc for %d\n", new); | ||
898 | goto out_unlock; | ||
899 | } | ||
900 | |||
901 | desc = move_irq_desc(desc, node); | ||
902 | __set_bit(new, intc_irq_map); | 1016 | __set_bit(new, intc_irq_map); |
903 | irq = new; | ||
904 | } | 1017 | } |
905 | 1018 | ||
1019 | desc = irq_to_desc_alloc_node(new, node); | ||
1020 | if (unlikely(!desc)) { | ||
1021 | pr_info("can't get irq_desc for %d\n", new); | ||
1022 | goto out_unlock; | ||
1023 | } | ||
1024 | |||
1025 | desc = move_irq_desc(desc, node); | ||
1026 | irq = new; | ||
1027 | |||
906 | out_unlock: | 1028 | out_unlock: |
907 | spin_unlock_irqrestore(&vector_lock, flags); | 1029 | spin_unlock_irqrestore(&vector_lock, flags); |
908 | 1030 | ||
@@ -921,7 +1043,7 @@ int create_irq(void) | |||
921 | int nid = cpu_to_node(smp_processor_id()); | 1043 | int nid = cpu_to_node(smp_processor_id()); |
922 | int irq; | 1044 | int irq; |
923 | 1045 | ||
924 | irq = create_irq_on_node(NR_IRQS_LEGACY, nid); | 1046 | irq = create_irq_nr(NR_IRQS_LEGACY, nid); |
925 | if (irq == 0) | 1047 | if (irq == 0) |
926 | irq = -1; | 1048 | irq = -1; |
927 | 1049 | ||
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c index 082604edc4c2..cf0303acab8e 100644 --- a/drivers/sh/pfc.c +++ b/drivers/sh/pfc.c | |||
@@ -337,12 +337,39 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, | |||
337 | if (!enum_id) | 337 | if (!enum_id) |
338 | break; | 338 | break; |
339 | 339 | ||
340 | /* first check if this is a function enum */ | ||
340 | in_range = enum_in_range(enum_id, &gpioc->function); | 341 | in_range = enum_in_range(enum_id, &gpioc->function); |
341 | if (!in_range && range) { | 342 | if (!in_range) { |
342 | in_range = enum_in_range(enum_id, range); | 343 | /* not a function enum */ |
343 | 344 | if (range) { | |
344 | if (in_range && enum_id == range->force) | 345 | /* |
345 | continue; | 346 | * other range exists, so this pin is |
347 | * a regular GPIO pin that now is being | ||
348 | * bound to a specific direction. | ||
349 | * | ||
350 | * for this case we only allow function enums | ||
351 | * and the enums that match the other range. | ||
352 | */ | ||
353 | in_range = enum_in_range(enum_id, range); | ||
354 | |||
355 | /* | ||
356 | * special case pass through for fixed | ||
357 | * input-only or output-only pins without | ||
358 | * function enum register association. | ||
359 | */ | ||
360 | if (in_range && enum_id == range->force) | ||
361 | continue; | ||
362 | } else { | ||
363 | /* | ||
364 | * no other range exists, so this pin | ||
365 | * must then be of the function type. | ||
366 | * | ||
367 | * allow function type pins to select | ||
368 | * any combination of function/in/out | ||
369 | * in their MARK lists. | ||
370 | */ | ||
371 | in_range = 1; | ||
372 | } | ||
346 | } | 373 | } |
347 | 374 | ||
348 | if (!in_range) | 375 | if (!in_range) |