diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-11-19 02:43:23 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-11-19 02:43:23 -0500 |
commit | dfcd6e438927ad8c54278e5b1a34a4fe76e57ad2 (patch) | |
tree | abbf7999568e51141ccc8297bc095d095e1f6f75 /drivers/sh | |
parent | d53e4307c2f3856167407a1d9b8f8fa001286066 (diff) | |
parent | f278ea849e15147269190e943937fa82e66078b1 (diff) |
Merge branch 'common/clkfwk' into sh-fixes-for-linus
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/clk/core.c | 3 | ||||
-rw-r--r-- | drivers/sh/clk/cpg.c | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c index 87743e7d4d42..3f5e387ed564 100644 --- a/drivers/sh/clk/core.c +++ b/drivers/sh/clk/core.c | |||
@@ -418,8 +418,11 @@ int clk_register(struct clk *clk) | |||
418 | list_add(&clk->sibling, &root_clks); | 418 | list_add(&clk->sibling, &root_clks); |
419 | 419 | ||
420 | list_add(&clk->node, &clock_list); | 420 | list_add(&clk->node, &clock_list); |
421 | |||
422 | #ifdef CONFIG_SH_CLK_CPG_LEGACY | ||
421 | if (clk->ops && clk->ops->init) | 423 | if (clk->ops && clk->ops->init) |
422 | clk->ops->init(clk); | 424 | clk->ops->init(clk); |
425 | #endif | ||
423 | 426 | ||
424 | out_unlock: | 427 | out_unlock: |
425 | mutex_unlock(&clock_list_sem); | 428 | mutex_unlock(&clock_list_sem); |
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 359e9a322c7b..6172335ae323 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c | |||
@@ -131,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk) | |||
131 | unsigned long value; | 131 | unsigned long value; |
132 | int ret; | 132 | int ret; |
133 | 133 | ||
134 | ret = sh_clk_div6_set_rate(clk, clk->rate, 0); | 134 | ret = sh_clk_div6_set_rate(clk, clk->rate); |
135 | if (ret == 0) { | 135 | if (ret == 0) { |
136 | value = __raw_readl(clk->enable_reg); | 136 | value = __raw_readl(clk->enable_reg); |
137 | value &= ~0x100; /* clear stop bit to enable clock */ | 137 | value &= ~0x100; /* clear stop bit to enable clock */ |