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authorMagnus Damm <damm@opensource.se>2011-12-13 11:00:46 -0500
committerPaul Mundt <lethal@linux-sh.org>2012-01-08 19:33:51 -0500
commitad4a07ff8da7147b391f1ff0034f313a8b9da9e5 (patch)
treebc6efed70c3b063df7f9ccb156b4a03f5adb0a55 /drivers/sh
parent92554d97c6dcc448afd56f96bbe933998868be74 (diff)
sh: pfc: Convert index to field and value pair
Update the way the PFC code is passing bitfield selection between configure register functions. Convert the code from using index only to bitfield number and selected value. First step towards future variable bitfield width support. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/sh')
-rw-r--r--drivers/sh/pfc.c45
1 files changed, 18 insertions, 27 deletions
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
index cfca0aaf9820..41e7c8f63b10 100644
--- a/drivers/sh/pfc.c
+++ b/drivers/sh/pfc.c
@@ -287,7 +287,8 @@ static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
287} 287}
288 288
289static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, 289static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
290 struct pinmux_cfg_reg **crp, int *indexp, 290 struct pinmux_cfg_reg **crp,
291 int *fieldp, int *valuep,
291 unsigned long **cntp) 292 unsigned long **cntp)
292{ 293{
293 struct pinmux_cfg_reg *config_reg; 294 struct pinmux_cfg_reg *config_reg;
@@ -306,7 +307,8 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
306 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) { 307 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) {
307 if (config_reg->enum_ids[n] == enum_id) { 308 if (config_reg->enum_ids[n] == enum_id) {
308 *crp = config_reg; 309 *crp = config_reg;
309 *indexp = n; 310 *fieldp = n / (1 << f_width);
311 *valuep = n % (1 << f_width);
310 *cntp = &config_reg->cnt[n / (1 << f_width)]; 312 *cntp = &config_reg->cnt[n / (1 << f_width)];
311 return 0; 313 return 0;
312 } 314 }
@@ -349,36 +351,22 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
349 351
350static void write_config_reg(struct pinmux_info *gpioc, 352static void write_config_reg(struct pinmux_info *gpioc,
351 struct pinmux_cfg_reg *crp, 353 struct pinmux_cfg_reg *crp,
352 int index) 354 int field, int value)
353{ 355{
354 unsigned long ncomb, pos, value; 356 void __iomem *mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
355 void __iomem *mapped_reg;
356
357 ncomb = 1 << crp->field_width;
358 pos = index / ncomb;
359 value = index % ncomb;
360
361 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
362 357
363 gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width, 358 gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width,
364 pos, value, crp->reg); 359 field, value, crp->reg);
365} 360}
366 361
367static int check_config_reg(struct pinmux_info *gpioc, 362static int check_config_reg(struct pinmux_info *gpioc,
368 struct pinmux_cfg_reg *crp, 363 struct pinmux_cfg_reg *crp,
369 int index) 364 int field, int value)
370{ 365{
371 unsigned long ncomb, pos, value; 366 void __iomem *mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
372 void __iomem *mapped_reg;
373
374 ncomb = 1 << crp->field_width;
375 pos = index / ncomb;
376 value = index % ncomb;
377
378 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
379 367
380 if (gpio_read_reg(mapped_reg, crp->reg_width, 368 if (gpio_read_reg(mapped_reg, crp->reg_width,
381 crp->field_width, pos, crp->reg) == value) 369 crp->field_width, field, crp->reg) == value)
382 return 0; 370 return 0;
383 371
384 return -1; 372 return -1;
@@ -392,7 +380,7 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
392 struct pinmux_cfg_reg *cr = NULL; 380 struct pinmux_cfg_reg *cr = NULL;
393 pinmux_enum_t enum_id; 381 pinmux_enum_t enum_id;
394 struct pinmux_range *range; 382 struct pinmux_range *range;
395 int in_range, pos, index; 383 int in_range, pos, field, value;
396 unsigned long *cntp; 384 unsigned long *cntp;
397 385
398 switch (pinmux_type) { 386 switch (pinmux_type) {
@@ -423,7 +411,8 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
423 411
424 pos = 0; 412 pos = 0;
425 enum_id = 0; 413 enum_id = 0;
426 index = 0; 414 field = 0;
415 value = 0;
427 while (1) { 416 while (1) {
428 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id); 417 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
429 if (pos <= 0) 418 if (pos <= 0)
@@ -470,17 +459,19 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
470 if (!in_range) 459 if (!in_range)
471 continue; 460 continue;
472 461
473 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0) 462 if (get_config_reg(gpioc, enum_id, &cr,
463 &field, &value, &cntp) != 0)
474 goto out_err; 464 goto out_err;
475 465
476 switch (cfg_mode) { 466 switch (cfg_mode) {
477 case GPIO_CFG_DRYRUN: 467 case GPIO_CFG_DRYRUN:
478 if (!*cntp || !check_config_reg(gpioc, cr, index)) 468 if (!*cntp || !check_config_reg(gpioc, cr,
469 field, value))
479 continue; 470 continue;
480 break; 471 break;
481 472
482 case GPIO_CFG_REQ: 473 case GPIO_CFG_REQ:
483 write_config_reg(gpioc, cr, index); 474 write_config_reg(gpioc, cr, field, value);
484 *cntp = *cntp + 1; 475 *cntp = *cntp + 1;
485 break; 476 break;
486 477