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authorPaul Mundt <lethal@linux-sh.org>2012-05-25 02:52:10 -0400
committerPaul Mundt <lethal@linux-sh.org>2012-05-25 02:52:10 -0400
commit0fa22168e00106797f28b2655aaefd0d16a6e67b (patch)
tree3080f6a40bddb704b65e30be1da0d97f11fccf1f /drivers/sh
parent75f5f8a56e0fdf6d32b3ae9c44c10bc0acd3857c (diff)
sh: clkfwk: Use shared sh_clk_div_set_rate()
Follows the sh_clk_div_recalc() change. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/sh')
-rw-r--r--drivers/sh/clk/cpg.c70
1 files changed, 28 insertions, 42 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 84aeeb8fe013..29ee5f7072a4 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -100,6 +100,28 @@ static unsigned long sh_clk_div_recalc(struct clk *clk)
100 return clk->freq_table[idx].frequency; 100 return clk->freq_table[idx].frequency;
101} 101}
102 102
103static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
104{
105 struct clk_div_table *dt = clk_to_div_table(clk);
106 unsigned long value;
107 int idx;
108
109 idx = clk_rate_table_find(clk, clk->freq_table, rate);
110 if (idx < 0)
111 return idx;
112
113 value = sh_clk_read(clk);
114 value &= ~(clk->div_mask << clk->enable_bit);
115 value |= (idx << clk->enable_bit);
116 sh_clk_write(value, clk);
117
118 /* XXX: Should use a post-change notifier */
119 if (dt->kick)
120 dt->kick(clk);
121
122 return 0;
123}
124
103/* 125/*
104 * div6 support 126 * div6 support
105 */ 127 */
@@ -152,28 +174,12 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
152 return 0; 174 return 0;
153} 175}
154 176
155static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
156{
157 unsigned long value;
158 int idx;
159
160 idx = clk_rate_table_find(clk, clk->freq_table, rate);
161 if (idx < 0)
162 return idx;
163
164 value = sh_clk_read(clk);
165 value &= ~clk->div_mask;
166 value |= idx;
167 sh_clk_write(value, clk);
168 return 0;
169}
170
171static int sh_clk_div6_enable(struct clk *clk) 177static int sh_clk_div6_enable(struct clk *clk)
172{ 178{
173 unsigned long value; 179 unsigned long value;
174 int ret; 180 int ret;
175 181
176 ret = sh_clk_div6_set_rate(clk, clk->rate); 182 ret = sh_clk_div_set_rate(clk, clk->rate);
177 if (ret == 0) { 183 if (ret == 0) {
178 value = sh_clk_read(clk); 184 value = sh_clk_read(clk);
179 value &= ~0x100; /* clear stop bit to enable clock */ 185 value &= ~0x100; /* clear stop bit to enable clock */
@@ -195,7 +201,7 @@ static void sh_clk_div6_disable(struct clk *clk)
195static struct sh_clk_ops sh_clk_div6_clk_ops = { 201static struct sh_clk_ops sh_clk_div6_clk_ops = {
196 .recalc = sh_clk_div_recalc, 202 .recalc = sh_clk_div_recalc,
197 .round_rate = sh_clk_div_round_rate, 203 .round_rate = sh_clk_div_round_rate,
198 .set_rate = sh_clk_div6_set_rate, 204 .set_rate = sh_clk_div_set_rate,
199 .enable = sh_clk_div6_enable, 205 .enable = sh_clk_div6_enable,
200 .disable = sh_clk_div6_disable, 206 .disable = sh_clk_div6_disable,
201}; 207};
@@ -203,7 +209,7 @@ static struct sh_clk_ops sh_clk_div6_clk_ops = {
203static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { 209static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
204 .recalc = sh_clk_div_recalc, 210 .recalc = sh_clk_div_recalc,
205 .round_rate = sh_clk_div_round_rate, 211 .round_rate = sh_clk_div_round_rate,
206 .set_rate = sh_clk_div6_set_rate, 212 .set_rate = sh_clk_div_set_rate,
207 .enable = sh_clk_div6_enable, 213 .enable = sh_clk_div6_enable,
208 .disable = sh_clk_div6_disable, 214 .disable = sh_clk_div6_disable,
209 .set_parent = sh_clk_div6_set_parent, 215 .set_parent = sh_clk_div6_set_parent,
@@ -319,26 +325,6 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
319 return 0; 325 return 0;
320} 326}
321 327
322static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
323{
324 struct clk_div_table *dt = clk_to_div_table(clk);
325 unsigned long value;
326 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
327 if (idx < 0)
328 return idx;
329
330 value = sh_clk_read(clk);
331 value &= ~(clk->div_mask << clk->enable_bit);
332 value |= (idx << clk->enable_bit);
333 sh_clk_write(value, clk);
334
335 /* XXX: Should use a post-change notifier */
336 if (dt->kick)
337 dt->kick(clk);
338
339 return 0;
340}
341
342static int sh_clk_div4_enable(struct clk *clk) 328static int sh_clk_div4_enable(struct clk *clk)
343{ 329{
344 sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk); 330 sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk);
@@ -352,13 +338,13 @@ static void sh_clk_div4_disable(struct clk *clk)
352 338
353static struct sh_clk_ops sh_clk_div4_clk_ops = { 339static struct sh_clk_ops sh_clk_div4_clk_ops = {
354 .recalc = sh_clk_div_recalc, 340 .recalc = sh_clk_div_recalc,
355 .set_rate = sh_clk_div4_set_rate, 341 .set_rate = sh_clk_div_set_rate,
356 .round_rate = sh_clk_div_round_rate, 342 .round_rate = sh_clk_div_round_rate,
357}; 343};
358 344
359static struct sh_clk_ops sh_clk_div4_enable_clk_ops = { 345static struct sh_clk_ops sh_clk_div4_enable_clk_ops = {
360 .recalc = sh_clk_div_recalc, 346 .recalc = sh_clk_div_recalc,
361 .set_rate = sh_clk_div4_set_rate, 347 .set_rate = sh_clk_div_set_rate,
362 .round_rate = sh_clk_div_round_rate, 348 .round_rate = sh_clk_div_round_rate,
363 .enable = sh_clk_div4_enable, 349 .enable = sh_clk_div4_enable,
364 .disable = sh_clk_div4_disable, 350 .disable = sh_clk_div4_disable,
@@ -366,7 +352,7 @@ static struct sh_clk_ops sh_clk_div4_enable_clk_ops = {
366 352
367static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { 353static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = {
368 .recalc = sh_clk_div_recalc, 354 .recalc = sh_clk_div_recalc,
369 .set_rate = sh_clk_div4_set_rate, 355 .set_rate = sh_clk_div_set_rate,
370 .round_rate = sh_clk_div_round_rate, 356 .round_rate = sh_clk_div_round_rate,
371 .enable = sh_clk_div4_enable, 357 .enable = sh_clk_div4_enable,
372 .disable = sh_clk_div4_disable, 358 .disable = sh_clk_div4_disable,