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authorPaul Mundt <lethal@linux-sh.org>2010-10-18 08:32:58 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-10-18 08:32:58 -0400
commitde9186c257acb06ca8187cff1c94412b5f80a3bd (patch)
tree5f863be8c11182f5390c375b70c5e1e95bddcafd /drivers/sh/clk-cpg.c
parentc2590f4a8ddf461d33ac2085d966432b2a6a09f2 (diff)
sh: clkfwk: Shuffle around to match the intc split up.
This shuffles the clock framework code around to a drivers/sh/clk subdir, to follow the intc split up. This will make it easier to subsequently break things out as well as plug in different helpers for non-CPG users. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/sh/clk-cpg.c')
-rw-r--r--drivers/sh/clk-cpg.c350
1 files changed, 0 insertions, 350 deletions
diff --git a/drivers/sh/clk-cpg.c b/drivers/sh/clk-cpg.c
deleted file mode 100644
index 392627be4544..000000000000
--- a/drivers/sh/clk-cpg.c
+++ /dev/null
@@ -1,350 +0,0 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <linux/slab.h>
4#include <linux/io.h>
5#include <linux/sh_clk.h>
6
7static int sh_clk_mstp32_enable(struct clk *clk)
8{
9 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
10 clk->enable_reg);
11 return 0;
12}
13
14static void sh_clk_mstp32_disable(struct clk *clk)
15{
16 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
17 clk->enable_reg);
18}
19
20static struct clk_ops sh_clk_mstp32_clk_ops = {
21 .enable = sh_clk_mstp32_enable,
22 .disable = sh_clk_mstp32_disable,
23 .recalc = followparent_recalc,
24};
25
26int __init sh_clk_mstp32_register(struct clk *clks, int nr)
27{
28 struct clk *clkp;
29 int ret = 0;
30 int k;
31
32 for (k = 0; !ret && (k < nr); k++) {
33 clkp = clks + k;
34 clkp->ops = &sh_clk_mstp32_clk_ops;
35 ret |= clk_register(clkp);
36 }
37
38 return ret;
39}
40
41static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
42{
43 return clk_rate_table_round(clk, clk->freq_table, rate);
44}
45
46static int sh_clk_div6_divisors[64] = {
47 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
48 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
49 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
50 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
51};
52
53static struct clk_div_mult_table sh_clk_div6_table = {
54 .divisors = sh_clk_div6_divisors,
55 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
56};
57
58static unsigned long sh_clk_div6_recalc(struct clk *clk)
59{
60 struct clk_div_mult_table *table = &sh_clk_div6_table;
61 unsigned int idx;
62
63 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
64 table, NULL);
65
66 idx = __raw_readl(clk->enable_reg) & 0x003f;
67
68 return clk->freq_table[idx].frequency;
69}
70
71static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
72{
73 struct clk_div_mult_table *table = &sh_clk_div6_table;
74 u32 value;
75 int ret, i;
76
77 if (!clk->parent_table || !clk->parent_num)
78 return -EINVAL;
79
80 /* Search the parent */
81 for (i = 0; i < clk->parent_num; i++)
82 if (clk->parent_table[i] == parent)
83 break;
84
85 if (i == clk->parent_num)
86 return -ENODEV;
87
88 ret = clk_reparent(clk, parent);
89 if (ret < 0)
90 return ret;
91
92 value = __raw_readl(clk->enable_reg) &
93 ~(((1 << clk->src_width) - 1) << clk->src_shift);
94
95 __raw_writel(value | (i << clk->src_shift), clk->enable_reg);
96
97 /* Rebuild the frequency table */
98 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
99 table, &clk->arch_flags);
100
101 return 0;
102}
103
104static int sh_clk_div6_set_rate(struct clk *clk,
105 unsigned long rate, int algo_id)
106{
107 unsigned long value;
108 int idx;
109
110 idx = clk_rate_table_find(clk, clk->freq_table, rate);
111 if (idx < 0)
112 return idx;
113
114 value = __raw_readl(clk->enable_reg);
115 value &= ~0x3f;
116 value |= idx;
117 __raw_writel(value, clk->enable_reg);
118 return 0;
119}
120
121static int sh_clk_div6_enable(struct clk *clk)
122{
123 unsigned long value;
124 int ret;
125
126 ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
127 if (ret == 0) {
128 value = __raw_readl(clk->enable_reg);
129 value &= ~0x100; /* clear stop bit to enable clock */
130 __raw_writel(value, clk->enable_reg);
131 }
132 return ret;
133}
134
135static void sh_clk_div6_disable(struct clk *clk)
136{
137 unsigned long value;
138
139 value = __raw_readl(clk->enable_reg);
140 value |= 0x100; /* stop clock */
141 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
142 __raw_writel(value, clk->enable_reg);
143}
144
145static struct clk_ops sh_clk_div6_clk_ops = {
146 .recalc = sh_clk_div6_recalc,
147 .round_rate = sh_clk_div_round_rate,
148 .set_rate = sh_clk_div6_set_rate,
149 .enable = sh_clk_div6_enable,
150 .disable = sh_clk_div6_disable,
151};
152
153static struct clk_ops sh_clk_div6_reparent_clk_ops = {
154 .recalc = sh_clk_div6_recalc,
155 .round_rate = sh_clk_div_round_rate,
156 .set_rate = sh_clk_div6_set_rate,
157 .enable = sh_clk_div6_enable,
158 .disable = sh_clk_div6_disable,
159 .set_parent = sh_clk_div6_set_parent,
160};
161
162static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
163 struct clk_ops *ops)
164{
165 struct clk *clkp;
166 void *freq_table;
167 int nr_divs = sh_clk_div6_table.nr_divisors;
168 int freq_table_size = sizeof(struct cpufreq_frequency_table);
169 int ret = 0;
170 int k;
171
172 freq_table_size *= (nr_divs + 1);
173 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
174 if (!freq_table) {
175 pr_err("sh_clk_div6_register: unable to alloc memory\n");
176 return -ENOMEM;
177 }
178
179 for (k = 0; !ret && (k < nr); k++) {
180 clkp = clks + k;
181
182 clkp->ops = ops;
183 clkp->freq_table = freq_table + (k * freq_table_size);
184 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
185
186 ret = clk_register(clkp);
187 }
188
189 return ret;
190}
191
192int __init sh_clk_div6_register(struct clk *clks, int nr)
193{
194 return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops);
195}
196
197int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
198{
199 return sh_clk_div6_register_ops(clks, nr,
200 &sh_clk_div6_reparent_clk_ops);
201}
202
203static unsigned long sh_clk_div4_recalc(struct clk *clk)
204{
205 struct clk_div4_table *d4t = clk->priv;
206 struct clk_div_mult_table *table = d4t->div_mult_table;
207 unsigned int idx;
208
209 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
210 table, &clk->arch_flags);
211
212 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
213
214 return clk->freq_table[idx].frequency;
215}
216
217static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
218{
219 struct clk_div4_table *d4t = clk->priv;
220 struct clk_div_mult_table *table = d4t->div_mult_table;
221 u32 value;
222 int ret;
223
224 /* we really need a better way to determine parent index, but for
225 * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
226 * no CLK_ENABLE_ON_INIT means external clock...
227 */
228
229 if (parent->flags & CLK_ENABLE_ON_INIT)
230 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
231 else
232 value = __raw_readl(clk->enable_reg) | (1 << 7);
233
234 ret = clk_reparent(clk, parent);
235 if (ret < 0)
236 return ret;
237
238 __raw_writel(value, clk->enable_reg);
239
240 /* Rebiuld the frequency table */
241 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
242 table, &clk->arch_flags);
243
244 return 0;
245}
246
247static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
248{
249 struct clk_div4_table *d4t = clk->priv;
250 unsigned long value;
251 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
252 if (idx < 0)
253 return idx;
254
255 value = __raw_readl(clk->enable_reg);
256 value &= ~(0xf << clk->enable_bit);
257 value |= (idx << clk->enable_bit);
258 __raw_writel(value, clk->enable_reg);
259
260 if (d4t->kick)
261 d4t->kick(clk);
262
263 return 0;
264}
265
266static int sh_clk_div4_enable(struct clk *clk)
267{
268 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
269 return 0;
270}
271
272static void sh_clk_div4_disable(struct clk *clk)
273{
274 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
275}
276
277static struct clk_ops sh_clk_div4_clk_ops = {
278 .recalc = sh_clk_div4_recalc,
279 .set_rate = sh_clk_div4_set_rate,
280 .round_rate = sh_clk_div_round_rate,
281};
282
283static struct clk_ops sh_clk_div4_enable_clk_ops = {
284 .recalc = sh_clk_div4_recalc,
285 .set_rate = sh_clk_div4_set_rate,
286 .round_rate = sh_clk_div_round_rate,
287 .enable = sh_clk_div4_enable,
288 .disable = sh_clk_div4_disable,
289};
290
291static struct clk_ops sh_clk_div4_reparent_clk_ops = {
292 .recalc = sh_clk_div4_recalc,
293 .set_rate = sh_clk_div4_set_rate,
294 .round_rate = sh_clk_div_round_rate,
295 .enable = sh_clk_div4_enable,
296 .disable = sh_clk_div4_disable,
297 .set_parent = sh_clk_div4_set_parent,
298};
299
300static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
301 struct clk_div4_table *table, struct clk_ops *ops)
302{
303 struct clk *clkp;
304 void *freq_table;
305 int nr_divs = table->div_mult_table->nr_divisors;
306 int freq_table_size = sizeof(struct cpufreq_frequency_table);
307 int ret = 0;
308 int k;
309
310 freq_table_size *= (nr_divs + 1);
311 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
312 if (!freq_table) {
313 pr_err("sh_clk_div4_register: unable to alloc memory\n");
314 return -ENOMEM;
315 }
316
317 for (k = 0; !ret && (k < nr); k++) {
318 clkp = clks + k;
319
320 clkp->ops = ops;
321 clkp->priv = table;
322
323 clkp->freq_table = freq_table + (k * freq_table_size);
324 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
325
326 ret = clk_register(clkp);
327 }
328
329 return ret;
330}
331
332int __init sh_clk_div4_register(struct clk *clks, int nr,
333 struct clk_div4_table *table)
334{
335 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
336}
337
338int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
339 struct clk_div4_table *table)
340{
341 return sh_clk_div4_register_ops(clks, nr, table,
342 &sh_clk_div4_enable_clk_ops);
343}
344
345int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
346 struct clk_div4_table *table)
347{
348 return sh_clk_div4_register_ops(clks, nr, table,
349 &sh_clk_div4_reparent_clk_ops);
350}
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