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authorGreg Ungerer <gerg@snapgear.com>2006-06-25 20:33:10 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-25 20:43:33 -0400
commit76aa698f331475147825ae135eae98bfd457825b (patch)
tree3c4c8a4faae8122fe6a66ddf2bcd1e704569444b /drivers/serial
parent7c99df64f0be6763bf5079560ccd96911c231b7b (diff)
[PATCH] m68knommu: 532x UART support
ColdFire serial driver support for the new 532x CPU family UARTs. Patch submitted by Matt Waddel <Matt.Waddel@freescale.com>. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/mcfserial.c28
1 files changed, 25 insertions, 3 deletions
diff --git a/drivers/serial/mcfserial.c b/drivers/serial/mcfserial.c
index 8cbbb954df2c..8ad242934368 100644
--- a/drivers/serial/mcfserial.c
+++ b/drivers/serial/mcfserial.c
@@ -60,11 +60,11 @@ struct timer_list mcfrs_timer_struct;
60#if defined(CONFIG_HW_FEITH) 60#if defined(CONFIG_HW_FEITH)
61#define CONSOLE_BAUD_RATE 38400 61#define CONSOLE_BAUD_RATE 38400
62#define DEFAULT_CBAUD B38400 62#define DEFAULT_CBAUD B38400
63#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) 63#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || defined(CONFIG_M5329EVB)
64#define CONSOLE_BAUD_RATE 115200 64#define CONSOLE_BAUD_RATE 115200
65#define DEFAULT_CBAUD B115200 65#define DEFAULT_CBAUD B115200
66#elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \ 66#elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
67 defined(CONFIG_senTec) || defined(CONFIG_SNEHA) 67 defined(CONFIG_senTec) || defined(CONFIG_SNEHA) || defined(CONFIG_AVNET)
68#define CONSOLE_BAUD_RATE 19200 68#define CONSOLE_BAUD_RATE 19200
69#define DEFAULT_CBAUD B19200 69#define DEFAULT_CBAUD B19200
70#endif 70#endif
@@ -93,7 +93,7 @@ static struct tty_driver *mcfrs_serial_driver;
93#undef SERIAL_DEBUG_FLOW 93#undef SERIAL_DEBUG_FLOW
94 94
95#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 95#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
96 defined(CONFIG_M520x) 96 defined(CONFIG_M520x) || defined(CONFIG_M532x)
97#define IRQBASE (MCFINT_VECBASE+MCFINT_UART0) 97#define IRQBASE (MCFINT_VECBASE+MCFINT_UART0)
98#else 98#else
99#define IRQBASE 73 99#define IRQBASE 73
@@ -1545,6 +1545,28 @@ static void mcfrs_irqinit(struct mcf_serial *info)
1545 *feci2c_par |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 1545 *feci2c_par |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2
1546 | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; 1546 | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
1547 } 1547 }
1548#elif defined(CONFIG_M532x)
1549 volatile unsigned char *uartp;
1550 uartp = info->addr;
1551 switch (info->line) {
1552 case 0:
1553 MCF_INTC0_ICR26 = 0x3;
1554 MCF_INTC0_CIMR = 26;
1555 /* GPIO initialization */
1556 MCF_GPIO_PAR_UART |= 0x000F;
1557 break;
1558 case 1:
1559 MCF_INTC0_ICR27 = 0x3;
1560 MCF_INTC0_CIMR = 27;
1561 /* GPIO initialization */
1562 MCF_GPIO_PAR_UART |= 0x0FF0;
1563 break;
1564 case 2:
1565 MCF_INTC0_ICR28 = 0x3;
1566 MCF_INTC0_CIMR = 28;
1567 /* GPIOs also must be initalized, depends on board */
1568 break;
1569 }
1548#else 1570#else
1549 volatile unsigned char *icrp, *uartp; 1571 volatile unsigned char *icrp, *uartp;
1550 1572