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authorJeff Garzik <jeff@garzik.org>2006-03-29 17:24:55 -0500
committerJeff Garzik <jeff@garzik.org>2006-03-29 17:24:55 -0500
commit74d89c16735d83349ea74232031819e989a49156 (patch)
tree1d8ded9c76b6ebe97c3841bbb986aacd63a801e5 /drivers/serial
parent52a3220599647ba429fcbca2388ec35b850fa72f (diff)
parent05c8e0ac5c37e9739a852b526afeecae97607cbb (diff)
Merge branch 'upstream'
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/8250.c2
-rw-r--r--drivers/serial/8250_acpi.c183
-rw-r--r--drivers/serial/8250_au1x00.c2
-rw-r--r--drivers/serial/8250_hp300.c10
-rw-r--r--drivers/serial/Kconfig25
-rw-r--r--drivers/serial/Makefile2
-rw-r--r--drivers/serial/amba-pl010.c270
-rw-r--r--drivers/serial/au1x00_uart.c1287
-rw-r--r--drivers/serial/ioc4_serial.c387
-rw-r--r--drivers/serial/mpc52xx_uart.c2
-rw-r--r--drivers/serial/mpsc.c260
-rw-r--r--drivers/serial/mpsc.h289
-rw-r--r--drivers/serial/serial_txx9.c2
-rw-r--r--drivers/serial/sunsu.c2
14 files changed, 632 insertions, 2091 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 5996d3cd0ed8..674b15c78f68 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -1528,7 +1528,7 @@ static int serial8250_startup(struct uart_port *port)
1528 1528
1529 /* 1529 /*
1530 * Clear the FIFO buffers and disable them. 1530 * Clear the FIFO buffers and disable them.
1531 * (they will be reeanbled in set_termios()) 1531 * (they will be reenabled in set_termios())
1532 */ 1532 */
1533 serial8250_clear_fifos(up); 1533 serial8250_clear_fifos(up);
1534 1534
diff --git a/drivers/serial/8250_acpi.c b/drivers/serial/8250_acpi.c
deleted file mode 100644
index 809f89ab965c..000000000000
--- a/drivers/serial/8250_acpi.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * Copyright (c) 2002-2003 Matthew Wilcox for Hewlett-Packard
3 * Copyright (C) 2004 Hewlett-Packard Co
4 * Bjorn Helgaas <bjorn.helgaas@hp.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/acpi.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/serial_core.h>
16
17#include <acpi/acpi_bus.h>
18
19#include <asm/io.h>
20
21#include "8250.h"
22
23struct serial_private {
24 int line;
25};
26
27static acpi_status acpi_serial_mmio(struct uart_port *port,
28 struct acpi_resource_address64 *addr)
29{
30 port->mapbase = addr->minimum;
31 port->iotype = UPIO_MEM;
32 port->flags |= UPF_IOREMAP;
33 return AE_OK;
34}
35
36static acpi_status acpi_serial_port(struct uart_port *port,
37 struct acpi_resource_io *io)
38{
39 if (io->address_length) {
40 port->iobase = io->minimum;
41 port->iotype = UPIO_PORT;
42 } else
43 printk(KERN_ERR "%s: zero-length IO port range?\n", __FUNCTION__);
44 return AE_OK;
45}
46
47static acpi_status acpi_serial_ext_irq(struct uart_port *port,
48 struct acpi_resource_extended_irq *ext_irq)
49{
50 int rc;
51
52 if (ext_irq->interrupt_count > 0) {
53 rc = acpi_register_gsi(ext_irq->interrupts[0],
54 ext_irq->triggering, ext_irq->polarity);
55 if (rc < 0)
56 return AE_ERROR;
57 port->irq = rc;
58 }
59 return AE_OK;
60}
61
62static acpi_status acpi_serial_irq(struct uart_port *port,
63 struct acpi_resource_irq *irq)
64{
65 int rc;
66
67 if (irq->interrupt_count > 0) {
68 rc = acpi_register_gsi(irq->interrupts[0],
69 irq->triggering, irq->polarity);
70 if (rc < 0)
71 return AE_ERROR;
72 port->irq = rc;
73 }
74 return AE_OK;
75}
76
77static acpi_status acpi_serial_resource(struct acpi_resource *res, void *data)
78{
79 struct uart_port *port = (struct uart_port *) data;
80 struct acpi_resource_address64 addr;
81 acpi_status status;
82
83 status = acpi_resource_to_address64(res, &addr);
84 if (ACPI_SUCCESS(status))
85 return acpi_serial_mmio(port, &addr);
86 else if (res->type == ACPI_RESOURCE_TYPE_IO)
87 return acpi_serial_port(port, &res->data.io);
88 else if (res->type == ACPI_RESOURCE_TYPE_EXTENDED_IRQ)
89 return acpi_serial_ext_irq(port, &res->data.extended_irq);
90 else if (res->type == ACPI_RESOURCE_TYPE_IRQ)
91 return acpi_serial_irq(port, &res->data.irq);
92 return AE_OK;
93}
94
95static int acpi_serial_add(struct acpi_device *device)
96{
97 struct serial_private *priv;
98 acpi_status status;
99 struct uart_port port;
100 int result;
101
102 memset(&port, 0, sizeof(struct uart_port));
103
104 port.uartclk = 1843200;
105 port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
106
107 priv = kmalloc(sizeof(struct serial_private), GFP_KERNEL);
108 if (!priv) {
109 result = -ENOMEM;
110 goto fail;
111 }
112 memset(priv, 0, sizeof(*priv));
113
114 status = acpi_walk_resources(device->handle, METHOD_NAME__CRS,
115 acpi_serial_resource, &port);
116 if (ACPI_FAILURE(status)) {
117 result = -ENODEV;
118 goto fail;
119 }
120
121 if (!port.mapbase && !port.iobase) {
122 printk(KERN_ERR "%s: no iomem or port address in %s _CRS\n",
123 __FUNCTION__, device->pnp.bus_id);
124 result = -ENODEV;
125 goto fail;
126 }
127
128 priv->line = serial8250_register_port(&port);
129 if (priv->line < 0) {
130 printk(KERN_WARNING "Couldn't register serial port %s: %d\n",
131 device->pnp.bus_id, priv->line);
132 result = -ENODEV;
133 goto fail;
134 }
135
136 acpi_driver_data(device) = priv;
137 return 0;
138
139fail:
140 kfree(priv);
141
142 return result;
143}
144
145static int acpi_serial_remove(struct acpi_device *device, int type)
146{
147 struct serial_private *priv;
148
149 if (!device || !acpi_driver_data(device))
150 return -EINVAL;
151
152 priv = acpi_driver_data(device);
153 serial8250_unregister_port(priv->line);
154 kfree(priv);
155
156 return 0;
157}
158
159static struct acpi_driver acpi_serial_driver = {
160 .name = "serial",
161 .class = "",
162 .ids = "PNP0501",
163 .ops = {
164 .add = acpi_serial_add,
165 .remove = acpi_serial_remove,
166 },
167};
168
169static int __init acpi_serial_init(void)
170{
171 return acpi_bus_register_driver(&acpi_serial_driver);
172}
173
174static void __exit acpi_serial_exit(void)
175{
176 acpi_bus_unregister_driver(&acpi_serial_driver);
177}
178
179module_init(acpi_serial_init);
180module_exit(acpi_serial_exit);
181
182MODULE_LICENSE("GPL");
183MODULE_DESCRIPTION("Generic 8250/16x50 ACPI serial driver");
diff --git a/drivers/serial/8250_au1x00.c b/drivers/serial/8250_au1x00.c
index 8d8d7a70d03e..3d1bfd07208d 100644
--- a/drivers/serial/8250_au1x00.c
+++ b/drivers/serial/8250_au1x00.c
@@ -51,7 +51,7 @@ static struct plat_serial8250_port au1x00_data[] = {
51#elif defined(CONFIG_SOC_AU1100) 51#elif defined(CONFIG_SOC_AU1100)
52 PORT(UART0_ADDR, AU1100_UART0_INT), 52 PORT(UART0_ADDR, AU1100_UART0_INT),
53 PORT(UART1_ADDR, AU1100_UART1_INT), 53 PORT(UART1_ADDR, AU1100_UART1_INT),
54 PORT(UART2_ADDR, AU1100_UART2_INT), 54 /* The internal UART2 does not exist on the AU1100 processor. */
55 PORT(UART3_ADDR, AU1100_UART3_INT), 55 PORT(UART3_ADDR, AU1100_UART3_INT),
56#elif defined(CONFIG_SOC_AU1550) 56#elif defined(CONFIG_SOC_AU1550)
57 PORT(UART0_ADDR, AU1550_UART0_INT), 57 PORT(UART0_ADDR, AU1550_UART0_INT),
diff --git a/drivers/serial/8250_hp300.c b/drivers/serial/8250_hp300.c
index 4315afe9c080..53e81a44c1a3 100644
--- a/drivers/serial/8250_hp300.c
+++ b/drivers/serial/8250_hp300.c
@@ -55,6 +55,8 @@ static struct dio_driver hpdca_driver = {
55 55
56#endif 56#endif
57 57
58static unsigned int num_ports;
59
58extern int hp300_uart_scode; 60extern int hp300_uart_scode;
59 61
60/* Offset to UART registers from base of DCA */ 62/* Offset to UART registers from base of DCA */
@@ -199,6 +201,8 @@ static int __devinit hpdca_init_one(struct dio_dev *d,
199 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff); 201 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
200 udelay(100); 202 udelay(100);
201 203
204 num_ports++;
205
202 return 0; 206 return 0;
203} 207}
204#endif 208#endif
@@ -206,7 +210,6 @@ static int __devinit hpdca_init_one(struct dio_dev *d,
206static int __init hp300_8250_init(void) 210static int __init hp300_8250_init(void)
207{ 211{
208 static int called = 0; 212 static int called = 0;
209 int num_ports;
210#ifdef CONFIG_HPAPCI 213#ifdef CONFIG_HPAPCI
211 int line; 214 int line;
212 unsigned long base; 215 unsigned long base;
@@ -221,11 +224,8 @@ static int __init hp300_8250_init(void)
221 if (!MACH_IS_HP300) 224 if (!MACH_IS_HP300)
222 return -ENODEV; 225 return -ENODEV;
223 226
224 num_ports = 0;
225
226#ifdef CONFIG_HPDCA 227#ifdef CONFIG_HPDCA
227 if (dio_module_init(&hpdca_driver) == 0) 228 dio_register_driver(&hpdca_driver);
228 num_ports++;
229#endif 229#endif
230#ifdef CONFIG_HPAPCI 230#ifdef CONFIG_HPAPCI
231 if (hp300_model < HP_400) { 231 if (hp300_model < HP_400) {
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c66ef96c71b4..fe0d8b8e91c8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -77,14 +77,6 @@ config SERIAL_8250_CS
77 77
78 If unsure, say N. 78 If unsure, say N.
79 79
80config SERIAL_8250_ACPI
81 bool "8250/16550 device discovery via ACPI namespace"
82 default y if IA64
83 depends on ACPI && SERIAL_8250
84 ---help---
85 If you wish to enable serial port discovery via the ACPI
86 namespace, say Y here. If unsure, say N.
87
88config SERIAL_8250_NR_UARTS 80config SERIAL_8250_NR_UARTS
89 int "Maximum number of 8250/16550 serial ports" 81 int "Maximum number of 8250/16550 serial ports"
90 depends on SERIAL_8250 82 depends on SERIAL_8250
@@ -628,22 +620,6 @@ config SERIAL_SH_SCI_CONSOLE
628 depends on SERIAL_SH_SCI=y 620 depends on SERIAL_SH_SCI=y
629 select SERIAL_CORE_CONSOLE 621 select SERIAL_CORE_CONSOLE
630 622
631config SERIAL_AU1X00
632 bool "Enable Au1x00 UART Support"
633 depends on MIPS && SOC_AU1X00
634 select SERIAL_CORE
635 help
636 If you have an Alchemy AU1X00 processor (MIPS based) and you want
637 to use serial ports, say Y. Otherwise, say N.
638
639config SERIAL_AU1X00_CONSOLE
640 bool "Enable Au1x00 serial console"
641 depends on SERIAL_AU1X00
642 select SERIAL_CORE_CONSOLE
643 help
644 If you have an Alchemy AU1X00 processor (MIPS based) and you want
645 to use a console on a serial port, say Y. Otherwise, say N.
646
647config SERIAL_CORE 623config SERIAL_CORE
648 tristate 624 tristate
649 625
@@ -827,6 +803,7 @@ config SERIAL_ICOM
827 tristate "IBM Multiport Serial Adapter" 803 tristate "IBM Multiport Serial Adapter"
828 depends on PCI && (PPC_ISERIES || PPC_PSERIES) 804 depends on PCI && (PPC_ISERIES || PPC_PSERIES)
829 select SERIAL_CORE 805 select SERIAL_CORE
806 select FW_LOADER
830 help 807 help
831 This driver is for a family of multiport serial adapters 808 This driver is for a family of multiport serial adapters
832 including 2 port RVX, 2 port internal modem, 4 port internal 809 including 2 port RVX, 2 port internal modem, 4 port internal
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 50c221af9e6d..d2b4c214876b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -5,7 +5,6 @@
5# 5#
6 6
7serial-8250-y := 7serial-8250-y :=
8serial-8250-$(CONFIG_SERIAL_8250_ACPI) += 8250_acpi.o
9serial-8250-$(CONFIG_PNP) += 8250_pnp.o 8serial-8250-$(CONFIG_PNP) += 8250_pnp.o
10serial-8250-$(CONFIG_GSC) += 8250_gsc.o 9serial-8250-$(CONFIG_GSC) += 8250_gsc.o
11serial-8250-$(CONFIG_PCI) += 8250_pci.o 10serial-8250-$(CONFIG_PCI) += 8250_pci.o
@@ -42,7 +41,6 @@ obj-$(CONFIG_SERIAL_COLDFIRE) += mcfserial.o
42obj-$(CONFIG_V850E_UART) += v850e_uart.o 41obj-$(CONFIG_V850E_UART) += v850e_uart.o
43obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o 42obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
44obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o 43obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
45obj-$(CONFIG_SERIAL_AU1X00) += au1x00_uart.o
46obj-$(CONFIG_SERIAL_DZ) += dz.o 44obj-$(CONFIG_SERIAL_DZ) += dz.o
47obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o 45obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
48obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o 46obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index e04d5e82d9ae..1631414000a2 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -51,8 +51,6 @@
51#include <linux/amba/serial.h> 51#include <linux/amba/serial.h>
52 52
53#include <asm/io.h> 53#include <asm/io.h>
54#include <asm/irq.h>
55#include <asm/hardware.h>
56 54
57#define UART_NR 2 55#define UART_NR 2
58 56
@@ -62,47 +60,19 @@
62 60
63#define AMBA_ISR_PASS_LIMIT 256 61#define AMBA_ISR_PASS_LIMIT 256
64 62
65/*
66 * Access macros for the AMBA UARTs
67 */
68#define UART_GET_INT_STATUS(p) readb((p)->membase + UART010_IIR)
69#define UART_PUT_ICR(p, c) writel((c), (p)->membase + UART010_ICR)
70#define UART_GET_FR(p) readb((p)->membase + UART01x_FR)
71#define UART_GET_CHAR(p) readb((p)->membase + UART01x_DR)
72#define UART_PUT_CHAR(p, c) writel((c), (p)->membase + UART01x_DR)
73#define UART_GET_RSR(p) readb((p)->membase + UART01x_RSR)
74#define UART_GET_CR(p) readb((p)->membase + UART010_CR)
75#define UART_PUT_CR(p,c) writel((c), (p)->membase + UART010_CR)
76#define UART_GET_LCRL(p) readb((p)->membase + UART010_LCRL)
77#define UART_PUT_LCRL(p,c) writel((c), (p)->membase + UART010_LCRL)
78#define UART_GET_LCRM(p) readb((p)->membase + UART010_LCRM)
79#define UART_PUT_LCRM(p,c) writel((c), (p)->membase + UART010_LCRM)
80#define UART_GET_LCRH(p) readb((p)->membase + UART010_LCRH)
81#define UART_PUT_LCRH(p,c) writel((c), (p)->membase + UART010_LCRH)
82#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 63#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
83#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 64#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
84#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART01x_FR_TMSK) == 0)
85 65
86#define UART_DUMMY_RSR_RX /*256*/0 66#define UART_DUMMY_RSR_RX 256
87#define UART_PORT_SIZE 64 67#define UART_PORT_SIZE 64
88 68
89/* 69/*
90 * On the Integrator platform, the port RTS and DTR are provided by
91 * bits in the following SC_CTRLS register bits:
92 * RTS DTR
93 * UART0 7 6
94 * UART1 5 4
95 */
96#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
97#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
98
99/*
100 * We wrap our port structure around the generic uart_port. 70 * We wrap our port structure around the generic uart_port.
101 */ 71 */
102struct uart_amba_port { 72struct uart_amba_port {
103 struct uart_port port; 73 struct uart_port port;
104 unsigned int dtr_mask; 74 struct amba_device *dev;
105 unsigned int rts_mask; 75 struct amba_pl010_data *data;
106 unsigned int old_status; 76 unsigned int old_status;
107}; 77};
108 78
@@ -110,36 +80,36 @@ static void pl010_stop_tx(struct uart_port *port)
110{ 80{
111 unsigned int cr; 81 unsigned int cr;
112 82
113 cr = UART_GET_CR(port); 83 cr = readb(port->membase + UART010_CR);
114 cr &= ~UART010_CR_TIE; 84 cr &= ~UART010_CR_TIE;
115 UART_PUT_CR(port, cr); 85 writel(cr, port->membase + UART010_CR);
116} 86}
117 87
118static void pl010_start_tx(struct uart_port *port) 88static void pl010_start_tx(struct uart_port *port)
119{ 89{
120 unsigned int cr; 90 unsigned int cr;
121 91
122 cr = UART_GET_CR(port); 92 cr = readb(port->membase + UART010_CR);
123 cr |= UART010_CR_TIE; 93 cr |= UART010_CR_TIE;
124 UART_PUT_CR(port, cr); 94 writel(cr, port->membase + UART010_CR);
125} 95}
126 96
127static void pl010_stop_rx(struct uart_port *port) 97static void pl010_stop_rx(struct uart_port *port)
128{ 98{
129 unsigned int cr; 99 unsigned int cr;
130 100
131 cr = UART_GET_CR(port); 101 cr = readb(port->membase + UART010_CR);
132 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 102 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
133 UART_PUT_CR(port, cr); 103 writel(cr, port->membase + UART010_CR);
134} 104}
135 105
136static void pl010_enable_ms(struct uart_port *port) 106static void pl010_enable_ms(struct uart_port *port)
137{ 107{
138 unsigned int cr; 108 unsigned int cr;
139 109
140 cr = UART_GET_CR(port); 110 cr = readb(port->membase + UART010_CR);
141 cr |= UART010_CR_MSIE; 111 cr |= UART010_CR_MSIE;
142 UART_PUT_CR(port, cr); 112 writel(cr, port->membase + UART010_CR);
143} 113}
144 114
145static void 115static void
@@ -152,9 +122,9 @@ pl010_rx_chars(struct uart_port *port)
152 struct tty_struct *tty = port->info->tty; 122 struct tty_struct *tty = port->info->tty;
153 unsigned int status, ch, flag, rsr, max_count = 256; 123 unsigned int status, ch, flag, rsr, max_count = 256;
154 124
155 status = UART_GET_FR(port); 125 status = readb(port->membase + UART01x_FR);
156 while (UART_RX_DATA(status) && max_count--) { 126 while (UART_RX_DATA(status) && max_count--) {
157 ch = UART_GET_CHAR(port); 127 ch = readb(port->membase + UART01x_DR);
158 flag = TTY_NORMAL; 128 flag = TTY_NORMAL;
159 129
160 port->icount.rx++; 130 port->icount.rx++;
@@ -163,7 +133,7 @@ pl010_rx_chars(struct uart_port *port)
163 * Note that the error handling code is 133 * Note that the error handling code is
164 * out of the main execution path 134 * out of the main execution path
165 */ 135 */
166 rsr = UART_GET_RSR(port) | UART_DUMMY_RSR_RX; 136 rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
167 if (unlikely(rsr & UART01x_RSR_ANY)) { 137 if (unlikely(rsr & UART01x_RSR_ANY)) {
168 if (rsr & UART01x_RSR_BE) { 138 if (rsr & UART01x_RSR_BE) {
169 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 139 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
@@ -193,7 +163,7 @@ pl010_rx_chars(struct uart_port *port)
193 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag); 163 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
194 164
195 ignore_char: 165 ignore_char:
196 status = UART_GET_FR(port); 166 status = readb(port->membase + UART01x_FR);
197 } 167 }
198 tty_flip_buffer_push(tty); 168 tty_flip_buffer_push(tty);
199 return; 169 return;
@@ -205,7 +175,7 @@ static void pl010_tx_chars(struct uart_port *port)
205 int count; 175 int count;
206 176
207 if (port->x_char) { 177 if (port->x_char) {
208 UART_PUT_CHAR(port, port->x_char); 178 writel(port->x_char, port->membase + UART01x_DR);
209 port->icount.tx++; 179 port->icount.tx++;
210 port->x_char = 0; 180 port->x_char = 0;
211 return; 181 return;
@@ -217,7 +187,7 @@ static void pl010_tx_chars(struct uart_port *port)
217 187
218 count = port->fifosize >> 1; 188 count = port->fifosize >> 1;
219 do { 189 do {
220 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 190 writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
221 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
222 port->icount.tx++; 192 port->icount.tx++;
223 if (uart_circ_empty(xmit)) 193 if (uart_circ_empty(xmit))
@@ -236,9 +206,9 @@ static void pl010_modem_status(struct uart_port *port)
236 struct uart_amba_port *uap = (struct uart_amba_port *)port; 206 struct uart_amba_port *uap = (struct uart_amba_port *)port;
237 unsigned int status, delta; 207 unsigned int status, delta;
238 208
239 UART_PUT_ICR(&uap->port, 0); 209 writel(0, uap->port.membase + UART010_ICR);
240 210
241 status = UART_GET_FR(&uap->port) & UART01x_FR_MODEM_ANY; 211 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
242 212
243 delta = status ^ uap->old_status; 213 delta = status ^ uap->old_status;
244 uap->old_status = status; 214 uap->old_status = status;
@@ -266,7 +236,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
266 236
267 spin_lock(&port->lock); 237 spin_lock(&port->lock);
268 238
269 status = UART_GET_INT_STATUS(port); 239 status = readb(port->membase + UART010_IIR);
270 if (status) { 240 if (status) {
271 do { 241 do {
272 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 242 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
@@ -283,7 +253,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
283 if (pass_counter-- == 0) 253 if (pass_counter-- == 0)
284 break; 254 break;
285 255
286 status = UART_GET_INT_STATUS(port); 256 status = readb(port->membase + UART010_IIR);
287 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 257 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
288 UART010_IIR_TIS)); 258 UART010_IIR_TIS));
289 handled = 1; 259 handled = 1;
@@ -296,7 +266,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
296 266
297static unsigned int pl010_tx_empty(struct uart_port *port) 267static unsigned int pl010_tx_empty(struct uart_port *port)
298{ 268{
299 return UART_GET_FR(port) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 269 return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
300} 270}
301 271
302static unsigned int pl010_get_mctrl(struct uart_port *port) 272static unsigned int pl010_get_mctrl(struct uart_port *port)
@@ -304,7 +274,7 @@ static unsigned int pl010_get_mctrl(struct uart_port *port)
304 unsigned int result = 0; 274 unsigned int result = 0;
305 unsigned int status; 275 unsigned int status;
306 276
307 status = UART_GET_FR(port); 277 status = readb(port->membase + UART01x_FR);
308 if (status & UART01x_FR_DCD) 278 if (status & UART01x_FR_DCD)
309 result |= TIOCM_CAR; 279 result |= TIOCM_CAR;
310 if (status & UART01x_FR_DSR) 280 if (status & UART01x_FR_DSR)
@@ -318,20 +288,9 @@ static unsigned int pl010_get_mctrl(struct uart_port *port)
318static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 288static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
319{ 289{
320 struct uart_amba_port *uap = (struct uart_amba_port *)port; 290 struct uart_amba_port *uap = (struct uart_amba_port *)port;
321 unsigned int ctrls = 0, ctrlc = 0;
322
323 if (mctrl & TIOCM_RTS)
324 ctrlc |= uap->rts_mask;
325 else
326 ctrls |= uap->rts_mask;
327
328 if (mctrl & TIOCM_DTR)
329 ctrlc |= uap->dtr_mask;
330 else
331 ctrls |= uap->dtr_mask;
332 291
333 __raw_writel(ctrls, SC_CTRLS); 292 if (uap->data)
334 __raw_writel(ctrlc, SC_CTRLC); 293 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
335} 294}
336 295
337static void pl010_break_ctl(struct uart_port *port, int break_state) 296static void pl010_break_ctl(struct uart_port *port, int break_state)
@@ -340,12 +299,12 @@ static void pl010_break_ctl(struct uart_port *port, int break_state)
340 unsigned int lcr_h; 299 unsigned int lcr_h;
341 300
342 spin_lock_irqsave(&port->lock, flags); 301 spin_lock_irqsave(&port->lock, flags);
343 lcr_h = UART_GET_LCRH(port); 302 lcr_h = readb(port->membase + UART010_LCRH);
344 if (break_state == -1) 303 if (break_state == -1)
345 lcr_h |= UART01x_LCRH_BRK; 304 lcr_h |= UART01x_LCRH_BRK;
346 else 305 else
347 lcr_h &= ~UART01x_LCRH_BRK; 306 lcr_h &= ~UART01x_LCRH_BRK;
348 UART_PUT_LCRH(port, lcr_h); 307 writel(lcr_h, port->membase + UART010_LCRH);
349 spin_unlock_irqrestore(&port->lock, flags); 308 spin_unlock_irqrestore(&port->lock, flags);
350} 309}
351 310
@@ -364,13 +323,13 @@ static int pl010_startup(struct uart_port *port)
364 /* 323 /*
365 * initialise the old status of the modem signals 324 * initialise the old status of the modem signals
366 */ 325 */
367 uap->old_status = UART_GET_FR(port) & UART01x_FR_MODEM_ANY; 326 uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
368 327
369 /* 328 /*
370 * Finally, enable interrupts 329 * Finally, enable interrupts
371 */ 330 */
372 UART_PUT_CR(port, UART01x_CR_UARTEN | UART010_CR_RIE | 331 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
373 UART010_CR_RTIE); 332 port->membase + UART010_CR);
374 333
375 return 0; 334 return 0;
376} 335}
@@ -385,11 +344,12 @@ static void pl010_shutdown(struct uart_port *port)
385 /* 344 /*
386 * disable all interrupts, disable the port 345 * disable all interrupts, disable the port
387 */ 346 */
388 UART_PUT_CR(port, 0); 347 writel(0, port->membase + UART010_CR);
389 348
390 /* disable break condition and fifos */ 349 /* disable break condition and fifos */
391 UART_PUT_LCRH(port, UART_GET_LCRH(port) & 350 writel(readb(port->membase + UART010_LCRH) &
392 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN)); 351 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
352 port->membase + UART010_LCRH);
393} 353}
394 354
395static void 355static void
@@ -466,25 +426,25 @@ pl010_set_termios(struct uart_port *port, struct termios *termios,
466 port->ignore_status_mask |= UART_DUMMY_RSR_RX; 426 port->ignore_status_mask |= UART_DUMMY_RSR_RX;
467 427
468 /* first, disable everything */ 428 /* first, disable everything */
469 old_cr = UART_GET_CR(port) & ~UART010_CR_MSIE; 429 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
470 430
471 if (UART_ENABLE_MS(port, termios->c_cflag)) 431 if (UART_ENABLE_MS(port, termios->c_cflag))
472 old_cr |= UART010_CR_MSIE; 432 old_cr |= UART010_CR_MSIE;
473 433
474 UART_PUT_CR(port, 0); 434 writel(0, port->membase + UART010_CR);
475 435
476 /* Set baud rate */ 436 /* Set baud rate */
477 quot -= 1; 437 quot -= 1;
478 UART_PUT_LCRM(port, ((quot & 0xf00) >> 8)); 438 writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
479 UART_PUT_LCRL(port, (quot & 0xff)); 439 writel(quot & 0xff, port->membase + UART010_LCRL);
480 440
481 /* 441 /*
482 * ----------v----------v----------v----------v----- 442 * ----------v----------v----------v----------v-----
483 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 443 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
484 * ----------^----------^----------^----------^----- 444 * ----------^----------^----------^----------^-----
485 */ 445 */
486 UART_PUT_LCRH(port, lcr_h); 446 writel(lcr_h, port->membase + UART010_LCRH);
487 UART_PUT_CR(port, old_cr); 447 writel(old_cr, port->membase + UART010_CR);
488 448
489 spin_unlock_irqrestore(&port->lock, flags); 449 spin_unlock_irqrestore(&port->lock, flags);
490} 450}
@@ -556,59 +516,32 @@ static struct uart_ops amba_pl010_pops = {
556 .verify_port = pl010_verify_port, 516 .verify_port = pl010_verify_port,
557}; 517};
558 518
559static struct uart_amba_port amba_ports[UART_NR] = { 519static struct uart_amba_port *amba_ports[UART_NR];
560 {
561 .port = {
562 .membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
563 .mapbase = INTEGRATOR_UART0_BASE,
564 .iotype = UPIO_MEM,
565 .irq = IRQ_UARTINT0,
566 .uartclk = 14745600,
567 .fifosize = 16,
568 .ops = &amba_pl010_pops,
569 .flags = UPF_BOOT_AUTOCONF,
570 .line = 0,
571 },
572 .dtr_mask = 1 << 5,
573 .rts_mask = 1 << 4,
574 },
575 {
576 .port = {
577 .membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
578 .mapbase = INTEGRATOR_UART1_BASE,
579 .iotype = UPIO_MEM,
580 .irq = IRQ_UARTINT1,
581 .uartclk = 14745600,
582 .fifosize = 16,
583 .ops = &amba_pl010_pops,
584 .flags = UPF_BOOT_AUTOCONF,
585 .line = 1,
586 },
587 .dtr_mask = 1 << 7,
588 .rts_mask = 1 << 6,
589 }
590};
591 520
592#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 521#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
593 522
594static void pl010_console_putchar(struct uart_port *port, int ch) 523static void pl010_console_putchar(struct uart_port *port, int ch)
595{ 524{
596 while (!UART_TX_READY(UART_GET_FR(port))) 525 unsigned int status;
526
527 do {
528 status = readb(port->membase + UART01x_FR);
597 barrier(); 529 barrier();
598 UART_PUT_CHAR(port, ch); 530 } while (!UART_TX_READY(status));
531 writel(ch, port->membase + UART01x_DR);
599} 532}
600 533
601static void 534static void
602pl010_console_write(struct console *co, const char *s, unsigned int count) 535pl010_console_write(struct console *co, const char *s, unsigned int count)
603{ 536{
604 struct uart_port *port = &amba_ports[co->index].port; 537 struct uart_port *port = &amba_ports[co->index]->port;
605 unsigned int status, old_cr; 538 unsigned int status, old_cr;
606 539
607 /* 540 /*
608 * First save the CR then disable the interrupts 541 * First save the CR then disable the interrupts
609 */ 542 */
610 old_cr = UART_GET_CR(port); 543 old_cr = readb(port->membase + UART010_CR);
611 UART_PUT_CR(port, UART01x_CR_UARTEN); 544 writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
612 545
613 uart_console_write(port, s, count, pl010_console_putchar); 546 uart_console_write(port, s, count, pl010_console_putchar);
614 547
@@ -617,18 +550,19 @@ pl010_console_write(struct console *co, const char *s, unsigned int count)
617 * and restore the TCR 550 * and restore the TCR
618 */ 551 */
619 do { 552 do {
620 status = UART_GET_FR(port); 553 status = readb(port->membase + UART01x_FR);
554 barrier();
621 } while (status & UART01x_FR_BUSY); 555 } while (status & UART01x_FR_BUSY);
622 UART_PUT_CR(port, old_cr); 556 writel(old_cr, port->membase + UART010_CR);
623} 557}
624 558
625static void __init 559static void __init
626pl010_console_get_options(struct uart_port *port, int *baud, 560pl010_console_get_options(struct uart_port *port, int *baud,
627 int *parity, int *bits) 561 int *parity, int *bits)
628{ 562{
629 if (UART_GET_CR(port) & UART01x_CR_UARTEN) { 563 if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) {
630 unsigned int lcr_h, quot; 564 unsigned int lcr_h, quot;
631 lcr_h = UART_GET_LCRH(port); 565 lcr_h = readb(port->membase + UART010_LCRH);
632 566
633 *parity = 'n'; 567 *parity = 'n';
634 if (lcr_h & UART01x_LCRH_PEN) { 568 if (lcr_h & UART01x_LCRH_PEN) {
@@ -643,7 +577,7 @@ pl010_console_get_options(struct uart_port *port, int *baud,
643 else 577 else
644 *bits = 8; 578 *bits = 8;
645 579
646 quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8; 580 quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8;
647 *baud = port->uartclk / (16 * (quot + 1)); 581 *baud = port->uartclk / (16 * (quot + 1));
648 } 582 }
649} 583}
@@ -663,7 +597,7 @@ static int __init pl010_console_setup(struct console *co, char *options)
663 */ 597 */
664 if (co->index >= UART_NR) 598 if (co->index >= UART_NR)
665 co->index = 0; 599 co->index = 0;
666 port = &amba_ports[co->index].port; 600 port = &amba_ports[co->index]->port;
667 601
668 if (options) 602 if (options)
669 uart_parse_options(options, &baud, &parity, &bits, &flow); 603 uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -684,24 +618,6 @@ static struct console amba_console = {
684 .data = &amba_reg, 618 .data = &amba_reg,
685}; 619};
686 620
687static int __init amba_console_init(void)
688{
689 /*
690 * All port initializations are done statically
691 */
692 register_console(&amba_console);
693 return 0;
694}
695console_initcall(amba_console_init);
696
697static int __init amba_late_console_init(void)
698{
699 if (!(amba_console.flags & CON_ENABLED))
700 register_console(&amba_console);
701 return 0;
702}
703late_initcall(amba_late_console_init);
704
705#define AMBA_CONSOLE &amba_console 621#define AMBA_CONSOLE &amba_console
706#else 622#else
707#define AMBA_CONSOLE NULL 623#define AMBA_CONSOLE NULL
@@ -719,30 +635,76 @@ static struct uart_driver amba_reg = {
719 635
720static int pl010_probe(struct amba_device *dev, void *id) 636static int pl010_probe(struct amba_device *dev, void *id)
721{ 637{
722 int i; 638 struct uart_amba_port *port;
639 void __iomem *base;
640 int i, ret;
723 641
724 for (i = 0; i < UART_NR; i++) { 642 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
725 if (amba_ports[i].port.mapbase != dev->res.start) 643 if (amba_ports[i] == NULL)
726 continue; 644 break;
727 645
728 amba_ports[i].port.dev = &dev->dev; 646 if (i == ARRAY_SIZE(amba_ports)) {
729 uart_add_one_port(&amba_reg, &amba_ports[i].port); 647 ret = -EBUSY;
730 amba_set_drvdata(dev, &amba_ports[i]); 648 goto out;
731 break;
732 } 649 }
733 650
734 return 0; 651 port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
652 if (!port) {
653 ret = -ENOMEM;
654 goto out;
655 }
656
657 base = ioremap(dev->res.start, PAGE_SIZE);
658 if (!base) {
659 ret = -ENOMEM;
660 goto free;
661 }
662
663 port->port.dev = &dev->dev;
664 port->port.mapbase = dev->res.start;
665 port->port.membase = base;
666 port->port.iotype = UPIO_MEM;
667 port->port.irq = dev->irq[0];
668 port->port.uartclk = 14745600;
669 port->port.fifosize = 16;
670 port->port.ops = &amba_pl010_pops;
671 port->port.flags = UPF_BOOT_AUTOCONF;
672 port->port.line = i;
673 port->dev = dev;
674 port->data = dev->dev.platform_data;
675
676 amba_ports[i] = port;
677
678 amba_set_drvdata(dev, port);
679 ret = uart_add_one_port(&amba_reg, &port->port);
680 if (ret) {
681 amba_set_drvdata(dev, NULL);
682 amba_ports[i] = NULL;
683 iounmap(base);
684 free:
685 kfree(port);
686 }
687
688 out:
689 return ret;
735} 690}
736 691
737static int pl010_remove(struct amba_device *dev) 692static int pl010_remove(struct amba_device *dev)
738{ 693{
739 struct uart_amba_port *uap = amba_get_drvdata(dev); 694 struct uart_amba_port *port = amba_get_drvdata(dev);
740 695 int i;
741 if (uap)
742 uart_remove_one_port(&amba_reg, &uap->port);
743 696
744 amba_set_drvdata(dev, NULL); 697 amba_set_drvdata(dev, NULL);
745 698
699 uart_remove_one_port(&amba_reg, &port->port);
700
701 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
702 if (amba_ports[i] == port)
703 amba_ports[i] = NULL;
704
705 iounmap(port->port.membase);
706 kfree(port);
707
746 return 0; 708 return 0;
747} 709}
748 710
diff --git a/drivers/serial/au1x00_uart.c b/drivers/serial/au1x00_uart.c
deleted file mode 100644
index 948880ac5878..000000000000
--- a/drivers/serial/au1x00_uart.c
+++ /dev/null
@@ -1,1287 +0,0 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port. Currently, we don't
16 * support this very well, and it may well be dropped from this driver
17 * in future. As such, mapbase should be NULL.
18 *
19 * membase is an 'ioremapped' cookie. This is compatible with the old
20 * serial.c driver, and is currently the preferred form.
21 */
22#include <linux/config.h>
23#include <linux/module.h>
24#include <linux/tty.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/serial.h>
30#include <linux/serialP.h>
31#include <linux/delay.h>
32
33#include <asm/serial.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/mach-au1x00/au1000.h>
37
38#if defined(CONFIG_SERIAL_AU1X00_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
39#define SUPPORT_SYSRQ
40#endif
41
42#include <linux/serial_core.h>
43#include "8250.h"
44
45/*
46 * Debugging.
47 */
48#if 0
49#define DEBUG_AUTOCONF(fmt...) printk(fmt)
50#else
51#define DEBUG_AUTOCONF(fmt...) do { } while (0)
52#endif
53
54#if 0
55#define DEBUG_INTR(fmt...) printk(fmt)
56#else
57#define DEBUG_INTR(fmt...) do { } while (0)
58#endif
59
60#define PASS_LIMIT 256
61
62/*
63 * We default to IRQ0 for the "no irq" hack. Some
64 * machine types want others as well - they're free
65 * to redefine this in their header file.
66 */
67#define is_real_interrupt(irq) ((irq) != 0)
68
69static struct old_serial_port old_serial_port[] = {
70 { .baud_base = 0,
71 .iomem_base = (u8 *)UART0_ADDR,
72 .irq = AU1000_UART0_INT,
73 .flags = STD_COM_FLAGS,
74 .iomem_reg_shift = 2,
75 }, {
76 .baud_base = 0,
77 .iomem_base = (u8 *)UART1_ADDR,
78 .irq = AU1000_UART1_INT,
79 .flags = STD_COM_FLAGS,
80 .iomem_reg_shift = 2
81 }, {
82 .baud_base = 0,
83 .iomem_base = (u8 *)UART2_ADDR,
84 .irq = AU1000_UART2_INT,
85 .flags = STD_COM_FLAGS,
86 .iomem_reg_shift = 2
87 }, {
88 .baud_base = 0,
89 .iomem_base = (u8 *)UART3_ADDR,
90 .irq = AU1000_UART3_INT,
91 .flags = STD_COM_FLAGS,
92 .iomem_reg_shift = 2
93 }
94};
95
96#define UART_NR ARRAY_SIZE(old_serial_port)
97
98struct uart_8250_port {
99 struct uart_port port;
100 struct timer_list timer; /* "no irq" timer */
101 struct list_head list; /* ports on this IRQ */
102 unsigned short rev;
103 unsigned char acr;
104 unsigned char ier;
105 unsigned char lcr;
106 unsigned char mcr_mask; /* mask of user bits */
107 unsigned char mcr_force; /* mask of forced bits */
108 unsigned char lsr_break_flag;
109
110 /*
111 * We provide a per-port pm hook.
112 */
113 void (*pm)(struct uart_port *port,
114 unsigned int state, unsigned int old);
115};
116
117struct irq_info {
118 spinlock_t lock;
119 struct list_head *head;
120};
121
122static struct irq_info irq_lists[NR_IRQS];
123
124/*
125 * Here we define the default xmit fifo size used for each type of UART.
126 */
127static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
128 { "unknown", 1, 0 },
129 { "8250", 1, 0 },
130 { "16450", 1, 0 },
131 { "16550", 1, 0 },
132 /* PORT_16550A */
133 { "AU1X00_UART",16, UART_CLEAR_FIFO | UART_USE_FIFO },
134};
135
136static unsigned int serial_in(struct uart_8250_port *up, int offset)
137{
138 return au_readl((unsigned long)up->port.membase + offset);
139}
140
141static void serial_out(struct uart_8250_port *up, int offset, int value)
142{
143 au_writel(value, (unsigned long)up->port.membase + offset);
144}
145
146#define serial_inp(up, offset) serial_in(up, offset)
147#define serial_outp(up, offset, value) serial_out(up, offset, value)
148
149/*
150 * This routine is called by rs_init() to initialize a specific serial
151 * port. It determines what type of UART chip this serial port is
152 * using: 8250, 16450, 16550, 16550A. The important question is
153 * whether or not this UART is a 16550A or not, since this will
154 * determine whether or not we can use its FIFO features or not.
155 */
156static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
157{
158 unsigned char save_lcr, save_mcr;
159 unsigned long flags;
160
161 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
162 return;
163
164 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%08lx): ",
165 up->port.line, up->port.iobase, up->port.membase);
166
167 /*
168 * We really do need global IRQs disabled here - we're going to
169 * be frobbing the chips IRQ enable register to see if it exists.
170 */
171 spin_lock_irqsave(&up->port.lock, flags);
172// save_flags(flags); cli();
173
174 save_mcr = serial_in(up, UART_MCR);
175 save_lcr = serial_in(up, UART_LCR);
176
177 up->port.type = PORT_16550A;
178 serial_outp(up, UART_LCR, save_lcr);
179
180 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
181
182 if (up->port.type == PORT_UNKNOWN)
183 goto out;
184
185 /*
186 * Reset the UART.
187 */
188 serial_outp(up, UART_MCR, save_mcr);
189 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
190 UART_FCR_CLEAR_RCVR |
191 UART_FCR_CLEAR_XMIT));
192 serial_outp(up, UART_FCR, 0);
193 (void)serial_in(up, UART_RX);
194 serial_outp(up, UART_IER, 0);
195
196 out:
197 spin_unlock_irqrestore(&up->port.lock, flags);
198// restore_flags(flags);
199 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
200}
201
202static void serial8250_stop_tx(struct uart_port *port)
203{
204 struct uart_8250_port *up = (struct uart_8250_port *)port;
205
206 if (up->ier & UART_IER_THRI) {
207 up->ier &= ~UART_IER_THRI;
208 serial_out(up, UART_IER, up->ier);
209 }
210}
211
212static void serial8250_start_tx(struct uart_port *port)
213{
214 struct uart_8250_port *up = (struct uart_8250_port *)port;
215
216 if (!(up->ier & UART_IER_THRI)) {
217 up->ier |= UART_IER_THRI;
218 serial_out(up, UART_IER, up->ier);
219 }
220}
221
222static void serial8250_stop_rx(struct uart_port *port)
223{
224 struct uart_8250_port *up = (struct uart_8250_port *)port;
225
226 up->ier &= ~UART_IER_RLSI;
227 up->port.read_status_mask &= ~UART_LSR_DR;
228 serial_out(up, UART_IER, up->ier);
229}
230
231static void serial8250_enable_ms(struct uart_port *port)
232{
233 struct uart_8250_port *up = (struct uart_8250_port *)port;
234
235 up->ier |= UART_IER_MSI;
236 serial_out(up, UART_IER, up->ier);
237}
238
239static void
240receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
241{
242 struct tty_struct *tty = up->port.info->tty;
243 unsigned char ch, flag;
244 int max_count = 256;
245
246 do {
247 ch = serial_inp(up, UART_RX);
248 flag = TTY_NORMAL;
249 up->port.icount.rx++;
250
251 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
252 UART_LSR_FE | UART_LSR_OE))) {
253 /*
254 * For statistics only
255 */
256 if (*status & UART_LSR_BI) {
257 *status &= ~(UART_LSR_FE | UART_LSR_PE);
258 up->port.icount.brk++;
259 /*
260 * We do the SysRQ and SAK checking
261 * here because otherwise the break
262 * may get masked by ignore_status_mask
263 * or read_status_mask.
264 */
265 if (uart_handle_break(&up->port))
266 goto ignore_char;
267 } else if (*status & UART_LSR_PE)
268 up->port.icount.parity++;
269 else if (*status & UART_LSR_FE)
270 up->port.icount.frame++;
271 if (*status & UART_LSR_OE)
272 up->port.icount.overrun++;
273
274 /*
275 * Mask off conditions which should be ingored.
276 */
277 *status &= up->port.read_status_mask;
278
279#ifdef CONFIG_SERIAL_AU1X00_CONSOLE
280 if (up->port.line == up->port.cons->index) {
281 /* Recover the break flag from console xmit */
282 *status |= up->lsr_break_flag;
283 up->lsr_break_flag = 0;
284 }
285#endif
286 if (*status & UART_LSR_BI) {
287 DEBUG_INTR("handling break....");
288 flag = TTY_BREAK;
289 } else if (*status & UART_LSR_PE)
290 flag = TTY_PARITY;
291 else if (*status & UART_LSR_FE)
292 flag = TTY_FRAME;
293 }
294 if (uart_handle_sysrq_char(&up->port, ch, regs))
295 goto ignore_char;
296 if ((*status & up->port.ignore_status_mask) == 0)
297 tty_insert_flip_char(tty, ch, flag);
298 if (*status & UART_LSR_OE)
299 /*
300 * Overrun is special, since it's reported
301 * immediately, and doesn't affect the current
302 * character.
303 */
304 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
305 }
306 ignore_char:
307 *status = serial_inp(up, UART_LSR);
308 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
309 spin_unlock(&up->port.lock);
310 tty_flip_buffer_push(tty);
311 spin_lock(&up->port.lock);
312}
313
314static void transmit_chars(struct uart_8250_port *up)
315{
316 struct circ_buf *xmit = &up->port.info->xmit;
317 int count;
318
319 if (up->port.x_char) {
320 serial_outp(up, UART_TX, up->port.x_char);
321 up->port.icount.tx++;
322 up->port.x_char = 0;
323 return;
324 }
325 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
326 serial8250_stop_tx(&up->port);
327 return;
328 }
329
330 count = up->port.fifosize;
331 do {
332 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
333 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
334 up->port.icount.tx++;
335 if (uart_circ_empty(xmit))
336 break;
337 } while (--count > 0);
338
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(&up->port);
341
342 DEBUG_INTR("THRE...");
343
344 if (uart_circ_empty(xmit))
345 serial8250_stop_tx(&up->port);
346}
347
348static void check_modem_status(struct uart_8250_port *up)
349{
350 int status;
351
352 status = serial_in(up, UART_MSR);
353
354 if ((status & UART_MSR_ANY_DELTA) == 0)
355 return;
356
357 if (status & UART_MSR_TERI)
358 up->port.icount.rng++;
359 if (status & UART_MSR_DDSR)
360 up->port.icount.dsr++;
361 if (status & UART_MSR_DDCD)
362 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
363 if (status & UART_MSR_DCTS)
364 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
365
366 wake_up_interruptible(&up->port.info->delta_msr_wait);
367}
368
369/*
370 * This handles the interrupt from one port.
371 */
372static inline void
373serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
374{
375 unsigned int status = serial_inp(up, UART_LSR);
376
377 DEBUG_INTR("status = %x...", status);
378
379 if (status & UART_LSR_DR)
380 receive_chars(up, &status, regs);
381 check_modem_status(up);
382 if (status & UART_LSR_THRE)
383 transmit_chars(up);
384}
385
386/*
387 * This is the serial driver's interrupt routine.
388 *
389 * Arjan thinks the old way was overly complex, so it got simplified.
390 * Alan disagrees, saying that need the complexity to handle the weird
391 * nature of ISA shared interrupts. (This is a special exception.)
392 *
393 * In order to handle ISA shared interrupts properly, we need to check
394 * that all ports have been serviced, and therefore the ISA interrupt
395 * line has been de-asserted.
396 *
397 * This means we need to loop through all ports. checking that they
398 * don't have an interrupt pending.
399 */
400static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
401{
402 struct irq_info *i = dev_id;
403 struct list_head *l, *end = NULL;
404 int pass_counter = 0;
405
406 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
407
408 spin_lock(&i->lock);
409
410 l = i->head;
411 do {
412 struct uart_8250_port *up;
413 unsigned int iir;
414
415 up = list_entry(l, struct uart_8250_port, list);
416
417 iir = serial_in(up, UART_IIR);
418 if (!(iir & UART_IIR_NO_INT)) {
419 spin_lock(&up->port.lock);
420 serial8250_handle_port(up, regs);
421 spin_unlock(&up->port.lock);
422
423 end = NULL;
424 } else if (end == NULL)
425 end = l;
426
427 l = l->next;
428
429 if (l == i->head && pass_counter++ > PASS_LIMIT) {
430 /* If we hit this, we're dead. */
431 printk(KERN_ERR "serial8250: too much work for "
432 "irq%d\n", irq);
433 break;
434 }
435 } while (l != end);
436
437 spin_unlock(&i->lock);
438
439 DEBUG_INTR("end.\n");
440 /* FIXME! Was it really ours? */
441 return IRQ_HANDLED;
442}
443
444/*
445 * To support ISA shared interrupts, we need to have one interrupt
446 * handler that ensures that the IRQ line has been deasserted
447 * before returning. Failing to do this will result in the IRQ
448 * line being stuck active, and, since ISA irqs are edge triggered,
449 * no more IRQs will be seen.
450 */
451static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
452{
453 spin_lock_irq(&i->lock);
454
455 if (!list_empty(i->head)) {
456 if (i->head == &up->list)
457 i->head = i->head->next;
458 list_del(&up->list);
459 } else {
460 BUG_ON(i->head != &up->list);
461 i->head = NULL;
462 }
463
464 spin_unlock_irq(&i->lock);
465}
466
467static int serial_link_irq_chain(struct uart_8250_port *up)
468{
469 struct irq_info *i = irq_lists + up->port.irq;
470 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
471
472 spin_lock_irq(&i->lock);
473
474 if (i->head) {
475 list_add(&up->list, i->head);
476 spin_unlock_irq(&i->lock);
477
478 ret = 0;
479 } else {
480 INIT_LIST_HEAD(&up->list);
481 i->head = &up->list;
482 spin_unlock_irq(&i->lock);
483
484 ret = request_irq(up->port.irq, serial8250_interrupt,
485 irq_flags, "serial", i);
486 if (ret < 0)
487 serial_do_unlink(i, up);
488 }
489
490 return ret;
491}
492
493static void serial_unlink_irq_chain(struct uart_8250_port *up)
494{
495 struct irq_info *i = irq_lists + up->port.irq;
496
497 BUG_ON(i->head == NULL);
498
499 if (list_empty(i->head))
500 free_irq(up->port.irq, i);
501
502 serial_do_unlink(i, up);
503}
504
505/*
506 * This function is used to handle ports that do not have an
507 * interrupt. This doesn't work very well for 16450's, but gives
508 * barely passable results for a 16550A. (Although at the expense
509 * of much CPU overhead).
510 */
511static void serial8250_timeout(unsigned long data)
512{
513 struct uart_8250_port *up = (struct uart_8250_port *)data;
514 unsigned int timeout;
515 unsigned int iir;
516
517 iir = serial_in(up, UART_IIR);
518 if (!(iir & UART_IIR_NO_INT)) {
519 spin_lock(&up->port.lock);
520 serial8250_handle_port(up, NULL);
521 spin_unlock(&up->port.lock);
522 }
523
524 timeout = up->port.timeout;
525 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
526 mod_timer(&up->timer, jiffies + timeout);
527}
528
529static unsigned int serial8250_tx_empty(struct uart_port *port)
530{
531 struct uart_8250_port *up = (struct uart_8250_port *)port;
532 unsigned long flags;
533 unsigned int ret;
534
535 spin_lock_irqsave(&up->port.lock, flags);
536 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
537 spin_unlock_irqrestore(&up->port.lock, flags);
538
539 return ret;
540}
541
542static unsigned int serial8250_get_mctrl(struct uart_port *port)
543{
544 struct uart_8250_port *up = (struct uart_8250_port *)port;
545 unsigned char status;
546 unsigned int ret;
547
548 status = serial_in(up, UART_MSR);
549
550 ret = 0;
551 if (status & UART_MSR_DCD)
552 ret |= TIOCM_CAR;
553 if (status & UART_MSR_RI)
554 ret |= TIOCM_RNG;
555 if (status & UART_MSR_DSR)
556 ret |= TIOCM_DSR;
557 if (status & UART_MSR_CTS)
558 ret |= TIOCM_CTS;
559 return ret;
560}
561
562static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
563{
564 struct uart_8250_port *up = (struct uart_8250_port *)port;
565 unsigned char mcr = 0;
566
567 if (mctrl & TIOCM_RTS)
568 mcr |= UART_MCR_RTS;
569 if (mctrl & TIOCM_DTR)
570 mcr |= UART_MCR_DTR;
571 if (mctrl & TIOCM_OUT1)
572 mcr |= UART_MCR_OUT1;
573 if (mctrl & TIOCM_OUT2)
574 mcr |= UART_MCR_OUT2;
575 if (mctrl & TIOCM_LOOP)
576 mcr |= UART_MCR_LOOP;
577
578 mcr = (mcr & up->mcr_mask) | up->mcr_force;
579
580 serial_out(up, UART_MCR, mcr);
581}
582
583static void serial8250_break_ctl(struct uart_port *port, int break_state)
584{
585 struct uart_8250_port *up = (struct uart_8250_port *)port;
586 unsigned long flags;
587
588 spin_lock_irqsave(&up->port.lock, flags);
589 if (break_state == -1)
590 up->lcr |= UART_LCR_SBC;
591 else
592 up->lcr &= ~UART_LCR_SBC;
593 serial_out(up, UART_LCR, up->lcr);
594 spin_unlock_irqrestore(&up->port.lock, flags);
595}
596
597static int serial8250_startup(struct uart_port *port)
598{
599 struct uart_8250_port *up = (struct uart_8250_port *)port;
600 unsigned long flags;
601 int retval;
602
603 /*
604 * Clear the FIFO buffers and disable them.
605 * (they will be reeanbled in set_termios())
606 */
607 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
608 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
609 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
610 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
611 serial_outp(up, UART_FCR, 0);
612 }
613
614 /*
615 * Clear the interrupt registers.
616 */
617 (void) serial_inp(up, UART_LSR);
618 (void) serial_inp(up, UART_RX);
619 (void) serial_inp(up, UART_IIR);
620 (void) serial_inp(up, UART_MSR);
621
622 /*
623 * At this point, there's no way the LSR could still be 0xff;
624 * if it is, then bail out, because there's likely no UART
625 * here.
626 */
627 if (!(up->port.flags & UPF_BUGGY_UART) &&
628 (serial_inp(up, UART_LSR) == 0xff)) {
629 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
630 return -ENODEV;
631 }
632
633 retval = serial_link_irq_chain(up);
634 if (retval)
635 return retval;
636
637 /*
638 * Now, initialize the UART
639 */
640 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
641
642 spin_lock_irqsave(&up->port.lock, flags);
643 if (up->port.flags & UPF_FOURPORT) {
644 if (!is_real_interrupt(up->port.irq))
645 up->port.mctrl |= TIOCM_OUT1;
646 } else
647 /*
648 * Most PC uarts need OUT2 raised to enable interrupts.
649 */
650 if (is_real_interrupt(up->port.irq))
651 up->port.mctrl |= TIOCM_OUT2;
652
653 serial8250_set_mctrl(&up->port, up->port.mctrl);
654 spin_unlock_irqrestore(&up->port.lock, flags);
655
656 /*
657 * Finally, enable interrupts. Note: Modem status interrupts
658 * are set via set_termios(), which will be occurring imminently
659 * anyway, so we don't enable them here.
660 */
661 up->ier = UART_IER_RLSI | UART_IER_RDI;
662 serial_outp(up, UART_IER, up->ier);
663
664 if (up->port.flags & UPF_FOURPORT) {
665 unsigned int icp;
666 /*
667 * Enable interrupts on the AST Fourport board
668 */
669 icp = (up->port.iobase & 0xfe0) | 0x01f;
670 outb_p(0x80, icp);
671 (void) inb_p(icp);
672 }
673
674 /*
675 * And clear the interrupt registers again for luck.
676 */
677 (void) serial_inp(up, UART_LSR);
678 (void) serial_inp(up, UART_RX);
679 (void) serial_inp(up, UART_IIR);
680 (void) serial_inp(up, UART_MSR);
681
682 return 0;
683}
684
685static void serial8250_shutdown(struct uart_port *port)
686{
687 struct uart_8250_port *up = (struct uart_8250_port *)port;
688 unsigned long flags;
689
690 /*
691 * Disable interrupts from this port
692 */
693 up->ier = 0;
694 serial_outp(up, UART_IER, 0);
695
696 spin_lock_irqsave(&up->port.lock, flags);
697 if (up->port.flags & UPF_FOURPORT) {
698 /* reset interrupts on the AST Fourport board */
699 inb((up->port.iobase & 0xfe0) | 0x1f);
700 up->port.mctrl |= TIOCM_OUT1;
701 } else
702 up->port.mctrl &= ~TIOCM_OUT2;
703
704 serial8250_set_mctrl(&up->port, up->port.mctrl);
705 spin_unlock_irqrestore(&up->port.lock, flags);
706
707 /*
708 * Disable break condition and FIFOs
709 */
710 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
711 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
712 UART_FCR_CLEAR_RCVR |
713 UART_FCR_CLEAR_XMIT);
714 serial_outp(up, UART_FCR, 0);
715
716 /*
717 * Read data port to reset things, and then unlink from
718 * the IRQ chain.
719 */
720 (void) serial_in(up, UART_RX);
721
722 if (!is_real_interrupt(up->port.irq))
723 del_timer_sync(&up->timer);
724 else
725 serial_unlink_irq_chain(up);
726}
727
728static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
729{
730 unsigned int quot;
731
732 /*
733 * Handle magic divisors for baud rates above baud_base on
734 * SMSC SuperIO chips.
735 */
736 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
737 baud == (port->uartclk/4))
738 quot = 0x8001;
739 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
740 baud == (port->uartclk/8))
741 quot = 0x8002;
742 else
743 quot = uart_get_divisor(port, baud);
744
745 return quot;
746}
747
748static void
749serial8250_set_termios(struct uart_port *port, struct termios *termios,
750 struct termios *old)
751{
752 struct uart_8250_port *up = (struct uart_8250_port *)port;
753 unsigned char cval, fcr = 0;
754 unsigned long flags;
755 unsigned int baud, quot;
756
757 switch (termios->c_cflag & CSIZE) {
758 case CS5:
759 cval = UART_LCR_WLEN5;
760 break;
761 case CS6:
762 cval = UART_LCR_WLEN6;
763 break;
764 case CS7:
765 cval = UART_LCR_WLEN7;
766 break;
767 default:
768 case CS8:
769 cval = UART_LCR_WLEN8;
770 break;
771 }
772
773 if (termios->c_cflag & CSTOPB)
774 cval |= UART_LCR_STOP;
775 if (termios->c_cflag & PARENB)
776 cval |= UART_LCR_PARITY;
777 if (!(termios->c_cflag & PARODD))
778 cval |= UART_LCR_EPAR;
779#ifdef CMSPAR
780 if (termios->c_cflag & CMSPAR)
781 cval |= UART_LCR_SPAR;
782#endif
783
784 /*
785 * Ask the core to calculate the divisor for us.
786 */
787 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
788 quot = serial8250_get_divisor(port, baud);
789 quot = 0x35; /* FIXME */
790
791 /*
792 * Work around a bug in the Oxford Semiconductor 952 rev B
793 * chip which causes it to seriously miscalculate baud rates
794 * when DLL is 0.
795 */
796 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
797 up->rev == 0x5201)
798 quot ++;
799
800 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
801 if (baud < 2400)
802 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIGGER_1;
803 else
804 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIGGER_8;
805 }
806
807 /*
808 * Ok, we're now changing the port state. Do it with
809 * interrupts disabled.
810 */
811 spin_lock_irqsave(&up->port.lock, flags);
812
813 /*
814 * Update the per-port timeout.
815 */
816 uart_update_timeout(port, termios->c_cflag, baud);
817
818 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
819 if (termios->c_iflag & INPCK)
820 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
821 if (termios->c_iflag & (BRKINT | PARMRK))
822 up->port.read_status_mask |= UART_LSR_BI;
823
824 /*
825 * Characteres to ignore
826 */
827 up->port.ignore_status_mask = 0;
828 if (termios->c_iflag & IGNPAR)
829 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
830 if (termios->c_iflag & IGNBRK) {
831 up->port.ignore_status_mask |= UART_LSR_BI;
832 /*
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too (for real raw support).
835 */
836 if (termios->c_iflag & IGNPAR)
837 up->port.ignore_status_mask |= UART_LSR_OE;
838 }
839
840 /*
841 * ignore all characters if CREAD is not set
842 */
843 if ((termios->c_cflag & CREAD) == 0)
844 up->port.ignore_status_mask |= UART_LSR_DR;
845
846 /*
847 * CTS flow control flag and modem status interrupts
848 */
849 up->ier &= ~UART_IER_MSI;
850 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
851 up->ier |= UART_IER_MSI;
852
853 serial_out(up, UART_IER, up->ier);
854 serial_outp(up, 0x28, quot & 0xffff);
855 up->lcr = cval; /* Save LCR */
856 if (up->port.type != PORT_16750) {
857 if (fcr & UART_FCR_ENABLE_FIFO) {
858 /* emulated UARTs (Lucent Venus 167x) need two steps */
859 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
860 }
861 serial_outp(up, UART_FCR, fcr); /* set fcr */
862 }
863 spin_unlock_irqrestore(&up->port.lock, flags);
864}
865
866static void
867serial8250_pm(struct uart_port *port, unsigned int state,
868 unsigned int oldstate)
869{
870 struct uart_8250_port *up = (struct uart_8250_port *)port;
871 if (state) {
872 /* sleep */
873 if (up->pm)
874 up->pm(port, state, oldstate);
875 } else {
876 /* wake */
877 if (up->pm)
878 up->pm(port, state, oldstate);
879 }
880}
881
882/*
883 * Resource handling. This is complicated by the fact that resources
884 * depend on the port type. Maybe we should be claiming the standard
885 * 8250 ports, and then trying to get other resources as necessary?
886 */
887static int
888serial8250_request_std_resource(struct uart_8250_port *up, struct resource **res)
889{
890 unsigned int size = 8 << up->port.regshift;
891 int ret = 0;
892
893 switch (up->port.iotype) {
894 case UPIO_MEM:
895 if (up->port.mapbase) {
896 *res = request_mem_region(up->port.mapbase, size, "serial");
897 if (!*res)
898 ret = -EBUSY;
899 }
900 break;
901
902 case UPIO_HUB6:
903 case UPIO_PORT:
904 *res = request_region(up->port.iobase, size, "serial");
905 if (!*res)
906 ret = -EBUSY;
907 break;
908 }
909 return ret;
910}
911
912
913static void serial8250_release_port(struct uart_port *port)
914{
915 struct uart_8250_port *up = (struct uart_8250_port *)port;
916 unsigned long start, offset = 0, size = 0;
917
918 size <<= up->port.regshift;
919
920 switch (up->port.iotype) {
921 case UPIO_MEM:
922 if (up->port.mapbase) {
923 /*
924 * Unmap the area.
925 */
926 iounmap(up->port.membase);
927 up->port.membase = NULL;
928
929 start = up->port.mapbase;
930
931 if (size)
932 release_mem_region(start + offset, size);
933 release_mem_region(start, 8 << up->port.regshift);
934 }
935 break;
936
937 case UPIO_HUB6:
938 case UPIO_PORT:
939 start = up->port.iobase;
940
941 if (size)
942 release_region(start + offset, size);
943 release_region(start + offset, 8 << up->port.regshift);
944 break;
945
946 default:
947 break;
948 }
949}
950
951static int serial8250_request_port(struct uart_port *port)
952{
953 struct uart_8250_port *up = (struct uart_8250_port *)port;
954 struct resource *res = NULL, *res_rsa = NULL;
955 int ret = 0;
956
957 ret = serial8250_request_std_resource(up, &res);
958
959 /*
960 * If we have a mapbase, then request that as well.
961 */
962 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
963 int size = res->end - res->start + 1;
964
965 up->port.membase = ioremap(up->port.mapbase, size);
966 if (!up->port.membase)
967 ret = -ENOMEM;
968 }
969
970 if (ret < 0) {
971 if (res_rsa)
972 release_resource(res_rsa);
973 if (res)
974 release_resource(res);
975 }
976 return ret;
977}
978
979static void serial8250_config_port(struct uart_port *port, int flags)
980{
981 struct uart_8250_port *up = (struct uart_8250_port *)port;
982 struct resource *res_std = NULL, *res_rsa = NULL;
983 int probeflags = PROBE_ANY;
984
985 probeflags &= ~PROBE_RSA;
986
987 if (flags & UART_CONFIG_TYPE)
988 autoconfig(up, probeflags);
989
990 /*
991 * If the port wasn't an RSA port, release the resource.
992 */
993 if (up->port.type != PORT_RSA && res_rsa)
994 release_resource(res_rsa);
995
996 if (up->port.type == PORT_UNKNOWN && res_std)
997 release_resource(res_std);
998}
999
1000static int
1001serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
1002{
1003 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
1004 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
1005 ser->type > PORT_MAX_8250 || ser->type == PORT_CIRRUS ||
1006 ser->type == PORT_STARTECH)
1007 return -EINVAL;
1008 return 0;
1009}
1010
1011static const char *
1012serial8250_type(struct uart_port *port)
1013{
1014 int type = port->type;
1015
1016 if (type >= ARRAY_SIZE(uart_config))
1017 type = 0;
1018 return uart_config[type].name;
1019}
1020
1021static struct uart_ops serial8250_pops = {
1022 .tx_empty = serial8250_tx_empty,
1023 .set_mctrl = serial8250_set_mctrl,
1024 .get_mctrl = serial8250_get_mctrl,
1025 .stop_tx = serial8250_stop_tx,
1026 .start_tx = serial8250_start_tx,
1027 .stop_rx = serial8250_stop_rx,
1028 .enable_ms = serial8250_enable_ms,
1029 .break_ctl = serial8250_break_ctl,
1030 .startup = serial8250_startup,
1031 .shutdown = serial8250_shutdown,
1032 .set_termios = serial8250_set_termios,
1033 .pm = serial8250_pm,
1034 .type = serial8250_type,
1035 .release_port = serial8250_release_port,
1036 .request_port = serial8250_request_port,
1037 .config_port = serial8250_config_port,
1038 .verify_port = serial8250_verify_port,
1039};
1040
1041static struct uart_8250_port serial8250_ports[UART_NR];
1042
1043static void __init serial8250_isa_init_ports(void)
1044{
1045 struct uart_8250_port *up;
1046 static int first = 1;
1047 int i;
1048
1049 if (!first)
1050 return;
1051 first = 0;
1052
1053 for (i = 0, up = serial8250_ports; i < ARRAY_SIZE(old_serial_port);
1054 i++, up++) {
1055 up->port.iobase = old_serial_port[i].port;
1056 up->port.irq = old_serial_port[i].irq;
1057 up->port.uartclk = get_au1x00_uart_baud_base();
1058 up->port.flags = old_serial_port[i].flags;
1059 up->port.hub6 = old_serial_port[i].hub6;
1060 up->port.membase = old_serial_port[i].iomem_base;
1061 up->port.iotype = old_serial_port[i].io_type;
1062 up->port.regshift = old_serial_port[i].iomem_reg_shift;
1063 up->port.ops = &serial8250_pops;
1064 }
1065}
1066
1067static void __init serial8250_register_ports(struct uart_driver *drv)
1068{
1069 int i;
1070
1071 serial8250_isa_init_ports();
1072
1073 for (i = 0; i < UART_NR; i++) {
1074 struct uart_8250_port *up = &serial8250_ports[i];
1075
1076 up->port.line = i;
1077 up->port.ops = &serial8250_pops;
1078 init_timer(&up->timer);
1079 up->timer.function = serial8250_timeout;
1080
1081 /*
1082 * ALPHA_KLUDGE_MCR needs to be killed.
1083 */
1084 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
1085 up->mcr_force = ALPHA_KLUDGE_MCR;
1086
1087 uart_add_one_port(drv, &up->port);
1088 }
1089}
1090
1091#ifdef CONFIG_SERIAL_AU1X00_CONSOLE
1092
1093#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1094
1095/*
1096 * Wait for transmitter & holding register to empty
1097 */
1098static inline void wait_for_xmitr(struct uart_8250_port *up)
1099{
1100 unsigned int status, tmout = 10000;
1101
1102 /* Wait up to 10ms for the character(s) to be sent. */
1103 do {
1104 status = serial_in(up, UART_LSR);
1105
1106 if (status & UART_LSR_BI)
1107 up->lsr_break_flag = UART_LSR_BI;
1108
1109 if (--tmout == 0)
1110 break;
1111 udelay(1);
1112 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1113
1114 /* Wait up to 1s for flow control if necessary */
1115 if (up->port.flags & UPF_CONS_FLOW) {
1116 tmout = 1000000;
1117 while (--tmout &&
1118 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1119 udelay(1);
1120 }
1121}
1122
1123static void au1x00_console_putchar(struct uart_port *port, int ch)
1124{
1125 struct uart_8250_port *up = (struct uart_8250_port *)port;
1126
1127 wait_for_xmitr(up);
1128 serial_out(up, UART_TX, ch);
1129}
1130
1131/*
1132 * Print a string to the serial port trying not to disturb
1133 * any possible real use of the port...
1134 *
1135 * The console_lock must be held when we get here.
1136 */
1137static void
1138serial8250_console_write(struct console *co, const char *s, unsigned int count)
1139{
1140 struct uart_8250_port *up = &serial8250_ports[co->index];
1141 unsigned int ier;
1142
1143 /*
1144 * First save the UER then disable the interrupts
1145 */
1146 ier = serial_in(up, UART_IER);
1147 serial_out(up, UART_IER, 0);
1148
1149 uart_console_write(&up->port, s, count, au1x00_console_putchar);
1150
1151 /*
1152 * Finally, wait for transmitter to become empty
1153 * and restore the IER
1154 */
1155 wait_for_xmitr(up);
1156 serial_out(up, UART_IER, ier);
1157}
1158
1159static int __init serial8250_console_setup(struct console *co, char *options)
1160{
1161 struct uart_port *port;
1162 int baud = 9600;
1163 int bits = 8;
1164 int parity = 'n';
1165 int flow = 'n';
1166
1167 /*
1168 * Check whether an invalid uart number has been specified, and
1169 * if so, search for the first available port that does have
1170 * console support.
1171 */
1172 if (co->index >= UART_NR)
1173 co->index = 0;
1174 port = &serial8250_ports[co->index].port;
1175
1176 /*
1177 * Temporary fix.
1178 */
1179 spin_lock_init(&port->lock);
1180
1181 if (options)
1182 uart_parse_options(options, &baud, &parity, &bits, &flow);
1183
1184 return uart_set_options(port, co, baud, parity, bits, flow);
1185}
1186
1187extern struct uart_driver serial8250_reg;
1188static struct console serial8250_console = {
1189 .name = "ttyS",
1190 .write = serial8250_console_write,
1191 .device = uart_console_device,
1192 .setup = serial8250_console_setup,
1193 .flags = CON_PRINTBUFFER,
1194 .index = -1,
1195 .data = &serial8250_reg,
1196};
1197
1198static int __init serial8250_console_init(void)
1199{
1200 serial8250_isa_init_ports();
1201 register_console(&serial8250_console);
1202 return 0;
1203}
1204console_initcall(serial8250_console_init);
1205
1206#define SERIAL8250_CONSOLE &serial8250_console
1207#else
1208#define SERIAL8250_CONSOLE NULL
1209#endif
1210
1211static struct uart_driver serial8250_reg = {
1212 .owner = THIS_MODULE,
1213 .driver_name = "serial",
1214 .devfs_name = "tts/",
1215 .dev_name = "ttyS",
1216 .major = TTY_MAJOR,
1217 .minor = 64,
1218 .nr = UART_NR,
1219 .cons = SERIAL8250_CONSOLE,
1220};
1221
1222int __init early_serial_setup(struct uart_port *port)
1223{
1224 serial8250_isa_init_ports();
1225 serial8250_ports[port->line].port = *port;
1226 serial8250_ports[port->line].port.ops = &serial8250_pops;
1227 return 0;
1228}
1229
1230/**
1231 * serial8250_suspend_port - suspend one serial port
1232 * @line: serial line number
1233 * @level: the level of port suspension, as per uart_suspend_port
1234 *
1235 * Suspend one serial port.
1236 */
1237void serial8250_suspend_port(int line)
1238{
1239 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
1240}
1241
1242/**
1243 * serial8250_resume_port - resume one serial port
1244 * @line: serial line number
1245 * @level: the level of port resumption, as per uart_resume_port
1246 *
1247 * Resume one serial port.
1248 */
1249void serial8250_resume_port(int line)
1250{
1251 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
1252}
1253
1254static int __init serial8250_init(void)
1255{
1256 int ret, i;
1257
1258 printk(KERN_INFO "Serial: Au1x00 driver\n");
1259
1260 for (i = 0; i < NR_IRQS; i++)
1261 spin_lock_init(&irq_lists[i].lock);
1262
1263 ret = uart_register_driver(&serial8250_reg);
1264 if (ret >= 0)
1265 serial8250_register_ports(&serial8250_reg);
1266
1267 return ret;
1268}
1269
1270static void __exit serial8250_exit(void)
1271{
1272 int i;
1273
1274 for (i = 0; i < UART_NR; i++)
1275 uart_remove_one_port(&serial8250_reg, &serial8250_ports[i].port);
1276
1277 uart_unregister_driver(&serial8250_reg);
1278}
1279
1280module_init(serial8250_init);
1281module_exit(serial8250_exit);
1282
1283EXPORT_SYMBOL(serial8250_suspend_port);
1284EXPORT_SYMBOL(serial8250_resume_port);
1285
1286MODULE_LICENSE("GPL");
1287MODULE_DESCRIPTION("Au1x00 serial driver\n");
diff --git a/drivers/serial/ioc4_serial.c b/drivers/serial/ioc4_serial.c
index a37579ce6d76..c620209d7b9a 100644
--- a/drivers/serial/ioc4_serial.c
+++ b/drivers/serial/ioc4_serial.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved. 6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */ 7 */
8 8
9 9
@@ -323,9 +323,12 @@ static unsigned int Num_of_ioc4_cards;
323#define IOC4_FIFO_CHARS 255 323#define IOC4_FIFO_CHARS 255
324 324
325/* Device name we're using */ 325/* Device name we're using */
326#define DEVICE_NAME "ttyIOC" 326#define DEVICE_NAME_RS232 "ttyIOC"
327#define DEVICE_MAJOR 204 327#define DEVICE_NAME_RS422 "ttyAIOC"
328#define DEVICE_MINOR 50 328#define DEVICE_MAJOR 204
329#define DEVICE_MINOR_RS232 50
330#define DEVICE_MINOR_RS422 84
331
329 332
330/* register offsets */ 333/* register offsets */
331#define IOC4_SERIAL_OFFSET 0x300 334#define IOC4_SERIAL_OFFSET 0x300
@@ -341,10 +344,8 @@ static unsigned int Num_of_ioc4_cards;
341#define MAX_BAUD_SUPPORTED 115200 344#define MAX_BAUD_SUPPORTED 115200
342 345
343/* protocol types supported */ 346/* protocol types supported */
344enum sio_proto { 347#define PROTO_RS232 3
345 PROTO_RS232, 348#define PROTO_RS422 7
346 PROTO_RS422
347};
348 349
349/* Notification types */ 350/* Notification types */
350#define N_DATA_READY 0x01 351#define N_DATA_READY 0x01
@@ -395,11 +396,17 @@ enum sio_proto {
395/* 396/*
396 * This is the entry saved by the driver - one per card 397 * This is the entry saved by the driver - one per card
397 */ 398 */
399
400#define UART_PORT_MIN 0
401#define UART_PORT_RS232 UART_PORT_MIN
402#define UART_PORT_RS422 1
403#define UART_PORT_COUNT 2 /* one for each mode */
404
398struct ioc4_control { 405struct ioc4_control {
399 int ic_irq; 406 int ic_irq;
400 struct { 407 struct {
401 /* uart ports are allocated here */ 408 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
402 struct uart_port icp_uart_port; 409 struct uart_port icp_uart_port[UART_PORT_COUNT];
403 /* Handy reference material */ 410 /* Handy reference material */
404 struct ioc4_port *icp_port; 411 struct ioc4_port *icp_port;
405 } ic_port[IOC4_NUM_SERIAL_PORTS]; 412 } ic_port[IOC4_NUM_SERIAL_PORTS];
@@ -443,7 +450,9 @@ struct ioc4_soft {
443 450
444/* Local port info for each IOC4 serial ports */ 451/* Local port info for each IOC4 serial ports */
445struct ioc4_port { 452struct ioc4_port {
446 struct uart_port *ip_port; 453 struct uart_port *ip_port; /* current active port ptr */
454 /* Ptrs for all ports */
455 struct uart_port *ip_all_ports[UART_PORT_COUNT];
447 /* Back ptrs for this port */ 456 /* Back ptrs for this port */
448 struct ioc4_control *ip_control; 457 struct ioc4_control *ip_control;
449 struct pci_dev *ip_pdev; 458 struct pci_dev *ip_pdev;
@@ -502,6 +511,9 @@ struct ioc4_port {
502#define DCD_ON 0x02 511#define DCD_ON 0x02
503#define LOWAT_WRITTEN 0x04 512#define LOWAT_WRITTEN 0x04
504#define READ_ABORTED 0x08 513#define READ_ABORTED 0x08
514#define PORT_ACTIVE 0x10
515#define PORT_INACTIVE 0 /* This is the value when "off" */
516
505 517
506/* Since each port has different register offsets and bitmasks 518/* Since each port has different register offsets and bitmasks
507 * for everything, we'll store those that we need in tables so we 519 * for everything, we'll store those that we need in tables so we
@@ -623,6 +635,23 @@ struct ring_buffer {
623static void receive_chars(struct uart_port *); 635static void receive_chars(struct uart_port *);
624static void handle_intr(void *arg, uint32_t sio_ir); 636static void handle_intr(void *arg, uint32_t sio_ir);
625 637
638/*
639 * port_is_active - determines if this port is currently active
640 * @port: ptr to soft struct for this port
641 * @uart_port: uart port to test for
642 */
643static inline int port_is_active(struct ioc4_port *port,
644 struct uart_port *uart_port)
645{
646 if (port) {
647 if ((port->ip_flags & PORT_ACTIVE)
648 && (port->ip_port == uart_port))
649 return 1;
650 }
651 return 0;
652}
653
654
626/** 655/**
627 * write_ireg - write the interrupt regs 656 * write_ireg - write the interrupt regs
628 * @ioc4_soft: ptr to soft struct for this port 657 * @ioc4_soft: ptr to soft struct for this port
@@ -708,19 +737,33 @@ static int set_baud(struct ioc4_port *port, int baud)
708/** 737/**
709 * get_ioc4_port - given a uart port, return the control structure 738 * get_ioc4_port - given a uart port, return the control structure
710 * @port: uart port 739 * @port: uart port
740 * @set: set this port as current
711 */ 741 */
712static struct ioc4_port *get_ioc4_port(struct uart_port *the_port) 742static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
713{ 743{
714 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev); 744 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
715 struct ioc4_control *control = idd->idd_serial_data; 745 struct ioc4_control *control = idd->idd_serial_data;
716 int ii; 746 struct ioc4_port *port;
747 int port_num, port_type;
717 748
718 if (control) { 749 if (control) {
719 for ( ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++ ) { 750 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
720 if (!control->ic_port[ii].icp_port) 751 port_num++ ) {
752 port = control->ic_port[port_num].icp_port;
753 if (!port)
721 continue; 754 continue;
722 if (the_port == control->ic_port[ii].icp_port->ip_port) 755 for (port_type = UART_PORT_MIN;
723 return control->ic_port[ii].icp_port; 756 port_type < UART_PORT_COUNT;
757 port_type++) {
758 if (the_port == port->ip_all_ports
759 [port_type]) {
760 /* set local copy */
761 if (set) {
762 port->ip_port = the_port;
763 }
764 return port;
765 }
766 }
724 } 767 }
725 } 768 }
726 return NULL; 769 return NULL;
@@ -946,6 +989,7 @@ intr_connect(struct ioc4_soft *soft, int type,
946 * @arg: handler arg 989 * @arg: handler arg
947 * @regs: registers 990 * @regs: registers
948 */ 991 */
992
949static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs) 993static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
950{ 994{
951 struct ioc4_soft *soft; 995 struct ioc4_soft *soft;
@@ -953,7 +997,7 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
953 int xx, num_intrs = 0; 997 int xx, num_intrs = 0;
954 int intr_type; 998 int intr_type;
955 int handled = 0; 999 int handled = 0;
956 struct ioc4_intr_info *ii; 1000 struct ioc4_intr_info *intr_info;
957 1001
958 soft = arg; 1002 soft = arg;
959 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) { 1003 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
@@ -966,13 +1010,13 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
966 * which interrupt bits are set. 1010 * which interrupt bits are set.
967 */ 1011 */
968 for (xx = 0; xx < num_intrs; xx++) { 1012 for (xx = 0; xx < num_intrs; xx++) {
969 ii = &soft->is_intr_type[intr_type].is_intr_info[xx]; 1013 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
970 if ((this_mir = this_ir & ii->sd_bits)) { 1014 if ((this_mir = this_ir & intr_info->sd_bits)) {
971 /* Disable owned interrupts, call handler */ 1015 /* Disable owned interrupts, call handler */
972 handled++; 1016 handled++;
973 write_ireg(soft, ii->sd_bits, IOC4_W_IEC, 1017 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
974 intr_type); 1018 intr_type);
975 ii->sd_intr(ii->sd_info, this_mir); 1019 intr_info->sd_intr(intr_info->sd_info, this_mir);
976 this_ir &= ~this_mir; 1020 this_ir &= ~this_mir;
977 } 1021 }
978 } 1022 }
@@ -980,7 +1024,6 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
980#ifdef DEBUG_INTERRUPTS 1024#ifdef DEBUG_INTERRUPTS
981 { 1025 {
982 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr; 1026 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
983 spinlock_t *lp = &soft->is_ir_lock;
984 unsigned long flag; 1027 unsigned long flag;
985 1028
986 spin_lock_irqsave(&soft->is_ir_lock, flag); 1029 spin_lock_irqsave(&soft->is_ir_lock, flag);
@@ -1177,7 +1220,7 @@ static inline int local_open(struct ioc4_port *port)
1177{ 1220{
1178 int spiniter = 0; 1221 int spiniter = 0;
1179 1222
1180 port->ip_flags = 0; 1223 port->ip_flags = PORT_ACTIVE;
1181 1224
1182 /* Pause the DMA interface if necessary */ 1225 /* Pause the DMA interface if necessary */
1183 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1226 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
@@ -1187,6 +1230,7 @@ static inline int local_open(struct ioc4_port *port)
1187 & IOC4_SSCR_PAUSE_STATE) == 0) { 1230 & IOC4_SSCR_PAUSE_STATE) == 0) {
1188 spiniter++; 1231 spiniter++;
1189 if (spiniter > MAXITER) { 1232 if (spiniter > MAXITER) {
1233 port->ip_flags = PORT_INACTIVE;
1190 return -1; 1234 return -1;
1191 } 1235 }
1192 } 1236 }
@@ -1506,14 +1550,13 @@ static int set_notification(struct ioc4_port *port, int mask, int set_on)
1506/** 1550/**
1507 * set_mcr - set the master control reg 1551 * set_mcr - set the master control reg
1508 * @the_port: port to use 1552 * @the_port: port to use
1509 * @set: set ?
1510 * @mask1: mcr mask 1553 * @mask1: mcr mask
1511 * @mask2: shadow mask 1554 * @mask2: shadow mask
1512 */ 1555 */
1513static inline int set_mcr(struct uart_port *the_port, int set, 1556static inline int set_mcr(struct uart_port *the_port,
1514 int mask1, int mask2) 1557 int mask1, int mask2)
1515{ 1558{
1516 struct ioc4_port *port = get_ioc4_port(the_port); 1559 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1517 uint32_t shadow; 1560 uint32_t shadow;
1518 int spiniter = 0; 1561 int spiniter = 0;
1519 char mcr; 1562 char mcr;
@@ -1536,13 +1579,9 @@ static inline int set_mcr(struct uart_port *the_port, int set,
1536 mcr = (shadow & 0xff000000) >> 24; 1579 mcr = (shadow & 0xff000000) >> 24;
1537 1580
1538 /* Set new value */ 1581 /* Set new value */
1539 if (set) { 1582 mcr |= mask1;
1540 mcr |= mask1; 1583 shadow |= mask2;
1541 shadow |= mask2; 1584
1542 } else {
1543 mcr &= ~mask1;
1544 shadow &= ~mask2;
1545 }
1546 writeb(mcr, &port->ip_uart_regs->i4u_mcr); 1585 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1547 writel(shadow, &port->ip_serial_regs->shadow); 1586 writel(shadow, &port->ip_serial_regs->shadow);
1548 1587
@@ -1558,7 +1597,7 @@ static inline int set_mcr(struct uart_port *the_port, int set,
1558 * @port: port to use 1597 * @port: port to use
1559 * @proto: protocol to use 1598 * @proto: protocol to use
1560 */ 1599 */
1561static int ioc4_set_proto(struct ioc4_port *port, enum sio_proto proto) 1600static int ioc4_set_proto(struct ioc4_port *port, int proto)
1562{ 1601{
1563 struct hooks *hooks = port->ip_hooks; 1602 struct hooks *hooks = port->ip_hooks;
1564 1603
@@ -1589,7 +1628,7 @@ static void transmit_chars(struct uart_port *the_port)
1589 int result; 1628 int result;
1590 char *start; 1629 char *start;
1591 struct tty_struct *tty; 1630 struct tty_struct *tty;
1592 struct ioc4_port *port = get_ioc4_port(the_port); 1631 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1593 struct uart_info *info; 1632 struct uart_info *info;
1594 1633
1595 if (!the_port) 1634 if (!the_port)
@@ -1645,7 +1684,7 @@ static void
1645ioc4_change_speed(struct uart_port *the_port, 1684ioc4_change_speed(struct uart_port *the_port,
1646 struct termios *new_termios, struct termios *old_termios) 1685 struct termios *new_termios, struct termios *old_termios)
1647{ 1686{
1648 struct ioc4_port *port = get_ioc4_port(the_port); 1687 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1649 int baud, bits; 1688 int baud, bits;
1650 unsigned cflag; 1689 unsigned cflag;
1651 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8; 1690 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
@@ -1752,7 +1791,7 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1752 if (!the_port) 1791 if (!the_port)
1753 return -1; 1792 return -1;
1754 1793
1755 port = get_ioc4_port(the_port); 1794 port = get_ioc4_port(the_port, 0);
1756 if (!port) 1795 if (!port)
1757 return -1; 1796 return -1;
1758 1797
@@ -1760,6 +1799,9 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1760 1799
1761 local_open(port); 1800 local_open(port);
1762 1801
1802 /* set the protocol - mapbase has the port type */
1803 ioc4_set_proto(port, the_port->mapbase);
1804
1763 /* set the speed of the serial port */ 1805 /* set the speed of the serial port */
1764 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0); 1806 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0);
1765 1807
@@ -1768,17 +1810,17 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1768 1810
1769/* 1811/*
1770 * ioc4_cb_output_lowat - called when the output low water mark is hit 1812 * ioc4_cb_output_lowat - called when the output low water mark is hit
1771 * @port: port to output 1813 * @the_port: port to output
1772 */ 1814 */
1773static void ioc4_cb_output_lowat(struct ioc4_port *port) 1815static void ioc4_cb_output_lowat(struct uart_port *the_port)
1774{ 1816{
1775 unsigned long pflags; 1817 unsigned long pflags;
1776 1818
1777 /* ip_lock is set on the call here */ 1819 /* ip_lock is set on the call here */
1778 if (port->ip_port) { 1820 if (the_port) {
1779 spin_lock_irqsave(&port->ip_port->lock, pflags); 1821 spin_lock_irqsave(&the_port->lock, pflags);
1780 transmit_chars(port->ip_port); 1822 transmit_chars(the_port);
1781 spin_unlock_irqrestore(&port->ip_port->lock, pflags); 1823 spin_unlock_irqrestore(&the_port->lock, pflags);
1782 } 1824 }
1783} 1825}
1784 1826
@@ -1923,7 +1965,7 @@ static void handle_intr(void *arg, uint32_t sio_ir)
1923 &port->ip_mem->sio_ir.raw); 1965 &port->ip_mem->sio_ir.raw);
1924 1966
1925 if (port->ip_notify & N_OUTPUT_LOWAT) 1967 if (port->ip_notify & N_OUTPUT_LOWAT)
1926 ioc4_cb_output_lowat(port); 1968 ioc4_cb_output_lowat(port->ip_port);
1927 } 1969 }
1928 1970
1929 /* Handle tx_mt. Must come after tx_explicit. */ 1971 /* Handle tx_mt. Must come after tx_explicit. */
@@ -1936,7 +1978,7 @@ static void handle_intr(void *arg, uint32_t sio_ir)
1936 * So send the notification now. 1978 * So send the notification now.
1937 */ 1979 */
1938 if (port->ip_notify & N_OUTPUT_LOWAT) { 1980 if (port->ip_notify & N_OUTPUT_LOWAT) {
1939 ioc4_cb_output_lowat(port); 1981 ioc4_cb_output_lowat(port->ip_port);
1940 1982
1941 /* We need to reload the sio_ir since the lowat 1983 /* We need to reload the sio_ir since the lowat
1942 * call may have caused another write to occur, 1984 * call may have caused another write to occur,
@@ -2023,7 +2065,7 @@ static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2023 int len) 2065 int len)
2024{ 2066{
2025 int prod_ptr, cons_ptr, total; 2067 int prod_ptr, cons_ptr, total;
2026 struct ioc4_port *port = get_ioc4_port(the_port); 2068 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2027 struct ring *inring; 2069 struct ring *inring;
2028 struct ring_entry *entry; 2070 struct ring_entry *entry;
2029 struct hooks *hooks = port->ip_hooks; 2071 struct hooks *hooks = port->ip_hooks;
@@ -2335,17 +2377,27 @@ static void receive_chars(struct uart_port *the_port)
2335 */ 2377 */
2336static const char *ic4_type(struct uart_port *the_port) 2378static const char *ic4_type(struct uart_port *the_port)
2337{ 2379{
2338 return "SGI IOC4 Serial"; 2380 if (the_port->mapbase == PROTO_RS232)
2381 return "SGI IOC4 Serial [rs232]";
2382 else
2383 return "SGI IOC4 Serial [rs422]";
2339} 2384}
2340 2385
2341/** 2386/**
2342 * ic4_tx_empty - Is the transmitter empty? We pretend we're always empty 2387 * ic4_tx_empty - Is the transmitter empty?
2343 * @port: Port to operate on (we ignore since we always return 1) 2388 * @port: Port to operate on
2344 * 2389 *
2345 */ 2390 */
2346static unsigned int ic4_tx_empty(struct uart_port *the_port) 2391static unsigned int ic4_tx_empty(struct uart_port *the_port)
2347{ 2392{
2348 return 1; 2393 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2394 unsigned int ret = 0;
2395
2396 if (port_is_active(port, the_port)) {
2397 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2398 ret = TIOCSER_TEMT;
2399 }
2400 return ret;
2349} 2401}
2350 2402
2351/** 2403/**
@@ -2355,6 +2407,10 @@ static unsigned int ic4_tx_empty(struct uart_port *the_port)
2355 */ 2407 */
2356static void ic4_stop_tx(struct uart_port *the_port) 2408static void ic4_stop_tx(struct uart_port *the_port)
2357{ 2409{
2410 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2411
2412 if (port_is_active(port, the_port))
2413 set_notification(port, N_OUTPUT_LOWAT, 0);
2358} 2414}
2359 2415
2360/** 2416/**
@@ -2377,11 +2433,12 @@ static void ic4_shutdown(struct uart_port *the_port)
2377 struct ioc4_port *port; 2433 struct ioc4_port *port;
2378 struct uart_info *info; 2434 struct uart_info *info;
2379 2435
2380 port = get_ioc4_port(the_port); 2436 port = get_ioc4_port(the_port, 0);
2381 if (!port) 2437 if (!port)
2382 return; 2438 return;
2383 2439
2384 info = the_port->info; 2440 info = the_port->info;
2441 port->ip_port = NULL;
2385 2442
2386 wake_up_interruptible(&info->delta_msr_wait); 2443 wake_up_interruptible(&info->delta_msr_wait);
2387 2444
@@ -2390,6 +2447,7 @@ static void ic4_shutdown(struct uart_port *the_port)
2390 2447
2391 spin_lock_irqsave(&the_port->lock, port_flags); 2448 spin_lock_irqsave(&the_port->lock, port_flags);
2392 set_notification(port, N_ALL, 0); 2449 set_notification(port, N_ALL, 0);
2450 port->ip_flags = PORT_INACTIVE;
2393 spin_unlock_irqrestore(&the_port->lock, port_flags); 2451 spin_unlock_irqrestore(&the_port->lock, port_flags);
2394} 2452}
2395 2453
@@ -2402,6 +2460,11 @@ static void ic4_shutdown(struct uart_port *the_port)
2402static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl) 2460static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2403{ 2461{
2404 unsigned char mcr = 0; 2462 unsigned char mcr = 0;
2463 struct ioc4_port *port;
2464
2465 port = get_ioc4_port(the_port, 0);
2466 if (!port_is_active(port, the_port))
2467 return;
2405 2468
2406 if (mctrl & TIOCM_RTS) 2469 if (mctrl & TIOCM_RTS)
2407 mcr |= UART_MCR_RTS; 2470 mcr |= UART_MCR_RTS;
@@ -2414,7 +2477,7 @@ static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2414 if (mctrl & TIOCM_LOOP) 2477 if (mctrl & TIOCM_LOOP)
2415 mcr |= UART_MCR_LOOP; 2478 mcr |= UART_MCR_LOOP;
2416 2479
2417 set_mcr(the_port, 1, mcr, IOC4_SHADOW_DTR); 2480 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2418} 2481}
2419 2482
2420/** 2483/**
@@ -2424,11 +2487,11 @@ static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2424 */ 2487 */
2425static unsigned int ic4_get_mctrl(struct uart_port *the_port) 2488static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2426{ 2489{
2427 struct ioc4_port *port = get_ioc4_port(the_port); 2490 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2428 uint32_t shadow; 2491 uint32_t shadow;
2429 unsigned int ret = 0; 2492 unsigned int ret = 0;
2430 2493
2431 if (!port) 2494 if (!port_is_active(port, the_port))
2432 return 0; 2495 return 0;
2433 2496
2434 shadow = readl(&port->ip_serial_regs->shadow); 2497 shadow = readl(&port->ip_serial_regs->shadow);
@@ -2448,9 +2511,9 @@ static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2448 */ 2511 */
2449static void ic4_start_tx(struct uart_port *the_port) 2512static void ic4_start_tx(struct uart_port *the_port)
2450{ 2513{
2451 struct ioc4_port *port = get_ioc4_port(the_port); 2514 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2452 2515
2453 if (port) { 2516 if (port_is_active(port, the_port)) {
2454 set_notification(port, N_OUTPUT_LOWAT, 1); 2517 set_notification(port, N_OUTPUT_LOWAT, 1);
2455 enable_intrs(port, port->ip_hooks->intr_tx_mt); 2518 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2456 } 2519 }
@@ -2467,7 +2530,7 @@ static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2467} 2530}
2468 2531
2469/** 2532/**
2470 * ic4_startup - Start up the serial port - always return 0 (We're always on) 2533 * ic4_startup - Start up the serial port
2471 * @port: Port to operate on 2534 * @port: Port to operate on
2472 * 2535 *
2473 */ 2536 */
@@ -2479,17 +2542,16 @@ static int ic4_startup(struct uart_port *the_port)
2479 struct uart_info *info; 2542 struct uart_info *info;
2480 unsigned long port_flags; 2543 unsigned long port_flags;
2481 2544
2482 if (!the_port) { 2545 if (!the_port)
2483 return -ENODEV; 2546 return -ENODEV;
2484 } 2547 port = get_ioc4_port(the_port, 1);
2485 port = get_ioc4_port(the_port); 2548 if (!port)
2486 if (!port) {
2487 return -ENODEV; 2549 return -ENODEV;
2488 }
2489 info = the_port->info; 2550 info = the_port->info;
2490 2551
2491 control = port->ip_control; 2552 control = port->ip_control;
2492 if (!control) { 2553 if (!control) {
2554 port->ip_port = NULL;
2493 return -ENODEV; 2555 return -ENODEV;
2494 } 2556 }
2495 2557
@@ -2551,28 +2613,104 @@ static struct uart_ops ioc4_ops = {
2551 * Boot-time initialization code 2613 * Boot-time initialization code
2552 */ 2614 */
2553 2615
2554static struct uart_driver ioc4_uart = { 2616static struct uart_driver ioc4_uart_rs232 = {
2555 .owner = THIS_MODULE, 2617 .owner = THIS_MODULE,
2556 .driver_name = "ioc4_serial", 2618 .driver_name = "ioc4_serial_rs232",
2557 .dev_name = DEVICE_NAME, 2619 .dev_name = DEVICE_NAME_RS232,
2558 .major = DEVICE_MAJOR, 2620 .major = DEVICE_MAJOR,
2559 .minor = DEVICE_MINOR, 2621 .minor = DEVICE_MINOR_RS232,
2560 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS, 2622 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2561}; 2623};
2562 2624
2625static struct uart_driver ioc4_uart_rs422 = {
2626 .owner = THIS_MODULE,
2627 .driver_name = "ioc4_serial_rs422",
2628 .dev_name = DEVICE_NAME_RS422,
2629 .major = DEVICE_MAJOR,
2630 .minor = DEVICE_MINOR_RS422,
2631 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2632};
2633
2634
2563/** 2635/**
2564 * ioc4_serial_core_attach - register with serial core 2636 * ioc4_serial_remove_one - detach function
2637 *
2638 * @idd: IOC4 master module data for this IOC4
2639 */
2640
2641static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2642{
2643 int port_num, port_type;
2644 struct ioc4_control *control;
2645 struct uart_port *the_port;
2646 struct ioc4_port *port;
2647 struct ioc4_soft *soft;
2648
2649 control = idd->idd_serial_data;
2650
2651 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2652 for (port_type = UART_PORT_MIN;
2653 port_type < UART_PORT_COUNT;
2654 port_type++) {
2655 the_port = &control->ic_port[port_num].icp_uart_port
2656 [port_type];
2657 if (the_port) {
2658 switch (port_type) {
2659 case UART_PORT_RS422:
2660 uart_remove_one_port(&ioc4_uart_rs422,
2661 the_port);
2662 break;
2663 default:
2664 case UART_PORT_RS232:
2665 uart_remove_one_port(&ioc4_uart_rs232,
2666 the_port);
2667 break;
2668 }
2669 }
2670 }
2671 port = control->ic_port[port_num].icp_port;
2672 /* we allocate in pairs */
2673 if (!(port_num & 1) && port) {
2674 pci_free_consistent(port->ip_pdev,
2675 TOTAL_RING_BUF_SIZE,
2676 port->ip_cpu_ringbuf,
2677 port->ip_dma_ringbuf);
2678 kfree(port);
2679 }
2680 }
2681 soft = control->ic_soft;
2682 if (soft) {
2683 free_irq(control->ic_irq, soft);
2684 if (soft->is_ioc4_serial_addr) {
2685 release_region((unsigned long)
2686 soft->is_ioc4_serial_addr,
2687 sizeof(struct ioc4_serial));
2688 }
2689 kfree(soft);
2690 }
2691 kfree(control);
2692 idd->idd_serial_data = NULL;
2693
2694 return 0;
2695}
2696
2697
2698/**
2699 * ioc4_serial_core_attach_rs232 - register with serial core
2565 * This is done during pci probing 2700 * This is done during pci probing
2566 * @pdev: handle for this card 2701 * @pdev: handle for this card
2567 */ 2702 */
2568static inline int 2703static inline int
2569ioc4_serial_core_attach(struct pci_dev *pdev) 2704ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2570{ 2705{
2571 struct ioc4_port *port; 2706 struct ioc4_port *port;
2572 struct uart_port *the_port; 2707 struct uart_port *the_port;
2573 struct ioc4_driver_data *idd = pci_get_drvdata(pdev); 2708 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2574 struct ioc4_control *control = idd->idd_serial_data; 2709 struct ioc4_control *control = idd->idd_serial_data;
2575 int ii; 2710 int port_num;
2711 int port_type_idx;
2712 struct uart_driver *u_driver;
2713
2576 2714
2577 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n", 2715 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2578 __FUNCTION__, pdev, (void *)control)); 2716 __FUNCTION__, pdev, (void *)control));
@@ -2580,28 +2718,36 @@ ioc4_serial_core_attach(struct pci_dev *pdev)
2580 if (!control) 2718 if (!control)
2581 return -ENODEV; 2719 return -ENODEV;
2582 2720
2721 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2722 : UART_PORT_RS422;
2723
2724 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2725 : &ioc4_uart_rs422;
2726
2583 /* once around for each port on this card */ 2727 /* once around for each port on this card */
2584 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) { 2728 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2585 the_port = &control->ic_port[ii].icp_uart_port; 2729 the_port = &control->ic_port[port_num].icp_uart_port
2586 port = control->ic_port[ii].icp_port; 2730 [port_type_idx];
2587 port->ip_port = the_port; 2731 port = control->ic_port[port_num].icp_port;
2732 port->ip_all_ports[port_type_idx] = the_port;
2588 2733
2589 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p\n", 2734 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2590 __FUNCTION__, (void *)the_port, 2735 __FUNCTION__, (void *)the_port,
2591 (void *)port)); 2736 (void *)port,
2737 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2592 2738
2593 /* membase, iobase and mapbase just need to be non-0 */ 2739 /* membase, iobase and mapbase just need to be non-0 */
2594 the_port->membase = (unsigned char __iomem *)1; 2740 the_port->membase = (unsigned char __iomem *)1;
2595 the_port->iobase = (pdev->bus->number << 16) | ii; 2741 the_port->iobase = (pdev->bus->number << 16) | port_num;
2596 the_port->line = (Num_of_ioc4_cards << 2) | ii; 2742 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2597 the_port->mapbase = 1; 2743 the_port->mapbase = port_type;
2598 the_port->type = PORT_16550A; 2744 the_port->type = PORT_16550A;
2599 the_port->fifosize = IOC4_FIFO_CHARS; 2745 the_port->fifosize = IOC4_FIFO_CHARS;
2600 the_port->ops = &ioc4_ops; 2746 the_port->ops = &ioc4_ops;
2601 the_port->irq = control->ic_irq; 2747 the_port->irq = control->ic_irq;
2602 the_port->dev = &pdev->dev; 2748 the_port->dev = &pdev->dev;
2603 spin_lock_init(&the_port->lock); 2749 spin_lock_init(&the_port->lock);
2604 if (uart_add_one_port(&ioc4_uart, the_port) < 0) { 2750 if (uart_add_one_port(u_driver, the_port) < 0) {
2605 printk(KERN_WARNING 2751 printk(KERN_WARNING
2606 "%s: unable to add port %d bus %d\n", 2752 "%s: unable to add port %d bus %d\n",
2607 __FUNCTION__, the_port->line, pdev->bus->number); 2753 __FUNCTION__, the_port->line, pdev->bus->number);
@@ -2610,8 +2756,6 @@ ioc4_serial_core_attach(struct pci_dev *pdev)
2610 ("IOC4 serial port %d irq = %d, bus %d\n", 2756 ("IOC4 serial port %d irq = %d, bus %d\n",
2611 the_port->line, the_port->irq, pdev->bus->number)); 2757 the_port->line, the_port->irq, pdev->bus->number));
2612 } 2758 }
2613 /* all ports are rs232 for now */
2614 ioc4_set_proto(port, PROTO_RS232);
2615 } 2759 }
2616 return 0; 2760 return 0;
2617} 2761}
@@ -2631,7 +2775,8 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2631 int ret = 0; 2775 int ret = 0;
2632 2776
2633 2777
2634 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev, idd->idd_pci_id)); 2778 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev,
2779 idd->idd_pci_id));
2635 2780
2636 /* request serial registers */ 2781 /* request serial registers */
2637 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET; 2782 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
@@ -2653,11 +2798,11 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2653 goto out2; 2798 goto out2;
2654 } 2799 }
2655 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n", 2800 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2656 __FUNCTION__, (void *)idd->idd_misc_regs, (void *)serial)); 2801 __FUNCTION__, (void *)idd->idd_misc_regs,
2802 (void *)serial));
2657 2803
2658 /* Get memory for the new card */ 2804 /* Get memory for the new card */
2659 control = kmalloc(sizeof(struct ioc4_control) * IOC4_NUM_SERIAL_PORTS, 2805 control = kmalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2660 GFP_KERNEL);
2661 2806
2662 if (!control) { 2807 if (!control) {
2663 printk(KERN_WARNING "ioc4_attach_one" 2808 printk(KERN_WARNING "ioc4_attach_one"
@@ -2702,7 +2847,7 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2702 2847
2703 /* Hook up interrupt handler */ 2848 /* Hook up interrupt handler */
2704 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, SA_SHIRQ, 2849 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, SA_SHIRQ,
2705 "sgi-ioc4serial", (void *)soft)) { 2850 "sgi-ioc4serial", soft)) {
2706 control->ic_irq = idd->idd_pdev->irq; 2851 control->ic_irq = idd->idd_pdev->irq;
2707 } else { 2852 } else {
2708 printk(KERN_WARNING 2853 printk(KERN_WARNING
@@ -2713,16 +2858,21 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2713 if (ret) 2858 if (ret)
2714 goto out4; 2859 goto out4;
2715 2860
2716 /* register port with the serial core */ 2861 /* register port with the serial core - 1 rs232, 1 rs422 */
2717 2862
2718 if ((ret = ioc4_serial_core_attach(idd->idd_pdev))) 2863 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2719 goto out4; 2864 goto out4;
2720 2865
2866 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2867 goto out5;
2868
2721 Num_of_ioc4_cards++; 2869 Num_of_ioc4_cards++;
2722 2870
2723 return ret; 2871 return ret;
2724 2872
2725 /* error exits that give back resources */ 2873 /* error exits that give back resources */
2874out5:
2875 ioc4_serial_remove_one(idd);
2726out4: 2876out4:
2727 kfree(soft); 2877 kfree(soft);
2728out3: 2878out3:
@@ -2735,52 +2885,6 @@ out1:
2735} 2885}
2736 2886
2737 2887
2738/**
2739 * ioc4_serial_remove_one - detach function
2740 *
2741 * @idd: IOC4 master module data for this IOC4
2742 */
2743
2744int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2745{
2746 int ii;
2747 struct ioc4_control *control;
2748 struct uart_port *the_port;
2749 struct ioc4_port *port;
2750 struct ioc4_soft *soft;
2751
2752 control = idd->idd_serial_data;
2753
2754 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2755 the_port = &control->ic_port[ii].icp_uart_port;
2756 if (the_port) {
2757 uart_remove_one_port(&ioc4_uart, the_port);
2758 }
2759 port = control->ic_port[ii].icp_port;
2760 if (!(ii & 1) && port) {
2761 pci_free_consistent(port->ip_pdev,
2762 TOTAL_RING_BUF_SIZE,
2763 (void *)port->ip_cpu_ringbuf,
2764 port->ip_dma_ringbuf);
2765 kfree(port);
2766 }
2767 }
2768 soft = control->ic_soft;
2769 if (soft) {
2770 free_irq(control->ic_irq, (void *)soft);
2771 if (soft->is_ioc4_serial_addr) {
2772 release_region((unsigned long)
2773 soft->is_ioc4_serial_addr,
2774 sizeof(struct ioc4_serial));
2775 }
2776 kfree(soft);
2777 }
2778 kfree(control);
2779 idd->idd_serial_data = NULL;
2780
2781 return 0;
2782}
2783
2784static struct ioc4_submodule ioc4_serial_submodule = { 2888static struct ioc4_submodule ioc4_serial_submodule = {
2785 .is_name = "IOC4_serial", 2889 .is_name = "IOC4_serial",
2786 .is_owner = THIS_MODULE, 2890 .is_owner = THIS_MODULE,
@@ -2796,9 +2900,15 @@ int ioc4_serial_init(void)
2796 int ret; 2900 int ret;
2797 2901
2798 /* register with serial core */ 2902 /* register with serial core */
2799 if ((ret = uart_register_driver(&ioc4_uart)) < 0) { 2903 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2904 printk(KERN_WARNING
2905 "%s: Couldn't register rs232 IOC4 serial driver\n",
2906 __FUNCTION__);
2907 return ret;
2908 }
2909 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2800 printk(KERN_WARNING 2910 printk(KERN_WARNING
2801 "%s: Couldn't register IOC4 serial driver\n", 2911 "%s: Couldn't register rs422 IOC4 serial driver\n",
2802 __FUNCTION__); 2912 __FUNCTION__);
2803 return ret; 2913 return ret;
2804 } 2914 }
@@ -2810,7 +2920,8 @@ int ioc4_serial_init(void)
2810static void __devexit ioc4_serial_exit(void) 2920static void __devexit ioc4_serial_exit(void)
2811{ 2921{
2812 ioc4_unregister_submodule(&ioc4_serial_submodule); 2922 ioc4_unregister_submodule(&ioc4_serial_submodule);
2813 uart_unregister_driver(&ioc4_uart); 2923 uart_unregister_driver(&ioc4_uart_rs232);
2924 uart_unregister_driver(&ioc4_uart_rs422);
2814} 2925}
2815 2926
2816module_init(ioc4_serial_init); 2927module_init(ioc4_serial_init);
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index 928e6cf12dca..6459edc7f5c5 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -40,7 +40,7 @@
40 * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and 40 * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and
41 * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly 41 * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly
42 * fpr the console code : without this 1:1 mapping, at early boot time, when we 42 * fpr the console code : without this 1:1 mapping, at early boot time, when we
43 * are parsing the kernel args console=ttyPSC?, we wouldn't know wich PSC it 43 * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it
44 * will be mapped to. 44 * will be mapped to.
45 */ 45 */
46 46
diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
index 0ca83ac31d07..94681922ea0a 100644
--- a/drivers/serial/mpsc.c
+++ b/drivers/serial/mpsc.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * drivers/serial/mpsc.c
3 *
4 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, 2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
5 * GT64260, MV64340, MV64360, GT96100, ... ). 3 * GT64260, MV64340, MV64360, GT96100, ... ).
6 * 4 *
@@ -52,9 +50,263 @@
52 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. 50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
53 */ 51 */
54 52
53#include <linux/config.h>
54
55#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
56#define SUPPORT_SYSRQ
57#endif
58
59#include <linux/module.h>
60#include <linux/moduleparam.h>
61#include <linux/tty.h>
62#include <linux/tty_flip.h>
63#include <linux/ioport.h>
64#include <linux/init.h>
65#include <linux/console.h>
66#include <linux/sysrq.h>
67#include <linux/serial.h>
68#include <linux/serial_core.h>
69#include <linux/delay.h>
70#include <linux/device.h>
71#include <linux/dma-mapping.h>
72#include <linux/mv643xx.h>
55#include <linux/platform_device.h> 73#include <linux/platform_device.h>
56 74
57#include "mpsc.h" 75#include <asm/io.h>
76#include <asm/irq.h>
77
78#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
79#define SUPPORT_SYSRQ
80#endif
81
82#define MPSC_NUM_CTLRS 2
83
84/*
85 * Descriptors and buffers must be cache line aligned.
86 * Buffers lengths must be multiple of cache line size.
87 * Number of Tx & Rx descriptors must be powers of 2.
88 */
89#define MPSC_RXR_ENTRIES 32
90#define MPSC_RXRE_SIZE dma_get_cache_alignment()
91#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
92#define MPSC_RXBE_SIZE dma_get_cache_alignment()
93#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
94
95#define MPSC_TXR_ENTRIES 32
96#define MPSC_TXRE_SIZE dma_get_cache_alignment()
97#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
98#define MPSC_TXBE_SIZE dma_get_cache_alignment()
99#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
100
101#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
102 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
103 dma_get_cache_alignment() /* for alignment */)
104
105/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
106struct mpsc_rx_desc {
107 u16 bufsize;
108 u16 bytecnt;
109 u32 cmdstat;
110 u32 link;
111 u32 buf_ptr;
112} __attribute((packed));
113
114struct mpsc_tx_desc {
115 u16 bytecnt;
116 u16 shadow;
117 u32 cmdstat;
118 u32 link;
119 u32 buf_ptr;
120} __attribute((packed));
121
122/*
123 * Some regs that have the erratum that you can't read them are are shared
124 * between the two MPSC controllers. This struct contains those shared regs.
125 */
126struct mpsc_shared_regs {
127 phys_addr_t mpsc_routing_base_p;
128 phys_addr_t sdma_intr_base_p;
129
130 void __iomem *mpsc_routing_base;
131 void __iomem *sdma_intr_base;
132
133 u32 MPSC_MRR_m;
134 u32 MPSC_RCRR_m;
135 u32 MPSC_TCRR_m;
136 u32 SDMA_INTR_CAUSE_m;
137 u32 SDMA_INTR_MASK_m;
138};
139
140/* The main driver data structure */
141struct mpsc_port_info {
142 struct uart_port port; /* Overlay uart_port structure */
143
144 /* Internal driver state for this ctlr */
145 u8 ready;
146 u8 rcv_data;
147 tcflag_t c_iflag; /* save termios->c_iflag */
148 tcflag_t c_cflag; /* save termios->c_cflag */
149
150 /* Info passed in from platform */
151 u8 mirror_regs; /* Need to mirror regs? */
152 u8 cache_mgmt; /* Need manual cache mgmt? */
153 u8 brg_can_tune; /* BRG has baud tuning? */
154 u32 brg_clk_src;
155 u16 mpsc_max_idle;
156 int default_baud;
157 int default_bits;
158 int default_parity;
159 int default_flow;
160
161 /* Physical addresses of various blocks of registers (from platform) */
162 phys_addr_t mpsc_base_p;
163 phys_addr_t sdma_base_p;
164 phys_addr_t brg_base_p;
165
166 /* Virtual addresses of various blocks of registers (from platform) */
167 void __iomem *mpsc_base;
168 void __iomem *sdma_base;
169 void __iomem *brg_base;
170
171 /* Descriptor ring and buffer allocations */
172 void *dma_region;
173 dma_addr_t dma_region_p;
174
175 dma_addr_t rxr; /* Rx descriptor ring */
176 dma_addr_t rxr_p; /* Phys addr of rxr */
177 u8 *rxb; /* Rx Ring I/O buf */
178 u8 *rxb_p; /* Phys addr of rxb */
179 u32 rxr_posn; /* First desc w/ Rx data */
180
181 dma_addr_t txr; /* Tx descriptor ring */
182 dma_addr_t txr_p; /* Phys addr of txr */
183 u8 *txb; /* Tx Ring I/O buf */
184 u8 *txb_p; /* Phys addr of txb */
185 int txr_head; /* Where new data goes */
186 int txr_tail; /* Where sent data comes off */
187
188 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
189 u32 MPSC_MPCR_m;
190 u32 MPSC_CHR_1_m;
191 u32 MPSC_CHR_2_m;
192 u32 MPSC_CHR_10_m;
193 u32 BRG_BCR_m;
194 struct mpsc_shared_regs *shared_regs;
195};
196
197/* Hooks to platform-specific code */
198int mpsc_platform_register_driver(void);
199void mpsc_platform_unregister_driver(void);
200
201/* Hooks back in to mpsc common to be called by platform-specific code */
202struct mpsc_port_info *mpsc_device_probe(int index);
203struct mpsc_port_info *mpsc_device_remove(int index);
204
205/* Main MPSC Configuration Register Offsets */
206#define MPSC_MMCRL 0x0000
207#define MPSC_MMCRH 0x0004
208#define MPSC_MPCR 0x0008
209#define MPSC_CHR_1 0x000c
210#define MPSC_CHR_2 0x0010
211#define MPSC_CHR_3 0x0014
212#define MPSC_CHR_4 0x0018
213#define MPSC_CHR_5 0x001c
214#define MPSC_CHR_6 0x0020
215#define MPSC_CHR_7 0x0024
216#define MPSC_CHR_8 0x0028
217#define MPSC_CHR_9 0x002c
218#define MPSC_CHR_10 0x0030
219#define MPSC_CHR_11 0x0034
220
221#define MPSC_MPCR_FRZ (1 << 9)
222#define MPSC_MPCR_CL_5 0
223#define MPSC_MPCR_CL_6 1
224#define MPSC_MPCR_CL_7 2
225#define MPSC_MPCR_CL_8 3
226#define MPSC_MPCR_SBL_1 0
227#define MPSC_MPCR_SBL_2 1
228
229#define MPSC_CHR_2_TEV (1<<1)
230#define MPSC_CHR_2_TA (1<<7)
231#define MPSC_CHR_2_TTCS (1<<9)
232#define MPSC_CHR_2_REV (1<<17)
233#define MPSC_CHR_2_RA (1<<23)
234#define MPSC_CHR_2_CRD (1<<25)
235#define MPSC_CHR_2_EH (1<<31)
236#define MPSC_CHR_2_PAR_ODD 0
237#define MPSC_CHR_2_PAR_SPACE 1
238#define MPSC_CHR_2_PAR_EVEN 2
239#define MPSC_CHR_2_PAR_MARK 3
240
241/* MPSC Signal Routing */
242#define MPSC_MRR 0x0000
243#define MPSC_RCRR 0x0004
244#define MPSC_TCRR 0x0008
245
246/* Serial DMA Controller Interface Registers */
247#define SDMA_SDC 0x0000
248#define SDMA_SDCM 0x0008
249#define SDMA_RX_DESC 0x0800
250#define SDMA_RX_BUF_PTR 0x0808
251#define SDMA_SCRDP 0x0810
252#define SDMA_TX_DESC 0x0c00
253#define SDMA_SCTDP 0x0c10
254#define SDMA_SFTDP 0x0c14
255
256#define SDMA_DESC_CMDSTAT_PE (1<<0)
257#define SDMA_DESC_CMDSTAT_CDL (1<<1)
258#define SDMA_DESC_CMDSTAT_FR (1<<3)
259#define SDMA_DESC_CMDSTAT_OR (1<<6)
260#define SDMA_DESC_CMDSTAT_BR (1<<9)
261#define SDMA_DESC_CMDSTAT_MI (1<<10)
262#define SDMA_DESC_CMDSTAT_A (1<<11)
263#define SDMA_DESC_CMDSTAT_AM (1<<12)
264#define SDMA_DESC_CMDSTAT_CT (1<<13)
265#define SDMA_DESC_CMDSTAT_C (1<<14)
266#define SDMA_DESC_CMDSTAT_ES (1<<15)
267#define SDMA_DESC_CMDSTAT_L (1<<16)
268#define SDMA_DESC_CMDSTAT_F (1<<17)
269#define SDMA_DESC_CMDSTAT_P (1<<18)
270#define SDMA_DESC_CMDSTAT_EI (1<<23)
271#define SDMA_DESC_CMDSTAT_O (1<<31)
272
273#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
274 SDMA_DESC_CMDSTAT_EI)
275
276#define SDMA_SDC_RFT (1<<0)
277#define SDMA_SDC_SFM (1<<1)
278#define SDMA_SDC_BLMR (1<<6)
279#define SDMA_SDC_BLMT (1<<7)
280#define SDMA_SDC_POVR (1<<8)
281#define SDMA_SDC_RIFB (1<<9)
282
283#define SDMA_SDCM_ERD (1<<7)
284#define SDMA_SDCM_AR (1<<15)
285#define SDMA_SDCM_STD (1<<16)
286#define SDMA_SDCM_TXD (1<<23)
287#define SDMA_SDCM_AT (1<<31)
288
289#define SDMA_0_CAUSE_RXBUF (1<<0)
290#define SDMA_0_CAUSE_RXERR (1<<1)
291#define SDMA_0_CAUSE_TXBUF (1<<2)
292#define SDMA_0_CAUSE_TXEND (1<<3)
293#define SDMA_1_CAUSE_RXBUF (1<<8)
294#define SDMA_1_CAUSE_RXERR (1<<9)
295#define SDMA_1_CAUSE_TXBUF (1<<10)
296#define SDMA_1_CAUSE_TXEND (1<<11)
297
298#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
299 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
300#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
301 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
302
303/* SDMA Interrupt registers */
304#define SDMA_INTR_CAUSE 0x0000
305#define SDMA_INTR_MASK 0x0080
306
307/* Baud Rate Generator Interface Registers */
308#define BRG_BCR 0x0000
309#define BRG_BTR 0x0004
58 310
59/* 311/*
60 * Define how this driver is known to the outside (we've been assigned a 312 * Define how this driver is known to the outside (we've been assigned a
@@ -1165,7 +1417,7 @@ mpsc_startup(struct uart_port *port)
1165 flag = SA_SHIRQ; 1417 flag = SA_SHIRQ;
1166 1418
1167 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, 1419 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1168 "mpsc/sdma", pi)) 1420 "mpsc-sdma", pi))
1169 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", 1421 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1170 pi->port.irq); 1422 pi->port.irq);
1171 1423
diff --git a/drivers/serial/mpsc.h b/drivers/serial/mpsc.h
deleted file mode 100644
index 678dbcf06c8f..000000000000
--- a/drivers/serial/mpsc.h
+++ /dev/null
@@ -1,289 +0,0 @@
1/*
2 * drivers/serial/mpsc.h
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __MPSC_H__
13#define __MPSC_H__
14
15#include <linux/config.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/delay.h>
27#include <linux/device.h>
28#include <linux/dma-mapping.h>
29#include <linux/mv643xx.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33
34#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
35#define SUPPORT_SYSRQ
36#endif
37
38#define MPSC_NUM_CTLRS 2
39
40/*
41 * Descriptors and buffers must be cache line aligned.
42 * Buffers lengths must be multiple of cache line size.
43 * Number of Tx & Rx descriptors must be powers of 2.
44 */
45#define MPSC_RXR_ENTRIES 32
46#define MPSC_RXRE_SIZE dma_get_cache_alignment()
47#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
48#define MPSC_RXBE_SIZE dma_get_cache_alignment()
49#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
50
51#define MPSC_TXR_ENTRIES 32
52#define MPSC_TXRE_SIZE dma_get_cache_alignment()
53#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
54#define MPSC_TXBE_SIZE dma_get_cache_alignment()
55#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
56
57#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
58 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
59 dma_get_cache_alignment() /* for alignment */)
60
61/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
62struct mpsc_rx_desc {
63 u16 bufsize;
64 u16 bytecnt;
65 u32 cmdstat;
66 u32 link;
67 u32 buf_ptr;
68} __attribute((packed));
69
70struct mpsc_tx_desc {
71 u16 bytecnt;
72 u16 shadow;
73 u32 cmdstat;
74 u32 link;
75 u32 buf_ptr;
76} __attribute((packed));
77
78/*
79 * Some regs that have the erratum that you can't read them are are shared
80 * between the two MPSC controllers. This struct contains those shared regs.
81 */
82struct mpsc_shared_regs {
83 phys_addr_t mpsc_routing_base_p;
84 phys_addr_t sdma_intr_base_p;
85
86 void __iomem *mpsc_routing_base;
87 void __iomem *sdma_intr_base;
88
89 u32 MPSC_MRR_m;
90 u32 MPSC_RCRR_m;
91 u32 MPSC_TCRR_m;
92 u32 SDMA_INTR_CAUSE_m;
93 u32 SDMA_INTR_MASK_m;
94};
95
96/* The main driver data structure */
97struct mpsc_port_info {
98 struct uart_port port; /* Overlay uart_port structure */
99
100 /* Internal driver state for this ctlr */
101 u8 ready;
102 u8 rcv_data;
103 tcflag_t c_iflag; /* save termios->c_iflag */
104 tcflag_t c_cflag; /* save termios->c_cflag */
105
106 /* Info passed in from platform */
107 u8 mirror_regs; /* Need to mirror regs? */
108 u8 cache_mgmt; /* Need manual cache mgmt? */
109 u8 brg_can_tune; /* BRG has baud tuning? */
110 u32 brg_clk_src;
111 u16 mpsc_max_idle;
112 int default_baud;
113 int default_bits;
114 int default_parity;
115 int default_flow;
116
117 /* Physical addresses of various blocks of registers (from platform) */
118 phys_addr_t mpsc_base_p;
119 phys_addr_t sdma_base_p;
120 phys_addr_t brg_base_p;
121
122 /* Virtual addresses of various blocks of registers (from platform) */
123 void __iomem *mpsc_base;
124 void __iomem *sdma_base;
125 void __iomem *brg_base;
126
127 /* Descriptor ring and buffer allocations */
128 void *dma_region;
129 dma_addr_t dma_region_p;
130
131 dma_addr_t rxr; /* Rx descriptor ring */
132 dma_addr_t rxr_p; /* Phys addr of rxr */
133 u8 *rxb; /* Rx Ring I/O buf */
134 u8 *rxb_p; /* Phys addr of rxb */
135 u32 rxr_posn; /* First desc w/ Rx data */
136
137 dma_addr_t txr; /* Tx descriptor ring */
138 dma_addr_t txr_p; /* Phys addr of txr */
139 u8 *txb; /* Tx Ring I/O buf */
140 u8 *txb_p; /* Phys addr of txb */
141 int txr_head; /* Where new data goes */
142 int txr_tail; /* Where sent data comes off */
143
144 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
145 u32 MPSC_MPCR_m;
146 u32 MPSC_CHR_1_m;
147 u32 MPSC_CHR_2_m;
148 u32 MPSC_CHR_10_m;
149 u32 BRG_BCR_m;
150 struct mpsc_shared_regs *shared_regs;
151};
152
153/* Hooks to platform-specific code */
154int mpsc_platform_register_driver(void);
155void mpsc_platform_unregister_driver(void);
156
157/* Hooks back in to mpsc common to be called by platform-specific code */
158struct mpsc_port_info *mpsc_device_probe(int index);
159struct mpsc_port_info *mpsc_device_remove(int index);
160
161/*
162 *****************************************************************************
163 *
164 * Multi-Protocol Serial Controller Interface Registers
165 *
166 *****************************************************************************
167 */
168
169/* Main Configuratino Register Offsets */
170#define MPSC_MMCRL 0x0000
171#define MPSC_MMCRH 0x0004
172#define MPSC_MPCR 0x0008
173#define MPSC_CHR_1 0x000c
174#define MPSC_CHR_2 0x0010
175#define MPSC_CHR_3 0x0014
176#define MPSC_CHR_4 0x0018
177#define MPSC_CHR_5 0x001c
178#define MPSC_CHR_6 0x0020
179#define MPSC_CHR_7 0x0024
180#define MPSC_CHR_8 0x0028
181#define MPSC_CHR_9 0x002c
182#define MPSC_CHR_10 0x0030
183#define MPSC_CHR_11 0x0034
184
185#define MPSC_MPCR_FRZ (1 << 9)
186#define MPSC_MPCR_CL_5 0
187#define MPSC_MPCR_CL_6 1
188#define MPSC_MPCR_CL_7 2
189#define MPSC_MPCR_CL_8 3
190#define MPSC_MPCR_SBL_1 0
191#define MPSC_MPCR_SBL_2 1
192
193#define MPSC_CHR_2_TEV (1<<1)
194#define MPSC_CHR_2_TA (1<<7)
195#define MPSC_CHR_2_TTCS (1<<9)
196#define MPSC_CHR_2_REV (1<<17)
197#define MPSC_CHR_2_RA (1<<23)
198#define MPSC_CHR_2_CRD (1<<25)
199#define MPSC_CHR_2_EH (1<<31)
200#define MPSC_CHR_2_PAR_ODD 0
201#define MPSC_CHR_2_PAR_SPACE 1
202#define MPSC_CHR_2_PAR_EVEN 2
203#define MPSC_CHR_2_PAR_MARK 3
204
205/* MPSC Signal Routing */
206#define MPSC_MRR 0x0000
207#define MPSC_RCRR 0x0004
208#define MPSC_TCRR 0x0008
209
210/*
211 *****************************************************************************
212 *
213 * Serial DMA Controller Interface Registers
214 *
215 *****************************************************************************
216 */
217
218#define SDMA_SDC 0x0000
219#define SDMA_SDCM 0x0008
220#define SDMA_RX_DESC 0x0800
221#define SDMA_RX_BUF_PTR 0x0808
222#define SDMA_SCRDP 0x0810
223#define SDMA_TX_DESC 0x0c00
224#define SDMA_SCTDP 0x0c10
225#define SDMA_SFTDP 0x0c14
226
227#define SDMA_DESC_CMDSTAT_PE (1<<0)
228#define SDMA_DESC_CMDSTAT_CDL (1<<1)
229#define SDMA_DESC_CMDSTAT_FR (1<<3)
230#define SDMA_DESC_CMDSTAT_OR (1<<6)
231#define SDMA_DESC_CMDSTAT_BR (1<<9)
232#define SDMA_DESC_CMDSTAT_MI (1<<10)
233#define SDMA_DESC_CMDSTAT_A (1<<11)
234#define SDMA_DESC_CMDSTAT_AM (1<<12)
235#define SDMA_DESC_CMDSTAT_CT (1<<13)
236#define SDMA_DESC_CMDSTAT_C (1<<14)
237#define SDMA_DESC_CMDSTAT_ES (1<<15)
238#define SDMA_DESC_CMDSTAT_L (1<<16)
239#define SDMA_DESC_CMDSTAT_F (1<<17)
240#define SDMA_DESC_CMDSTAT_P (1<<18)
241#define SDMA_DESC_CMDSTAT_EI (1<<23)
242#define SDMA_DESC_CMDSTAT_O (1<<31)
243
244#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
245 SDMA_DESC_CMDSTAT_EI)
246
247#define SDMA_SDC_RFT (1<<0)
248#define SDMA_SDC_SFM (1<<1)
249#define SDMA_SDC_BLMR (1<<6)
250#define SDMA_SDC_BLMT (1<<7)
251#define SDMA_SDC_POVR (1<<8)
252#define SDMA_SDC_RIFB (1<<9)
253
254#define SDMA_SDCM_ERD (1<<7)
255#define SDMA_SDCM_AR (1<<15)
256#define SDMA_SDCM_STD (1<<16)
257#define SDMA_SDCM_TXD (1<<23)
258#define SDMA_SDCM_AT (1<<31)
259
260#define SDMA_0_CAUSE_RXBUF (1<<0)
261#define SDMA_0_CAUSE_RXERR (1<<1)
262#define SDMA_0_CAUSE_TXBUF (1<<2)
263#define SDMA_0_CAUSE_TXEND (1<<3)
264#define SDMA_1_CAUSE_RXBUF (1<<8)
265#define SDMA_1_CAUSE_RXERR (1<<9)
266#define SDMA_1_CAUSE_TXBUF (1<<10)
267#define SDMA_1_CAUSE_TXEND (1<<11)
268
269#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
270 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
271#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
272 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
273
274/* SDMA Interrupt registers */
275#define SDMA_INTR_CAUSE 0x0000
276#define SDMA_INTR_MASK 0x0080
277
278/*
279 *****************************************************************************
280 *
281 * Baud Rate Generator Interface Registers
282 *
283 *****************************************************************************
284 */
285
286#define BRG_BCR 0x0000
287#define BRG_BTR 0x0004
288
289#endif /* __MPSC_H__ */
diff --git a/drivers/serial/serial_txx9.c b/drivers/serial/serial_txx9.c
index b848b7d94412..3bdee64d1a99 100644
--- a/drivers/serial/serial_txx9.c
+++ b/drivers/serial/serial_txx9.c
@@ -483,7 +483,7 @@ static int serial_txx9_startup(struct uart_port *port)
483 483
484 /* 484 /*
485 * Clear the FIFO buffers and disable them. 485 * Clear the FIFO buffers and disable them.
486 * (they will be reeanbled in set_termios()) 486 * (they will be reenabled in set_termios())
487 */ 487 */
488 sio_set(up, TXX9_SIFCR, 488 sio_set(up, TXX9_SIFCR,
489 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE); 489 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index 9fe2283d91e5..1c4396c2962d 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -641,7 +641,7 @@ static int sunsu_startup(struct uart_port *port)
641 641
642 /* 642 /*
643 * Clear the FIFO buffers and disable them. 643 * Clear the FIFO buffers and disable them.
644 * (they will be reeanbled in set_termios()) 644 * (they will be reenabled in set_termios())
645 */ 645 */
646 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) { 646 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
647 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 647 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 12:48:11 -0500