diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-03-02 18:31:07 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-03-02 18:31:07 -0500 |
commit | 64ed28a87a0c075e91c1c5b0fe7d225a6cc6ae39 (patch) | |
tree | a434977a6caa9b41cc0daaf71dbd76ac8693aba6 /drivers/serial | |
parent | b93a4afcff7be859e30cad2a305731516057d6cf (diff) | |
parent | 17ccb834d517c66c09123c24ba8553c5b14e0f78 (diff) |
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6 into devel-stable
Conflicts:
arch/arm/Kconfig
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/Kconfig | 2 | ||||
-rw-r--r-- | drivers/serial/sh-sci.h | 242 |
2 files changed, 16 insertions, 228 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ebdd2b984d16..df62f4ea4f69 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -1003,7 +1003,7 @@ config SERIAL_IP22_ZILOG_CONSOLE | |||
1003 | 1003 | ||
1004 | config SERIAL_SH_SCI | 1004 | config SERIAL_SH_SCI |
1005 | tristate "SuperH SCI(F) serial port support" | 1005 | tristate "SuperH SCI(F) serial port support" |
1006 | depends on HAVE_CLK && (SUPERH || H8300) | 1006 | depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) |
1007 | select SERIAL_CORE | 1007 | select SERIAL_CORE |
1008 | 1008 | ||
1009 | config SERIAL_SH_SCI_NR_UARTS | 1009 | config SERIAL_SH_SCI_NR_UARTS |
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 0efcded59ae6..fad67d33b0bd 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -30,7 +30,8 @@ | |||
30 | */ | 30 | */ |
31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | 31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 |
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
33 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
34 | defined(CONFIG_ARCH_SHMOBILE) | ||
34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | 35 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
35 | # define PORT_PTCR 0xA405011EUL | 36 | # define PORT_PTCR 0xA405011EUL |
36 | # define PORT_PVCR 0xA4050122UL | 37 | # define PORT_PVCR 0xA4050122UL |
@@ -228,7 +229,8 @@ | |||
228 | 229 | ||
229 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 230 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
230 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 231 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
231 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 232 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
233 | defined(CONFIG_ARCH_SHMOBILE) | ||
232 | # define SCIF_ORER 0x0200 | 234 | # define SCIF_ORER 0x0200 |
233 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | 235 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) |
234 | # define SCIF_RFDC_MASK 0x007f | 236 | # define SCIF_RFDC_MASK 0x007f |
@@ -261,7 +263,8 @@ | |||
261 | 263 | ||
262 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 264 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
263 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 265 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
264 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 266 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
267 | defined(CONFIG_ARCH_SHMOBILE) | ||
265 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) | 268 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
266 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | 269 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) |
267 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | 270 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) |
@@ -356,7 +359,7 @@ | |||
356 | SCI_OUT(sci_size, sci_offset, value); \ | 359 | SCI_OUT(sci_size, sci_offset, value); \ |
357 | } | 360 | } |
358 | 361 | ||
359 | #ifdef CONFIG_CPU_SH3 | 362 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) |
360 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 363 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
361 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | 364 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ |
362 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | 365 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ |
@@ -366,7 +369,8 @@ | |||
366 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | 369 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) |
367 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 370 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
368 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 371 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
369 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 372 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
373 | defined(CONFIG_ARCH_SHMOBILE) | ||
370 | #define SCIF_FNS(name, scif_offset, scif_size) \ | 374 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
371 | CPU_SCIF_FNS(name, scif_offset, scif_size) | 375 | CPU_SCIF_FNS(name, scif_offset, scif_size) |
372 | #else | 376 | #else |
@@ -401,7 +405,8 @@ | |||
401 | 405 | ||
402 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 406 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
403 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 407 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
404 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 408 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
409 | defined(CONFIG_ARCH_SHMOBILE) | ||
405 | 410 | ||
406 | SCIF_FNS(SCSMR, 0x00, 16) | 411 | SCIF_FNS(SCSMR, 0x00, 16) |
407 | SCIF_FNS(SCBRR, 0x04, 8) | 412 | SCIF_FNS(SCBRR, 0x04, 8) |
@@ -413,7 +418,7 @@ SCIF_FNS(SCFCR, 0x18, 16) | |||
413 | SCIF_FNS(SCFDR, 0x1c, 16) | 418 | SCIF_FNS(SCFDR, 0x1c, 16) |
414 | SCIF_FNS(SCxTDR, 0x20, 8) | 419 | SCIF_FNS(SCxTDR, 0x20, 8) |
415 | SCIF_FNS(SCxRDR, 0x24, 8) | 420 | SCIF_FNS(SCxRDR, 0x24, 8) |
416 | SCIF_FNS(SCLSR, 0x24, 16) | 421 | SCIF_FNS(SCLSR, 0x00, 0) |
417 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | 422 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
418 | defined(CONFIG_CPU_SUBTYPE_SH7724) | 423 | defined(CONFIG_CPU_SUBTYPE_SH7724) |
419 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | 424 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) |
@@ -518,34 +523,6 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
518 | { | 523 | { |
519 | if (port->mapbase == 0xfffffe80) | 524 | if (port->mapbase == 0xfffffe80) |
520 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | 525 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ |
521 | if (port->mapbase == 0xa4000150) | ||
522 | return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | ||
523 | if (port->mapbase == 0xa4000140) | ||
524 | return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | ||
525 | return 1; | ||
526 | } | ||
527 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
528 | static inline int sci_rxd_in(struct uart_port *port) | ||
529 | { | ||
530 | if (port->mapbase == SCIF0) | ||
531 | return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | ||
532 | if (port->mapbase == SCIF2) | ||
533 | return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | ||
534 | return 1; | ||
535 | } | ||
536 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | ||
537 | static inline int sci_rxd_in(struct uart_port *port) | ||
538 | { | ||
539 | return sci_in(port,SCxSR)&0x0010 ? 1 : 0; | ||
540 | } | ||
541 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
542 | defined(CONFIG_CPU_SUBTYPE_SH7721) | ||
543 | static inline int sci_rxd_in(struct uart_port *port) | ||
544 | { | ||
545 | if (port->mapbase == 0xa4430000) | ||
546 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | ||
547 | else if (port->mapbase == 0xa4438000) | ||
548 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | ||
549 | return 1; | 526 | return 1; |
550 | } | 527 | } |
551 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 528 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
@@ -558,207 +535,17 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
558 | { | 535 | { |
559 | if (port->mapbase == 0xffe00000) | 536 | if (port->mapbase == 0xffe00000) |
560 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | 537 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
561 | if (port->mapbase == 0xffe80000) | ||
562 | return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
563 | return 1; | ||
564 | } | ||
565 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
566 | static inline int sci_rxd_in(struct uart_port *port) | ||
567 | { | ||
568 | if (port->mapbase == 0xffe80000) | ||
569 | return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
570 | return 1; | 538 | return 1; |
571 | } | 539 | } |
572 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | ||
573 | static inline int sci_rxd_in(struct uart_port *port) | ||
574 | { | ||
575 | if (port->mapbase == 0xfe4b0000) | ||
576 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; | ||
577 | if (port->mapbase == 0xfe4c0000) | ||
578 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; | ||
579 | if (port->mapbase == 0xfe4d0000) | ||
580 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; | ||
581 | } | ||
582 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
583 | static inline int sci_rxd_in(struct uart_port *port) | ||
584 | { | ||
585 | if (port->mapbase == 0xfe600000) | ||
586 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
587 | if (port->mapbase == 0xfe610000) | ||
588 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
589 | if (port->mapbase == 0xfe620000) | ||
590 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
591 | return 1; | ||
592 | } | ||
593 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
594 | static inline int sci_rxd_in(struct uart_port *port) | ||
595 | { | ||
596 | if (port->mapbase == 0xffe00000) | ||
597 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
598 | if (port->mapbase == 0xffe10000) | ||
599 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
600 | if (port->mapbase == 0xffe20000) | ||
601 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
602 | if (port->mapbase == 0xffe30000) | ||
603 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
604 | return 1; | ||
605 | } | ||
606 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) | ||
607 | static inline int sci_rxd_in(struct uart_port *port) | ||
608 | { | ||
609 | if (port->mapbase == 0xffe00000) | ||
610 | return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | ||
611 | return 1; | ||
612 | } | ||
613 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) | ||
614 | static inline int sci_rxd_in(struct uart_port *port) | ||
615 | { | ||
616 | if (port->mapbase == 0xffe00000) | ||
617 | return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | ||
618 | if (port->mapbase == 0xffe10000) | ||
619 | return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | ||
620 | if (port->mapbase == 0xffe20000) | ||
621 | return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | ||
622 | |||
623 | return 1; | ||
624 | } | ||
625 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | ||
626 | static inline int sci_rxd_in(struct uart_port *port) | ||
627 | { | ||
628 | if (port->mapbase == 0xffe00000) | ||
629 | return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | ||
630 | if (port->mapbase == 0xffe10000) | ||
631 | return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | ||
632 | if (port->mapbase == 0xffe20000) | ||
633 | return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | ||
634 | if (port->mapbase == 0xa4e30000) | ||
635 | return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | ||
636 | if (port->mapbase == 0xa4e40000) | ||
637 | return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | ||
638 | if (port->mapbase == 0xa4e50000) | ||
639 | return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | ||
640 | return 1; | ||
641 | } | ||
642 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
643 | # define SCFSR 0x0010 | ||
644 | # define SCASSR 0x0014 | ||
645 | static inline int sci_rxd_in(struct uart_port *port) | ||
646 | { | ||
647 | if (port->type == PORT_SCIF) | ||
648 | return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; | ||
649 | if (port->type == PORT_SCIFA) | ||
650 | return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; | ||
651 | return 1; | ||
652 | } | ||
653 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | ||
654 | static inline int sci_rxd_in(struct uart_port *port) | ||
655 | { | ||
656 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | ||
657 | } | ||
658 | #elif defined(__H8300H__) || defined(__H8300S__) | 540 | #elif defined(__H8300H__) || defined(__H8300S__) |
659 | static inline int sci_rxd_in(struct uart_port *port) | 541 | static inline int sci_rxd_in(struct uart_port *port) |
660 | { | 542 | { |
661 | int ch = (port->mapbase - SMR0) >> 3; | 543 | int ch = (port->mapbase - SMR0) >> 3; |
662 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | 544 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; |
663 | } | 545 | } |
664 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | 546 | #else /* default case for non-SCI processors */ |
665 | static inline int sci_rxd_in(struct uart_port *port) | ||
666 | { | ||
667 | if (port->mapbase == 0xffe00000) | ||
668 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
669 | if (port->mapbase == 0xffe08000) | ||
670 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
671 | if (port->mapbase == 0xffe10000) | ||
672 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | ||
673 | |||
674 | return 1; | ||
675 | } | ||
676 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) | ||
677 | static inline int sci_rxd_in(struct uart_port *port) | ||
678 | { | ||
679 | if (port->mapbase == 0xff923000) | ||
680 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
681 | if (port->mapbase == 0xff924000) | ||
682 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
683 | if (port->mapbase == 0xff925000) | ||
684 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
685 | return 1; | ||
686 | } | ||
687 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | ||
688 | static inline int sci_rxd_in(struct uart_port *port) | ||
689 | { | ||
690 | if (port->mapbase == 0xffe00000) | ||
691 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
692 | if (port->mapbase == 0xffe10000) | ||
693 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
694 | return 1; | ||
695 | } | ||
696 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | ||
697 | defined(CONFIG_CPU_SUBTYPE_SH7786) | ||
698 | static inline int sci_rxd_in(struct uart_port *port) | ||
699 | { | ||
700 | if (port->mapbase == 0xffea0000) | ||
701 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
702 | if (port->mapbase == 0xffeb0000) | ||
703 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
704 | if (port->mapbase == 0xffec0000) | ||
705 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
706 | if (port->mapbase == 0xffed0000) | ||
707 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
708 | if (port->mapbase == 0xffee0000) | ||
709 | return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | ||
710 | if (port->mapbase == 0xffef0000) | ||
711 | return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | ||
712 | return 1; | ||
713 | } | ||
714 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ | ||
715 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | ||
716 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | ||
717 | defined(CONFIG_CPU_SUBTYPE_SH7263) | ||
718 | static inline int sci_rxd_in(struct uart_port *port) | ||
719 | { | ||
720 | if (port->mapbase == 0xfffe8000) | ||
721 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
722 | if (port->mapbase == 0xfffe8800) | ||
723 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
724 | if (port->mapbase == 0xfffe9000) | ||
725 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
726 | if (port->mapbase == 0xfffe9800) | ||
727 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
728 | #if defined(CONFIG_CPU_SUBTYPE_SH7201) | ||
729 | if (port->mapbase == 0xfffeA000) | ||
730 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
731 | if (port->mapbase == 0xfffeA800) | ||
732 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
733 | if (port->mapbase == 0xfffeB000) | ||
734 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
735 | if (port->mapbase == 0xfffeB800) | ||
736 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
737 | #endif | ||
738 | return 1; | ||
739 | } | ||
740 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | ||
741 | static inline int sci_rxd_in(struct uart_port *port) | ||
742 | { | ||
743 | if (port->mapbase == 0xf8400000) | ||
744 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
745 | if (port->mapbase == 0xf8410000) | ||
746 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
747 | if (port->mapbase == 0xf8420000) | ||
748 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
749 | return 1; | ||
750 | } | ||
751 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) | ||
752 | static inline int sci_rxd_in(struct uart_port *port) | 547 | static inline int sci_rxd_in(struct uart_port *port) |
753 | { | 548 | { |
754 | if (port->mapbase == 0xffc30000) | ||
755 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
756 | if (port->mapbase == 0xffc40000) | ||
757 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
758 | if (port->mapbase == 0xffc50000) | ||
759 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
760 | if (port->mapbase == 0xffc60000) | ||
761 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
762 | return 1; | 549 | return 1; |
763 | } | 550 | } |
764 | #endif | 551 | #endif |
@@ -801,7 +588,8 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
801 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) | 588 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
802 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 589 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
803 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 590 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
804 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 591 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
592 | defined(CONFIG_ARCH_SHMOBILE) | ||
805 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) | 593 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
806 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | 594 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
807 | defined(CONFIG_CPU_SUBTYPE_SH7724) | 595 | defined(CONFIG_CPU_SUBTYPE_SH7724) |