Merge branch 'linus' into core/locking

7 files changed, 60 insertions, 107 deletions

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c94d3c4b7521..579d63a81aa2 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1276,7 +1276,7 @@ config SERIAL_SGI_IOC3
           say Y or M.  Otherwise, say N.
 
 config SERIAL_NETX
-        bool "NetX serial port support"
+        tristate "NetX serial port support"
         depends on ARM && ARCH_NETX
         select SERIAL_CORE
         help
@@ -1288,7 +1288,7 @@ config SERIAL_NETX
 
 config SERIAL_NETX_CONSOLE
         bool "Console on NetX serial port"
-        depends on SERIAL_NETX
+        depends on SERIAL_NETX=y
         select SERIAL_CORE_CONSOLE
         help
           If you have enabled the serial port on the Hilscher NetX SoC
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 61fb8b6d19af..d5efd6c77904 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -1258,6 +1258,8 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
                 atmel_port->clk = clk_get(&pdev->dev, "usart");
                 clk_enable(atmel_port->clk);
                 port->uartclk = clk_get_rate(atmel_port->clk);
+                clk_disable(atmel_port->clk);
+                /* only enable clock when USART is in use */
         }
 
         atmel_port->use_dma_rx = data->use_dma_rx;
@@ -1379,6 +1381,8 @@ static int __init atmel_console_setup(struct console *co, char *options)
                 return -ENODEV;
         }
 
+        clk_enable(atmel_ports[co->index].clk);
+
         UART_PUT_IDR(port, -1);
         UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
         UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
@@ -1403,7 +1407,7 @@ static struct console atmel_console = {
         .data           = &atmel_uart,
 };
 
-#define ATMEL_CONSOLE_DEVICE    &atmel_console
+#define ATMEL_CONSOLE_DEVICE    (&atmel_console)
 
 /*
  * Early console initialization (before VM subsystem initialized).
@@ -1534,6 +1538,15 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
         if (ret)
                 goto err_add_port;
 
+        if (atmel_is_console_port(&port->uart)
+                        && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
+                /*
+                 * The serial core enabled the clock for us, so undo
+                 * the clk_enable() in atmel_console_setup()
+                 */
+                clk_disable(port->clk);
+        }
+
         device_init_wakeup(&pdev->dev, 1);
         platform_set_drvdata(pdev, port);
 
@@ -1544,7 +1557,6 @@ err_add_port:
         port->rx_ring.buf = NULL;
 err_alloc_ring:
         if (!atmel_is_console_port(&port->uart)) {
-                clk_disable(port->clk);
                 clk_put(port->clk);
                 port->clk = NULL;
         }
@@ -1568,7 +1580,6 @@ static int __devexit atmel_serial_remove(struct platform_device *pdev)
 
         /* "port" is allocated statically, so we shouldn't free it */
 
-        clk_disable(atmel_port->clk);
         clk_put(atmel_port->clk);
 
         return ret;
diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c
index 211c21797ce0..8b2c619a09f2 100644
--- a/drivers/serial/crisv10.c
+++ b/drivers/serial/crisv10.c
@@ -34,14 +34,14 @@ static char *serial_version = "$Revision: 1.25 $";
 #include <asm/system.h>
 #include <linux/delay.h>
 
-#include <asm/arch/svinto.h>
+#include <arch/svinto.h>
 
 /* non-arch dependent serial structures are in linux/serial.h */
 #include <linux/serial.h>
 /* while we keep our own stuff (struct e100_serial) in a local .h file */
 #include "crisv10.h"
 #include <asm/fasttimer.h>
-#include <asm/arch/io_interface_mux.h>
+#include <arch/io_interface_mux.h>
 
 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
 #ifndef CONFIG_ETRAX_FAST_TIMER
diff --git a/drivers/serial/crisv10.h b/drivers/serial/crisv10.h
index e3c5c8c3c09b..f36a729280bc 100644
--- a/drivers/serial/crisv10.h
+++ b/drivers/serial/crisv10.h
@@ -10,7 +10,7 @@
 #include <linux/circ_buf.h>
 #include <asm/termios.h>
 #include <asm/dma.h>
-#include <asm/arch/io_interface_mux.h>
+#include <arch/io_interface_mux.h>
 
 /* Software state per channel */
 
diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c
index 3f489329e8d3..3e5dda8518b7 100644
--- a/drivers/serial/netx-serial.c
+++ b/drivers/serial/netx-serial.c
@@ -42,8 +42,6 @@
 #define SERIAL_NX_MAJOR 204
 #define MINOR_START     170
 
-#ifdef CONFIG_SERIAL_NETX_CONSOLE
-
 enum uart_regs {
         UART_DR              = 0x00,
         UART_SR              = 0x04,
@@ -528,6 +526,8 @@ static struct netx_port netx_ports[] = {
         }
 };
 
+#ifdef CONFIG_SERIAL_NETX_CONSOLE
+
 static void netx_console_putchar(struct uart_port *port, int ch)
 {
         while (readl(port->membase + UART_FR) & FR_BUSY);
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index f0658d2c45b2..5c0f32c7fbf6 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
 }
 #endif
 
-#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
-    defined(__H8300H__) || defined(__H8300S__)
+#if defined(__H8300H__) || defined(__H8300S__)
 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
 {
         int ch = (port->mapbase - SMR0) >> 3;
@@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
 #define sci_init_pins_irda NULL
 #endif
 
-#ifdef SCI_ONLY
-#define sci_init_pins_scif NULL
-#endif
-
-#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
 {
@@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port)
         return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
 }
 #endif
-#endif /* SCIF_ONLY || SCI_AND_SCIF */
 
 static inline int sci_txroom(struct uart_port *port)
 {
@@ -485,11 +478,9 @@ static void sci_transmit_chars(struct uart_port *port)
                 return;
         }
 
-#ifndef SCI_ONLY
         if (port->type == PORT_SCIF)
                 count = scif_txroom(port);
         else
-#endif
                 count = sci_txroom(port);
 
         do {
@@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port)
         } else {
                 ctrl = sci_in(port, SCSCR);
 
-#if !defined(SCI_ONLY)
                 if (port->type == PORT_SCIF) {
                         sci_in(port, SCxSR); /* Dummy read */
                         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
                 }
-#endif
 
                 ctrl |= SCI_CTRL_FLAGS_TIE;
                 sci_out(port, SCSCR, ctrl);
@@ -547,11 +536,9 @@ static inline void sci_receive_chars(struct uart_port *port)
                 return;
 
         while (1) {
-#if !defined(SCI_ONLY)
                 if (port->type == PORT_SCIF)
                         count = scif_rxroom(port);
                 else
-#endif
                         count = sci_rxroom(port);
 
                 /* Don't copy more bytes than there is room for in the buffer */
@@ -810,26 +797,27 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
 
 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
 {
-        unsigned short ssr_status, scr_status;
-        struct uart_port *port = ptr;
+        unsigned short ssr_status, scr_status;
+        struct uart_port *port = ptr;
+        irqreturn_t ret = IRQ_NONE;
 
         ssr_status = sci_in(port,SCxSR);
         scr_status = sci_in(port,SCSCR);
 
         /* Tx Interrupt */
-        if ((ssr_status & 0x0020) && (scr_status & 0x0080))
-                sci_tx_interrupt(irq, ptr);
+        if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
+                ret = sci_tx_interrupt(irq, ptr);
         /* Rx Interrupt */
-        if ((ssr_status & 0x0002) && (scr_status & 0x0040))
-                sci_rx_interrupt(irq, ptr);
+        if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
+                ret = sci_rx_interrupt(irq, ptr);
         /* Error Interrupt */
-        if ((ssr_status & 0x0080) && (scr_status & 0x0400))
-                sci_er_interrupt(irq, ptr);
+        if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
+                ret = sci_er_interrupt(irq, ptr);
         /* Break Interrupt */
-        if ((ssr_status & 0x0010) && (scr_status & 0x0200))
-                sci_br_interrupt(irq, ptr);
+        if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
+                ret = sci_br_interrupt(irq, ptr);
 
-        return IRQ_HANDLED;
+        return ret;
 }
 
 #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
@@ -1054,10 +1042,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 
         sci_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
 
-#if !defined(SCI_ONLY)
         if (port->type == PORT_SCIF)
                 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
-#endif
 
         smr_val = sci_in(port, SCSMR) & 3;
         if ((termios->c_cflag & CSIZE) == CS7)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 7cd28b226800..6163a45f968f 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -16,7 +16,6 @@
 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define SCI_AND_SCIF
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 # define SCIF0          0xA4400000
 # define SCIF2          0xA4410000
@@ -30,17 +29,15 @@
  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  */
 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721)
 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define SCIF_ONLY
 #define SCIF_ORER    0x0200   /* overrun error bit */
 #elif defined(CONFIG_SH_RTS7751R2D)
+# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
@@ -53,28 +50,24 @@
 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
-# define SCI_AND_SCIF
 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
 # define PACR 0xa4050100
 # define PBCR 0xa4050102
 # define SCSCR_INIT(port)          0x3B
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 # define PADR                   0xA4050120
 # define PSDR                   0xA405013e
@@ -82,7 +75,6 @@
 # define PSCR                   0xA405011E
 # define SCIF_ORER              0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
 # define SCSPTR0                SCPDR0
@@ -97,12 +89,10 @@
 # define SCSPTR5                0xa4050128
 # define SCIF_ORER              0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 # define SCIF_BASE_ADDR    0x01030000
 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
@@ -111,14 +101,11 @@
 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define SCI_ONLY
 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 #elif defined(CONFIG_H8S2678)
 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define SCI_ONLY
 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
@@ -126,20 +113,17 @@
 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 # define SCIF_ORER 0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 # define SCIF_ORER      0x0001          /* Overrun error bit */
 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
@@ -149,7 +133,6 @@
 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 # define SCIF_OPER      0x0001          /* Overrun error bit */
 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
       defined(CONFIG_CPU_SUBTYPE_SH7263)
@@ -158,14 +141,12 @@
 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
@@ -173,7 +154,6 @@
 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 # define SCIF_ORER 0x0001               /* Overrun error bit */
 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-# define SCIF_ONLY
 #else
 # error CPU subtype not defined
 #endif
@@ -186,6 +166,7 @@
 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7722)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
@@ -244,55 +225,28 @@
 # define SCIF_TXROOM_MAX 16
 #endif
 
-#if defined(SCI_ONLY)
-# define SCxSR_TEND(port)               SCI_TEND
-# define SCxSR_ERRORS(port)             SCI_ERRORS
-# define SCxSR_RDxF(port)               SCI_RDRF
-# define SCxSR_TDxE(port)               SCI_TDRE
-# define SCxSR_ORER(port)               SCI_ORER
-# define SCxSR_FER(port)                SCI_FER
-# define SCxSR_PER(port)                SCI_PER
-# define SCxSR_BRK(port)                0x00
-# define SCxSR_RDxF_CLEAR(port)         0xbc
-# define SCxSR_ERROR_CLEAR(port)        0xc4
-# define SCxSR_TDxE_CLEAR(port)         0x78
-# define SCxSR_BREAK_CLEAR(port)        0xc4
-#elif defined(SCIF_ONLY)
-# define SCxSR_TEND(port)               SCIF_TEND
-# define SCxSR_ERRORS(port)             SCIF_ERRORS
-# define SCxSR_RDxF(port)               SCIF_RDF
-# define SCxSR_TDxE(port)               SCIF_TDFE
+#define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
+#define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
+#define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
+#define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
+#define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
+#define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
+#define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
+
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
-# define SCxSR_ORER(port)               SCIF_ORER
+# define SCxSR_ORER(port)       (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
 #else
-# define SCxSR_ORER(port)               0x0000
+# define SCxSR_ORER(port)       (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
 #endif
-# define SCxSR_FER(port)                SCIF_FER
-# define SCxSR_PER(port)                SCIF_PER
-# define SCxSR_BRK(port)                SCIF_BRK
+
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
     defined(CONFIG_CPU_SUBTYPE_SH7721)
-# define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
-# define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
-# define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
-# define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
-#else
-/* SH7705 can also use this, clearing is same between 7705 and 7709 */
-# define SCxSR_RDxF_CLEAR(port)         0x00fc
-# define SCxSR_ERROR_CLEAR(port)        0x0073
-# define SCxSR_TDxE_CLEAR(port)         0x00df
-# define SCxSR_BREAK_CLEAR(port)        0x00e3
-#endif
+# define SCxSR_RDxF_CLEAR(port)  (sci_in(port, SCxSR) & 0xfffc)
+# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
+# define SCxSR_TDxE_CLEAR(port)  (sci_in(port, SCxSR) & 0xffdf)
+# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
 #else
-# define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
-# define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
-# define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
-# define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
-# define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
-# define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
-# define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
-# define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
@@ -574,18 +528,20 @@ static inline int sci_rxd_in(struct uart_port *port)
       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
-      defined(CONFIG_CPU_SUBTYPE_SH4_202)
+      defined(CONFIG_CPU_SUBTYPE_SH7091)
 static inline int sci_rxd_in(struct uart_port *port)
 {
-#ifndef SCIF_ONLY
         if (port->mapbase == 0xffe00000)
                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
-#endif
-#ifndef SCI_ONLY
         if (port->mapbase == 0xffe80000)
                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
-#endif
+        return 1;
+}
+#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+        if (port->mapbase == 0xffe80000)
+                return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
         return 1;
 }
 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
@@ -651,7 +607,7 @@ static inline int sci_rxd_in(struct uart_port *port)
 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 static inline int sci_rxd_in(struct uart_port *port)
 {
-         return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
+         return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 }
 #elif defined(__H8300H__) || defined(__H8300S__)
 static inline int sci_rxd_in(struct uart_port *port)