aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/serial
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-07 17:39:20 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-07 17:39:20 -0500
commit56b85f32d530d09d6805488ad00775d4e0e3baab (patch)
treee7fbe69e338ef775d3b2dd822aa915d259b4bc94 /drivers/serial
parent3e5b08cbbf78bedd316904ab0cf3b27119433ee5 (diff)
parent568389c257fa7d74ce36c2f78bad31965fded4cf (diff)
Merge branch 'tty-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6
* 'tty-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6: (36 commits) serial: apbuart: Fixup apbuart_console_init() TTY: Add tty ioctl to figure device node of the system console. tty: add 'active' sysfs attribute to tty0 and console device drivers: serial: apbuart: Handle OF failures gracefully Serial: Avoid unbalanced IRQ wake disable during resume tty: fix typos/errors in tty_driver.h comments pch_uart : fix warnings for 64bit compile 8250: fix uninitialized FIFOs ip2: fix compiler warning on ip2main_pci_tbl specialix: fix compiler warning on specialix_pci_tbl rocket: fix compiler warning on rocket_pci_ids 8250: add a UPIO_DWAPB32 for 32 bit accesses 8250: use container_of() instead of casting serial: omap-serial: Add support for kernel debugger serial: fix pch_uart kconfig & build drivers: char: hvc: add arm JTAG DCC console support RS485 documentation: add 16C950 UART description serial: ifx6x60: fix memory leak serial: ifx6x60: free IRQ on error Serial: EG20T: add PCH_UART driver ... Fixed up conflicts in drivers/serial/apbuart.c with evil merge that makes the code look fairly sane (unlike either side).
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/8250.c109
-rw-r--r--drivers/serial/8250_pci.c36
-rw-r--r--drivers/serial/Kconfig25
-rw-r--r--drivers/serial/Makefile5
-rw-r--r--drivers/serial/apbuart.c57
-rw-r--r--drivers/serial/cpm_uart/cpm_uart.h6
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_core.c19
-rw-r--r--drivers/serial/ifx6x60.c1406
-rw-r--r--drivers/serial/ifx6x60.h129
-rw-r--r--drivers/serial/mpc52xx_uart.c6
-rw-r--r--drivers/serial/omap-serial.c38
-rw-r--r--drivers/serial/pch_uart.c1451
-rw-r--r--drivers/serial/serial_core.c10
-rw-r--r--drivers/serial/vt8500_serial.c648
14 files changed, 3867 insertions, 78 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index ee74c934de89..b25e6e490530 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -454,21 +454,40 @@ static void tsi_serial_out(struct uart_port *p, int offset, int value)
454 writeb(value, p->membase + offset); 454 writeb(value, p->membase + offset);
455} 455}
456 456
457/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
458static inline void dwapb_save_out_value(struct uart_port *p, int offset,
459 int value)
460{
461 struct uart_8250_port *up =
462 container_of(p, struct uart_8250_port, port);
463
464 if (offset == UART_LCR)
465 up->lcr = value;
466}
467
468/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
469static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
470{
471 if (offset == UART_TX || offset == UART_IER)
472 p->serial_in(p, UART_IER);
473}
474
457static void dwapb_serial_out(struct uart_port *p, int offset, int value) 475static void dwapb_serial_out(struct uart_port *p, int offset, int value)
458{ 476{
459 int save_offset = offset; 477 int save_offset = offset;
460 offset = map_8250_out_reg(p, offset) << p->regshift; 478 offset = map_8250_out_reg(p, offset) << p->regshift;
461 /* Save the LCR value so it can be re-written when a 479 dwapb_save_out_value(p, save_offset, value);
462 * Busy Detect interrupt occurs. */
463 if (save_offset == UART_LCR) {
464 struct uart_8250_port *up = (struct uart_8250_port *)p;
465 up->lcr = value;
466 }
467 writeb(value, p->membase + offset); 480 writeb(value, p->membase + offset);
468 /* Read the IER to ensure any interrupt is cleared before 481 dwapb_check_clear_ier(p, save_offset);
469 * returning from ISR. */ 482}
470 if (save_offset == UART_TX || save_offset == UART_IER) 483
471 value = p->serial_in(p, UART_IER); 484static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
485{
486 int save_offset = offset;
487 offset = map_8250_out_reg(p, offset) << p->regshift;
488 dwapb_save_out_value(p, save_offset, value);
489 writel(value, p->membase + offset);
490 dwapb_check_clear_ier(p, save_offset);
472} 491}
473 492
474static unsigned int io_serial_in(struct uart_port *p, int offset) 493static unsigned int io_serial_in(struct uart_port *p, int offset)
@@ -485,7 +504,8 @@ static void io_serial_out(struct uart_port *p, int offset, int value)
485 504
486static void set_io_from_upio(struct uart_port *p) 505static void set_io_from_upio(struct uart_port *p)
487{ 506{
488 struct uart_8250_port *up = (struct uart_8250_port *)p; 507 struct uart_8250_port *up =
508 container_of(p, struct uart_8250_port, port);
489 switch (p->iotype) { 509 switch (p->iotype) {
490 case UPIO_HUB6: 510 case UPIO_HUB6:
491 p->serial_in = hub6_serial_in; 511 p->serial_in = hub6_serial_in;
@@ -518,6 +538,11 @@ static void set_io_from_upio(struct uart_port *p)
518 p->serial_out = dwapb_serial_out; 538 p->serial_out = dwapb_serial_out;
519 break; 539 break;
520 540
541 case UPIO_DWAPB32:
542 p->serial_in = mem32_serial_in;
543 p->serial_out = dwapb32_serial_out;
544 break;
545
521 default: 546 default:
522 p->serial_in = io_serial_in; 547 p->serial_in = io_serial_in;
523 p->serial_out = io_serial_out; 548 p->serial_out = io_serial_out;
@@ -536,6 +561,7 @@ serial_out_sync(struct uart_8250_port *up, int offset, int value)
536 case UPIO_MEM32: 561 case UPIO_MEM32:
537 case UPIO_AU: 562 case UPIO_AU:
538 case UPIO_DWAPB: 563 case UPIO_DWAPB:
564 case UPIO_DWAPB32:
539 p->serial_out(p, offset, value); 565 p->serial_out(p, offset, value);
540 p->serial_in(p, UART_LCR); /* safe, no side-effects */ 566 p->serial_in(p, UART_LCR); /* safe, no side-effects */
541 break; 567 break;
@@ -1319,7 +1345,8 @@ static inline void __stop_tx(struct uart_8250_port *p)
1319 1345
1320static void serial8250_stop_tx(struct uart_port *port) 1346static void serial8250_stop_tx(struct uart_port *port)
1321{ 1347{
1322 struct uart_8250_port *up = (struct uart_8250_port *)port; 1348 struct uart_8250_port *up =
1349 container_of(port, struct uart_8250_port, port);
1323 1350
1324 __stop_tx(up); 1351 __stop_tx(up);
1325 1352
@@ -1336,7 +1363,8 @@ static void transmit_chars(struct uart_8250_port *up);
1336 1363
1337static void serial8250_start_tx(struct uart_port *port) 1364static void serial8250_start_tx(struct uart_port *port)
1338{ 1365{
1339 struct uart_8250_port *up = (struct uart_8250_port *)port; 1366 struct uart_8250_port *up =
1367 container_of(port, struct uart_8250_port, port);
1340 1368
1341 if (!(up->ier & UART_IER_THRI)) { 1369 if (!(up->ier & UART_IER_THRI)) {
1342 up->ier |= UART_IER_THRI; 1370 up->ier |= UART_IER_THRI;
@@ -1364,7 +1392,8 @@ static void serial8250_start_tx(struct uart_port *port)
1364 1392
1365static void serial8250_stop_rx(struct uart_port *port) 1393static void serial8250_stop_rx(struct uart_port *port)
1366{ 1394{
1367 struct uart_8250_port *up = (struct uart_8250_port *)port; 1395 struct uart_8250_port *up =
1396 container_of(port, struct uart_8250_port, port);
1368 1397
1369 up->ier &= ~UART_IER_RLSI; 1398 up->ier &= ~UART_IER_RLSI;
1370 up->port.read_status_mask &= ~UART_LSR_DR; 1399 up->port.read_status_mask &= ~UART_LSR_DR;
@@ -1373,7 +1402,8 @@ static void serial8250_stop_rx(struct uart_port *port)
1373 1402
1374static void serial8250_enable_ms(struct uart_port *port) 1403static void serial8250_enable_ms(struct uart_port *port)
1375{ 1404{
1376 struct uart_8250_port *up = (struct uart_8250_port *)port; 1405 struct uart_8250_port *up =
1406 container_of(port, struct uart_8250_port, port);
1377 1407
1378 /* no MSR capabilities */ 1408 /* no MSR capabilities */
1379 if (up->bugs & UART_BUG_NOMSR) 1409 if (up->bugs & UART_BUG_NOMSR)
@@ -1581,7 +1611,8 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1581 handled = 1; 1611 handled = 1;
1582 1612
1583 end = NULL; 1613 end = NULL;
1584 } else if (up->port.iotype == UPIO_DWAPB && 1614 } else if ((up->port.iotype == UPIO_DWAPB ||
1615 up->port.iotype == UPIO_DWAPB32) &&
1585 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 1616 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1586 /* The DesignWare APB UART has an Busy Detect (0x07) 1617 /* The DesignWare APB UART has an Busy Detect (0x07)
1587 * interrupt meaning an LCR write attempt occured while the 1618 * interrupt meaning an LCR write attempt occured while the
@@ -1781,7 +1812,8 @@ static void serial8250_backup_timeout(unsigned long data)
1781 1812
1782static unsigned int serial8250_tx_empty(struct uart_port *port) 1813static unsigned int serial8250_tx_empty(struct uart_port *port)
1783{ 1814{
1784 struct uart_8250_port *up = (struct uart_8250_port *)port; 1815 struct uart_8250_port *up =
1816 container_of(port, struct uart_8250_port, port);
1785 unsigned long flags; 1817 unsigned long flags;
1786 unsigned int lsr; 1818 unsigned int lsr;
1787 1819
@@ -1795,7 +1827,8 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
1795 1827
1796static unsigned int serial8250_get_mctrl(struct uart_port *port) 1828static unsigned int serial8250_get_mctrl(struct uart_port *port)
1797{ 1829{
1798 struct uart_8250_port *up = (struct uart_8250_port *)port; 1830 struct uart_8250_port *up =
1831 container_of(port, struct uart_8250_port, port);
1799 unsigned int status; 1832 unsigned int status;
1800 unsigned int ret; 1833 unsigned int ret;
1801 1834
@@ -1815,7 +1848,8 @@ static unsigned int serial8250_get_mctrl(struct uart_port *port)
1815 1848
1816static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 1849static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1817{ 1850{
1818 struct uart_8250_port *up = (struct uart_8250_port *)port; 1851 struct uart_8250_port *up =
1852 container_of(port, struct uart_8250_port, port);
1819 unsigned char mcr = 0; 1853 unsigned char mcr = 0;
1820 1854
1821 if (mctrl & TIOCM_RTS) 1855 if (mctrl & TIOCM_RTS)
@@ -1836,7 +1870,8 @@ static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1836 1870
1837static void serial8250_break_ctl(struct uart_port *port, int break_state) 1871static void serial8250_break_ctl(struct uart_port *port, int break_state)
1838{ 1872{
1839 struct uart_8250_port *up = (struct uart_8250_port *)port; 1873 struct uart_8250_port *up =
1874 container_of(port, struct uart_8250_port, port);
1840 unsigned long flags; 1875 unsigned long flags;
1841 1876
1842 spin_lock_irqsave(&up->port.lock, flags); 1877 spin_lock_irqsave(&up->port.lock, flags);
@@ -1890,7 +1925,8 @@ static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1890 1925
1891static int serial8250_get_poll_char(struct uart_port *port) 1926static int serial8250_get_poll_char(struct uart_port *port)
1892{ 1927{
1893 struct uart_8250_port *up = (struct uart_8250_port *)port; 1928 struct uart_8250_port *up =
1929 container_of(port, struct uart_8250_port, port);
1894 unsigned char lsr = serial_inp(up, UART_LSR); 1930 unsigned char lsr = serial_inp(up, UART_LSR);
1895 1931
1896 if (!(lsr & UART_LSR_DR)) 1932 if (!(lsr & UART_LSR_DR))
@@ -1904,7 +1940,8 @@ static void serial8250_put_poll_char(struct uart_port *port,
1904 unsigned char c) 1940 unsigned char c)
1905{ 1941{
1906 unsigned int ier; 1942 unsigned int ier;
1907 struct uart_8250_port *up = (struct uart_8250_port *)port; 1943 struct uart_8250_port *up =
1944 container_of(port, struct uart_8250_port, port);
1908 1945
1909 /* 1946 /*
1910 * First save the IER then disable the interrupts 1947 * First save the IER then disable the interrupts
@@ -1938,11 +1975,14 @@ static void serial8250_put_poll_char(struct uart_port *port,
1938 1975
1939static int serial8250_startup(struct uart_port *port) 1976static int serial8250_startup(struct uart_port *port)
1940{ 1977{
1941 struct uart_8250_port *up = (struct uart_8250_port *)port; 1978 struct uart_8250_port *up =
1979 container_of(port, struct uart_8250_port, port);
1942 unsigned long flags; 1980 unsigned long flags;
1943 unsigned char lsr, iir; 1981 unsigned char lsr, iir;
1944 int retval; 1982 int retval;
1945 1983
1984 up->port.fifosize = uart_config[up->port.type].fifo_size;
1985 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1946 up->capabilities = uart_config[up->port.type].flags; 1986 up->capabilities = uart_config[up->port.type].flags;
1947 up->mcr = 0; 1987 up->mcr = 0;
1948 1988
@@ -2166,7 +2206,8 @@ dont_test_tx_en:
2166 2206
2167static void serial8250_shutdown(struct uart_port *port) 2207static void serial8250_shutdown(struct uart_port *port)
2168{ 2208{
2169 struct uart_8250_port *up = (struct uart_8250_port *)port; 2209 struct uart_8250_port *up =
2210 container_of(port, struct uart_8250_port, port);
2170 unsigned long flags; 2211 unsigned long flags;
2171 2212
2172 /* 2213 /*
@@ -2235,7 +2276,8 @@ void
2235serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, 2276serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2236 struct ktermios *old) 2277 struct ktermios *old)
2237{ 2278{
2238 struct uart_8250_port *up = (struct uart_8250_port *)port; 2279 struct uart_8250_port *up =
2280 container_of(port, struct uart_8250_port, port);
2239 unsigned char cval, fcr = 0; 2281 unsigned char cval, fcr = 0;
2240 unsigned long flags; 2282 unsigned long flags;
2241 unsigned int baud, quot; 2283 unsigned int baud, quot;
@@ -2435,7 +2477,8 @@ serial8250_set_ldisc(struct uart_port *port, int new)
2435void serial8250_do_pm(struct uart_port *port, unsigned int state, 2477void serial8250_do_pm(struct uart_port *port, unsigned int state,
2436 unsigned int oldstate) 2478 unsigned int oldstate)
2437{ 2479{
2438 struct uart_8250_port *p = (struct uart_8250_port *)port; 2480 struct uart_8250_port *p =
2481 container_of(port, struct uart_8250_port, port);
2439 2482
2440 serial8250_set_sleep(p, state != 0); 2483 serial8250_set_sleep(p, state != 0);
2441} 2484}
@@ -2476,6 +2519,7 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
2476 case UPIO_MEM32: 2519 case UPIO_MEM32:
2477 case UPIO_MEM: 2520 case UPIO_MEM:
2478 case UPIO_DWAPB: 2521 case UPIO_DWAPB:
2522 case UPIO_DWAPB32:
2479 if (!up->port.mapbase) 2523 if (!up->port.mapbase)
2480 break; 2524 break;
2481 2525
@@ -2513,6 +2557,7 @@ static void serial8250_release_std_resource(struct uart_8250_port *up)
2513 case UPIO_MEM32: 2557 case UPIO_MEM32:
2514 case UPIO_MEM: 2558 case UPIO_MEM:
2515 case UPIO_DWAPB: 2559 case UPIO_DWAPB:
2560 case UPIO_DWAPB32:
2516 if (!up->port.mapbase) 2561 if (!up->port.mapbase)
2517 break; 2562 break;
2518 2563
@@ -2566,7 +2611,8 @@ static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2566 2611
2567static void serial8250_release_port(struct uart_port *port) 2612static void serial8250_release_port(struct uart_port *port)
2568{ 2613{
2569 struct uart_8250_port *up = (struct uart_8250_port *)port; 2614 struct uart_8250_port *up =
2615 container_of(port, struct uart_8250_port, port);
2570 2616
2571 serial8250_release_std_resource(up); 2617 serial8250_release_std_resource(up);
2572 if (up->port.type == PORT_RSA) 2618 if (up->port.type == PORT_RSA)
@@ -2575,7 +2621,8 @@ static void serial8250_release_port(struct uart_port *port)
2575 2621
2576static int serial8250_request_port(struct uart_port *port) 2622static int serial8250_request_port(struct uart_port *port)
2577{ 2623{
2578 struct uart_8250_port *up = (struct uart_8250_port *)port; 2624 struct uart_8250_port *up =
2625 container_of(port, struct uart_8250_port, port);
2579 int ret = 0; 2626 int ret = 0;
2580 2627
2581 ret = serial8250_request_std_resource(up); 2628 ret = serial8250_request_std_resource(up);
@@ -2590,7 +2637,8 @@ static int serial8250_request_port(struct uart_port *port)
2590 2637
2591static void serial8250_config_port(struct uart_port *port, int flags) 2638static void serial8250_config_port(struct uart_port *port, int flags)
2592{ 2639{
2593 struct uart_8250_port *up = (struct uart_8250_port *)port; 2640 struct uart_8250_port *up =
2641 container_of(port, struct uart_8250_port, port);
2594 int probeflags = PROBE_ANY; 2642 int probeflags = PROBE_ANY;
2595 int ret; 2643 int ret;
2596 2644
@@ -2771,7 +2819,8 @@ serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2771 2819
2772static void serial8250_console_putchar(struct uart_port *port, int ch) 2820static void serial8250_console_putchar(struct uart_port *port, int ch)
2773{ 2821{
2774 struct uart_8250_port *up = (struct uart_8250_port *)port; 2822 struct uart_8250_port *up =
2823 container_of(port, struct uart_8250_port, port);
2775 2824
2776 wait_for_xmitr(up, UART_LSR_THRE); 2825 wait_for_xmitr(up, UART_LSR_THRE);
2777 serial_out(up, UART_TX, ch); 2826 serial_out(up, UART_TX, ch);
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 842e3b2a02b1..8b8930f700b5 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -957,6 +957,22 @@ pci_default_setup(struct serial_private *priv,
957 return setup_port(priv, port, bar, offset, board->reg_shift); 957 return setup_port(priv, port, bar, offset, board->reg_shift);
958} 958}
959 959
960static int
961ce4100_serial_setup(struct serial_private *priv,
962 const struct pciserial_board *board,
963 struct uart_port *port, int idx)
964{
965 int ret;
966
967 ret = setup_port(priv, port, 0, 0, board->reg_shift);
968 port->iotype = UPIO_MEM32;
969 port->type = PORT_XSCALE;
970 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
971 port->regshift = 2;
972
973 return ret;
974}
975
960static int skip_tx_en_setup(struct serial_private *priv, 976static int skip_tx_en_setup(struct serial_private *priv,
961 const struct pciserial_board *board, 977 const struct pciserial_board *board,
962 struct uart_port *port, int idx) 978 struct uart_port *port, int idx)
@@ -981,6 +997,7 @@ static int skip_tx_en_setup(struct serial_private *priv,
981#define PCI_SUBDEVICE_ID_POCTAL232 0x0308 997#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
982#define PCI_SUBDEVICE_ID_POCTAL422 0x0408 998#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
983#define PCI_VENDOR_ID_ADVANTECH 0x13fe 999#define PCI_VENDOR_ID_ADVANTECH 0x13fe
1000#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
984#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1001#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
985#define PCI_DEVICE_ID_TITAN_200I 0x8028 1002#define PCI_DEVICE_ID_TITAN_200I 0x8028
986#define PCI_DEVICE_ID_TITAN_400I 0x8048 1003#define PCI_DEVICE_ID_TITAN_400I 0x8048
@@ -1072,6 +1089,13 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1072 .subdevice = PCI_ANY_ID, 1089 .subdevice = PCI_ANY_ID,
1073 .setup = skip_tx_en_setup, 1090 .setup = skip_tx_en_setup,
1074 }, 1091 },
1092 {
1093 .vendor = PCI_VENDOR_ID_INTEL,
1094 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1095 .subvendor = PCI_ANY_ID,
1096 .subdevice = PCI_ANY_ID,
1097 .setup = ce4100_serial_setup,
1098 },
1075 /* 1099 /*
1076 * ITE 1100 * ITE
1077 */ 1101 */
@@ -1592,6 +1616,7 @@ enum pci_board_num_t {
1592 pbn_ADDIDATA_PCIe_2_3906250, 1616 pbn_ADDIDATA_PCIe_2_3906250,
1593 pbn_ADDIDATA_PCIe_4_3906250, 1617 pbn_ADDIDATA_PCIe_4_3906250,
1594 pbn_ADDIDATA_PCIe_8_3906250, 1618 pbn_ADDIDATA_PCIe_8_3906250,
1619 pbn_ce4100_1_115200,
1595}; 1620};
1596 1621
1597/* 1622/*
@@ -2281,6 +2306,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
2281 .uart_offset = 0x200, 2306 .uart_offset = 0x200,
2282 .first_offset = 0x1000, 2307 .first_offset = 0x1000,
2283 }, 2308 },
2309 [pbn_ce4100_1_115200] = {
2310 .flags = FL_BASE0,
2311 .num_ports = 1,
2312 .base_baud = 921600,
2313 .reg_shift = 2,
2314 },
2284}; 2315};
2285 2316
2286static const struct pci_device_id softmodem_blacklist[] = { 2317static const struct pci_device_id softmodem_blacklist[] = {
@@ -3765,6 +3796,11 @@ static struct pci_device_id serial_pci_tbl[] = {
3765 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 3796 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3766 0xA000, 0x3004, 3797 0xA000, 0x3004,
3767 0, 0, pbn_b0_bt_4_115200 }, 3798 0, 0, pbn_b0_bt_4_115200 },
3799 /* Intel CE4100 */
3800 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3802 pbn_ce4100_1_115200 },
3803
3768 3804
3769 /* 3805 /*
3770 * These entries match devices with class COMMUNICATION_SERIAL, 3806 * These entries match devices with class COMMUNICATION_SERIAL,
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index aff9dcd051c6..ec3c214598d0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1381,6 +1381,16 @@ config SERIAL_MSM_CONSOLE
1381 depends on SERIAL_MSM=y 1381 depends on SERIAL_MSM=y
1382 select SERIAL_CORE_CONSOLE 1382 select SERIAL_CORE_CONSOLE
1383 1383
1384config SERIAL_VT8500
1385 bool "VIA VT8500 on-chip serial port support"
1386 depends on ARM && ARCH_VT8500
1387 select SERIAL_CORE
1388
1389config SERIAL_VT8500_CONSOLE
1390 bool "VIA VT8500 serial console support"
1391 depends on SERIAL_VT8500=y
1392 select SERIAL_CORE_CONSOLE
1393
1384config SERIAL_NETX 1394config SERIAL_NETX
1385 tristate "NetX serial port support" 1395 tristate "NetX serial port support"
1386 depends on ARM && ARCH_NETX 1396 depends on ARM && ARCH_NETX
@@ -1632,4 +1642,19 @@ config SERIAL_ALTERA_UART_CONSOLE
1632 help 1642 help
1633 Enable a Altera UART port to be the system console. 1643 Enable a Altera UART port to be the system console.
1634 1644
1645config SERIAL_IFX6X60
1646 tristate "SPI protocol driver for Infineon 6x60 modem (EXPERIMENTAL)"
1647 depends on GPIOLIB && SPI && EXPERIMENTAL
1648 help
1649 Support for the IFX6x60 modem devices on Intel MID platforms.
1650
1651config SERIAL_PCH_UART
1652 tristate "Intel EG20T PCH UART"
1653 depends on PCI && DMADEVICES
1654 select SERIAL_CORE
1655 select PCH_DMA
1656 help
1657 This driver is for PCH(Platform controller Hub) UART of Intel EG20T
1658 which is an IOH(Input/Output Hub) for x86 embedded processor.
1659 Enabling PCH_DMA, this PCH UART works as DMA mode.
1635endmenu 1660endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index c5705765454f..8ea92e9c73b0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -80,12 +80,15 @@ obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
80obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o 80obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
81obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o 81obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
82obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o 82obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
83obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
83obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o 84obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
84obj-$(CONFIG_SERIAL_QE) += ucc_uart.o 85obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
85obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o 86obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
86obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o 87obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
87obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o 88obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
88obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o 89obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
90obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o
89obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o 91obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
90obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o 92obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
91obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o 93obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
94obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
diff --git a/drivers/serial/apbuart.c b/drivers/serial/apbuart.c
index 767ce9e396c5..095a5d562618 100644
--- a/drivers/serial/apbuart.c
+++ b/drivers/serial/apbuart.c
@@ -521,11 +521,12 @@ static struct console grlib_apbuart_console = {
521}; 521};
522 522
523 523
524static void grlib_apbuart_configure(void); 524static int grlib_apbuart_configure(void);
525 525
526static int __init apbuart_console_init(void) 526static int __init apbuart_console_init(void)
527{ 527{
528 grlib_apbuart_configure(); 528 if (grlib_apbuart_configure())
529 return -ENODEV;
529 register_console(&grlib_apbuart_console); 530 register_console(&grlib_apbuart_console);
530 return 0; 531 return 0;
531} 532}
@@ -596,57 +597,49 @@ static struct of_platform_driver grlib_apbuart_of_driver = {
596}; 597};
597 598
598 599
599static void grlib_apbuart_configure(void) 600static int grlib_apbuart_configure(void)
600{ 601{
601 static int enum_done;
602 struct device_node *np, *rp; 602 struct device_node *np, *rp;
603 struct uart_port *port = NULL;
604 const u32 *prop; 603 const u32 *prop;
605 int freq_khz; 604 int freq_khz, line = 0;
606 int v = 0, d = 0;
607 unsigned int addr;
608 int irq, line;
609 struct amba_prom_registers *regs;
610
611 if (enum_done)
612 return;
613 605
614 /* Get bus frequency */ 606 /* Get bus frequency */
615 rp = of_find_node_by_path("/"); 607 rp = of_find_node_by_path("/");
608 if (!rp)
609 return -ENODEV;
616 rp = of_get_next_child(rp, NULL); 610 rp = of_get_next_child(rp, NULL);
611 if (!rp)
612 return -ENODEV;
617 prop = of_get_property(rp, "clock-frequency", NULL); 613 prop = of_get_property(rp, "clock-frequency", NULL);
614 if (!prop)
615 return -ENODEV;
618 freq_khz = *prop; 616 freq_khz = *prop;
619 617
620 line = 0;
621 for_each_matching_node(np, apbuart_match) { 618 for_each_matching_node(np, apbuart_match) {
619 const int *irqs, *ampopts;
620 const struct amba_prom_registers *regs;
621 struct uart_port *port;
622 unsigned long addr;
622 623
623 int *vendor = (int *) of_get_property(np, "vendor", NULL); 624 ampopts = of_get_property(np, "ampopts", NULL);
624 int *device = (int *) of_get_property(np, "device", NULL);
625 int *irqs = (int *) of_get_property(np, "interrupts", NULL);
626 int *ampopts = (int *) of_get_property(np, "ampopts", NULL);
627 regs = (struct amba_prom_registers *)
628 of_get_property(np, "reg", NULL);
629
630 if (ampopts && (*ampopts == 0)) 625 if (ampopts && (*ampopts == 0))
631 continue; /* Ignore if used by another OS instance */ 626 continue; /* Ignore if used by another OS instance */
632 if (vendor) 627
633 v = *vendor; 628 irqs = of_get_property(np, "interrupts", NULL);
634 if (device) 629 regs = of_get_property(np, "reg", NULL);
635 d = *device;
636 630
637 if (!irqs || !regs) 631 if (!irqs || !regs)
638 return; 632 continue;
639 633
640 grlib_apbuart_nodes[line] = np; 634 grlib_apbuart_nodes[line] = np;
641 635
642 addr = regs->phys_addr; 636 addr = regs->phys_addr;
643 irq = *irqs;
644 637
645 port = &grlib_apbuart_ports[line]; 638 port = &grlib_apbuart_ports[line];
646 639
647 port->mapbase = addr; 640 port->mapbase = addr;
648 port->membase = ioremap(addr, sizeof(struct grlib_apbuart_regs_map)); 641 port->membase = ioremap(addr, sizeof(struct grlib_apbuart_regs_map));
649 port->irq = irq; 642 port->irq = *irqs;
650 port->iotype = UPIO_MEM; 643 port->iotype = UPIO_MEM;
651 port->ops = &grlib_apbuart_ops; 644 port->ops = &grlib_apbuart_ops;
652 port->flags = UPF_BOOT_AUTOCONF; 645 port->flags = UPF_BOOT_AUTOCONF;
@@ -658,12 +651,10 @@ static void grlib_apbuart_configure(void)
658 /* We support maximum UART_NR uarts ... */ 651 /* We support maximum UART_NR uarts ... */
659 if (line == UART_NR) 652 if (line == UART_NR)
660 break; 653 break;
661
662 } 654 }
663 655
664 enum_done = 1;
665
666 grlib_apbuart_driver.nr = grlib_apbuart_port_nr = line; 656 grlib_apbuart_driver.nr = grlib_apbuart_port_nr = line;
657 return line ? 0 : -ENODEV;
667} 658}
668 659
669static int __init grlib_apbuart_init(void) 660static int __init grlib_apbuart_init(void)
@@ -671,7 +662,9 @@ static int __init grlib_apbuart_init(void)
671 int ret; 662 int ret;
672 663
673 /* Find all APBUARTS in device the tree and initialize their ports */ 664 /* Find all APBUARTS in device the tree and initialize their ports */
674 grlib_apbuart_configure(); 665 ret = grlib_apbuart_configure();
666 if (ret)
667 return ret;
675 668
676 printk(KERN_INFO "Serial: GRLIB APBUART driver\n"); 669 printk(KERN_INFO "Serial: GRLIB APBUART driver\n");
677 670
diff --git a/drivers/serial/cpm_uart/cpm_uart.h b/drivers/serial/cpm_uart/cpm_uart.h
index 7274b527a3c1..b754dcf0fda5 100644
--- a/drivers/serial/cpm_uart/cpm_uart.h
+++ b/drivers/serial/cpm_uart/cpm_uart.h
@@ -76,18 +76,12 @@ struct uart_cpm_port {
76 unsigned char *tx_buf; 76 unsigned char *tx_buf;
77 unsigned char *rx_buf; 77 unsigned char *rx_buf;
78 u32 flags; 78 u32 flags;
79 void (*set_lineif)(struct uart_cpm_port *);
80 struct clk *clk; 79 struct clk *clk;
81 u8 brg; 80 u8 brg;
82 uint dp_addr; 81 uint dp_addr;
83 void *mem_addr; 82 void *mem_addr;
84 dma_addr_t dma_addr; 83 dma_addr_t dma_addr;
85 u32 mem_size; 84 u32 mem_size;
86 /* helpers */
87 int baud;
88 int bits;
89 /* Keep track of 'odd' SMC2 wirings */
90 int is_portb;
91 /* wait on close if needed */ 85 /* wait on close if needed */
92 int wait_closing; 86 int wait_closing;
93 /* value to combine with opcode to form cpm command */ 87 /* value to combine with opcode to form cpm command */
diff --git a/drivers/serial/cpm_uart/cpm_uart_core.c b/drivers/serial/cpm_uart/cpm_uart_core.c
index f2b8adcc6c92..8692ff98fc07 100644
--- a/drivers/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/serial/cpm_uart/cpm_uart_core.c
@@ -72,6 +72,8 @@ static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
72 72
73/**************************************************************/ 73/**************************************************************/
74 74
75#define HW_BUF_SPD_THRESHOLD 9600
76
75/* 77/*
76 * Check, if transmit buffers are processed 78 * Check, if transmit buffers are processed
77*/ 79*/
@@ -503,6 +505,11 @@ static void cpm_uart_set_termios(struct uart_port *port,
503 pr_debug("CPM uart[%d]:set_termios\n", port->line); 505 pr_debug("CPM uart[%d]:set_termios\n", port->line);
504 506
505 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 507 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
508 if (baud <= HW_BUF_SPD_THRESHOLD ||
509 (pinfo->port.state && pinfo->port.state->port.tty->low_latency))
510 pinfo->rx_fifosize = 1;
511 else
512 pinfo->rx_fifosize = RX_BUF_SIZE;
506 513
507 /* Character length programmed into the mode register is the 514 /* Character length programmed into the mode register is the
508 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, 515 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
@@ -594,6 +601,17 @@ static void cpm_uart_set_termios(struct uart_port *port,
594 */ 601 */
595 bits++; 602 bits++;
596 if (IS_SMC(pinfo)) { 603 if (IS_SMC(pinfo)) {
604 /*
605 * MRBLR can be changed while an SMC/SCC is operating only
606 * if it is done in a single bus cycle with one 16-bit move
607 * (not two 8-bit bus cycles back-to-back). This occurs when
608 * the cp shifts control to the next RxBD, so the change does
609 * not take effect immediately. To guarantee the exact RxBD
610 * on which the change occurs, change MRBLR only while the
611 * SMC/SCC receiver is disabled.
612 */
613 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
614
597 /* Set the mode register. We want to keep a copy of the 615 /* Set the mode register. We want to keep a copy of the
598 * enables, because we want to put them back if they were 616 * enables, because we want to put them back if they were
599 * present. 617 * present.
@@ -604,6 +622,7 @@ static void cpm_uart_set_termios(struct uart_port *port,
604 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | 622 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
605 SMCMR_SM_UART | prev_mode); 623 SMCMR_SM_UART | prev_mode);
606 } else { 624 } else {
625 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
607 out_be16(&sccp->scc_psmr, (sbits << 12) | scval); 626 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
608 } 627 }
609 628
diff --git a/drivers/serial/ifx6x60.c b/drivers/serial/ifx6x60.c
new file mode 100644
index 000000000000..ab93763862d5
--- /dev/null
+++ b/drivers/serial/ifx6x60.c
@@ -0,0 +1,1406 @@
1/****************************************************************************
2 *
3 * Driver for the IFX 6x60 spi modem.
4 *
5 * Copyright (C) 2008 Option International
6 * Copyright (C) 2008 Filip Aben <f.aben@option.com>
7 * Denis Joseph Barrow <d.barow@option.com>
8 * Jan Dumon <j.dumon@option.com>
9 *
10 * Copyright (C) 2009, 2010 Intel Corp
11 * Russ Gorby <richardx.r.gorby@intel.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
25 * USA
26 *
27 * Driver modified by Intel from Option gtm501l_spi.c
28 *
29 * Notes
30 * o The driver currently assumes a single device only. If you need to
31 * change this then look for saved_ifx_dev and add a device lookup
32 * o The driver is intended to be big-endian safe but has never been
33 * tested that way (no suitable hardware). There are a couple of FIXME
34 * notes by areas that may need addressing
35 * o Some of the GPIO naming/setup assumptions may need revisiting if
36 * you need to use this driver for another platform.
37 *
38 *****************************************************************************/
39#include <linux/module.h>
40#include <linux/termios.h>
41#include <linux/tty.h>
42#include <linux/device.h>
43#include <linux/spi/spi.h>
44#include <linux/tty.h>
45#include <linux/kfifo.h>
46#include <linux/tty_flip.h>
47#include <linux/timer.h>
48#include <linux/serial.h>
49#include <linux/interrupt.h>
50#include <linux/irq.h>
51#include <linux/rfkill.h>
52#include <linux/fs.h>
53#include <linux/ip.h>
54#include <linux/dmapool.h>
55#include <linux/gpio.h>
56#include <linux/sched.h>
57#include <linux/time.h>
58#include <linux/wait.h>
59#include <linux/tty.h>
60#include <linux/pm.h>
61#include <linux/pm_runtime.h>
62#include <linux/spi/ifx_modem.h>
63#include <linux/delay.h>
64
65#include "ifx6x60.h"
66
67#define IFX_SPI_MORE_MASK 0x10
68#define IFX_SPI_MORE_BIT 12 /* bit position in u16 */
69#define IFX_SPI_CTS_BIT 13 /* bit position in u16 */
70#define IFX_SPI_TTY_ID 0
71#define IFX_SPI_TIMEOUT_SEC 2
72#define IFX_SPI_HEADER_0 (-1)
73#define IFX_SPI_HEADER_F (-2)
74
75/* forward reference */
76static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev);
77
78/* local variables */
79static int spi_b16 = 1; /* 8 or 16 bit word length */
80static struct tty_driver *tty_drv;
81static struct ifx_spi_device *saved_ifx_dev;
82static struct lock_class_key ifx_spi_key;
83
84/* GPIO/GPE settings */
85
86/**
87 * mrdy_set_high - set MRDY GPIO
88 * @ifx: device we are controlling
89 *
90 */
91static inline void mrdy_set_high(struct ifx_spi_device *ifx)
92{
93 gpio_set_value(ifx->gpio.mrdy, 1);
94}
95
96/**
97 * mrdy_set_low - clear MRDY GPIO
98 * @ifx: device we are controlling
99 *
100 */
101static inline void mrdy_set_low(struct ifx_spi_device *ifx)
102{
103 gpio_set_value(ifx->gpio.mrdy, 0);
104}
105
106/**
107 * ifx_spi_power_state_set
108 * @ifx_dev: our SPI device
109 * @val: bits to set
110 *
111 * Set bit in power status and signal power system if status becomes non-0
112 */
113static void
114ifx_spi_power_state_set(struct ifx_spi_device *ifx_dev, unsigned char val)
115{
116 unsigned long flags;
117
118 spin_lock_irqsave(&ifx_dev->power_lock, flags);
119
120 /*
121 * if power status is already non-0, just update, else
122 * tell power system
123 */
124 if (!ifx_dev->power_status)
125 pm_runtime_get(&ifx_dev->spi_dev->dev);
126 ifx_dev->power_status |= val;
127
128 spin_unlock_irqrestore(&ifx_dev->power_lock, flags);
129}
130
131/**
132 * ifx_spi_power_state_clear - clear power bit
133 * @ifx_dev: our SPI device
134 * @val: bits to clear
135 *
136 * clear bit in power status and signal power system if status becomes 0
137 */
138static void
139ifx_spi_power_state_clear(struct ifx_spi_device *ifx_dev, unsigned char val)
140{
141 unsigned long flags;
142
143 spin_lock_irqsave(&ifx_dev->power_lock, flags);
144
145 if (ifx_dev->power_status) {
146 ifx_dev->power_status &= ~val;
147 if (!ifx_dev->power_status)
148 pm_runtime_put(&ifx_dev->spi_dev->dev);
149 }
150
151 spin_unlock_irqrestore(&ifx_dev->power_lock, flags);
152}
153
154/**
155 * swap_buf
156 * @buf: our buffer
157 * @len : number of bytes (not words) in the buffer
158 * @end: end of buffer
159 *
160 * Swap the contents of a buffer into big endian format
161 */
162static inline void swap_buf(u16 *buf, int len, void *end)
163{
164 int n;
165
166 len = ((len + 1) >> 1);
167 if ((void *)&buf[len] > end) {
168 pr_err("swap_buf: swap exceeds boundary (%p > %p)!",
169 &buf[len], end);
170 return;
171 }
172 for (n = 0; n < len; n++) {
173 *buf = cpu_to_be16(*buf);
174 buf++;
175 }
176}
177
178/**
179 * mrdy_assert - assert MRDY line
180 * @ifx_dev: our SPI device
181 *
182 * Assert mrdy and set timer to wait for SRDY interrupt, if SRDY is low
183 * now.
184 *
185 * FIXME: Can SRDY even go high as we are running this code ?
186 */
187static void mrdy_assert(struct ifx_spi_device *ifx_dev)
188{
189 int val = gpio_get_value(ifx_dev->gpio.srdy);
190 if (!val) {
191 if (!test_and_set_bit(IFX_SPI_STATE_TIMER_PENDING,
192 &ifx_dev->flags)) {
193 ifx_dev->spi_timer.expires =
194 jiffies + IFX_SPI_TIMEOUT_SEC*HZ;
195 add_timer(&ifx_dev->spi_timer);
196
197 }
198 }
199 ifx_spi_power_state_set(ifx_dev, IFX_SPI_POWER_DATA_PENDING);
200 mrdy_set_high(ifx_dev);
201}
202
203/**
204 * ifx_spi_hangup - hang up an IFX device
205 * @ifx_dev: our SPI device
206 *
207 * Hang up the tty attached to the IFX device if one is currently
208 * open. If not take no action
209 */
210static void ifx_spi_ttyhangup(struct ifx_spi_device *ifx_dev)
211{
212 struct tty_port *pport = &ifx_dev->tty_port;
213 struct tty_struct *tty = tty_port_tty_get(pport);
214 if (tty) {
215 tty_hangup(tty);
216 tty_kref_put(tty);
217 }
218}
219
220/**
221 * ifx_spi_timeout - SPI timeout
222 * @arg: our SPI device
223 *
224 * The SPI has timed out: hang up the tty. Users will then see a hangup
225 * and error events.
226 */
227static void ifx_spi_timeout(unsigned long arg)
228{
229 struct ifx_spi_device *ifx_dev = (struct ifx_spi_device *)arg;
230
231 dev_warn(&ifx_dev->spi_dev->dev, "*** SPI Timeout ***");
232 ifx_spi_ttyhangup(ifx_dev);
233 mrdy_set_low(ifx_dev);
234 clear_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags);
235}
236
237/* char/tty operations */
238
239/**
240 * ifx_spi_tiocmget - get modem lines
241 * @tty: our tty device
242 * @filp: file handle issuing the request
243 *
244 * Map the signal state into Linux modem flags and report the value
245 * in Linux terms
246 */
247static int ifx_spi_tiocmget(struct tty_struct *tty, struct file *filp)
248{
249 unsigned int value;
250 struct ifx_spi_device *ifx_dev = tty->driver_data;
251
252 value =
253 (test_bit(IFX_SPI_RTS, &ifx_dev->signal_state) ? TIOCM_RTS : 0) |
254 (test_bit(IFX_SPI_DTR, &ifx_dev->signal_state) ? TIOCM_DTR : 0) |
255 (test_bit(IFX_SPI_CTS, &ifx_dev->signal_state) ? TIOCM_CTS : 0) |
256 (test_bit(IFX_SPI_DSR, &ifx_dev->signal_state) ? TIOCM_DSR : 0) |
257 (test_bit(IFX_SPI_DCD, &ifx_dev->signal_state) ? TIOCM_CAR : 0) |
258 (test_bit(IFX_SPI_RI, &ifx_dev->signal_state) ? TIOCM_RNG : 0);
259 return value;
260}
261
262/**
263 * ifx_spi_tiocmset - set modem bits
264 * @tty: the tty structure
265 * @filp: file handle issuing the request
266 * @set: bits to set
267 * @clear: bits to clear
268 *
269 * The IFX6x60 only supports DTR and RTS. Set them accordingly
270 * and flag that an update to the modem is needed.
271 *
272 * FIXME: do we need to kick the tranfers when we do this ?
273 */
274static int ifx_spi_tiocmset(struct tty_struct *tty, struct file *filp,
275 unsigned int set, unsigned int clear)
276{
277 struct ifx_spi_device *ifx_dev = tty->driver_data;
278
279 if (set & TIOCM_RTS)
280 set_bit(IFX_SPI_RTS, &ifx_dev->signal_state);
281 if (set & TIOCM_DTR)
282 set_bit(IFX_SPI_DTR, &ifx_dev->signal_state);
283 if (clear & TIOCM_RTS)
284 clear_bit(IFX_SPI_RTS, &ifx_dev->signal_state);
285 if (clear & TIOCM_DTR)
286 clear_bit(IFX_SPI_DTR, &ifx_dev->signal_state);
287
288 set_bit(IFX_SPI_UPDATE, &ifx_dev->signal_state);
289 return 0;
290}
291
292/**
293 * ifx_spi_open - called on tty open
294 * @tty: our tty device
295 * @filp: file handle being associated with the tty
296 *
297 * Open the tty interface. We let the tty_port layer do all the work
298 * for us.
299 *
300 * FIXME: Remove single device assumption and saved_ifx_dev
301 */
302static int ifx_spi_open(struct tty_struct *tty, struct file *filp)
303{
304 return tty_port_open(&saved_ifx_dev->tty_port, tty, filp);
305}
306
307/**
308 * ifx_spi_close - called when our tty closes
309 * @tty: the tty being closed
310 * @filp: the file handle being closed
311 *
312 * Perform the close of the tty. We use the tty_port layer to do all
313 * our hard work.
314 */
315static void ifx_spi_close(struct tty_struct *tty, struct file *filp)
316{
317 struct ifx_spi_device *ifx_dev = tty->driver_data;
318 tty_port_close(&ifx_dev->tty_port, tty, filp);
319 /* FIXME: should we do an ifx_spi_reset here ? */
320}
321
322/**
323 * ifx_decode_spi_header - decode received header
324 * @buffer: the received data
325 * @length: decoded length
326 * @more: decoded more flag
327 * @received_cts: status of cts we received
328 *
329 * Note how received_cts is handled -- if header is all F it is left
330 * the same as it was, if header is all 0 it is set to 0 otherwise it is
331 * taken from the incoming header.
332 *
333 * FIXME: endianness
334 */
335static int ifx_spi_decode_spi_header(unsigned char *buffer, int *length,
336 unsigned char *more, unsigned char *received_cts)
337{
338 u16 h1;
339 u16 h2;
340 u16 *in_buffer = (u16 *)buffer;
341
342 h1 = *in_buffer;
343 h2 = *(in_buffer+1);
344
345 if (h1 == 0 && h2 == 0) {
346 *received_cts = 0;
347 return IFX_SPI_HEADER_0;
348 } else if (h1 == 0xffff && h2 == 0xffff) {
349 /* spi_slave_cts remains as it was */
350 return IFX_SPI_HEADER_F;
351 }
352
353 *length = h1 & 0xfff; /* upper bits of byte are flags */
354 *more = (buffer[1] >> IFX_SPI_MORE_BIT) & 1;
355 *received_cts = (buffer[3] >> IFX_SPI_CTS_BIT) & 1;
356 return 0;
357}
358
359/**
360 * ifx_setup_spi_header - set header fields
361 * @txbuffer: pointer to start of SPI buffer
362 * @tx_count: bytes
363 * @more: indicate if more to follow
364 *
365 * Format up an SPI header for a transfer
366 *
367 * FIXME: endianness?
368 */
369static void ifx_spi_setup_spi_header(unsigned char *txbuffer, int tx_count,
370 unsigned char more)
371{
372 *(u16 *)(txbuffer) = tx_count;
373 *(u16 *)(txbuffer+2) = IFX_SPI_PAYLOAD_SIZE;
374 txbuffer[1] |= (more << IFX_SPI_MORE_BIT) & IFX_SPI_MORE_MASK;
375}
376
377/**
378 * ifx_spi_wakeup_serial - SPI space made
379 * @port_data: our SPI device
380 *
381 * We have emptied the FIFO enough that we want to get more data
382 * queued into it. Poke the line discipline via tty_wakeup so that
383 * it will feed us more bits
384 */
385static void ifx_spi_wakeup_serial(struct ifx_spi_device *ifx_dev)
386{
387 struct tty_struct *tty;
388
389 tty = tty_port_tty_get(&ifx_dev->tty_port);
390 if (!tty)
391 return;
392 tty_wakeup(tty);
393 tty_kref_put(tty);
394}
395
396/**
397 * ifx_spi_prepare_tx_buffer - prepare transmit frame
398 * @ifx_dev: our SPI device
399 *
400 * The transmit buffr needs a header and various other bits of
401 * information followed by as much data as we can pull from the FIFO
402 * and transfer. This function formats up a suitable buffer in the
403 * ifx_dev->tx_buffer
404 *
405 * FIXME: performance - should we wake the tty when the queue is half
406 * empty ?
407 */
408static int ifx_spi_prepare_tx_buffer(struct ifx_spi_device *ifx_dev)
409{
410 int temp_count;
411 int queue_length;
412 int tx_count;
413 unsigned char *tx_buffer;
414
415 tx_buffer = ifx_dev->tx_buffer;
416 memset(tx_buffer, 0, IFX_SPI_TRANSFER_SIZE);
417
418 /* make room for required SPI header */
419 tx_buffer += IFX_SPI_HEADER_OVERHEAD;
420 tx_count = IFX_SPI_HEADER_OVERHEAD;
421
422 /* clear to signal no more data if this turns out to be the
423 * last buffer sent in a sequence */
424 ifx_dev->spi_more = 0;
425
426 /* if modem cts is set, just send empty buffer */
427 if (!ifx_dev->spi_slave_cts) {
428 /* see if there's tx data */
429 queue_length = kfifo_len(&ifx_dev->tx_fifo);
430 if (queue_length != 0) {
431 /* data to mux -- see if there's room for it */
432 temp_count = min(queue_length, IFX_SPI_PAYLOAD_SIZE);
433 temp_count = kfifo_out_locked(&ifx_dev->tx_fifo,
434 tx_buffer, temp_count,
435 &ifx_dev->fifo_lock);
436
437 /* update buffer pointer and data count in message */
438 tx_buffer += temp_count;
439 tx_count += temp_count;
440 if (temp_count == queue_length)
441 /* poke port to get more data */
442 ifx_spi_wakeup_serial(ifx_dev);
443 else /* more data in port, use next SPI message */
444 ifx_dev->spi_more = 1;
445 }
446 }
447 /* have data and info for header -- set up SPI header in buffer */
448 /* spi header needs payload size, not entire buffer size */
449 ifx_spi_setup_spi_header(ifx_dev->tx_buffer,
450 tx_count-IFX_SPI_HEADER_OVERHEAD,
451 ifx_dev->spi_more);
452 /* swap actual data in the buffer */
453 swap_buf((u16 *)(ifx_dev->tx_buffer), tx_count,
454 &ifx_dev->tx_buffer[IFX_SPI_TRANSFER_SIZE]);
455 return tx_count;
456}
457
458/**
459 * ifx_spi_write - line discipline write
460 * @tty: our tty device
461 * @buf: pointer to buffer to write (kernel space)
462 * @count: size of buffer
463 *
464 * Write the characters we have been given into the FIFO. If the device
465 * is not active then activate it, when the SRDY line is asserted back
466 * this will commence I/O
467 */
468static int ifx_spi_write(struct tty_struct *tty, const unsigned char *buf,
469 int count)
470{
471 struct ifx_spi_device *ifx_dev = tty->driver_data;
472 unsigned char *tmp_buf = (unsigned char *)buf;
473 int tx_count = kfifo_in_locked(&ifx_dev->tx_fifo, tmp_buf, count,
474 &ifx_dev->fifo_lock);
475 mrdy_assert(ifx_dev);
476 return tx_count;
477}
478
479/**
480 * ifx_spi_chars_in_buffer - line discipline helper
481 * @tty: our tty device
482 *
483 * Report how much data we can accept before we drop bytes. As we use
484 * a simple FIFO this is nice and easy.
485 */
486static int ifx_spi_write_room(struct tty_struct *tty)
487{
488 struct ifx_spi_device *ifx_dev = tty->driver_data;
489 return IFX_SPI_FIFO_SIZE - kfifo_len(&ifx_dev->tx_fifo);
490}
491
492/**
493 * ifx_spi_chars_in_buffer - line discipline helper
494 * @tty: our tty device
495 *
496 * Report how many characters we have buffered. In our case this is the
497 * number of bytes sitting in our transmit FIFO.
498 */
499static int ifx_spi_chars_in_buffer(struct tty_struct *tty)
500{
501 struct ifx_spi_device *ifx_dev = tty->driver_data;
502 return kfifo_len(&ifx_dev->tx_fifo);
503}
504
505/**
506 * ifx_port_hangup
507 * @port: our tty port
508 *
509 * tty port hang up. Called when tty_hangup processing is invoked either
510 * by loss of carrier, or by software (eg vhangup). Serialized against
511 * activate/shutdown by the tty layer.
512 */
513static void ifx_spi_hangup(struct tty_struct *tty)
514{
515 struct ifx_spi_device *ifx_dev = tty->driver_data;
516 tty_port_hangup(&ifx_dev->tty_port);
517}
518
519/**
520 * ifx_port_activate
521 * @port: our tty port
522 *
523 * tty port activate method - called for first open. Serialized
524 * with hangup and shutdown by the tty layer.
525 */
526static int ifx_port_activate(struct tty_port *port, struct tty_struct *tty)
527{
528 struct ifx_spi_device *ifx_dev =
529 container_of(port, struct ifx_spi_device, tty_port);
530
531 /* clear any old data; can't do this in 'close' */
532 kfifo_reset(&ifx_dev->tx_fifo);
533
534 /* put port data into this tty */
535 tty->driver_data = ifx_dev;
536
537 /* allows flip string push from int context */
538 tty->low_latency = 1;
539
540 return 0;
541}
542
543/**
544 * ifx_port_shutdown
545 * @port: our tty port
546 *
547 * tty port shutdown method - called for last port close. Serialized
548 * with hangup and activate by the tty layer.
549 */
550static void ifx_port_shutdown(struct tty_port *port)
551{
552 struct ifx_spi_device *ifx_dev =
553 container_of(port, struct ifx_spi_device, tty_port);
554
555 mrdy_set_low(ifx_dev);
556 clear_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags);
557 tasklet_kill(&ifx_dev->io_work_tasklet);
558}
559
560static const struct tty_port_operations ifx_tty_port_ops = {
561 .activate = ifx_port_activate,
562 .shutdown = ifx_port_shutdown,
563};
564
565static const struct tty_operations ifx_spi_serial_ops = {
566 .open = ifx_spi_open,
567 .close = ifx_spi_close,
568 .write = ifx_spi_write,
569 .hangup = ifx_spi_hangup,
570 .write_room = ifx_spi_write_room,
571 .chars_in_buffer = ifx_spi_chars_in_buffer,
572 .tiocmget = ifx_spi_tiocmget,
573 .tiocmset = ifx_spi_tiocmset,
574};
575
576/**
577 * ifx_spi_insert_fip_string - queue received data
578 * @ifx_ser: our SPI device
579 * @chars: buffer we have received
580 * @size: number of chars reeived
581 *
582 * Queue bytes to the tty assuming the tty side is currently open. If
583 * not the discard the data.
584 */
585static void ifx_spi_insert_flip_string(struct ifx_spi_device *ifx_dev,
586 unsigned char *chars, size_t size)
587{
588 struct tty_struct *tty = tty_port_tty_get(&ifx_dev->tty_port);
589 if (!tty)
590 return;
591 tty_insert_flip_string(tty, chars, size);
592 tty_flip_buffer_push(tty);
593 tty_kref_put(tty);
594}
595
596/**
597 * ifx_spi_complete - SPI transfer completed
598 * @ctx: our SPI device
599 *
600 * An SPI transfer has completed. Process any received data and kick off
601 * any further transmits we can commence.
602 */
603static void ifx_spi_complete(void *ctx)
604{
605 struct ifx_spi_device *ifx_dev = ctx;
606 struct tty_struct *tty;
607 struct tty_ldisc *ldisc = NULL;
608 int length;
609 int actual_length;
610 unsigned char more;
611 unsigned char cts;
612 int local_write_pending = 0;
613 int queue_length;
614 int srdy;
615 int decode_result;
616
617 mrdy_set_low(ifx_dev);
618
619 if (!ifx_dev->spi_msg.status) {
620 /* check header validity, get comm flags */
621 swap_buf((u16 *)ifx_dev->rx_buffer, IFX_SPI_HEADER_OVERHEAD,
622 &ifx_dev->rx_buffer[IFX_SPI_HEADER_OVERHEAD]);
623 decode_result = ifx_spi_decode_spi_header(ifx_dev->rx_buffer,
624 &length, &more, &cts);
625 if (decode_result == IFX_SPI_HEADER_0) {
626 dev_dbg(&ifx_dev->spi_dev->dev,
627 "ignore input: invalid header 0");
628 ifx_dev->spi_slave_cts = 0;
629 goto complete_exit;
630 } else if (decode_result == IFX_SPI_HEADER_F) {
631 dev_dbg(&ifx_dev->spi_dev->dev,
632 "ignore input: invalid header F");
633 goto complete_exit;
634 }
635
636 ifx_dev->spi_slave_cts = cts;
637
638 actual_length = min((unsigned int)length,
639 ifx_dev->spi_msg.actual_length);
640 swap_buf((u16 *)(ifx_dev->rx_buffer + IFX_SPI_HEADER_OVERHEAD),
641 actual_length,
642 &ifx_dev->rx_buffer[IFX_SPI_TRANSFER_SIZE]);
643 ifx_spi_insert_flip_string(
644 ifx_dev,
645 ifx_dev->rx_buffer + IFX_SPI_HEADER_OVERHEAD,
646 (size_t)actual_length);
647 } else {
648 dev_dbg(&ifx_dev->spi_dev->dev, "SPI transfer error %d",
649 ifx_dev->spi_msg.status);
650 }
651
652complete_exit:
653 if (ifx_dev->write_pending) {
654 ifx_dev->write_pending = 0;
655 local_write_pending = 1;
656 }
657
658 clear_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &(ifx_dev->flags));
659
660 queue_length = kfifo_len(&ifx_dev->tx_fifo);
661 srdy = gpio_get_value(ifx_dev->gpio.srdy);
662 if (!srdy)
663 ifx_spi_power_state_clear(ifx_dev, IFX_SPI_POWER_SRDY);
664
665 /* schedule output if there is more to do */
666 if (test_and_clear_bit(IFX_SPI_STATE_IO_READY, &ifx_dev->flags))
667 tasklet_schedule(&ifx_dev->io_work_tasklet);
668 else {
669 if (more || ifx_dev->spi_more || queue_length > 0 ||
670 local_write_pending) {
671 if (ifx_dev->spi_slave_cts) {
672 if (more)
673 mrdy_assert(ifx_dev);
674 } else
675 mrdy_assert(ifx_dev);
676 } else {
677 /*
678 * poke line discipline driver if any for more data
679 * may or may not get more data to write
680 * for now, say not busy
681 */
682 ifx_spi_power_state_clear(ifx_dev,
683 IFX_SPI_POWER_DATA_PENDING);
684 tty = tty_port_tty_get(&ifx_dev->tty_port);
685 if (tty) {
686 ldisc = tty_ldisc_ref(tty);
687 if (ldisc) {
688 ldisc->ops->write_wakeup(tty);
689 tty_ldisc_deref(ldisc);
690 }
691 tty_kref_put(tty);
692 }
693 }
694 }
695}
696
697/**
698 * ifx_spio_io - I/O tasklet
699 * @data: our SPI device
700 *
701 * Queue data for transmission if possible and then kick off the
702 * transfer.
703 */
704static void ifx_spi_io(unsigned long data)
705{
706 int retval;
707 struct ifx_spi_device *ifx_dev = (struct ifx_spi_device *) data;
708
709 if (!test_and_set_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &ifx_dev->flags)) {
710 if (ifx_dev->gpio.unack_srdy_int_nb > 0)
711 ifx_dev->gpio.unack_srdy_int_nb--;
712
713 ifx_spi_prepare_tx_buffer(ifx_dev);
714
715 spi_message_init(&ifx_dev->spi_msg);
716 INIT_LIST_HEAD(&ifx_dev->spi_msg.queue);
717
718 ifx_dev->spi_msg.context = ifx_dev;
719 ifx_dev->spi_msg.complete = ifx_spi_complete;
720
721 /* set up our spi transfer */
722 /* note len is BYTES, not transfers */
723 ifx_dev->spi_xfer.len = IFX_SPI_TRANSFER_SIZE;
724 ifx_dev->spi_xfer.cs_change = 0;
725 ifx_dev->spi_xfer.speed_hz = 12500000;
726 /* ifx_dev->spi_xfer.speed_hz = 390625; */
727 ifx_dev->spi_xfer.bits_per_word = spi_b16 ? 16 : 8;
728
729 ifx_dev->spi_xfer.tx_buf = ifx_dev->tx_buffer;
730 ifx_dev->spi_xfer.rx_buf = ifx_dev->rx_buffer;
731
732 /*
733 * setup dma pointers
734 */
735 if (ifx_dev->is_6160) {
736 ifx_dev->spi_msg.is_dma_mapped = 1;
737 ifx_dev->tx_dma = ifx_dev->tx_bus;
738 ifx_dev->rx_dma = ifx_dev->rx_bus;
739 ifx_dev->spi_xfer.tx_dma = ifx_dev->tx_dma;
740 ifx_dev->spi_xfer.rx_dma = ifx_dev->rx_dma;
741 } else {
742 ifx_dev->spi_msg.is_dma_mapped = 0;
743 ifx_dev->tx_dma = (dma_addr_t)0;
744 ifx_dev->rx_dma = (dma_addr_t)0;
745 ifx_dev->spi_xfer.tx_dma = (dma_addr_t)0;
746 ifx_dev->spi_xfer.rx_dma = (dma_addr_t)0;
747 }
748
749 spi_message_add_tail(&ifx_dev->spi_xfer, &ifx_dev->spi_msg);
750
751 /* Assert MRDY. This may have already been done by the write
752 * routine.
753 */
754 mrdy_assert(ifx_dev);
755
756 retval = spi_async(ifx_dev->spi_dev, &ifx_dev->spi_msg);
757 if (retval) {
758 clear_bit(IFX_SPI_STATE_IO_IN_PROGRESS,
759 &ifx_dev->flags);
760 tasklet_schedule(&ifx_dev->io_work_tasklet);
761 return;
762 }
763 } else
764 ifx_dev->write_pending = 1;
765}
766
767/**
768 * ifx_spi_free_port - free up the tty side
769 * @ifx_dev: IFX device going away
770 *
771 * Unregister and free up a port when the device goes away
772 */
773static void ifx_spi_free_port(struct ifx_spi_device *ifx_dev)
774{
775 if (ifx_dev->tty_dev)
776 tty_unregister_device(tty_drv, ifx_dev->minor);
777 kfifo_free(&ifx_dev->tx_fifo);
778}
779
780/**
781 * ifx_spi_create_port - create a new port
782 * @ifx_dev: our spi device
783 *
784 * Allocate and initialise the tty port that goes with this interface
785 * and add it to the tty layer so that it can be opened.
786 */
787static int ifx_spi_create_port(struct ifx_spi_device *ifx_dev)
788{
789 int ret = 0;
790 struct tty_port *pport = &ifx_dev->tty_port;
791
792 spin_lock_init(&ifx_dev->fifo_lock);
793 lockdep_set_class_and_subclass(&ifx_dev->fifo_lock,
794 &ifx_spi_key, 0);
795
796 if (kfifo_alloc(&ifx_dev->tx_fifo, IFX_SPI_FIFO_SIZE, GFP_KERNEL)) {
797 ret = -ENOMEM;
798 goto error_ret;
799 }
800
801 pport->ops = &ifx_tty_port_ops;
802 tty_port_init(pport);
803 ifx_dev->minor = IFX_SPI_TTY_ID;
804 ifx_dev->tty_dev = tty_register_device(tty_drv, ifx_dev->minor,
805 &ifx_dev->spi_dev->dev);
806 if (IS_ERR(ifx_dev->tty_dev)) {
807 dev_dbg(&ifx_dev->spi_dev->dev,
808 "%s: registering tty device failed", __func__);
809 ret = PTR_ERR(ifx_dev->tty_dev);
810 goto error_ret;
811 }
812 return 0;
813
814error_ret:
815 ifx_spi_free_port(ifx_dev);
816 return ret;
817}
818
819/**
820 * ifx_spi_handle_srdy - handle SRDY
821 * @ifx_dev: device asserting SRDY
822 *
823 * Check our device state and see what we need to kick off when SRDY
824 * is asserted. This usually means killing the timer and firing off the
825 * I/O processing.
826 */
827static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev)
828{
829 if (test_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags)) {
830 del_timer_sync(&ifx_dev->spi_timer);
831 clear_bit(IFX_SPI_STATE_TIMER_PENDING, &ifx_dev->flags);
832 }
833
834 ifx_spi_power_state_set(ifx_dev, IFX_SPI_POWER_SRDY);
835
836 if (!test_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &ifx_dev->flags))
837 tasklet_schedule(&ifx_dev->io_work_tasklet);
838 else
839 set_bit(IFX_SPI_STATE_IO_READY, &ifx_dev->flags);
840}
841
842/**
843 * ifx_spi_srdy_interrupt - SRDY asserted
844 * @irq: our IRQ number
845 * @dev: our ifx device
846 *
847 * The modem asserted SRDY. Handle the srdy event
848 */
849static irqreturn_t ifx_spi_srdy_interrupt(int irq, void *dev)
850{
851 struct ifx_spi_device *ifx_dev = dev;
852 ifx_dev->gpio.unack_srdy_int_nb++;
853 ifx_spi_handle_srdy(ifx_dev);
854 return IRQ_HANDLED;
855}
856
857/**
858 * ifx_spi_reset_interrupt - Modem has changed reset state
859 * @irq: interrupt number
860 * @dev: our device pointer
861 *
862 * The modem has either entered or left reset state. Check the GPIO
863 * line to see which.
864 *
865 * FIXME: review locking on MR_INPROGRESS versus
866 * parallel unsolicited reset/solicited reset
867 */
868static irqreturn_t ifx_spi_reset_interrupt(int irq, void *dev)
869{
870 struct ifx_spi_device *ifx_dev = dev;
871 int val = gpio_get_value(ifx_dev->gpio.reset_out);
872 int solreset = test_bit(MR_START, &ifx_dev->mdm_reset_state);
873
874 if (val == 0) {
875 /* entered reset */
876 set_bit(MR_INPROGRESS, &ifx_dev->mdm_reset_state);
877 if (!solreset) {
878 /* unsolicited reset */
879 ifx_spi_ttyhangup(ifx_dev);
880 }
881 } else {
882 /* exited reset */
883 clear_bit(MR_INPROGRESS, &ifx_dev->mdm_reset_state);
884 if (solreset) {
885 set_bit(MR_COMPLETE, &ifx_dev->mdm_reset_state);
886 wake_up(&ifx_dev->mdm_reset_wait);
887 }
888 }
889 return IRQ_HANDLED;
890}
891
892/**
893 * ifx_spi_free_device - free device
894 * @ifx_dev: device to free
895 *
896 * Free the IFX device
897 */
898static void ifx_spi_free_device(struct ifx_spi_device *ifx_dev)
899{
900 ifx_spi_free_port(ifx_dev);
901 dma_free_coherent(&ifx_dev->spi_dev->dev,
902 IFX_SPI_TRANSFER_SIZE,
903 ifx_dev->tx_buffer,
904 ifx_dev->tx_bus);
905 dma_free_coherent(&ifx_dev->spi_dev->dev,
906 IFX_SPI_TRANSFER_SIZE,
907 ifx_dev->rx_buffer,
908 ifx_dev->rx_bus);
909}
910
911/**
912 * ifx_spi_reset - reset modem
913 * @ifx_dev: modem to reset
914 *
915 * Perform a reset on the modem
916 */
917static int ifx_spi_reset(struct ifx_spi_device *ifx_dev)
918{
919 int ret;
920 /*
921 * set up modem power, reset
922 *
923 * delays are required on some platforms for the modem
924 * to reset properly
925 */
926 set_bit(MR_START, &ifx_dev->mdm_reset_state);
927 gpio_set_value(ifx_dev->gpio.po, 0);
928 gpio_set_value(ifx_dev->gpio.reset, 0);
929 msleep(25);
930 gpio_set_value(ifx_dev->gpio.reset, 1);
931 msleep(1);
932 gpio_set_value(ifx_dev->gpio.po, 1);
933 msleep(1);
934 gpio_set_value(ifx_dev->gpio.po, 0);
935 ret = wait_event_timeout(ifx_dev->mdm_reset_wait,
936 test_bit(MR_COMPLETE,
937 &ifx_dev->mdm_reset_state),
938 IFX_RESET_TIMEOUT);
939 if (!ret)
940 dev_warn(&ifx_dev->spi_dev->dev, "Modem reset timeout: (state:%lx)",
941 ifx_dev->mdm_reset_state);
942
943 ifx_dev->mdm_reset_state = 0;
944 return ret;
945}
946
947/**
948 * ifx_spi_spi_probe - probe callback
949 * @spi: our possible matching SPI device
950 *
951 * Probe for a 6x60 modem on SPI bus. Perform any needed device and
952 * GPIO setup.
953 *
954 * FIXME:
955 * - Support for multiple devices
956 * - Split out MID specific GPIO handling eventually
957 */
958
959static int ifx_spi_spi_probe(struct spi_device *spi)
960{
961 int ret;
962 int srdy;
963 struct ifx_modem_platform_data *pl_data = NULL;
964 struct ifx_spi_device *ifx_dev;
965
966 if (saved_ifx_dev) {
967 dev_dbg(&spi->dev, "ignoring subsequent detection");
968 return -ENODEV;
969 }
970
971 /* initialize structure to hold our device variables */
972 ifx_dev = kzalloc(sizeof(struct ifx_spi_device), GFP_KERNEL);
973 if (!ifx_dev) {
974 dev_err(&spi->dev, "spi device allocation failed");
975 return -ENOMEM;
976 }
977 saved_ifx_dev = ifx_dev;
978 ifx_dev->spi_dev = spi;
979 clear_bit(IFX_SPI_STATE_IO_IN_PROGRESS, &ifx_dev->flags);
980 spin_lock_init(&ifx_dev->write_lock);
981 spin_lock_init(&ifx_dev->power_lock);
982 ifx_dev->power_status = 0;
983 init_timer(&ifx_dev->spi_timer);
984 ifx_dev->spi_timer.function = ifx_spi_timeout;
985 ifx_dev->spi_timer.data = (unsigned long)ifx_dev;
986 ifx_dev->is_6160 = pl_data->is_6160;
987
988 /* ensure SPI protocol flags are initialized to enable transfer */
989 ifx_dev->spi_more = 0;
990 ifx_dev->spi_slave_cts = 0;
991
992 /*initialize transfer and dma buffers */
993 ifx_dev->tx_buffer = dma_alloc_coherent(&ifx_dev->spi_dev->dev,
994 IFX_SPI_TRANSFER_SIZE,
995 &ifx_dev->tx_bus,
996 GFP_KERNEL);
997 if (!ifx_dev->tx_buffer) {
998 dev_err(&spi->dev, "DMA-TX buffer allocation failed");
999 ret = -ENOMEM;
1000 goto error_ret;
1001 }
1002 ifx_dev->rx_buffer = dma_alloc_coherent(&ifx_dev->spi_dev->dev,
1003 IFX_SPI_TRANSFER_SIZE,
1004 &ifx_dev->rx_bus,
1005 GFP_KERNEL);
1006 if (!ifx_dev->rx_buffer) {
1007 dev_err(&spi->dev, "DMA-RX buffer allocation failed");
1008 ret = -ENOMEM;
1009 goto error_ret;
1010 }
1011
1012 /* initialize waitq for modem reset */
1013 init_waitqueue_head(&ifx_dev->mdm_reset_wait);
1014
1015 spi_set_drvdata(spi, ifx_dev);
1016 tasklet_init(&ifx_dev->io_work_tasklet, ifx_spi_io,
1017 (unsigned long)ifx_dev);
1018
1019 set_bit(IFX_SPI_STATE_PRESENT, &ifx_dev->flags);
1020
1021 /* create our tty port */
1022 ret = ifx_spi_create_port(ifx_dev);
1023 if (ret != 0) {
1024 dev_err(&spi->dev, "create default tty port failed");
1025 goto error_ret;
1026 }
1027
1028 pl_data = (struct ifx_modem_platform_data *)spi->dev.platform_data;
1029 if (pl_data) {
1030 ifx_dev->gpio.reset = pl_data->rst_pmu;
1031 ifx_dev->gpio.po = pl_data->pwr_on;
1032 ifx_dev->gpio.mrdy = pl_data->mrdy;
1033 ifx_dev->gpio.srdy = pl_data->srdy;
1034 ifx_dev->gpio.reset_out = pl_data->rst_out;
1035 } else {
1036 dev_err(&spi->dev, "missing platform data!");
1037 ret = -ENODEV;
1038 goto error_ret;
1039 }
1040
1041 dev_info(&spi->dev, "gpios %d, %d, %d, %d, %d",
1042 ifx_dev->gpio.reset, ifx_dev->gpio.po, ifx_dev->gpio.mrdy,
1043 ifx_dev->gpio.srdy, ifx_dev->gpio.reset_out);
1044
1045 /* Configure gpios */
1046 ret = gpio_request(ifx_dev->gpio.reset, "ifxModem");
1047 if (ret < 0) {
1048 dev_err(&spi->dev, "Unable to allocate GPIO%d (RESET)",
1049 ifx_dev->gpio.reset);
1050 goto error_ret;
1051 }
1052 ret += gpio_direction_output(ifx_dev->gpio.reset, 0);
1053 ret += gpio_export(ifx_dev->gpio.reset, 1);
1054 if (ret) {
1055 dev_err(&spi->dev, "Unable to configure GPIO%d (RESET)",
1056 ifx_dev->gpio.reset);
1057 ret = -EBUSY;
1058 goto error_ret2;
1059 }
1060
1061 ret = gpio_request(ifx_dev->gpio.po, "ifxModem");
1062 ret += gpio_direction_output(ifx_dev->gpio.po, 0);
1063 ret += gpio_export(ifx_dev->gpio.po, 1);
1064 if (ret) {
1065 dev_err(&spi->dev, "Unable to configure GPIO%d (ON)",
1066 ifx_dev->gpio.po);
1067 ret = -EBUSY;
1068 goto error_ret3;
1069 }
1070
1071 ret = gpio_request(ifx_dev->gpio.mrdy, "ifxModem");
1072 if (ret < 0) {
1073 dev_err(&spi->dev, "Unable to allocate GPIO%d (MRDY)",
1074 ifx_dev->gpio.mrdy);
1075 goto error_ret3;
1076 }
1077 ret += gpio_export(ifx_dev->gpio.mrdy, 1);
1078 ret += gpio_direction_output(ifx_dev->gpio.mrdy, 0);
1079 if (ret) {
1080 dev_err(&spi->dev, "Unable to configure GPIO%d (MRDY)",
1081 ifx_dev->gpio.mrdy);
1082 ret = -EBUSY;
1083 goto error_ret4;
1084 }
1085
1086 ret = gpio_request(ifx_dev->gpio.srdy, "ifxModem");
1087 if (ret < 0) {
1088 dev_err(&spi->dev, "Unable to allocate GPIO%d (SRDY)",
1089 ifx_dev->gpio.srdy);
1090 ret = -EBUSY;
1091 goto error_ret4;
1092 }
1093 ret += gpio_export(ifx_dev->gpio.srdy, 1);
1094 ret += gpio_direction_input(ifx_dev->gpio.srdy);
1095 if (ret) {
1096 dev_err(&spi->dev, "Unable to configure GPIO%d (SRDY)",
1097 ifx_dev->gpio.srdy);
1098 ret = -EBUSY;
1099 goto error_ret5;
1100 }
1101
1102 ret = gpio_request(ifx_dev->gpio.reset_out, "ifxModem");
1103 if (ret < 0) {
1104 dev_err(&spi->dev, "Unable to allocate GPIO%d (RESET_OUT)",
1105 ifx_dev->gpio.reset_out);
1106 goto error_ret5;
1107 }
1108 ret += gpio_export(ifx_dev->gpio.reset_out, 1);
1109 ret += gpio_direction_input(ifx_dev->gpio.reset_out);
1110 if (ret) {
1111 dev_err(&spi->dev, "Unable to configure GPIO%d (RESET_OUT)",
1112 ifx_dev->gpio.reset_out);
1113 ret = -EBUSY;
1114 goto error_ret6;
1115 }
1116
1117 ret = request_irq(gpio_to_irq(ifx_dev->gpio.reset_out),
1118 ifx_spi_reset_interrupt,
1119 IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING, DRVNAME,
1120 (void *)ifx_dev);
1121 if (ret) {
1122 dev_err(&spi->dev, "Unable to get irq %x\n",
1123 gpio_to_irq(ifx_dev->gpio.reset_out));
1124 goto error_ret6;
1125 }
1126
1127 ret = ifx_spi_reset(ifx_dev);
1128
1129 ret = request_irq(gpio_to_irq(ifx_dev->gpio.srdy),
1130 ifx_spi_srdy_interrupt,
1131 IRQF_TRIGGER_RISING, DRVNAME,
1132 (void *)ifx_dev);
1133 if (ret) {
1134 dev_err(&spi->dev, "Unable to get irq %x",
1135 gpio_to_irq(ifx_dev->gpio.srdy));
1136 goto error_ret7;
1137 }
1138
1139 /* set pm runtime power state and register with power system */
1140 pm_runtime_set_active(&spi->dev);
1141 pm_runtime_enable(&spi->dev);
1142
1143 /* handle case that modem is already signaling SRDY */
1144 /* no outgoing tty open at this point, this just satisfies the
1145 * modem's read and should reset communication properly
1146 */
1147 srdy = gpio_get_value(ifx_dev->gpio.srdy);
1148
1149 if (srdy) {
1150 mrdy_assert(ifx_dev);
1151 ifx_spi_handle_srdy(ifx_dev);
1152 } else
1153 mrdy_set_low(ifx_dev);
1154 return 0;
1155
1156error_ret7:
1157 free_irq(gpio_to_irq(ifx_dev->gpio.reset_out), (void *)ifx_dev);
1158error_ret6:
1159 gpio_free(ifx_dev->gpio.srdy);
1160error_ret5:
1161 gpio_free(ifx_dev->gpio.mrdy);
1162error_ret4:
1163 gpio_free(ifx_dev->gpio.reset);
1164error_ret3:
1165 gpio_free(ifx_dev->gpio.po);
1166error_ret2:
1167 gpio_free(ifx_dev->gpio.reset_out);
1168error_ret:
1169 ifx_spi_free_device(ifx_dev);
1170 saved_ifx_dev = NULL;
1171 return ret;
1172}
1173
1174/**
1175 * ifx_spi_spi_remove - SPI device was removed
1176 * @spi: SPI device
1177 *
1178 * FIXME: We should be shutting the device down here not in
1179 * the module unload path.
1180 */
1181
1182static int ifx_spi_spi_remove(struct spi_device *spi)
1183{
1184 struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi);
1185 /* stop activity */
1186 tasklet_kill(&ifx_dev->io_work_tasklet);
1187 /* free irq */
1188 free_irq(gpio_to_irq(ifx_dev->gpio.reset_out), (void *)ifx_dev);
1189 free_irq(gpio_to_irq(ifx_dev->gpio.srdy), (void *)ifx_dev);
1190
1191 gpio_free(ifx_dev->gpio.srdy);
1192 gpio_free(ifx_dev->gpio.mrdy);
1193 gpio_free(ifx_dev->gpio.reset);
1194 gpio_free(ifx_dev->gpio.po);
1195 gpio_free(ifx_dev->gpio.reset_out);
1196
1197 /* free allocations */
1198 ifx_spi_free_device(ifx_dev);
1199
1200 saved_ifx_dev = NULL;
1201 return 0;
1202}
1203
1204/**
1205 * ifx_spi_spi_shutdown - called on SPI shutdown
1206 * @spi: SPI device
1207 *
1208 * No action needs to be taken here
1209 */
1210
1211static void ifx_spi_spi_shutdown(struct spi_device *spi)
1212{
1213}
1214
1215/*
1216 * various suspends and resumes have nothing to do
1217 * no hardware to save state for
1218 */
1219
1220/**
1221 * ifx_spi_spi_suspend - suspend SPI on system suspend
1222 * @dev: device being suspended
1223 *
1224 * Suspend the SPI side. No action needed on Intel MID platforms, may
1225 * need extending for other systems.
1226 */
1227static int ifx_spi_spi_suspend(struct spi_device *spi, pm_message_t msg)
1228{
1229 return 0;
1230}
1231
1232/**
1233 * ifx_spi_spi_resume - resume SPI side on system resume
1234 * @dev: device being suspended
1235 *
1236 * Suspend the SPI side. No action needed on Intel MID platforms, may
1237 * need extending for other systems.
1238 */
1239static int ifx_spi_spi_resume(struct spi_device *spi)
1240{
1241 return 0;
1242}
1243
1244/**
1245 * ifx_spi_pm_suspend - suspend modem on system suspend
1246 * @dev: device being suspended
1247 *
1248 * Suspend the modem. No action needed on Intel MID platforms, may
1249 * need extending for other systems.
1250 */
1251static int ifx_spi_pm_suspend(struct device *dev)
1252{
1253 return 0;
1254}
1255
1256/**
1257 * ifx_spi_pm_resume - resume modem on system resume
1258 * @dev: device being suspended
1259 *
1260 * Allow the modem to resume. No action needed.
1261 *
1262 * FIXME: do we need to reset anything here ?
1263 */
1264static int ifx_spi_pm_resume(struct device *dev)
1265{
1266 return 0;
1267}
1268
1269/**
1270 * ifx_spi_pm_runtime_resume - suspend modem
1271 * @dev: device being suspended
1272 *
1273 * Allow the modem to resume. No action needed.
1274 */
1275static int ifx_spi_pm_runtime_resume(struct device *dev)
1276{
1277 return 0;
1278}
1279
1280/**
1281 * ifx_spi_pm_runtime_suspend - suspend modem
1282 * @dev: device being suspended
1283 *
1284 * Allow the modem to suspend and thus suspend to continue up the
1285 * device tree.
1286 */
1287static int ifx_spi_pm_runtime_suspend(struct device *dev)
1288{
1289 return 0;
1290}
1291
1292/**
1293 * ifx_spi_pm_runtime_idle - check if modem idle
1294 * @dev: our device
1295 *
1296 * Check conditions and queue runtime suspend if idle.
1297 */
1298static int ifx_spi_pm_runtime_idle(struct device *dev)
1299{
1300 struct spi_device *spi = to_spi_device(dev);
1301 struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi);
1302
1303 if (!ifx_dev->power_status)
1304 pm_runtime_suspend(dev);
1305
1306 return 0;
1307}
1308
1309static const struct dev_pm_ops ifx_spi_pm = {
1310 .resume = ifx_spi_pm_resume,
1311 .suspend = ifx_spi_pm_suspend,
1312 .runtime_resume = ifx_spi_pm_runtime_resume,
1313 .runtime_suspend = ifx_spi_pm_runtime_suspend,
1314 .runtime_idle = ifx_spi_pm_runtime_idle
1315};
1316
1317static const struct spi_device_id ifx_id_table[] = {
1318 {"ifx6160", 0},
1319 {"ifx6260", 0},
1320 { }
1321};
1322MODULE_DEVICE_TABLE(spi, ifx_id_table);
1323
1324/* spi operations */
1325static const struct spi_driver ifx_spi_driver_6160 = {
1326 .driver = {
1327 .name = "ifx6160",
1328 .bus = &spi_bus_type,
1329 .pm = &ifx_spi_pm,
1330 .owner = THIS_MODULE},
1331 .probe = ifx_spi_spi_probe,
1332 .shutdown = ifx_spi_spi_shutdown,
1333 .remove = __devexit_p(ifx_spi_spi_remove),
1334 .suspend = ifx_spi_spi_suspend,
1335 .resume = ifx_spi_spi_resume,
1336 .id_table = ifx_id_table
1337};
1338
1339/**
1340 * ifx_spi_exit - module exit
1341 *
1342 * Unload the module.
1343 */
1344
1345static void __exit ifx_spi_exit(void)
1346{
1347 /* unregister */
1348 tty_unregister_driver(tty_drv);
1349 spi_unregister_driver((void *)&ifx_spi_driver_6160);
1350}
1351
1352/**
1353 * ifx_spi_init - module entry point
1354 *
1355 * Initialise the SPI and tty interfaces for the IFX SPI driver
1356 * We need to initialize upper-edge spi driver after the tty
1357 * driver because otherwise the spi probe will race
1358 */
1359
1360static int __init ifx_spi_init(void)
1361{
1362 int result;
1363
1364 tty_drv = alloc_tty_driver(1);
1365 if (!tty_drv) {
1366 pr_err("%s: alloc_tty_driver failed", DRVNAME);
1367 return -ENOMEM;
1368 }
1369
1370 tty_drv->magic = TTY_DRIVER_MAGIC;
1371 tty_drv->owner = THIS_MODULE;
1372 tty_drv->driver_name = DRVNAME;
1373 tty_drv->name = TTYNAME;
1374 tty_drv->minor_start = IFX_SPI_TTY_ID;
1375 tty_drv->num = 1;
1376 tty_drv->type = TTY_DRIVER_TYPE_SERIAL;
1377 tty_drv->subtype = SERIAL_TYPE_NORMAL;
1378 tty_drv->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
1379 tty_drv->init_termios = tty_std_termios;
1380
1381 tty_set_operations(tty_drv, &ifx_spi_serial_ops);
1382
1383 result = tty_register_driver(tty_drv);
1384 if (result) {
1385 pr_err("%s: tty_register_driver failed(%d)",
1386 DRVNAME, result);
1387 put_tty_driver(tty_drv);
1388 return result;
1389 }
1390
1391 result = spi_register_driver((void *)&ifx_spi_driver_6160);
1392 if (result) {
1393 pr_err("%s: spi_register_driver failed(%d)",
1394 DRVNAME, result);
1395 tty_unregister_driver(tty_drv);
1396 }
1397 return result;
1398}
1399
1400module_init(ifx_spi_init);
1401module_exit(ifx_spi_exit);
1402
1403MODULE_AUTHOR("Intel");
1404MODULE_DESCRIPTION("IFX6x60 spi driver");
1405MODULE_LICENSE("GPL");
1406MODULE_INFO(Version, "0.1-IFX6x60");
diff --git a/drivers/serial/ifx6x60.h b/drivers/serial/ifx6x60.h
new file mode 100644
index 000000000000..deb7b8d977dc
--- /dev/null
+++ b/drivers/serial/ifx6x60.h
@@ -0,0 +1,129 @@
1/****************************************************************************
2 *
3 * Driver for the IFX spi modem.
4 *
5 * Copyright (C) 2009, 2010 Intel Corp
6 * Jim Stanley <jim.stanley@intel.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
21 * USA
22 *
23 *
24 *
25 *****************************************************************************/
26#ifndef _IFX6X60_H
27#define _IFX6X60_H
28
29#define DRVNAME "ifx6x60"
30#define TTYNAME "ttyIFX"
31
32/* #define IFX_THROTTLE_CODE */
33
34#define IFX_SPI_MAX_MINORS 1
35#define IFX_SPI_TRANSFER_SIZE 2048
36#define IFX_SPI_FIFO_SIZE 4096
37
38#define IFX_SPI_HEADER_OVERHEAD 4
39#define IFX_RESET_TIMEOUT msecs_to_jiffies(50)
40
41/* device flags bitfield definitions */
42#define IFX_SPI_STATE_PRESENT 0
43#define IFX_SPI_STATE_IO_IN_PROGRESS 1
44#define IFX_SPI_STATE_IO_READY 2
45#define IFX_SPI_STATE_TIMER_PENDING 3
46
47/* flow control bitfields */
48#define IFX_SPI_DCD 0
49#define IFX_SPI_CTS 1
50#define IFX_SPI_DSR 2
51#define IFX_SPI_RI 3
52#define IFX_SPI_DTR 4
53#define IFX_SPI_RTS 5
54#define IFX_SPI_TX_FC 6
55#define IFX_SPI_RX_FC 7
56#define IFX_SPI_UPDATE 8
57
58#define IFX_SPI_PAYLOAD_SIZE (IFX_SPI_TRANSFER_SIZE - \
59 IFX_SPI_HEADER_OVERHEAD)
60
61#define IFX_SPI_IRQ_TYPE DETECT_EDGE_RISING
62#define IFX_SPI_GPIO_TARGET 0
63#define IFX_SPI_GPIO0 0x105
64
65#define IFX_SPI_STATUS_TIMEOUT (2000*HZ)
66
67/* values for bits in power status byte */
68#define IFX_SPI_POWER_DATA_PENDING 1
69#define IFX_SPI_POWER_SRDY 2
70
71struct ifx_spi_device {
72 /* Our SPI device */
73 struct spi_device *spi_dev;
74
75 /* Port specific data */
76 struct kfifo tx_fifo;
77 spinlock_t fifo_lock;
78 unsigned long signal_state;
79
80 /* TTY Layer logic */
81 struct tty_port tty_port;
82 struct device *tty_dev;
83 int minor;
84
85 /* Low level I/O work */
86 struct tasklet_struct io_work_tasklet;
87 unsigned long flags;
88 dma_addr_t rx_dma;
89 dma_addr_t tx_dma;
90
91 int is_6160; /* Modem type */
92
93 spinlock_t write_lock;
94 int write_pending;
95 spinlock_t power_lock;
96 unsigned char power_status;
97
98 unsigned char *rx_buffer;
99 unsigned char *tx_buffer;
100 dma_addr_t rx_bus;
101 dma_addr_t tx_bus;
102 unsigned char spi_more;
103 unsigned char spi_slave_cts;
104
105 struct timer_list spi_timer;
106
107 struct spi_message spi_msg;
108 struct spi_transfer spi_xfer;
109
110 struct {
111 /* gpio lines */
112 unsigned short srdy; /* slave-ready gpio */
113 unsigned short mrdy; /* master-ready gpio */
114 unsigned short reset; /* modem-reset gpio */
115 unsigned short po; /* modem-on gpio */
116 unsigned short reset_out; /* modem-in-reset gpio */
117 /* state/stats */
118 int unack_srdy_int_nb;
119 } gpio;
120
121 /* modem reset */
122 unsigned long mdm_reset_state;
123#define MR_START 0
124#define MR_INPROGRESS 1
125#define MR_COMPLETE 2
126 wait_queue_head_t mdm_reset_wait;
127};
128
129#endif /* _IFX6X60_H */
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index c4399e23565a..126ec7f568ec 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -838,7 +838,11 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
838static const char * 838static const char *
839mpc52xx_uart_type(struct uart_port *port) 839mpc52xx_uart_type(struct uart_port *port)
840{ 840{
841 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL; 841 /*
842 * We keep using PORT_MPC52xx for historic reasons although it applies
843 * for MPC512x, too, but print "MPC5xxx" to not irritate users
844 */
845 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
842} 846}
843 847
844static void 848static void
diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c
index 1201eff1831e..7f2f01058789 100644
--- a/drivers/serial/omap-serial.c
+++ b/drivers/serial/omap-serial.c
@@ -866,12 +866,6 @@ serial_omap_type(struct uart_port *port)
866 return up->name; 866 return up->name;
867} 867}
868 868
869#ifdef CONFIG_SERIAL_OMAP_CONSOLE
870
871static struct uart_omap_port *serial_omap_console_ports[4];
872
873static struct uart_driver serial_omap_reg;
874
875#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 869#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
876 870
877static inline void wait_for_xmitr(struct uart_omap_port *up) 871static inline void wait_for_xmitr(struct uart_omap_port *up)
@@ -905,6 +899,34 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
905 } 899 }
906} 900}
907 901
902#ifdef CONFIG_CONSOLE_POLL
903
904static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
905{
906 struct uart_omap_port *up = (struct uart_omap_port *)port;
907 wait_for_xmitr(up);
908 serial_out(up, UART_TX, ch);
909}
910
911static int serial_omap_poll_get_char(struct uart_port *port)
912{
913 struct uart_omap_port *up = (struct uart_omap_port *)port;
914 unsigned int status = serial_in(up, UART_LSR);
915
916 if (!(status & UART_LSR_DR))
917 return NO_POLL_CHAR;
918
919 return serial_in(up, UART_RX);
920}
921
922#endif /* CONFIG_CONSOLE_POLL */
923
924#ifdef CONFIG_SERIAL_OMAP_CONSOLE
925
926static struct uart_omap_port *serial_omap_console_ports[4];
927
928static struct uart_driver serial_omap_reg;
929
908static void serial_omap_console_putchar(struct uart_port *port, int ch) 930static void serial_omap_console_putchar(struct uart_port *port, int ch)
909{ 931{
910 struct uart_omap_port *up = (struct uart_omap_port *)port; 932 struct uart_omap_port *up = (struct uart_omap_port *)port;
@@ -1022,6 +1044,10 @@ static struct uart_ops serial_omap_pops = {
1022 .request_port = serial_omap_request_port, 1044 .request_port = serial_omap_request_port,
1023 .config_port = serial_omap_config_port, 1045 .config_port = serial_omap_config_port,
1024 .verify_port = serial_omap_verify_port, 1046 .verify_port = serial_omap_verify_port,
1047#ifdef CONFIG_CONSOLE_POLL
1048 .poll_put_char = serial_omap_poll_put_char,
1049 .poll_get_char = serial_omap_poll_get_char,
1050#endif
1025}; 1051};
1026 1052
1027static struct uart_driver serial_omap_reg = { 1053static struct uart_driver serial_omap_reg = {
diff --git a/drivers/serial/pch_uart.c b/drivers/serial/pch_uart.c
new file mode 100644
index 000000000000..70a61458ec42
--- /dev/null
+++ b/drivers/serial/pch_uart.c
@@ -0,0 +1,1451 @@
1/*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/serial_reg.h>
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/serial_core.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24
25#include <linux/dmaengine.h>
26#include <linux/pch_dma.h>
27
28enum {
29 PCH_UART_HANDLED_RX_INT_SHIFT,
30 PCH_UART_HANDLED_TX_INT_SHIFT,
31 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
32 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
33 PCH_UART_HANDLED_MS_INT_SHIFT,
34};
35
36enum {
37 PCH_UART_8LINE,
38 PCH_UART_2LINE,
39};
40
41#define PCH_UART_DRIVER_DEVICE "ttyPCH"
42
43#define PCH_UART_NR_GE_256FIFO 1
44#define PCH_UART_NR_GE_64FIFO 3
45#define PCH_UART_NR_GE (PCH_UART_NR_GE_256FIFO+PCH_UART_NR_GE_64FIFO)
46#define PCH_UART_NR PCH_UART_NR_GE
47
48#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
49#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
50#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
51 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
52#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
53 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
54#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
55
56#define PCH_UART_RBR 0x00
57#define PCH_UART_THR 0x00
58
59#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
60 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
61#define PCH_UART_IER_ERBFI 0x00000001
62#define PCH_UART_IER_ETBEI 0x00000002
63#define PCH_UART_IER_ELSI 0x00000004
64#define PCH_UART_IER_EDSSI 0x00000008
65
66#define PCH_UART_IIR_IP 0x00000001
67#define PCH_UART_IIR_IID 0x00000006
68#define PCH_UART_IIR_MSI 0x00000000
69#define PCH_UART_IIR_TRI 0x00000002
70#define PCH_UART_IIR_RRI 0x00000004
71#define PCH_UART_IIR_REI 0x00000006
72#define PCH_UART_IIR_TOI 0x00000008
73#define PCH_UART_IIR_FIFO256 0x00000020
74#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
75#define PCH_UART_IIR_FE 0x000000C0
76
77#define PCH_UART_FCR_FIFOE 0x00000001
78#define PCH_UART_FCR_RFR 0x00000002
79#define PCH_UART_FCR_TFR 0x00000004
80#define PCH_UART_FCR_DMS 0x00000008
81#define PCH_UART_FCR_FIFO256 0x00000020
82#define PCH_UART_FCR_RFTL 0x000000C0
83
84#define PCH_UART_FCR_RFTL1 0x00000000
85#define PCH_UART_FCR_RFTL64 0x00000040
86#define PCH_UART_FCR_RFTL128 0x00000080
87#define PCH_UART_FCR_RFTL224 0x000000C0
88#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
89#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
90#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
91#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
92#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
93#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
94#define PCH_UART_FCR_RFTL_SHIFT 6
95
96#define PCH_UART_LCR_WLS 0x00000003
97#define PCH_UART_LCR_STB 0x00000004
98#define PCH_UART_LCR_PEN 0x00000008
99#define PCH_UART_LCR_EPS 0x00000010
100#define PCH_UART_LCR_SP 0x00000020
101#define PCH_UART_LCR_SB 0x00000040
102#define PCH_UART_LCR_DLAB 0x00000080
103#define PCH_UART_LCR_NP 0x00000000
104#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
105#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
106#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
107#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
108 PCH_UART_LCR_SP)
109
110#define PCH_UART_LCR_5BIT 0x00000000
111#define PCH_UART_LCR_6BIT 0x00000001
112#define PCH_UART_LCR_7BIT 0x00000002
113#define PCH_UART_LCR_8BIT 0x00000003
114
115#define PCH_UART_MCR_DTR 0x00000001
116#define PCH_UART_MCR_RTS 0x00000002
117#define PCH_UART_MCR_OUT 0x0000000C
118#define PCH_UART_MCR_LOOP 0x00000010
119#define PCH_UART_MCR_AFE 0x00000020
120
121#define PCH_UART_LSR_DR 0x00000001
122#define PCH_UART_LSR_ERR (1<<7)
123
124#define PCH_UART_MSR_DCTS 0x00000001
125#define PCH_UART_MSR_DDSR 0x00000002
126#define PCH_UART_MSR_TERI 0x00000004
127#define PCH_UART_MSR_DDCD 0x00000008
128#define PCH_UART_MSR_CTS 0x00000010
129#define PCH_UART_MSR_DSR 0x00000020
130#define PCH_UART_MSR_RI 0x00000040
131#define PCH_UART_MSR_DCD 0x00000080
132#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
133 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
134
135#define PCH_UART_DLL 0x00
136#define PCH_UART_DLM 0x01
137
138#define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
139
140#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
141#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
142#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
143#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
144#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
145
146#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
147#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
148#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
149#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
150#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
151#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
152#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
153#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
154#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
155#define PCH_UART_HAL_STB1 0
156#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
157
158#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
159#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
160#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
161 PCH_UART_HAL_CLR_RX_FIFO)
162
163#define PCH_UART_HAL_DMA_MODE0 0
164#define PCH_UART_HAL_FIFO_DIS 0
165#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
166#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
167 PCH_UART_FCR_FIFO256)
168#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
169#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
170#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
171#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
172#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
173#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
174#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
175#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
176#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
177#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
178#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
179#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
180#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
181#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
182
183#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
184#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
185#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
186#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
187#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
188
189#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
190#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
191#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
192#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
193#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
194
195struct pch_uart_buffer {
196 unsigned char *buf;
197 int size;
198};
199
200struct eg20t_port {
201 struct uart_port port;
202 int port_type;
203 void __iomem *membase;
204 resource_size_t mapbase;
205 unsigned int iobase;
206 struct pci_dev *pdev;
207 int fifo_size;
208 int base_baud;
209 int start_tx;
210 int start_rx;
211 int tx_empty;
212 int int_dis_flag;
213 int trigger;
214 int trigger_level;
215 struct pch_uart_buffer rxbuf;
216 unsigned int dmsr;
217 unsigned int fcr;
218 unsigned int use_dma;
219 unsigned int use_dma_flag;
220 struct dma_async_tx_descriptor *desc_tx;
221 struct dma_async_tx_descriptor *desc_rx;
222 struct pch_dma_slave param_tx;
223 struct pch_dma_slave param_rx;
224 struct dma_chan *chan_tx;
225 struct dma_chan *chan_rx;
226 struct scatterlist sg_tx;
227 struct scatterlist sg_rx;
228 int tx_dma_use;
229 void *rx_buf_virt;
230 dma_addr_t rx_buf_dma;
231};
232
233static unsigned int default_baud = 9600;
234static const int trigger_level_256[4] = { 1, 64, 128, 224 };
235static const int trigger_level_64[4] = { 1, 16, 32, 56 };
236static const int trigger_level_16[4] = { 1, 4, 8, 14 };
237static const int trigger_level_1[4] = { 1, 1, 1, 1 };
238
239static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
240 int base_baud)
241{
242 struct eg20t_port *priv = pci_get_drvdata(pdev);
243
244 priv->trigger_level = 1;
245 priv->fcr = 0;
246}
247
248static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
249{
250 unsigned int msr = ioread8(base + UART_MSR);
251 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
252
253 return msr;
254}
255
256static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
257 unsigned int flag)
258{
259 u8 ier = ioread8(priv->membase + UART_IER);
260 ier |= flag & PCH_UART_IER_MASK;
261 iowrite8(ier, priv->membase + UART_IER);
262}
263
264static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
265 unsigned int flag)
266{
267 u8 ier = ioread8(priv->membase + UART_IER);
268 ier &= ~(flag & PCH_UART_IER_MASK);
269 iowrite8(ier, priv->membase + UART_IER);
270}
271
272static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
273 unsigned int parity, unsigned int bits,
274 unsigned int stb)
275{
276 unsigned int dll, dlm, lcr;
277 int div;
278
279 div = DIV_ROUND(priv->base_baud / 16, baud);
280 if (div < 0 || USHRT_MAX <= div) {
281 pr_err("Invalid Baud(div=0x%x)\n", div);
282 return -EINVAL;
283 }
284
285 dll = (unsigned int)div & 0x00FFU;
286 dlm = ((unsigned int)div >> 8) & 0x00FFU;
287
288 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
289 pr_err("Invalid parity(0x%x)\n", parity);
290 return -EINVAL;
291 }
292
293 if (bits & ~PCH_UART_LCR_WLS) {
294 pr_err("Invalid bits(0x%x)\n", bits);
295 return -EINVAL;
296 }
297
298 if (stb & ~PCH_UART_LCR_STB) {
299 pr_err("Invalid STB(0x%x)\n", stb);
300 return -EINVAL;
301 }
302
303 lcr = parity;
304 lcr |= bits;
305 lcr |= stb;
306
307 pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
308 __func__, baud, div, lcr, jiffies);
309 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
310 iowrite8(dll, priv->membase + PCH_UART_DLL);
311 iowrite8(dlm, priv->membase + PCH_UART_DLM);
312 iowrite8(lcr, priv->membase + UART_LCR);
313
314 return 0;
315}
316
317static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
318 unsigned int flag)
319{
320 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
321 pr_err("%s:Invalid flag(0x%x)\n", __func__, flag);
322 return -EINVAL;
323 }
324
325 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
326 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
327 priv->membase + UART_FCR);
328 iowrite8(priv->fcr, priv->membase + UART_FCR);
329
330 return 0;
331}
332
333static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
334 unsigned int dmamode,
335 unsigned int fifo_size, unsigned int trigger)
336{
337 u8 fcr;
338
339 if (dmamode & ~PCH_UART_FCR_DMS) {
340 pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode);
341 return -EINVAL;
342 }
343
344 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
345 pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size);
346 return -EINVAL;
347 }
348
349 if (trigger & ~PCH_UART_FCR_RFTL) {
350 pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger);
351 return -EINVAL;
352 }
353
354 switch (priv->fifo_size) {
355 case 256:
356 priv->trigger_level =
357 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
358 break;
359 case 64:
360 priv->trigger_level =
361 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
362 break;
363 case 16:
364 priv->trigger_level =
365 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
366 break;
367 default:
368 priv->trigger_level =
369 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
370 break;
371 }
372 fcr =
373 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
374 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
375 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
376 priv->membase + UART_FCR);
377 iowrite8(fcr, priv->membase + UART_FCR);
378 priv->fcr = fcr;
379
380 return 0;
381}
382
383static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
384{
385 priv->dmsr = 0;
386 return get_msr(priv, priv->membase);
387}
388
389static int pch_uart_hal_write(struct eg20t_port *priv,
390 const unsigned char *buf, int tx_size)
391{
392 int i;
393 unsigned int thr;
394
395 for (i = 0; i < tx_size;) {
396 thr = buf[i++];
397 iowrite8(thr, priv->membase + PCH_UART_THR);
398 }
399 return i;
400}
401
402static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
403 int rx_size)
404{
405 int i;
406 u8 rbr, lsr;
407
408 lsr = ioread8(priv->membase + UART_LSR);
409 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
410 i < rx_size && lsr & UART_LSR_DR;
411 lsr = ioread8(priv->membase + UART_LSR)) {
412 rbr = ioread8(priv->membase + PCH_UART_RBR);
413 buf[i++] = rbr;
414 }
415 return i;
416}
417
418static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
419{
420 unsigned int iir;
421 int ret;
422
423 iir = ioread8(priv->membase + UART_IIR);
424 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
425 return ret;
426}
427
428static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
429{
430 return ioread8(priv->membase + UART_LSR);
431}
432
433static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
434{
435 unsigned int lcr;
436
437 lcr = ioread8(priv->membase + UART_LCR);
438 if (on)
439 lcr |= PCH_UART_LCR_SB;
440 else
441 lcr &= ~PCH_UART_LCR_SB;
442
443 iowrite8(lcr, priv->membase + UART_LCR);
444}
445
446static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
447 int size)
448{
449 struct uart_port *port;
450 struct tty_struct *tty;
451
452 port = &priv->port;
453 tty = tty_port_tty_get(&port->state->port);
454 if (!tty) {
455 pr_debug("%s:tty is busy now", __func__);
456 return -EBUSY;
457 }
458
459 tty_insert_flip_string(tty, buf, size);
460 tty_flip_buffer_push(tty);
461 tty_kref_put(tty);
462
463 return 0;
464}
465
466static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
467{
468 int ret;
469 struct uart_port *port = &priv->port;
470
471 if (port->x_char) {
472 pr_debug("%s:X character send %02x (%lu)\n", __func__,
473 port->x_char, jiffies);
474 buf[0] = port->x_char;
475 port->x_char = 0;
476 ret = 1;
477 } else {
478 ret = 0;
479 }
480
481 return ret;
482}
483
484static int dma_push_rx(struct eg20t_port *priv, int size)
485{
486 struct tty_struct *tty;
487 int room;
488 struct uart_port *port = &priv->port;
489
490 port = &priv->port;
491 tty = tty_port_tty_get(&port->state->port);
492 if (!tty) {
493 pr_debug("%s:tty is busy now", __func__);
494 return 0;
495 }
496
497 room = tty_buffer_request_room(tty, size);
498
499 if (room < size)
500 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
501 size - room);
502 if (!room)
503 return room;
504
505 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
506
507 port->icount.rx += room;
508 tty_kref_put(tty);
509
510 return room;
511}
512
513static void pch_free_dma(struct uart_port *port)
514{
515 struct eg20t_port *priv;
516 priv = container_of(port, struct eg20t_port, port);
517
518 if (priv->chan_tx) {
519 dma_release_channel(priv->chan_tx);
520 priv->chan_tx = NULL;
521 }
522 if (priv->chan_rx) {
523 dma_release_channel(priv->chan_rx);
524 priv->chan_rx = NULL;
525 }
526 if (sg_dma_address(&priv->sg_rx))
527 dma_free_coherent(port->dev, port->fifosize,
528 sg_virt(&priv->sg_rx),
529 sg_dma_address(&priv->sg_rx));
530
531 return;
532}
533
534static bool filter(struct dma_chan *chan, void *slave)
535{
536 struct pch_dma_slave *param = slave;
537
538 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
539 chan->device->dev)) {
540 chan->private = param;
541 return true;
542 } else {
543 return false;
544 }
545}
546
547static void pch_request_dma(struct uart_port *port)
548{
549 dma_cap_mask_t mask;
550 struct dma_chan *chan;
551 struct pci_dev *dma_dev;
552 struct pch_dma_slave *param;
553 struct eg20t_port *priv =
554 container_of(port, struct eg20t_port, port);
555 dma_cap_zero(mask);
556 dma_cap_set(DMA_SLAVE, mask);
557
558 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
559 information */
560 /* Set Tx DMA */
561 param = &priv->param_tx;
562 param->dma_dev = &dma_dev->dev;
563 param->chan_id = priv->port.line;
564 param->tx_reg = port->mapbase + UART_TX;
565 chan = dma_request_channel(mask, filter, param);
566 if (!chan) {
567 pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__);
568 return;
569 }
570 priv->chan_tx = chan;
571
572 /* Set Rx DMA */
573 param = &priv->param_rx;
574 param->dma_dev = &dma_dev->dev;
575 param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */
576 param->rx_reg = port->mapbase + UART_RX;
577 chan = dma_request_channel(mask, filter, param);
578 if (!chan) {
579 pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__);
580 dma_release_channel(priv->chan_tx);
581 return;
582 }
583
584 /* Get Consistent memory for DMA */
585 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
586 &priv->rx_buf_dma, GFP_KERNEL);
587 priv->chan_rx = chan;
588}
589
590static void pch_dma_rx_complete(void *arg)
591{
592 struct eg20t_port *priv = arg;
593 struct uart_port *port = &priv->port;
594 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
595
596 if (!tty) {
597 pr_debug("%s:tty is busy now", __func__);
598 return;
599 }
600
601 if (dma_push_rx(priv, priv->trigger_level))
602 tty_flip_buffer_push(tty);
603
604 tty_kref_put(tty);
605}
606
607static void pch_dma_tx_complete(void *arg)
608{
609 struct eg20t_port *priv = arg;
610 struct uart_port *port = &priv->port;
611 struct circ_buf *xmit = &port->state->xmit;
612
613 xmit->tail += sg_dma_len(&priv->sg_tx);
614 xmit->tail &= UART_XMIT_SIZE - 1;
615 port->icount.tx += sg_dma_len(&priv->sg_tx);
616
617 async_tx_ack(priv->desc_tx);
618 priv->tx_dma_use = 0;
619}
620
621static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size)
622{
623 int count = 0;
624 struct uart_port *port = &priv->port;
625 struct circ_buf *xmit = &port->state->xmit;
626
627 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
628 goto pop_tx_end;
629
630 do {
631 int cnt_to_end =
632 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
633 int sz = min(size - count, cnt_to_end);
634 memcpy(&buf[count], &xmit->buf[xmit->tail], sz);
635 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
636 count += sz;
637 } while (!uart_circ_empty(xmit) && count < size);
638
639pop_tx_end:
640 pr_debug("%d characters. Remained %d characters. (%lu)\n",
641 count, size - count, jiffies);
642
643 return count;
644}
645
646static int handle_rx_to(struct eg20t_port *priv)
647{
648 struct pch_uart_buffer *buf;
649 int rx_size;
650 int ret;
651 if (!priv->start_rx) {
652 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
653 return 0;
654 }
655 buf = &priv->rxbuf;
656 do {
657 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
658 ret = push_rx(priv, buf->buf, rx_size);
659 if (ret)
660 return 0;
661 } while (rx_size == buf->size);
662
663 return PCH_UART_HANDLED_RX_INT;
664}
665
666static int handle_rx(struct eg20t_port *priv)
667{
668 return handle_rx_to(priv);
669}
670
671static int dma_handle_rx(struct eg20t_port *priv)
672{
673 struct uart_port *port = &priv->port;
674 struct dma_async_tx_descriptor *desc;
675 struct scatterlist *sg;
676
677 priv = container_of(port, struct eg20t_port, port);
678 sg = &priv->sg_rx;
679
680 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
681
682 sg_dma_len(sg) = priv->fifo_size;
683
684 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
685 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
686 ~PAGE_MASK);
687
688 sg_dma_address(sg) = priv->rx_buf_dma;
689
690 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
691 sg, 1, DMA_FROM_DEVICE,
692 DMA_PREP_INTERRUPT);
693 if (!desc)
694 return 0;
695
696 priv->desc_rx = desc;
697 desc->callback = pch_dma_rx_complete;
698 desc->callback_param = priv;
699 desc->tx_submit(desc);
700 dma_async_issue_pending(priv->chan_rx);
701
702 return PCH_UART_HANDLED_RX_INT;
703}
704
705static unsigned int handle_tx(struct eg20t_port *priv)
706{
707 struct uart_port *port = &priv->port;
708 struct circ_buf *xmit = &port->state->xmit;
709 int ret;
710 int fifo_size;
711 int tx_size;
712 int size;
713 int tx_empty;
714
715 if (!priv->start_tx) {
716 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
717 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
718 priv->tx_empty = 1;
719 return 0;
720 }
721
722 fifo_size = max(priv->fifo_size, 1);
723 tx_empty = 1;
724 if (pop_tx_x(priv, xmit->buf)) {
725 pch_uart_hal_write(priv, xmit->buf, 1);
726 port->icount.tx++;
727 tx_empty = 0;
728 fifo_size--;
729 }
730 size = min(xmit->head - xmit->tail, fifo_size);
731 tx_size = pop_tx(priv, xmit->buf, size);
732 if (tx_size > 0) {
733 ret = pch_uart_hal_write(priv, xmit->buf, tx_size);
734 port->icount.tx += ret;
735 tx_empty = 0;
736 }
737
738 priv->tx_empty = tx_empty;
739
740 if (tx_empty)
741 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
742
743 return PCH_UART_HANDLED_TX_INT;
744}
745
746static unsigned int dma_handle_tx(struct eg20t_port *priv)
747{
748 struct uart_port *port = &priv->port;
749 struct circ_buf *xmit = &port->state->xmit;
750 struct scatterlist *sg = &priv->sg_tx;
751 int nent;
752 int fifo_size;
753 int tx_empty;
754 struct dma_async_tx_descriptor *desc;
755
756 if (!priv->start_tx) {
757 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
758 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
759 priv->tx_empty = 1;
760 return 0;
761 }
762
763 fifo_size = max(priv->fifo_size, 1);
764 tx_empty = 1;
765 if (pop_tx_x(priv, xmit->buf)) {
766 pch_uart_hal_write(priv, xmit->buf, 1);
767 port->icount.tx++;
768 tx_empty = 0;
769 fifo_size--;
770 }
771
772 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
773
774 priv->tx_dma_use = 1;
775
776 sg_init_table(&priv->sg_tx, 1); /* Initialize SG table */
777
778 sg_set_page(&priv->sg_tx, virt_to_page(xmit->buf),
779 UART_XMIT_SIZE, (int)xmit->buf & ~PAGE_MASK);
780
781 nent = dma_map_sg(port->dev, &priv->sg_tx, 1, DMA_TO_DEVICE);
782 if (!nent) {
783 pr_err("%s:dma_map_sg Failed\n", __func__);
784 return 0;
785 }
786
787 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
788 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
789 sg->offset;
790 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail,
791 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
792 xmit->tail, UART_XMIT_SIZE));
793
794 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
795 sg, nent, DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
796 if (!desc) {
797 pr_err("%s:device_prep_slave_sg Failed\n", __func__);
798 return 0;
799 }
800
801 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
802
803 priv->desc_tx = desc;
804 desc->callback = pch_dma_tx_complete;
805 desc->callback_param = priv;
806
807 desc->tx_submit(desc);
808
809 dma_async_issue_pending(priv->chan_tx);
810
811 return PCH_UART_HANDLED_TX_INT;
812}
813
814static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
815{
816 u8 fcr = ioread8(priv->membase + UART_FCR);
817
818 /* Reset FIFO */
819 fcr |= UART_FCR_CLEAR_RCVR;
820 iowrite8(fcr, priv->membase + UART_FCR);
821
822 if (lsr & PCH_UART_LSR_ERR)
823 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
824
825 if (lsr & UART_LSR_FE)
826 dev_err(&priv->pdev->dev, "Framing Error\n");
827
828 if (lsr & UART_LSR_PE)
829 dev_err(&priv->pdev->dev, "Parity Error\n");
830
831 if (lsr & UART_LSR_OE)
832 dev_err(&priv->pdev->dev, "Overrun Error\n");
833}
834
835static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
836{
837 struct eg20t_port *priv = dev_id;
838 unsigned int handled;
839 u8 lsr;
840 int ret = 0;
841 unsigned int iid;
842 unsigned long flags;
843
844 spin_lock_irqsave(&priv->port.lock, flags);
845 handled = 0;
846 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
847 switch (iid) {
848 case PCH_UART_IID_RLS: /* Receiver Line Status */
849 lsr = pch_uart_hal_get_line_status(priv);
850 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
851 UART_LSR_PE | UART_LSR_OE)) {
852 pch_uart_err_ir(priv, lsr);
853 ret = PCH_UART_HANDLED_RX_ERR_INT;
854 }
855 break;
856 case PCH_UART_IID_RDR: /* Received Data Ready */
857 if (priv->use_dma)
858 ret = dma_handle_rx(priv);
859 else
860 ret = handle_rx(priv);
861 break;
862 case PCH_UART_IID_RDR_TO: /* Received Data Ready
863 (FIFO Timeout) */
864 ret = handle_rx_to(priv);
865 break;
866 case PCH_UART_IID_THRE: /* Transmitter Holding Register
867 Empty */
868 if (priv->use_dma)
869 ret = dma_handle_tx(priv);
870 else
871 ret = handle_tx(priv);
872 break;
873 case PCH_UART_IID_MS: /* Modem Status */
874 ret = PCH_UART_HANDLED_MS_INT;
875 break;
876 default: /* Never junp to this label */
877 pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies);
878 ret = -1;
879 break;
880 }
881 handled |= (unsigned int)ret;
882 }
883 if (handled == 0 && iid <= 1) {
884 if (priv->int_dis_flag)
885 priv->int_dis_flag = 0;
886 }
887
888 spin_unlock_irqrestore(&priv->port.lock, flags);
889 return IRQ_RETVAL(handled);
890}
891
892/* This function tests whether the transmitter fifo and shifter for the port
893 described by 'port' is empty. */
894static unsigned int pch_uart_tx_empty(struct uart_port *port)
895{
896 struct eg20t_port *priv;
897 int ret;
898 priv = container_of(port, struct eg20t_port, port);
899 if (priv->tx_empty)
900 ret = TIOCSER_TEMT;
901 else
902 ret = 0;
903
904 return ret;
905}
906
907/* Returns the current state of modem control inputs. */
908static unsigned int pch_uart_get_mctrl(struct uart_port *port)
909{
910 struct eg20t_port *priv;
911 u8 modem;
912 unsigned int ret = 0;
913
914 priv = container_of(port, struct eg20t_port, port);
915 modem = pch_uart_hal_get_modem(priv);
916
917 if (modem & UART_MSR_DCD)
918 ret |= TIOCM_CAR;
919
920 if (modem & UART_MSR_RI)
921 ret |= TIOCM_RNG;
922
923 if (modem & UART_MSR_DSR)
924 ret |= TIOCM_DSR;
925
926 if (modem & UART_MSR_CTS)
927 ret |= TIOCM_CTS;
928
929 return ret;
930}
931
932static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
933{
934 u32 mcr = 0;
935 unsigned int dat;
936 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
937
938 if (mctrl & TIOCM_DTR)
939 mcr |= UART_MCR_DTR;
940 if (mctrl & TIOCM_RTS)
941 mcr |= UART_MCR_RTS;
942 if (mctrl & TIOCM_LOOP)
943 mcr |= UART_MCR_LOOP;
944
945 if (mctrl) {
946 dat = pch_uart_get_mctrl(port);
947 dat |= mcr;
948 iowrite8(dat, priv->membase + UART_MCR);
949 }
950}
951
952static void pch_uart_stop_tx(struct uart_port *port)
953{
954 struct eg20t_port *priv;
955 priv = container_of(port, struct eg20t_port, port);
956 priv->start_tx = 0;
957 priv->tx_dma_use = 0;
958}
959
960static void pch_uart_start_tx(struct uart_port *port)
961{
962 struct eg20t_port *priv;
963
964 priv = container_of(port, struct eg20t_port, port);
965
966 if (priv->use_dma)
967 if (priv->tx_dma_use)
968 return;
969
970 priv->start_tx = 1;
971 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
972}
973
974static void pch_uart_stop_rx(struct uart_port *port)
975{
976 struct eg20t_port *priv;
977 priv = container_of(port, struct eg20t_port, port);
978 priv->start_rx = 0;
979 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
980 priv->int_dis_flag = 1;
981}
982
983/* Enable the modem status interrupts. */
984static void pch_uart_enable_ms(struct uart_port *port)
985{
986 struct eg20t_port *priv;
987 priv = container_of(port, struct eg20t_port, port);
988 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
989}
990
991/* Control the transmission of a break signal. */
992static void pch_uart_break_ctl(struct uart_port *port, int ctl)
993{
994 struct eg20t_port *priv;
995 unsigned long flags;
996
997 priv = container_of(port, struct eg20t_port, port);
998 spin_lock_irqsave(&port->lock, flags);
999 pch_uart_hal_set_break(priv, ctl);
1000 spin_unlock_irqrestore(&port->lock, flags);
1001}
1002
1003/* Grab any interrupt resources and initialise any low level driver state. */
1004static int pch_uart_startup(struct uart_port *port)
1005{
1006 struct eg20t_port *priv;
1007 int ret;
1008 int fifo_size;
1009 int trigger_level;
1010
1011 priv = container_of(port, struct eg20t_port, port);
1012 priv->tx_empty = 1;
1013 port->uartclk = priv->base_baud;
1014 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1015 ret = pch_uart_hal_set_line(priv, default_baud,
1016 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1017 PCH_UART_HAL_STB1);
1018 if (ret)
1019 return ret;
1020
1021 switch (priv->fifo_size) {
1022 case 256:
1023 fifo_size = PCH_UART_HAL_FIFO256;
1024 break;
1025 case 64:
1026 fifo_size = PCH_UART_HAL_FIFO64;
1027 break;
1028 case 16:
1029 fifo_size = PCH_UART_HAL_FIFO16;
1030 case 1:
1031 default:
1032 fifo_size = PCH_UART_HAL_FIFO_DIS;
1033 break;
1034 }
1035
1036 switch (priv->trigger) {
1037 case PCH_UART_HAL_TRIGGER1:
1038 trigger_level = 1;
1039 break;
1040 case PCH_UART_HAL_TRIGGER_L:
1041 trigger_level = priv->fifo_size / 4;
1042 break;
1043 case PCH_UART_HAL_TRIGGER_M:
1044 trigger_level = priv->fifo_size / 2;
1045 break;
1046 case PCH_UART_HAL_TRIGGER_H:
1047 default:
1048 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1049 break;
1050 }
1051
1052 priv->trigger_level = trigger_level;
1053 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1054 fifo_size, priv->trigger);
1055 if (ret < 0)
1056 return ret;
1057
1058 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1059 KBUILD_MODNAME, priv);
1060 if (ret < 0)
1061 return ret;
1062
1063 if (priv->use_dma)
1064 pch_request_dma(port);
1065
1066 priv->start_rx = 1;
1067 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1068 uart_update_timeout(port, CS8, default_baud);
1069
1070 return 0;
1071}
1072
1073static void pch_uart_shutdown(struct uart_port *port)
1074{
1075 struct eg20t_port *priv;
1076 int ret;
1077
1078 priv = container_of(port, struct eg20t_port, port);
1079 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1080 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1081 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1082 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1083 if (ret)
1084 pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1085
1086 if (priv->use_dma_flag)
1087 pch_free_dma(port);
1088
1089 free_irq(priv->port.irq, priv);
1090}
1091
1092/* Change the port parameters, including word length, parity, stop
1093 *bits. Update read_status_mask and ignore_status_mask to indicate
1094 *the types of events we are interested in receiving. */
1095static void pch_uart_set_termios(struct uart_port *port,
1096 struct ktermios *termios, struct ktermios *old)
1097{
1098 int baud;
1099 int rtn;
1100 unsigned int parity, bits, stb;
1101 struct eg20t_port *priv;
1102 unsigned long flags;
1103
1104 priv = container_of(port, struct eg20t_port, port);
1105 switch (termios->c_cflag & CSIZE) {
1106 case CS5:
1107 bits = PCH_UART_HAL_5BIT;
1108 break;
1109 case CS6:
1110 bits = PCH_UART_HAL_6BIT;
1111 break;
1112 case CS7:
1113 bits = PCH_UART_HAL_7BIT;
1114 break;
1115 default: /* CS8 */
1116 bits = PCH_UART_HAL_8BIT;
1117 break;
1118 }
1119 if (termios->c_cflag & CSTOPB)
1120 stb = PCH_UART_HAL_STB2;
1121 else
1122 stb = PCH_UART_HAL_STB1;
1123
1124 if (termios->c_cflag & PARENB) {
1125 if (!(termios->c_cflag & PARODD))
1126 parity = PCH_UART_HAL_PARITY_ODD;
1127 else
1128 parity = PCH_UART_HAL_PARITY_EVEN;
1129
1130 } else {
1131 parity = PCH_UART_HAL_PARITY_NONE;
1132 }
1133 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1134
1135 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1136
1137 spin_lock_irqsave(&port->lock, flags);
1138
1139 uart_update_timeout(port, termios->c_cflag, baud);
1140 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1141 if (rtn)
1142 goto out;
1143
1144 /* Don't rewrite B0 */
1145 if (tty_termios_baud_rate(termios))
1146 tty_termios_encode_baud_rate(termios, baud, baud);
1147
1148out:
1149 spin_unlock_irqrestore(&port->lock, flags);
1150}
1151
1152static const char *pch_uart_type(struct uart_port *port)
1153{
1154 return KBUILD_MODNAME;
1155}
1156
1157static void pch_uart_release_port(struct uart_port *port)
1158{
1159 struct eg20t_port *priv;
1160
1161 priv = container_of(port, struct eg20t_port, port);
1162 pci_iounmap(priv->pdev, priv->membase);
1163 pci_release_regions(priv->pdev);
1164}
1165
1166static int pch_uart_request_port(struct uart_port *port)
1167{
1168 struct eg20t_port *priv;
1169 int ret;
1170 void __iomem *membase;
1171
1172 priv = container_of(port, struct eg20t_port, port);
1173 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1174 if (ret < 0)
1175 return -EBUSY;
1176
1177 membase = pci_iomap(priv->pdev, 1, 0);
1178 if (!membase) {
1179 pci_release_regions(priv->pdev);
1180 return -EBUSY;
1181 }
1182 priv->membase = port->membase = membase;
1183
1184 return 0;
1185}
1186
1187static void pch_uart_config_port(struct uart_port *port, int type)
1188{
1189 struct eg20t_port *priv;
1190
1191 priv = container_of(port, struct eg20t_port, port);
1192 if (type & UART_CONFIG_TYPE) {
1193 port->type = priv->port_type;
1194 pch_uart_request_port(port);
1195 }
1196}
1197
1198static int pch_uart_verify_port(struct uart_port *port,
1199 struct serial_struct *serinfo)
1200{
1201 struct eg20t_port *priv;
1202
1203 priv = container_of(port, struct eg20t_port, port);
1204 if (serinfo->flags & UPF_LOW_LATENCY) {
1205 pr_info("PCH UART : Use PIO Mode (without DMA)\n");
1206 priv->use_dma = 0;
1207 serinfo->flags &= ~UPF_LOW_LATENCY;
1208 } else {
1209#ifndef CONFIG_PCH_DMA
1210 pr_err("%s : PCH DMA is not Loaded.\n", __func__);
1211 return -EOPNOTSUPP;
1212#endif
1213 priv->use_dma = 1;
1214 priv->use_dma_flag = 1;
1215 pr_info("PCH UART : Use DMA Mode\n");
1216 }
1217
1218 return 0;
1219}
1220
1221static struct uart_ops pch_uart_ops = {
1222 .tx_empty = pch_uart_tx_empty,
1223 .set_mctrl = pch_uart_set_mctrl,
1224 .get_mctrl = pch_uart_get_mctrl,
1225 .stop_tx = pch_uart_stop_tx,
1226 .start_tx = pch_uart_start_tx,
1227 .stop_rx = pch_uart_stop_rx,
1228 .enable_ms = pch_uart_enable_ms,
1229 .break_ctl = pch_uart_break_ctl,
1230 .startup = pch_uart_startup,
1231 .shutdown = pch_uart_shutdown,
1232 .set_termios = pch_uart_set_termios,
1233/* .pm = pch_uart_pm, Not supported yet */
1234/* .set_wake = pch_uart_set_wake, Not supported yet */
1235 .type = pch_uart_type,
1236 .release_port = pch_uart_release_port,
1237 .request_port = pch_uart_request_port,
1238 .config_port = pch_uart_config_port,
1239 .verify_port = pch_uart_verify_port
1240};
1241
1242static struct uart_driver pch_uart_driver = {
1243 .owner = THIS_MODULE,
1244 .driver_name = KBUILD_MODNAME,
1245 .dev_name = PCH_UART_DRIVER_DEVICE,
1246 .major = 0,
1247 .minor = 0,
1248 .nr = PCH_UART_NR,
1249};
1250
1251static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1252 int port_type)
1253{
1254 struct eg20t_port *priv;
1255 int ret;
1256 unsigned int iobase;
1257 unsigned int mapbase;
1258 unsigned char *rxbuf;
1259 int fifosize, base_baud;
1260 static int num;
1261
1262 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1263 if (priv == NULL)
1264 goto init_port_alloc_err;
1265
1266 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1267 if (!rxbuf)
1268 goto init_port_free_txbuf;
1269
1270 switch (port_type) {
1271 case PORT_UNKNOWN:
1272 fifosize = 256; /* UART0 */
1273 base_baud = 1843200; /* 1.8432MHz */
1274 break;
1275 case PORT_8250:
1276 fifosize = 64; /* UART1~3 */
1277 base_baud = 1843200; /* 1.8432MHz */
1278 break;
1279 default:
1280 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1281 goto init_port_hal_free;
1282 }
1283
1284 iobase = pci_resource_start(pdev, 0);
1285 mapbase = pci_resource_start(pdev, 1);
1286 priv->mapbase = mapbase;
1287 priv->iobase = iobase;
1288 priv->pdev = pdev;
1289 priv->tx_empty = 1;
1290 priv->rxbuf.buf = rxbuf;
1291 priv->rxbuf.size = PAGE_SIZE;
1292
1293 priv->fifo_size = fifosize;
1294 priv->base_baud = base_baud;
1295 priv->port_type = PORT_MAX_8250 + port_type + 1;
1296 priv->port.dev = &pdev->dev;
1297 priv->port.iobase = iobase;
1298 priv->port.membase = NULL;
1299 priv->port.mapbase = mapbase;
1300 priv->port.irq = pdev->irq;
1301 priv->port.iotype = UPIO_PORT;
1302 priv->port.ops = &pch_uart_ops;
1303 priv->port.flags = UPF_BOOT_AUTOCONF;
1304 priv->port.fifosize = fifosize;
1305 priv->port.line = num++;
1306 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1307
1308 pci_set_drvdata(pdev, priv);
1309 pch_uart_hal_request(pdev, fifosize, base_baud);
1310 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1311 if (ret < 0)
1312 goto init_port_hal_free;
1313
1314 return priv;
1315
1316init_port_hal_free:
1317 free_page((unsigned long)rxbuf);
1318init_port_free_txbuf:
1319 kfree(priv);
1320init_port_alloc_err:
1321
1322 return NULL;
1323}
1324
1325static void pch_uart_exit_port(struct eg20t_port *priv)
1326{
1327 uart_remove_one_port(&pch_uart_driver, &priv->port);
1328 pci_set_drvdata(priv->pdev, NULL);
1329 free_page((unsigned long)priv->rxbuf.buf);
1330}
1331
1332static void pch_uart_pci_remove(struct pci_dev *pdev)
1333{
1334 struct eg20t_port *priv;
1335
1336 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1337 pch_uart_exit_port(priv);
1338 pci_disable_device(pdev);
1339 kfree(priv);
1340 return;
1341}
1342#ifdef CONFIG_PM
1343static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1344{
1345 struct eg20t_port *priv = pci_get_drvdata(pdev);
1346
1347 uart_suspend_port(&pch_uart_driver, &priv->port);
1348
1349 pci_save_state(pdev);
1350 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1351 return 0;
1352}
1353
1354static int pch_uart_pci_resume(struct pci_dev *pdev)
1355{
1356 struct eg20t_port *priv = pci_get_drvdata(pdev);
1357 int ret;
1358
1359 pci_set_power_state(pdev, PCI_D0);
1360 pci_restore_state(pdev);
1361
1362 ret = pci_enable_device(pdev);
1363 if (ret) {
1364 dev_err(&pdev->dev,
1365 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1366 return ret;
1367 }
1368
1369 uart_resume_port(&pch_uart_driver, &priv->port);
1370
1371 return 0;
1372}
1373#else
1374#define pch_uart_pci_suspend NULL
1375#define pch_uart_pci_resume NULL
1376#endif
1377
1378static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1379 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1380 .driver_data = PCH_UART_8LINE},
1381 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1382 .driver_data = PCH_UART_2LINE},
1383 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1384 .driver_data = PCH_UART_2LINE},
1385 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1386 .driver_data = PCH_UART_2LINE},
1387 {0,},
1388};
1389
1390static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1391 const struct pci_device_id *id)
1392{
1393 int ret;
1394 struct eg20t_port *priv;
1395
1396 ret = pci_enable_device(pdev);
1397 if (ret < 0)
1398 goto probe_error;
1399
1400 priv = pch_uart_init_port(pdev, id->driver_data);
1401 if (!priv) {
1402 ret = -EBUSY;
1403 goto probe_disable_device;
1404 }
1405 pci_set_drvdata(pdev, priv);
1406
1407 return ret;
1408
1409probe_disable_device:
1410 pci_disable_device(pdev);
1411probe_error:
1412 return ret;
1413}
1414
1415static struct pci_driver pch_uart_pci_driver = {
1416 .name = "pch_uart",
1417 .id_table = pch_uart_pci_id,
1418 .probe = pch_uart_pci_probe,
1419 .remove = __devexit_p(pch_uart_pci_remove),
1420 .suspend = pch_uart_pci_suspend,
1421 .resume = pch_uart_pci_resume,
1422};
1423
1424static int __init pch_uart_module_init(void)
1425{
1426 int ret;
1427
1428 /* register as UART driver */
1429 ret = uart_register_driver(&pch_uart_driver);
1430 if (ret < 0)
1431 return ret;
1432
1433 /* register as PCI driver */
1434 ret = pci_register_driver(&pch_uart_pci_driver);
1435 if (ret < 0)
1436 uart_unregister_driver(&pch_uart_driver);
1437
1438 return ret;
1439}
1440module_init(pch_uart_module_init);
1441
1442static void __exit pch_uart_module_exit(void)
1443{
1444 pci_unregister_driver(&pch_uart_pci_driver);
1445 uart_unregister_driver(&pch_uart_driver);
1446}
1447module_exit(pch_uart_module_exit);
1448
1449MODULE_LICENSE("GPL v2");
1450MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1451module_param(default_baud, uint, S_IRUGO);
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index 9ffa5bee44ab..460a72d91bb7 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -1985,7 +1985,8 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport)
1985 1985
1986 tty_dev = device_find_child(uport->dev, &match, serial_match_port); 1986 tty_dev = device_find_child(uport->dev, &match, serial_match_port);
1987 if (device_may_wakeup(tty_dev)) { 1987 if (device_may_wakeup(tty_dev)) {
1988 enable_irq_wake(uport->irq); 1988 if (!enable_irq_wake(uport->irq))
1989 uport->irq_wake = 1;
1989 put_device(tty_dev); 1990 put_device(tty_dev);
1990 mutex_unlock(&port->mutex); 1991 mutex_unlock(&port->mutex);
1991 return 0; 1992 return 0;
@@ -2051,7 +2052,10 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
2051 2052
2052 tty_dev = device_find_child(uport->dev, &match, serial_match_port); 2053 tty_dev = device_find_child(uport->dev, &match, serial_match_port);
2053 if (!uport->suspended && device_may_wakeup(tty_dev)) { 2054 if (!uport->suspended && device_may_wakeup(tty_dev)) {
2054 disable_irq_wake(uport->irq); 2055 if (uport->irq_wake) {
2056 disable_irq_wake(uport->irq);
2057 uport->irq_wake = 0;
2058 }
2055 mutex_unlock(&port->mutex); 2059 mutex_unlock(&port->mutex);
2056 return 0; 2060 return 0;
2057 } 2061 }
@@ -2134,6 +2138,7 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
2134 case UPIO_AU: 2138 case UPIO_AU:
2135 case UPIO_TSI: 2139 case UPIO_TSI:
2136 case UPIO_DWAPB: 2140 case UPIO_DWAPB:
2141 case UPIO_DWAPB32:
2137 snprintf(address, sizeof(address), 2142 snprintf(address, sizeof(address),
2138 "MMIO 0x%llx", (unsigned long long)port->mapbase); 2143 "MMIO 0x%llx", (unsigned long long)port->mapbase);
2139 break; 2144 break;
@@ -2554,6 +2559,7 @@ int uart_match_port(struct uart_port *port1, struct uart_port *port2)
2554 case UPIO_AU: 2559 case UPIO_AU:
2555 case UPIO_TSI: 2560 case UPIO_TSI:
2556 case UPIO_DWAPB: 2561 case UPIO_DWAPB:
2562 case UPIO_DWAPB32:
2557 return (port1->mapbase == port2->mapbase); 2563 return (port1->mapbase == port2->mapbase);
2558 } 2564 }
2559 return 0; 2565 return 0;
diff --git a/drivers/serial/vt8500_serial.c b/drivers/serial/vt8500_serial.c
new file mode 100644
index 000000000000..322bf56c0d89
--- /dev/null
+++ b/drivers/serial/vt8500_serial.c
@@ -0,0 +1,648 @@
1/*
2 * drivers/serial/vt8500_serial.c
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 *
6 * Based on msm_serial.c, which is:
7 * Copyright (C) 2007 Google, Inc.
8 * Author: Robert Love <rlove@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21# define SUPPORT_SYSRQ
22#endif
23
24#include <linux/hrtimer.h>
25#include <linux/delay.h>
26#include <linux/module.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/irq.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_core.h>
35#include <linux/serial.h>
36#include <linux/slab.h>
37#include <linux/clk.h>
38#include <linux/platform_device.h>
39
40/*
41 * UART Register offsets
42 */
43
44#define VT8500_URTDR 0x0000 /* Transmit data */
45#define VT8500_URRDR 0x0004 /* Receive data */
46#define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
47#define VT8500_URLCR 0x000C /* Line control */
48#define VT8500_URICR 0x0010 /* IrDA control */
49#define VT8500_URIER 0x0014 /* Interrupt enable */
50#define VT8500_URISR 0x0018 /* Interrupt status */
51#define VT8500_URUSR 0x001c /* UART status */
52#define VT8500_URFCR 0x0020 /* FIFO control */
53#define VT8500_URFIDX 0x0024 /* FIFO index */
54#define VT8500_URBKR 0x0028 /* Break signal count */
55#define VT8500_URTOD 0x002c /* Time out divisor */
56#define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
57#define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
58
59/*
60 * Interrupt enable and status bits
61 */
62
63#define TXDE (1 << 0) /* Tx Data empty */
64#define RXDF (1 << 1) /* Rx Data full */
65#define TXFAE (1 << 2) /* Tx FIFO almost empty */
66#define TXFE (1 << 3) /* Tx FIFO empty */
67#define RXFAF (1 << 4) /* Rx FIFO almost full */
68#define RXFF (1 << 5) /* Rx FIFO full */
69#define TXUDR (1 << 6) /* Tx underrun */
70#define RXOVER (1 << 7) /* Rx overrun */
71#define PER (1 << 8) /* Parity error */
72#define FER (1 << 9) /* Frame error */
73#define TCTS (1 << 10) /* Toggle of CTS */
74#define RXTOUT (1 << 11) /* Rx timeout */
75#define BKDONE (1 << 12) /* Break signal done */
76#define ERR (1 << 13) /* AHB error response */
77
78#define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
79#define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
80
81struct vt8500_port {
82 struct uart_port uart;
83 char name[16];
84 struct clk *clk;
85 unsigned int ier;
86};
87
88static inline void vt8500_write(struct uart_port *port, unsigned int val,
89 unsigned int off)
90{
91 writel(val, port->membase + off);
92}
93
94static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
95{
96 return readl(port->membase + off);
97}
98
99static void vt8500_stop_tx(struct uart_port *port)
100{
101 struct vt8500_port *vt8500_port = container_of(port,
102 struct vt8500_port,
103 uart);
104
105 vt8500_port->ier &= ~TX_FIFO_INTS;
106 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
107}
108
109static void vt8500_stop_rx(struct uart_port *port)
110{
111 struct vt8500_port *vt8500_port = container_of(port,
112 struct vt8500_port,
113 uart);
114
115 vt8500_port->ier &= ~RX_FIFO_INTS;
116 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
117}
118
119static void vt8500_enable_ms(struct uart_port *port)
120{
121 struct vt8500_port *vt8500_port = container_of(port,
122 struct vt8500_port,
123 uart);
124
125 vt8500_port->ier |= TCTS;
126 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
127}
128
129static void handle_rx(struct uart_port *port)
130{
131 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
132 if (!tty) {
133 /* Discard data: no tty available */
134 int count = (vt8500_read(port, VT8500_URFIDX) & 0x1f00) >> 8;
135 u16 ch;
136 while (count--)
137 ch = readw(port->membase + VT8500_RXFIFO);
138 return;
139 }
140
141 /*
142 * Handle overrun
143 */
144 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
145 port->icount.overrun++;
146 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
147 }
148
149 /* and now the main RX loop */
150 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
151 unsigned int c;
152 char flag = TTY_NORMAL;
153
154 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
155
156 /* Mask conditions we're ignorning. */
157 c &= ~port->read_status_mask;
158
159 if (c & FER) {
160 port->icount.frame++;
161 flag = TTY_FRAME;
162 } else if (c & PER) {
163 port->icount.parity++;
164 flag = TTY_PARITY;
165 }
166 port->icount.rx++;
167
168 if (!uart_handle_sysrq_char(port, c))
169 tty_insert_flip_char(tty, c, flag);
170 }
171
172 tty_flip_buffer_push(tty);
173 tty_kref_put(tty);
174}
175
176static void handle_tx(struct uart_port *port)
177{
178 struct circ_buf *xmit = &port->state->xmit;
179
180 if (port->x_char) {
181 writeb(port->x_char, port->membase + VT8500_TXFIFO);
182 port->icount.tx++;
183 port->x_char = 0;
184 }
185 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
186 vt8500_stop_tx(port);
187 return;
188 }
189
190 while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
191 if (uart_circ_empty(xmit))
192 break;
193
194 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
195
196 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
197 port->icount.tx++;
198 }
199
200 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
201 uart_write_wakeup(port);
202
203 if (uart_circ_empty(xmit))
204 vt8500_stop_tx(port);
205}
206
207static void vt8500_start_tx(struct uart_port *port)
208{
209 struct vt8500_port *vt8500_port = container_of(port,
210 struct vt8500_port,
211 uart);
212
213 vt8500_port->ier &= ~TX_FIFO_INTS;
214 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
215 handle_tx(port);
216 vt8500_port->ier |= TX_FIFO_INTS;
217 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
218}
219
220static void handle_delta_cts(struct uart_port *port)
221{
222 port->icount.cts++;
223 wake_up_interruptible(&port->state->port.delta_msr_wait);
224}
225
226static irqreturn_t vt8500_irq(int irq, void *dev_id)
227{
228 struct uart_port *port = dev_id;
229 unsigned long isr;
230
231 spin_lock(&port->lock);
232 isr = vt8500_read(port, VT8500_URISR);
233
234 /* Acknowledge active status bits */
235 vt8500_write(port, isr, VT8500_URISR);
236
237 if (isr & RX_FIFO_INTS)
238 handle_rx(port);
239 if (isr & TX_FIFO_INTS)
240 handle_tx(port);
241 if (isr & TCTS)
242 handle_delta_cts(port);
243
244 spin_unlock(&port->lock);
245
246 return IRQ_HANDLED;
247}
248
249static unsigned int vt8500_tx_empty(struct uart_port *port)
250{
251 return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
252 TIOCSER_TEMT : 0;
253}
254
255static unsigned int vt8500_get_mctrl(struct uart_port *port)
256{
257 unsigned int usr;
258
259 usr = vt8500_read(port, VT8500_URUSR);
260 if (usr & (1 << 4))
261 return TIOCM_CTS;
262 else
263 return 0;
264}
265
266static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
267{
268}
269
270static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
271{
272 if (break_ctl)
273 vt8500_write(port, vt8500_read(port, VT8500_URLCR) | (1 << 9),
274 VT8500_URLCR);
275}
276
277static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
278{
279 unsigned long div;
280 unsigned int loops = 1000;
281
282 div = vt8500_read(port, VT8500_URDIV) & ~(0x3ff);
283
284 if (unlikely((baud < 900) || (baud > 921600)))
285 div |= 7;
286 else
287 div |= (921600 / baud) - 1;
288
289 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
290 cpu_relax();
291 vt8500_write(port, div, VT8500_URDIV);
292
293 return baud;
294}
295
296static int vt8500_startup(struct uart_port *port)
297{
298 struct vt8500_port *vt8500_port =
299 container_of(port, struct vt8500_port, uart);
300 int ret;
301
302 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
303 "vt8500_serial%d", port->line);
304
305 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
306 vt8500_port->name, port);
307 if (unlikely(ret))
308 return ret;
309
310 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
311
312 return 0;
313}
314
315static void vt8500_shutdown(struct uart_port *port)
316{
317 struct vt8500_port *vt8500_port =
318 container_of(port, struct vt8500_port, uart);
319
320 vt8500_port->ier = 0;
321
322 /* disable interrupts and FIFOs */
323 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
324 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
325 free_irq(port->irq, port);
326}
327
328static void vt8500_set_termios(struct uart_port *port,
329 struct ktermios *termios,
330 struct ktermios *old)
331{
332 struct vt8500_port *vt8500_port =
333 container_of(port, struct vt8500_port, uart);
334 unsigned long flags;
335 unsigned int baud, lcr;
336 unsigned int loops = 1000;
337
338 spin_lock_irqsave(&port->lock, flags);
339
340 /* calculate and set baud rate */
341 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
342 baud = vt8500_set_baud_rate(port, baud);
343 if (tty_termios_baud_rate(termios))
344 tty_termios_encode_baud_rate(termios, baud, baud);
345
346 /* calculate parity */
347 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
348 lcr &= ~((1 << 5) | (1 << 4));
349 if (termios->c_cflag & PARENB) {
350 lcr |= (1 << 4);
351 termios->c_cflag &= ~CMSPAR;
352 if (termios->c_cflag & PARODD)
353 lcr |= (1 << 5);
354 }
355
356 /* calculate bits per char */
357 lcr &= ~(1 << 2);
358 switch (termios->c_cflag & CSIZE) {
359 case CS7:
360 break;
361 case CS8:
362 default:
363 lcr |= (1 << 2);
364 termios->c_cflag &= ~CSIZE;
365 termios->c_cflag |= CS8;
366 break;
367 }
368
369 /* calculate stop bits */
370 lcr &= ~(1 << 3);
371 if (termios->c_cflag & CSTOPB)
372 lcr |= (1 << 3);
373
374 /* set parity, bits per char, and stop bit */
375 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
376
377 /* Configure status bits to ignore based on termio flags. */
378 port->read_status_mask = 0;
379 if (termios->c_iflag & IGNPAR)
380 port->read_status_mask = FER | PER;
381
382 uart_update_timeout(port, termios->c_cflag, baud);
383
384 /* Reset FIFOs */
385 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
386 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
387 && --loops)
388 cpu_relax();
389
390 /* Every possible FIFO-related interrupt */
391 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
392
393 /*
394 * CTS flow control
395 */
396 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
397 vt8500_port->ier |= TCTS;
398
399 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
400 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
401
402 spin_unlock_irqrestore(&port->lock, flags);
403}
404
405static const char *vt8500_type(struct uart_port *port)
406{
407 struct vt8500_port *vt8500_port =
408 container_of(port, struct vt8500_port, uart);
409 return vt8500_port->name;
410}
411
412static void vt8500_release_port(struct uart_port *port)
413{
414}
415
416static int vt8500_request_port(struct uart_port *port)
417{
418 return 0;
419}
420
421static void vt8500_config_port(struct uart_port *port, int flags)
422{
423 port->type = PORT_VT8500;
424}
425
426static int vt8500_verify_port(struct uart_port *port,
427 struct serial_struct *ser)
428{
429 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
430 return -EINVAL;
431 if (unlikely(port->irq != ser->irq))
432 return -EINVAL;
433 return 0;
434}
435
436static struct vt8500_port *vt8500_uart_ports[4];
437static struct uart_driver vt8500_uart_driver;
438
439#ifdef CONFIG_SERIAL_VT8500_CONSOLE
440
441static inline void wait_for_xmitr(struct uart_port *port)
442{
443 unsigned int status, tmout = 10000;
444
445 /* Wait up to 10ms for the character(s) to be sent. */
446 do {
447 status = vt8500_read(port, VT8500_URFIDX);
448
449 if (--tmout == 0)
450 break;
451 udelay(1);
452 } while (status & 0x10);
453}
454
455static void vt8500_console_putchar(struct uart_port *port, int c)
456{
457 wait_for_xmitr(port);
458 writeb(c, port->membase + VT8500_TXFIFO);
459}
460
461static void vt8500_console_write(struct console *co, const char *s,
462 unsigned int count)
463{
464 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
465 unsigned long ier;
466
467 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
468
469 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
470 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
471
472 uart_console_write(&vt8500_port->uart, s, count,
473 vt8500_console_putchar);
474
475 /*
476 * Finally, wait for transmitter to become empty
477 * and switch back to FIFO
478 */
479 wait_for_xmitr(&vt8500_port->uart);
480 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
481}
482
483static int __init vt8500_console_setup(struct console *co, char *options)
484{
485 struct vt8500_port *vt8500_port;
486 int baud = 9600;
487 int bits = 8;
488 int parity = 'n';
489 int flow = 'n';
490
491 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
492 return -ENXIO;
493
494 vt8500_port = vt8500_uart_ports[co->index];
495
496 if (!vt8500_port)
497 return -ENODEV;
498
499 if (options)
500 uart_parse_options(options, &baud, &parity, &bits, &flow);
501
502 return uart_set_options(&vt8500_port->uart,
503 co, baud, parity, bits, flow);
504}
505
506static struct console vt8500_console = {
507 .name = "ttyWMT",
508 .write = vt8500_console_write,
509 .device = uart_console_device,
510 .setup = vt8500_console_setup,
511 .flags = CON_PRINTBUFFER,
512 .index = -1,
513 .data = &vt8500_uart_driver,
514};
515
516#define VT8500_CONSOLE (&vt8500_console)
517
518#else
519#define VT8500_CONSOLE NULL
520#endif
521
522static struct uart_ops vt8500_uart_pops = {
523 .tx_empty = vt8500_tx_empty,
524 .set_mctrl = vt8500_set_mctrl,
525 .get_mctrl = vt8500_get_mctrl,
526 .stop_tx = vt8500_stop_tx,
527 .start_tx = vt8500_start_tx,
528 .stop_rx = vt8500_stop_rx,
529 .enable_ms = vt8500_enable_ms,
530 .break_ctl = vt8500_break_ctl,
531 .startup = vt8500_startup,
532 .shutdown = vt8500_shutdown,
533 .set_termios = vt8500_set_termios,
534 .type = vt8500_type,
535 .release_port = vt8500_release_port,
536 .request_port = vt8500_request_port,
537 .config_port = vt8500_config_port,
538 .verify_port = vt8500_verify_port,
539};
540
541static struct uart_driver vt8500_uart_driver = {
542 .owner = THIS_MODULE,
543 .driver_name = "vt8500_serial",
544 .dev_name = "ttyWMT",
545 .nr = 6,
546 .cons = VT8500_CONSOLE,
547};
548
549static int __init vt8500_serial_probe(struct platform_device *pdev)
550{
551 struct vt8500_port *vt8500_port;
552 struct resource *mmres, *irqres;
553 int ret;
554
555 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
556 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
557 if (!mmres || !irqres)
558 return -ENODEV;
559
560 vt8500_port = kzalloc(sizeof(struct vt8500_port), GFP_KERNEL);
561 if (!vt8500_port)
562 return -ENOMEM;
563
564 vt8500_port->uart.type = PORT_VT8500;
565 vt8500_port->uart.iotype = UPIO_MEM;
566 vt8500_port->uart.mapbase = mmres->start;
567 vt8500_port->uart.irq = irqres->start;
568 vt8500_port->uart.fifosize = 16;
569 vt8500_port->uart.ops = &vt8500_uart_pops;
570 vt8500_port->uart.line = pdev->id;
571 vt8500_port->uart.dev = &pdev->dev;
572 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
573 vt8500_port->uart.uartclk = 24000000;
574
575 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
576 "VT8500 UART%d", pdev->id);
577
578 vt8500_port->uart.membase = ioremap(mmres->start,
579 mmres->end - mmres->start + 1);
580 if (!vt8500_port->uart.membase) {
581 ret = -ENOMEM;
582 goto err;
583 }
584
585 vt8500_uart_ports[pdev->id] = vt8500_port;
586
587 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
588
589 platform_set_drvdata(pdev, vt8500_port);
590
591 return 0;
592
593err:
594 kfree(vt8500_port);
595 return ret;
596}
597
598static int __devexit vt8500_serial_remove(struct platform_device *pdev)
599{
600 struct vt8500_port *vt8500_port = platform_get_drvdata(pdev);
601
602 platform_set_drvdata(pdev, NULL);
603 uart_remove_one_port(&vt8500_uart_driver, &vt8500_port->uart);
604 kfree(vt8500_port);
605
606 return 0;
607}
608
609static struct platform_driver vt8500_platform_driver = {
610 .probe = vt8500_serial_probe,
611 .remove = vt8500_serial_remove,
612 .driver = {
613 .name = "vt8500_serial",
614 .owner = THIS_MODULE,
615 },
616};
617
618static int __init vt8500_serial_init(void)
619{
620 int ret;
621
622 ret = uart_register_driver(&vt8500_uart_driver);
623 if (unlikely(ret))
624 return ret;
625
626 ret = platform_driver_register(&vt8500_platform_driver);
627
628 if (unlikely(ret))
629 uart_unregister_driver(&vt8500_uart_driver);
630
631 return ret;
632}
633
634static void __exit vt8500_serial_exit(void)
635{
636#ifdef CONFIG_SERIAL_VT8500_CONSOLE
637 unregister_console(&vt8500_console);
638#endif
639 platform_driver_unregister(&vt8500_platform_driver);
640 uart_unregister_driver(&vt8500_uart_driver);
641}
642
643module_init(vt8500_serial_init);
644module_exit(vt8500_serial_exit);
645
646MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
647MODULE_DESCRIPTION("Driver for vt8500 serial device");
648MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 02:29:04 -0500