aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/serial
diff options
context:
space:
mode:
authorMarkus Brunner <super.firetwister@gmail.com>2007-08-19 19:59:33 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:49 -0400
commit3ea6bc3de4f15fcae84fb31eeea4d420685a3da2 (patch)
tree2b9e37135052aab926b7be0822d024c4ba71c32e /drivers/serial
parentdfc5ed2a939baf08f9385a8c6249b719cac63665 (diff)
sh: Add SH7720 CPU support.
This adds support for the SH7720 (SH3-DSP) CPU. Signed-off by: Markus Brunner <super.firetwister@gmail.com> Signed-off by: Mark Jonas <toertel@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/sh-sci.c33
-rw-r--r--drivers/serial/sh-sci.h33
2 files changed, 58 insertions, 8 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index e4abd3a79983..81318c580e22 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -4,6 +4,7 @@
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * 5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt 6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * 8 *
8 * based off of the old drivers/char/sh-sci.c by: 9 * based off of the old drivers/char/sh-sci.c by:
9 * 10 *
@@ -301,6 +302,38 @@ static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
301 } 302 }
302 sci_out(port, SCFCR, fcr_val); 303 sci_out(port, SCFCR, fcr_val);
303} 304}
305#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
306static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
307{
308 unsigned int fcr_val = 0;
309 unsigned short data;
310
311 if (cflag & CRTSCTS) {
312 /* enable RTS/CTS */
313 if (port->mapbase == 0xa4430000) { /* SCIF0 */
314 /* Clear PTCR bit 9-2; enable all scif pins but sck */
315 data = ctrl_inw(PORT_PTCR);
316 ctrl_outw((data & 0xfc03), PORT_PTCR);
317 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
318 /* Clear PVCR bit 9-2 */
319 data = ctrl_inw(PORT_PVCR);
320 ctrl_outw((data & 0xfc03), PORT_PVCR);
321 }
322 fcr_val |= SCFCR_MCE;
323 } else {
324 if (port->mapbase == 0xa4430000) { /* SCIF0 */
325 /* Clear PTCR bit 5-2; enable only tx and rx */
326 data = ctrl_inw(PORT_PTCR);
327 ctrl_outw((data & 0xffc3), PORT_PTCR);
328 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
329 /* Clear PVCR bit 5-2 */
330 data = ctrl_inw(PORT_PVCR);
331 ctrl_outw((data & 0xffc3), PORT_PVCR);
332 }
333 }
334 sci_out(port, SCFCR, fcr_val);
335}
336
304#elif defined(CONFIG_CPU_SH3) 337#elif defined(CONFIG_CPU_SH3)
305/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ 338/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
306static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 339static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 941c504fe80d..e89ae29645d6 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -10,19 +10,19 @@
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 * Removed SH7300 support (Jul 2007). 12 * Removed SH7300 support (Jul 2007).
13 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
13 */ 14 */
14#include <linux/serial_core.h> 15#include <linux/serial_core.h>
15#include <asm/io.h> 16#include <asm/io.h>
16 17
17#if defined(__H8300H__) || defined(__H8300S__)
18#include <asm/gpio.h> 18#include <asm/gpio.h>
19
19#if defined(CONFIG_H83007) || defined(CONFIG_H83068) 20#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
20#include <asm/regs306x.h> 21#include <asm/regs306x.h>
21#endif 22#endif
22#if defined(CONFIG_H8S2678) 23#if defined(CONFIG_H8S2678)
23#include <asm/regs267x.h> 24#include <asm/regs267x.h>
24#endif 25#endif
25#endif
26 26
27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
@@ -46,6 +46,10 @@
46 */ 46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY 48# define SCIF_ONLY
49#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
50# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51# define SCIF_ONLY
52#define SCIF_ORER 0x0200 /* overrun error bit */
49#elif defined(CONFIG_SH_RTS7751R2D) 53#elif defined(CONFIG_SH_RTS7751R2D)
50# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 54# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51# define SCIF_ORER 0x0001 /* overrun error bit */ 55# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -217,7 +221,8 @@
217#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 221#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 222#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219 223
220#if defined(CONFIG_CPU_SUBTYPE_SH7705) 224#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
225 defined(CONFIG_CPU_SUBTYPE_SH7720)
221#define SCIF_ORER 0x0200 226#define SCIF_ORER 0x0200
222#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 227#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
223#define SCIF_RFDC_MASK 0x007f 228#define SCIF_RFDC_MASK 0x007f
@@ -254,7 +259,8 @@
254# define SCxSR_FER(port) SCIF_FER 259# define SCxSR_FER(port) SCIF_FER
255# define SCxSR_PER(port) SCIF_PER 260# define SCxSR_PER(port) SCIF_PER
256# define SCxSR_BRK(port) SCIF_BRK 261# define SCxSR_BRK(port) SCIF_BRK
257#if defined(CONFIG_CPU_SUBTYPE_SH7705) 262#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
263 defined(CONFIG_CPU_SUBTYPE_SH7720)
258# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 264# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
259# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 265# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
260# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 266# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
@@ -362,7 +368,8 @@
362 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 368 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 369#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 370 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
365#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 371#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
372 defined(CONFIG_CPU_SUBTYPE_SH7720)
366#define SCIF_FNS(name, scif_offset, scif_size) \ 373#define SCIF_FNS(name, scif_offset, scif_size) \
367 CPU_SCIF_FNS(name, scif_offset, scif_size) 374 CPU_SCIF_FNS(name, scif_offset, scif_size)
368#else 375#else
@@ -388,7 +395,8 @@
388 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 395 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
389#endif 396#endif
390 397
391#if defined(CONFIG_CPU_SUBTYPE_SH7705) 398#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
399 defined(CONFIG_CPU_SUBTYPE_SH7720)
392 400
393SCIF_FNS(SCSMR, 0x00, 16) 401SCIF_FNS(SCSMR, 0x00, 16)
394SCIF_FNS(SCBRR, 0x04, 8) 402SCIF_FNS(SCBRR, 0x04, 8)
@@ -510,7 +518,15 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
510 return; 518 return;
511 } 519 }
512} 520}
513 521#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
522static inline int sci_rxd_in(struct uart_port *port)
523{
524 if (port->mapbase == 0xa4430000)
525 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
526 else if (port->mapbase == 0xa4438000)
527 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
528 return 1;
529}
514#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 530#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
515 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 531 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
516 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 532 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
@@ -692,7 +708,8 @@ static inline int sci_rxd_in(struct uart_port *port)
692#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 708#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
693 defined(CONFIG_CPU_SUBTYPE_SH7785) 709 defined(CONFIG_CPU_SUBTYPE_SH7785)
694#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 710#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
695#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 711#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
712 defined(CONFIG_CPU_SUBTYPE_SH7720)
696#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 713#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
697#elif defined(__H8300H__) || defined(__H8300S__) 714#elif defined(__H8300H__) || defined(__H8300S__)
698#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) 715#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)