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authorPeter Griffin <pgriffin@mpc-data.co.uk>2008-11-28 08:48:20 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-12-22 04:43:50 -0500
commit2825999e8a9bd7ab7e25a7e7475c7cdd10371a13 (patch)
tree2abe611b0ff90a255f6c00f0aacad4c1a2d8cdd5 /drivers/serial
parent135210b378d26f9a9a0c901d0089522c06b5807a (diff)
sh: Add support for SH7201 CPU subtype.
This patch adds support for the SH-2A FPU based SH7201 processor subtype. Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/sh-sci.h22
1 files changed, 20 insertions, 2 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 9f33b064172e..6da755d63529 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -133,13 +133,20 @@
133# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 133# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
134# define SCIF_OPER 0x0001 /* Overrun error bit */ 134# define SCIF_OPER 0x0001 /* Overrun error bit */
135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
136#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 136#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
137 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
137 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 138 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
138 defined(CONFIG_CPU_SUBTYPE_SH7263) 139 defined(CONFIG_CPU_SUBTYPE_SH7263)
139# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 140# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
140# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 141# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
141# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 142# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
142# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 143# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
144# if defined(CONFIG_CPU_SUBTYPE_SH7201)
145# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
146# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
147# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
148# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
149# endif
143# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 150# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
144#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 151#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
145# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 152# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
@@ -664,7 +671,8 @@ static inline int sci_rxd_in(struct uart_port *port)
664 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ 671 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
665 return 1; 672 return 1;
666} 673}
667#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 674#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
675 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
668 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 676 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
669 defined(CONFIG_CPU_SUBTYPE_SH7263) 677 defined(CONFIG_CPU_SUBTYPE_SH7263)
670static inline int sci_rxd_in(struct uart_port *port) 678static inline int sci_rxd_in(struct uart_port *port)
@@ -677,6 +685,16 @@ static inline int sci_rxd_in(struct uart_port *port)
677 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 685 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
678 if (port->mapbase == 0xfffe9800) 686 if (port->mapbase == 0xfffe9800)
679 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 687 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
688#if defined(CONFIG_CPU_SUBTYPE_SH7201)
689 if (port->mapbase == 0xfffeA000)
690 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
691 if (port->mapbase == 0xfffeA800)
692 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
693 if (port->mapbase == 0xfffeB000)
694 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
695 if (port->mapbase == 0xfffeB800)
696 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
697#endif
680 return 1; 698 return 1;
681} 699}
682#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 700#elif defined(CONFIG_CPU_SUBTYPE_SH7619)