diff options
author | Mark A. Greer <mgreer@mvista.com> | 2006-03-25 06:08:28 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-25 11:23:02 -0500 |
commit | e4294b3ecd1da9abeb66709c89f71b1ba888b3b1 (patch) | |
tree | 52c2a6661cebb58b8fab684303cd6b401f1284b5 /drivers/serial | |
parent | 6261c8e34f07f09270b37e14c05962c952cbeebe (diff) |
[PATCH] serial: merge mpsc.h into mpsc.c
Merge mpsc.h into mpsc.c because its the only file that #include's mpsc.h.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/mpsc.c | 258 | ||||
-rw-r--r-- | drivers/serial/mpsc.h | 290 |
2 files changed, 255 insertions, 293 deletions
diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c index ba30e2363cc0..94681922ea0a 100644 --- a/drivers/serial/mpsc.c +++ b/drivers/serial/mpsc.c | |||
@@ -1,6 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * drivers/serial/mpsc.c | ||
3 | * | ||
4 | * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, | 2 | * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, |
5 | * GT64260, MV64340, MV64360, GT96100, ... ). | 3 | * GT64260, MV64340, MV64360, GT96100, ... ). |
6 | * | 4 | * |
@@ -52,9 +50,263 @@ | |||
52 | * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. | 50 | * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. |
53 | */ | 51 | */ |
54 | 52 | ||
53 | #include <linux/config.h> | ||
54 | |||
55 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
56 | #define SUPPORT_SYSRQ | ||
57 | #endif | ||
58 | |||
59 | #include <linux/module.h> | ||
60 | #include <linux/moduleparam.h> | ||
61 | #include <linux/tty.h> | ||
62 | #include <linux/tty_flip.h> | ||
63 | #include <linux/ioport.h> | ||
64 | #include <linux/init.h> | ||
65 | #include <linux/console.h> | ||
66 | #include <linux/sysrq.h> | ||
67 | #include <linux/serial.h> | ||
68 | #include <linux/serial_core.h> | ||
69 | #include <linux/delay.h> | ||
70 | #include <linux/device.h> | ||
71 | #include <linux/dma-mapping.h> | ||
72 | #include <linux/mv643xx.h> | ||
55 | #include <linux/platform_device.h> | 73 | #include <linux/platform_device.h> |
56 | 74 | ||
57 | #include "mpsc.h" | 75 | #include <asm/io.h> |
76 | #include <asm/irq.h> | ||
77 | |||
78 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
79 | #define SUPPORT_SYSRQ | ||
80 | #endif | ||
81 | |||
82 | #define MPSC_NUM_CTLRS 2 | ||
83 | |||
84 | /* | ||
85 | * Descriptors and buffers must be cache line aligned. | ||
86 | * Buffers lengths must be multiple of cache line size. | ||
87 | * Number of Tx & Rx descriptors must be powers of 2. | ||
88 | */ | ||
89 | #define MPSC_RXR_ENTRIES 32 | ||
90 | #define MPSC_RXRE_SIZE dma_get_cache_alignment() | ||
91 | #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE) | ||
92 | #define MPSC_RXBE_SIZE dma_get_cache_alignment() | ||
93 | #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE) | ||
94 | |||
95 | #define MPSC_TXR_ENTRIES 32 | ||
96 | #define MPSC_TXRE_SIZE dma_get_cache_alignment() | ||
97 | #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE) | ||
98 | #define MPSC_TXBE_SIZE dma_get_cache_alignment() | ||
99 | #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE) | ||
100 | |||
101 | #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \ | ||
102 | MPSC_TXR_SIZE + MPSC_TXB_SIZE + \ | ||
103 | dma_get_cache_alignment() /* for alignment */) | ||
104 | |||
105 | /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */ | ||
106 | struct mpsc_rx_desc { | ||
107 | u16 bufsize; | ||
108 | u16 bytecnt; | ||
109 | u32 cmdstat; | ||
110 | u32 link; | ||
111 | u32 buf_ptr; | ||
112 | } __attribute((packed)); | ||
113 | |||
114 | struct mpsc_tx_desc { | ||
115 | u16 bytecnt; | ||
116 | u16 shadow; | ||
117 | u32 cmdstat; | ||
118 | u32 link; | ||
119 | u32 buf_ptr; | ||
120 | } __attribute((packed)); | ||
121 | |||
122 | /* | ||
123 | * Some regs that have the erratum that you can't read them are are shared | ||
124 | * between the two MPSC controllers. This struct contains those shared regs. | ||
125 | */ | ||
126 | struct mpsc_shared_regs { | ||
127 | phys_addr_t mpsc_routing_base_p; | ||
128 | phys_addr_t sdma_intr_base_p; | ||
129 | |||
130 | void __iomem *mpsc_routing_base; | ||
131 | void __iomem *sdma_intr_base; | ||
132 | |||
133 | u32 MPSC_MRR_m; | ||
134 | u32 MPSC_RCRR_m; | ||
135 | u32 MPSC_TCRR_m; | ||
136 | u32 SDMA_INTR_CAUSE_m; | ||
137 | u32 SDMA_INTR_MASK_m; | ||
138 | }; | ||
139 | |||
140 | /* The main driver data structure */ | ||
141 | struct mpsc_port_info { | ||
142 | struct uart_port port; /* Overlay uart_port structure */ | ||
143 | |||
144 | /* Internal driver state for this ctlr */ | ||
145 | u8 ready; | ||
146 | u8 rcv_data; | ||
147 | tcflag_t c_iflag; /* save termios->c_iflag */ | ||
148 | tcflag_t c_cflag; /* save termios->c_cflag */ | ||
149 | |||
150 | /* Info passed in from platform */ | ||
151 | u8 mirror_regs; /* Need to mirror regs? */ | ||
152 | u8 cache_mgmt; /* Need manual cache mgmt? */ | ||
153 | u8 brg_can_tune; /* BRG has baud tuning? */ | ||
154 | u32 brg_clk_src; | ||
155 | u16 mpsc_max_idle; | ||
156 | int default_baud; | ||
157 | int default_bits; | ||
158 | int default_parity; | ||
159 | int default_flow; | ||
160 | |||
161 | /* Physical addresses of various blocks of registers (from platform) */ | ||
162 | phys_addr_t mpsc_base_p; | ||
163 | phys_addr_t sdma_base_p; | ||
164 | phys_addr_t brg_base_p; | ||
165 | |||
166 | /* Virtual addresses of various blocks of registers (from platform) */ | ||
167 | void __iomem *mpsc_base; | ||
168 | void __iomem *sdma_base; | ||
169 | void __iomem *brg_base; | ||
170 | |||
171 | /* Descriptor ring and buffer allocations */ | ||
172 | void *dma_region; | ||
173 | dma_addr_t dma_region_p; | ||
174 | |||
175 | dma_addr_t rxr; /* Rx descriptor ring */ | ||
176 | dma_addr_t rxr_p; /* Phys addr of rxr */ | ||
177 | u8 *rxb; /* Rx Ring I/O buf */ | ||
178 | u8 *rxb_p; /* Phys addr of rxb */ | ||
179 | u32 rxr_posn; /* First desc w/ Rx data */ | ||
180 | |||
181 | dma_addr_t txr; /* Tx descriptor ring */ | ||
182 | dma_addr_t txr_p; /* Phys addr of txr */ | ||
183 | u8 *txb; /* Tx Ring I/O buf */ | ||
184 | u8 *txb_p; /* Phys addr of txb */ | ||
185 | int txr_head; /* Where new data goes */ | ||
186 | int txr_tail; /* Where sent data comes off */ | ||
187 | |||
188 | /* Mirrored values of regs we can't read (if 'mirror_regs' set) */ | ||
189 | u32 MPSC_MPCR_m; | ||
190 | u32 MPSC_CHR_1_m; | ||
191 | u32 MPSC_CHR_2_m; | ||
192 | u32 MPSC_CHR_10_m; | ||
193 | u32 BRG_BCR_m; | ||
194 | struct mpsc_shared_regs *shared_regs; | ||
195 | }; | ||
196 | |||
197 | /* Hooks to platform-specific code */ | ||
198 | int mpsc_platform_register_driver(void); | ||
199 | void mpsc_platform_unregister_driver(void); | ||
200 | |||
201 | /* Hooks back in to mpsc common to be called by platform-specific code */ | ||
202 | struct mpsc_port_info *mpsc_device_probe(int index); | ||
203 | struct mpsc_port_info *mpsc_device_remove(int index); | ||
204 | |||
205 | /* Main MPSC Configuration Register Offsets */ | ||
206 | #define MPSC_MMCRL 0x0000 | ||
207 | #define MPSC_MMCRH 0x0004 | ||
208 | #define MPSC_MPCR 0x0008 | ||
209 | #define MPSC_CHR_1 0x000c | ||
210 | #define MPSC_CHR_2 0x0010 | ||
211 | #define MPSC_CHR_3 0x0014 | ||
212 | #define MPSC_CHR_4 0x0018 | ||
213 | #define MPSC_CHR_5 0x001c | ||
214 | #define MPSC_CHR_6 0x0020 | ||
215 | #define MPSC_CHR_7 0x0024 | ||
216 | #define MPSC_CHR_8 0x0028 | ||
217 | #define MPSC_CHR_9 0x002c | ||
218 | #define MPSC_CHR_10 0x0030 | ||
219 | #define MPSC_CHR_11 0x0034 | ||
220 | |||
221 | #define MPSC_MPCR_FRZ (1 << 9) | ||
222 | #define MPSC_MPCR_CL_5 0 | ||
223 | #define MPSC_MPCR_CL_6 1 | ||
224 | #define MPSC_MPCR_CL_7 2 | ||
225 | #define MPSC_MPCR_CL_8 3 | ||
226 | #define MPSC_MPCR_SBL_1 0 | ||
227 | #define MPSC_MPCR_SBL_2 1 | ||
228 | |||
229 | #define MPSC_CHR_2_TEV (1<<1) | ||
230 | #define MPSC_CHR_2_TA (1<<7) | ||
231 | #define MPSC_CHR_2_TTCS (1<<9) | ||
232 | #define MPSC_CHR_2_REV (1<<17) | ||
233 | #define MPSC_CHR_2_RA (1<<23) | ||
234 | #define MPSC_CHR_2_CRD (1<<25) | ||
235 | #define MPSC_CHR_2_EH (1<<31) | ||
236 | #define MPSC_CHR_2_PAR_ODD 0 | ||
237 | #define MPSC_CHR_2_PAR_SPACE 1 | ||
238 | #define MPSC_CHR_2_PAR_EVEN 2 | ||
239 | #define MPSC_CHR_2_PAR_MARK 3 | ||
240 | |||
241 | /* MPSC Signal Routing */ | ||
242 | #define MPSC_MRR 0x0000 | ||
243 | #define MPSC_RCRR 0x0004 | ||
244 | #define MPSC_TCRR 0x0008 | ||
245 | |||
246 | /* Serial DMA Controller Interface Registers */ | ||
247 | #define SDMA_SDC 0x0000 | ||
248 | #define SDMA_SDCM 0x0008 | ||
249 | #define SDMA_RX_DESC 0x0800 | ||
250 | #define SDMA_RX_BUF_PTR 0x0808 | ||
251 | #define SDMA_SCRDP 0x0810 | ||
252 | #define SDMA_TX_DESC 0x0c00 | ||
253 | #define SDMA_SCTDP 0x0c10 | ||
254 | #define SDMA_SFTDP 0x0c14 | ||
255 | |||
256 | #define SDMA_DESC_CMDSTAT_PE (1<<0) | ||
257 | #define SDMA_DESC_CMDSTAT_CDL (1<<1) | ||
258 | #define SDMA_DESC_CMDSTAT_FR (1<<3) | ||
259 | #define SDMA_DESC_CMDSTAT_OR (1<<6) | ||
260 | #define SDMA_DESC_CMDSTAT_BR (1<<9) | ||
261 | #define SDMA_DESC_CMDSTAT_MI (1<<10) | ||
262 | #define SDMA_DESC_CMDSTAT_A (1<<11) | ||
263 | #define SDMA_DESC_CMDSTAT_AM (1<<12) | ||
264 | #define SDMA_DESC_CMDSTAT_CT (1<<13) | ||
265 | #define SDMA_DESC_CMDSTAT_C (1<<14) | ||
266 | #define SDMA_DESC_CMDSTAT_ES (1<<15) | ||
267 | #define SDMA_DESC_CMDSTAT_L (1<<16) | ||
268 | #define SDMA_DESC_CMDSTAT_F (1<<17) | ||
269 | #define SDMA_DESC_CMDSTAT_P (1<<18) | ||
270 | #define SDMA_DESC_CMDSTAT_EI (1<<23) | ||
271 | #define SDMA_DESC_CMDSTAT_O (1<<31) | ||
272 | |||
273 | #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \ | ||
274 | SDMA_DESC_CMDSTAT_EI) | ||
275 | |||
276 | #define SDMA_SDC_RFT (1<<0) | ||
277 | #define SDMA_SDC_SFM (1<<1) | ||
278 | #define SDMA_SDC_BLMR (1<<6) | ||
279 | #define SDMA_SDC_BLMT (1<<7) | ||
280 | #define SDMA_SDC_POVR (1<<8) | ||
281 | #define SDMA_SDC_RIFB (1<<9) | ||
282 | |||
283 | #define SDMA_SDCM_ERD (1<<7) | ||
284 | #define SDMA_SDCM_AR (1<<15) | ||
285 | #define SDMA_SDCM_STD (1<<16) | ||
286 | #define SDMA_SDCM_TXD (1<<23) | ||
287 | #define SDMA_SDCM_AT (1<<31) | ||
288 | |||
289 | #define SDMA_0_CAUSE_RXBUF (1<<0) | ||
290 | #define SDMA_0_CAUSE_RXERR (1<<1) | ||
291 | #define SDMA_0_CAUSE_TXBUF (1<<2) | ||
292 | #define SDMA_0_CAUSE_TXEND (1<<3) | ||
293 | #define SDMA_1_CAUSE_RXBUF (1<<8) | ||
294 | #define SDMA_1_CAUSE_RXERR (1<<9) | ||
295 | #define SDMA_1_CAUSE_TXBUF (1<<10) | ||
296 | #define SDMA_1_CAUSE_TXEND (1<<11) | ||
297 | |||
298 | #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \ | ||
299 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) | ||
300 | #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \ | ||
301 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) | ||
302 | |||
303 | /* SDMA Interrupt registers */ | ||
304 | #define SDMA_INTR_CAUSE 0x0000 | ||
305 | #define SDMA_INTR_MASK 0x0080 | ||
306 | |||
307 | /* Baud Rate Generator Interface Registers */ | ||
308 | #define BRG_BCR 0x0000 | ||
309 | #define BRG_BTR 0x0004 | ||
58 | 310 | ||
59 | /* | 311 | /* |
60 | * Define how this driver is known to the outside (we've been assigned a | 312 | * Define how this driver is known to the outside (we've been assigned a |
diff --git a/drivers/serial/mpsc.h b/drivers/serial/mpsc.h deleted file mode 100644 index 15913300cea7..000000000000 --- a/drivers/serial/mpsc.h +++ /dev/null | |||
@@ -1,290 +0,0 @@ | |||
1 | /* | ||
2 | * drivers/serial/mpsc.h | ||
3 | * | ||
4 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
5 | * | ||
6 | * 2004 (c) MontaVista, Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __MPSC_H__ | ||
13 | #define __MPSC_H__ | ||
14 | |||
15 | #include <linux/config.h> | ||
16 | |||
17 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
18 | #define SUPPORT_SYSRQ | ||
19 | #endif | ||
20 | |||
21 | #include <linux/module.h> | ||
22 | #include <linux/moduleparam.h> | ||
23 | #include <linux/tty.h> | ||
24 | #include <linux/tty_flip.h> | ||
25 | #include <linux/ioport.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/console.h> | ||
28 | #include <linux/sysrq.h> | ||
29 | #include <linux/serial.h> | ||
30 | #include <linux/serial_core.h> | ||
31 | #include <linux/delay.h> | ||
32 | #include <linux/device.h> | ||
33 | #include <linux/dma-mapping.h> | ||
34 | #include <linux/mv643xx.h> | ||
35 | |||
36 | #include <asm/io.h> | ||
37 | #include <asm/irq.h> | ||
38 | |||
39 | #define MPSC_NUM_CTLRS 2 | ||
40 | |||
41 | /* | ||
42 | * Descriptors and buffers must be cache line aligned. | ||
43 | * Buffers lengths must be multiple of cache line size. | ||
44 | * Number of Tx & Rx descriptors must be powers of 2. | ||
45 | */ | ||
46 | #define MPSC_RXR_ENTRIES 32 | ||
47 | #define MPSC_RXRE_SIZE dma_get_cache_alignment() | ||
48 | #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE) | ||
49 | #define MPSC_RXBE_SIZE dma_get_cache_alignment() | ||
50 | #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE) | ||
51 | |||
52 | #define MPSC_TXR_ENTRIES 32 | ||
53 | #define MPSC_TXRE_SIZE dma_get_cache_alignment() | ||
54 | #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE) | ||
55 | #define MPSC_TXBE_SIZE dma_get_cache_alignment() | ||
56 | #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE) | ||
57 | |||
58 | #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \ | ||
59 | MPSC_TXR_SIZE + MPSC_TXB_SIZE + \ | ||
60 | dma_get_cache_alignment() /* for alignment */) | ||
61 | |||
62 | /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */ | ||
63 | struct mpsc_rx_desc { | ||
64 | u16 bufsize; | ||
65 | u16 bytecnt; | ||
66 | u32 cmdstat; | ||
67 | u32 link; | ||
68 | u32 buf_ptr; | ||
69 | } __attribute((packed)); | ||
70 | |||
71 | struct mpsc_tx_desc { | ||
72 | u16 bytecnt; | ||
73 | u16 shadow; | ||
74 | u32 cmdstat; | ||
75 | u32 link; | ||
76 | u32 buf_ptr; | ||
77 | } __attribute((packed)); | ||
78 | |||
79 | /* | ||
80 | * Some regs that have the erratum that you can't read them are are shared | ||
81 | * between the two MPSC controllers. This struct contains those shared regs. | ||
82 | */ | ||
83 | struct mpsc_shared_regs { | ||
84 | phys_addr_t mpsc_routing_base_p; | ||
85 | phys_addr_t sdma_intr_base_p; | ||
86 | |||
87 | void __iomem *mpsc_routing_base; | ||
88 | void __iomem *sdma_intr_base; | ||
89 | |||
90 | u32 MPSC_MRR_m; | ||
91 | u32 MPSC_RCRR_m; | ||
92 | u32 MPSC_TCRR_m; | ||
93 | u32 SDMA_INTR_CAUSE_m; | ||
94 | u32 SDMA_INTR_MASK_m; | ||
95 | }; | ||
96 | |||
97 | /* The main driver data structure */ | ||
98 | struct mpsc_port_info { | ||
99 | struct uart_port port; /* Overlay uart_port structure */ | ||
100 | |||
101 | /* Internal driver state for this ctlr */ | ||
102 | u8 ready; | ||
103 | u8 rcv_data; | ||
104 | tcflag_t c_iflag; /* save termios->c_iflag */ | ||
105 | tcflag_t c_cflag; /* save termios->c_cflag */ | ||
106 | |||
107 | /* Info passed in from platform */ | ||
108 | u8 mirror_regs; /* Need to mirror regs? */ | ||
109 | u8 cache_mgmt; /* Need manual cache mgmt? */ | ||
110 | u8 brg_can_tune; /* BRG has baud tuning? */ | ||
111 | u32 brg_clk_src; | ||
112 | u16 mpsc_max_idle; | ||
113 | int default_baud; | ||
114 | int default_bits; | ||
115 | int default_parity; | ||
116 | int default_flow; | ||
117 | |||
118 | /* Physical addresses of various blocks of registers (from platform) */ | ||
119 | phys_addr_t mpsc_base_p; | ||
120 | phys_addr_t sdma_base_p; | ||
121 | phys_addr_t brg_base_p; | ||
122 | |||
123 | /* Virtual addresses of various blocks of registers (from platform) */ | ||
124 | void __iomem *mpsc_base; | ||
125 | void __iomem *sdma_base; | ||
126 | void __iomem *brg_base; | ||
127 | |||
128 | /* Descriptor ring and buffer allocations */ | ||
129 | void *dma_region; | ||
130 | dma_addr_t dma_region_p; | ||
131 | |||
132 | dma_addr_t rxr; /* Rx descriptor ring */ | ||
133 | dma_addr_t rxr_p; /* Phys addr of rxr */ | ||
134 | u8 *rxb; /* Rx Ring I/O buf */ | ||
135 | u8 *rxb_p; /* Phys addr of rxb */ | ||
136 | u32 rxr_posn; /* First desc w/ Rx data */ | ||
137 | |||
138 | dma_addr_t txr; /* Tx descriptor ring */ | ||
139 | dma_addr_t txr_p; /* Phys addr of txr */ | ||
140 | u8 *txb; /* Tx Ring I/O buf */ | ||
141 | u8 *txb_p; /* Phys addr of txb */ | ||
142 | int txr_head; /* Where new data goes */ | ||
143 | int txr_tail; /* Where sent data comes off */ | ||
144 | |||
145 | /* Mirrored values of regs we can't read (if 'mirror_regs' set) */ | ||
146 | u32 MPSC_MPCR_m; | ||
147 | u32 MPSC_CHR_1_m; | ||
148 | u32 MPSC_CHR_2_m; | ||
149 | u32 MPSC_CHR_10_m; | ||
150 | u32 BRG_BCR_m; | ||
151 | struct mpsc_shared_regs *shared_regs; | ||
152 | }; | ||
153 | |||
154 | /* Hooks to platform-specific code */ | ||
155 | int mpsc_platform_register_driver(void); | ||
156 | void mpsc_platform_unregister_driver(void); | ||
157 | |||
158 | /* Hooks back in to mpsc common to be called by platform-specific code */ | ||
159 | struct mpsc_port_info *mpsc_device_probe(int index); | ||
160 | struct mpsc_port_info *mpsc_device_remove(int index); | ||
161 | |||
162 | /* | ||
163 | ***************************************************************************** | ||
164 | * | ||
165 | * Multi-Protocol Serial Controller Interface Registers | ||
166 | * | ||
167 | ***************************************************************************** | ||
168 | */ | ||
169 | |||
170 | /* Main Configuratino Register Offsets */ | ||
171 | #define MPSC_MMCRL 0x0000 | ||
172 | #define MPSC_MMCRH 0x0004 | ||
173 | #define MPSC_MPCR 0x0008 | ||
174 | #define MPSC_CHR_1 0x000c | ||
175 | #define MPSC_CHR_2 0x0010 | ||
176 | #define MPSC_CHR_3 0x0014 | ||
177 | #define MPSC_CHR_4 0x0018 | ||
178 | #define MPSC_CHR_5 0x001c | ||
179 | #define MPSC_CHR_6 0x0020 | ||
180 | #define MPSC_CHR_7 0x0024 | ||
181 | #define MPSC_CHR_8 0x0028 | ||
182 | #define MPSC_CHR_9 0x002c | ||
183 | #define MPSC_CHR_10 0x0030 | ||
184 | #define MPSC_CHR_11 0x0034 | ||
185 | |||
186 | #define MPSC_MPCR_FRZ (1 << 9) | ||
187 | #define MPSC_MPCR_CL_5 0 | ||
188 | #define MPSC_MPCR_CL_6 1 | ||
189 | #define MPSC_MPCR_CL_7 2 | ||
190 | #define MPSC_MPCR_CL_8 3 | ||
191 | #define MPSC_MPCR_SBL_1 0 | ||
192 | #define MPSC_MPCR_SBL_2 1 | ||
193 | |||
194 | #define MPSC_CHR_2_TEV (1<<1) | ||
195 | #define MPSC_CHR_2_TA (1<<7) | ||
196 | #define MPSC_CHR_2_TTCS (1<<9) | ||
197 | #define MPSC_CHR_2_REV (1<<17) | ||
198 | #define MPSC_CHR_2_RA (1<<23) | ||
199 | #define MPSC_CHR_2_CRD (1<<25) | ||
200 | #define MPSC_CHR_2_EH (1<<31) | ||
201 | #define MPSC_CHR_2_PAR_ODD 0 | ||
202 | #define MPSC_CHR_2_PAR_SPACE 1 | ||
203 | #define MPSC_CHR_2_PAR_EVEN 2 | ||
204 | #define MPSC_CHR_2_PAR_MARK 3 | ||
205 | |||
206 | /* MPSC Signal Routing */ | ||
207 | #define MPSC_MRR 0x0000 | ||
208 | #define MPSC_RCRR 0x0004 | ||
209 | #define MPSC_TCRR 0x0008 | ||
210 | |||
211 | /* | ||
212 | ***************************************************************************** | ||
213 | * | ||
214 | * Serial DMA Controller Interface Registers | ||
215 | * | ||
216 | ***************************************************************************** | ||
217 | */ | ||
218 | |||
219 | #define SDMA_SDC 0x0000 | ||
220 | #define SDMA_SDCM 0x0008 | ||
221 | #define SDMA_RX_DESC 0x0800 | ||
222 | #define SDMA_RX_BUF_PTR 0x0808 | ||
223 | #define SDMA_SCRDP 0x0810 | ||
224 | #define SDMA_TX_DESC 0x0c00 | ||
225 | #define SDMA_SCTDP 0x0c10 | ||
226 | #define SDMA_SFTDP 0x0c14 | ||
227 | |||
228 | #define SDMA_DESC_CMDSTAT_PE (1<<0) | ||
229 | #define SDMA_DESC_CMDSTAT_CDL (1<<1) | ||
230 | #define SDMA_DESC_CMDSTAT_FR (1<<3) | ||
231 | #define SDMA_DESC_CMDSTAT_OR (1<<6) | ||
232 | #define SDMA_DESC_CMDSTAT_BR (1<<9) | ||
233 | #define SDMA_DESC_CMDSTAT_MI (1<<10) | ||
234 | #define SDMA_DESC_CMDSTAT_A (1<<11) | ||
235 | #define SDMA_DESC_CMDSTAT_AM (1<<12) | ||
236 | #define SDMA_DESC_CMDSTAT_CT (1<<13) | ||
237 | #define SDMA_DESC_CMDSTAT_C (1<<14) | ||
238 | #define SDMA_DESC_CMDSTAT_ES (1<<15) | ||
239 | #define SDMA_DESC_CMDSTAT_L (1<<16) | ||
240 | #define SDMA_DESC_CMDSTAT_F (1<<17) | ||
241 | #define SDMA_DESC_CMDSTAT_P (1<<18) | ||
242 | #define SDMA_DESC_CMDSTAT_EI (1<<23) | ||
243 | #define SDMA_DESC_CMDSTAT_O (1<<31) | ||
244 | |||
245 | #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \ | ||
246 | SDMA_DESC_CMDSTAT_EI) | ||
247 | |||
248 | #define SDMA_SDC_RFT (1<<0) | ||
249 | #define SDMA_SDC_SFM (1<<1) | ||
250 | #define SDMA_SDC_BLMR (1<<6) | ||
251 | #define SDMA_SDC_BLMT (1<<7) | ||
252 | #define SDMA_SDC_POVR (1<<8) | ||
253 | #define SDMA_SDC_RIFB (1<<9) | ||
254 | |||
255 | #define SDMA_SDCM_ERD (1<<7) | ||
256 | #define SDMA_SDCM_AR (1<<15) | ||
257 | #define SDMA_SDCM_STD (1<<16) | ||
258 | #define SDMA_SDCM_TXD (1<<23) | ||
259 | #define SDMA_SDCM_AT (1<<31) | ||
260 | |||
261 | #define SDMA_0_CAUSE_RXBUF (1<<0) | ||
262 | #define SDMA_0_CAUSE_RXERR (1<<1) | ||
263 | #define SDMA_0_CAUSE_TXBUF (1<<2) | ||
264 | #define SDMA_0_CAUSE_TXEND (1<<3) | ||
265 | #define SDMA_1_CAUSE_RXBUF (1<<8) | ||
266 | #define SDMA_1_CAUSE_RXERR (1<<9) | ||
267 | #define SDMA_1_CAUSE_TXBUF (1<<10) | ||
268 | #define SDMA_1_CAUSE_TXEND (1<<11) | ||
269 | |||
270 | #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \ | ||
271 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) | ||
272 | #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \ | ||
273 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) | ||
274 | |||
275 | /* SDMA Interrupt registers */ | ||
276 | #define SDMA_INTR_CAUSE 0x0000 | ||
277 | #define SDMA_INTR_MASK 0x0080 | ||
278 | |||
279 | /* | ||
280 | ***************************************************************************** | ||
281 | * | ||
282 | * Baud Rate Generator Interface Registers | ||
283 | * | ||
284 | ***************************************************************************** | ||
285 | */ | ||
286 | |||
287 | #define BRG_BCR 0x0000 | ||
288 | #define BRG_BTR 0x0004 | ||
289 | |||
290 | #endif /* __MPSC_H__ */ | ||