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author | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 18:40:39 -0500 |
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committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 18:40:39 -0500 |
commit | ea14fad0d416354a4e9bb1a04f32acba706f9548 (patch) | |
tree | 2c8acc5331f189aef1d40ddce3f40d6be9314e77 /drivers/serial | |
parent | 6ee7e78e7c78d871409ad4df30551c9355be7d0e (diff) | |
parent | 6705cda24fad1cb0ac82ac4f312df8ec735b39b0 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits)
[ARM] 4002/1: S3C24XX: leave parent IRQs unmasked
[ARM] 4001/1: S3C24XX: shorten reboot time
[ARM] 3983/2: remove unused argument to __bug()
[ARM] 4000/1: Osiris: add third serial port in
[ARM] 3999/1: RX3715: suspend to RAM support
[ARM] 3998/1: VR1000: LED platform devices
[ARM] 3995/1: iop13xx: add iop13xx support
[ARM] 3968/1: iop13xx: add iop13xx_defconfig
[ARM] Update mach-types
[ARM] Allow gcc to optimise arm_add_memory a little more
[ARM] 3991/1: i.MX/MX1 high resolution time source
[ARM] 3990/1: i.MX/MX1 more precise PLL decode
[ARM] 3986/1: H1940: suspend to RAM support
[ARM] 3985/1: ixp4xx clocksource cleanup
[ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)
[ARM] 3994/1: ixp23xx: fix handling of pci master aborts
[ARM] 3981/1: sched_clock for PXA2xx
[ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
[ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period
[ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter
...
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/atmel_serial.c | 10 | ||||
-rw-r--r-- | drivers/serial/atmel_serial.h | 11 |
2 files changed, 11 insertions, 10 deletions
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c index 391a1f4167a4..9217ee6c7865 100644 --- a/drivers/serial/atmel_serial.c +++ b/drivers/serial/atmel_serial.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/char/at91_serial.c | 2 | * linux/drivers/char/atmel_serial.c |
3 | * | 3 | * |
4 | * Driver for Atmel AT91 / AT32 Serial ports | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
5 | * Copyright (C) 2003 Rick Bronson | 5 | * Copyright (C) 2003 Rick Bronson |
@@ -36,11 +36,11 @@ | |||
36 | 36 | ||
37 | #include <asm/io.h> | 37 | #include <asm/io.h> |
38 | 38 | ||
39 | #include <asm/arch/at91rm9200_pdc.h> | ||
40 | #include <asm/mach/serial_at91.h> | 39 | #include <asm/mach/serial_at91.h> |
41 | #include <asm/arch/board.h> | 40 | #include <asm/arch/board.h> |
41 | #include <asm/arch/at91_pdc.h> | ||
42 | #ifdef CONFIG_ARM | 42 | #ifdef CONFIG_ARM |
43 | #include <asm/arch/system.h> | 43 | #include <asm/arch/cpu.h> |
44 | #include <asm/arch/gpio.h> | 44 | #include <asm/arch/gpio.h> |
45 | #endif | 45 | #endif |
46 | 46 | ||
@@ -137,8 +137,8 @@ static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) | |||
137 | unsigned int control = 0; | 137 | unsigned int control = 0; |
138 | unsigned int mode; | 138 | unsigned int mode; |
139 | 139 | ||
140 | #ifdef CONFIG_ARM | 140 | #ifdef CONFIG_ARCH_AT91RM9200 |
141 | if (arch_identify() == ARCH_ID_AT91RM9200) { | 141 | if (cpu_is_at91rm9200()) { |
142 | /* | 142 | /* |
143 | * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. | 143 | * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. |
144 | * We need to drive the pin manually. | 144 | * We need to drive the pin manually. |
diff --git a/drivers/serial/atmel_serial.h b/drivers/serial/atmel_serial.h index eced2ad1a8d9..fe1763b2a6d5 100644 --- a/drivers/serial/atmel_serial.h +++ b/drivers/serial/atmel_serial.h | |||
@@ -31,8 +31,8 @@ | |||
31 | #define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */ | 31 | #define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */ |
32 | #define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ | 32 | #define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ |
33 | #define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */ | 33 | #define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */ |
34 | #define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable */ | 34 | #define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ |
35 | #define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable */ | 35 | #define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ |
36 | #define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */ | 36 | #define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */ |
37 | #define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */ | 37 | #define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */ |
38 | 38 | ||
@@ -92,9 +92,9 @@ | |||
92 | #define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ | 92 | #define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ |
93 | #define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ | 93 | #define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ |
94 | #define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ | 94 | #define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ |
95 | #define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change */ | 95 | #define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ |
96 | #define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change */ | 96 | #define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ |
97 | #define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change */ | 97 | #define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ |
98 | #define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ | 98 | #define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ |
99 | #define ATMEL_US_RI (1 << 20) /* RI */ | 99 | #define ATMEL_US_RI (1 << 20) /* RI */ |
100 | #define ATMEL_US_DSR (1 << 21) /* DSR */ | 100 | #define ATMEL_US_DSR (1 << 21) /* DSR */ |
@@ -106,6 +106,7 @@ | |||
106 | #define ATMEL_US_CSR 0x14 /* Channel Status Register */ | 106 | #define ATMEL_US_CSR 0x14 /* Channel Status Register */ |
107 | #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ | 107 | #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ |
108 | #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ | 108 | #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ |
109 | #define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [SAM9 only] */ | ||
109 | 110 | ||
110 | #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ | 111 | #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ |
111 | #define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ | 112 | #define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ |