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authorMark A. Greer <mgreer@mvista.com>2007-07-31 03:39:01 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-31 18:39:41 -0400
commit2e89db75aee14f3f195836560e0973c9ff215f94 (patch)
tree167fff4fdb9c35068311897c50c0b3d460cf8c2c /drivers/serial
parent79f851733c71c5b2665d2b3ee857b9721846cd74 (diff)
serial: MPSC: Fix coding style and whitespace issues
Fix up mpsc.c to be aligned with Documentation/CodingStyle. Also fix up some whitespace issues. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/mpsc.c684
1 files changed, 283 insertions, 401 deletions
diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
index d948e8340d12..4d643c926657 100644
--- a/drivers/serial/mpsc.c
+++ b/drivers/serial/mpsc.c
@@ -93,9 +93,8 @@
93#define MPSC_TXBE_SIZE dma_get_cache_alignment() 93#define MPSC_TXBE_SIZE dma_get_cache_alignment()
94#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE) 94#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
95 95
96#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \ 96#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
97 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \ 97 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
98 dma_get_cache_alignment() /* for alignment */)
99 98
100/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */ 99/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
101struct mpsc_rx_desc { 100struct mpsc_rx_desc {
@@ -266,8 +265,8 @@ struct mpsc_port_info *mpsc_device_remove(int index);
266#define SDMA_DESC_CMDSTAT_EI (1<<23) 265#define SDMA_DESC_CMDSTAT_EI (1<<23)
267#define SDMA_DESC_CMDSTAT_O (1<<31) 266#define SDMA_DESC_CMDSTAT_O (1<<31)
268 267
269#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \ 268#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
270 SDMA_DESC_CMDSTAT_EI) 269 | SDMA_DESC_CMDSTAT_EI)
271 270
272#define SDMA_SDC_RFT (1<<0) 271#define SDMA_SDC_RFT (1<<0)
273#define SDMA_SDC_SFM (1<<1) 272#define SDMA_SDC_SFM (1<<1)
@@ -291,10 +290,10 @@ struct mpsc_port_info *mpsc_device_remove(int index);
291#define SDMA_1_CAUSE_TXBUF (1<<10) 290#define SDMA_1_CAUSE_TXBUF (1<<10)
292#define SDMA_1_CAUSE_TXEND (1<<11) 291#define SDMA_1_CAUSE_TXEND (1<<11)
293 292
294#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \ 293#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
295 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) 294 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
296#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \ 295#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
297 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) 296 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
298 297
299/* SDMA Interrupt registers */ 298/* SDMA Interrupt registers */
300#define SDMA_INTR_CAUSE 0x0000 299#define SDMA_INTR_CAUSE 0x0000
@@ -308,11 +307,11 @@ struct mpsc_port_info *mpsc_device_remove(int index);
308 * Define how this driver is known to the outside (we've been assigned a 307 * Define how this driver is known to the outside (we've been assigned a
309 * range on the "Low-density serial ports" major). 308 * range on the "Low-density serial ports" major).
310 */ 309 */
311#define MPSC_MAJOR 204 310#define MPSC_MAJOR 204
312#define MPSC_MINOR_START 44 311#define MPSC_MINOR_START 44
313#define MPSC_DRIVER_NAME "MPSC" 312#define MPSC_DRIVER_NAME "MPSC"
314#define MPSC_DEV_NAME "ttyMM" 313#define MPSC_DEV_NAME "ttyMM"
315#define MPSC_VERSION "1.00" 314#define MPSC_VERSION "1.00"
316 315
317static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS]; 316static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
318static struct mpsc_shared_regs mpsc_shared_regs; 317static struct mpsc_shared_regs mpsc_shared_regs;
@@ -328,8 +327,7 @@ static void mpsc_release_port(struct uart_port *port);
328 * 327 *
329 ****************************************************************************** 328 ******************************************************************************
330 */ 329 */
331static void 330static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
332mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
333{ 331{
334 u32 v; 332 u32 v;
335 333
@@ -345,11 +343,9 @@ mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
345 343
346 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, 344 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
347 pi->brg_base + BRG_BTR); 345 pi->brg_base + BRG_BTR);
348 return;
349} 346}
350 347
351static void 348static void mpsc_brg_enable(struct mpsc_port_info *pi)
352mpsc_brg_enable(struct mpsc_port_info *pi)
353{ 349{
354 u32 v; 350 u32 v;
355 351
@@ -359,11 +355,9 @@ mpsc_brg_enable(struct mpsc_port_info *pi)
359 if (pi->mirror_regs) 355 if (pi->mirror_regs)
360 pi->BRG_BCR_m = v; 356 pi->BRG_BCR_m = v;
361 writel(v, pi->brg_base + BRG_BCR); 357 writel(v, pi->brg_base + BRG_BCR);
362 return;
363} 358}
364 359
365static void 360static void mpsc_brg_disable(struct mpsc_port_info *pi)
366mpsc_brg_disable(struct mpsc_port_info *pi)
367{ 361{
368 u32 v; 362 u32 v;
369 363
@@ -373,21 +367,19 @@ mpsc_brg_disable(struct mpsc_port_info *pi)
373 if (pi->mirror_regs) 367 if (pi->mirror_regs)
374 pi->BRG_BCR_m = v; 368 pi->BRG_BCR_m = v;
375 writel(v, pi->brg_base + BRG_BCR); 369 writel(v, pi->brg_base + BRG_BCR);
376 return;
377} 370}
378 371
379static inline void 372/*
380mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) 373 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
374 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
375 * However, the input clock is divided by 16 in the MPSC b/c of how
376 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
377 * calculation by 16 to account for that. So the real calculation
378 * that accounts for the way the mpsc is set up is:
379 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
380 */
381static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
381{ 382{
382 /*
383 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
384 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
385 * However, the input clock is divided by 16 in the MPSC b/c of how
386 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
387 * calculation by 16 to account for that. So the real calculation
388 * that accounts for the way the mpsc is set up is:
389 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
390 */
391 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; 383 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
392 u32 v; 384 u32 v;
393 385
@@ -399,8 +391,6 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
399 pi->BRG_BCR_m = v; 391 pi->BRG_BCR_m = v;
400 writel(v, pi->brg_base + BRG_BCR); 392 writel(v, pi->brg_base + BRG_BCR);
401 mpsc_brg_enable(pi); 393 mpsc_brg_enable(pi);
402
403 return;
404} 394}
405 395
406/* 396/*
@@ -411,13 +401,12 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
411 ****************************************************************************** 401 ******************************************************************************
412 */ 402 */
413 403
414static void 404static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
415mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
416{ 405{
417 u32 v; 406 u32 v;
418 407
419 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n", 408 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
420 pi->port.line, burst_size); 409 pi->port.line, burst_size);
421 410
422 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */ 411 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
423 412
@@ -432,11 +421,9 @@ mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
432 421
433 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), 422 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
434 pi->sdma_base + SDMA_SDC); 423 pi->sdma_base + SDMA_SDC);
435 return;
436} 424}
437 425
438static void 426static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
439mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
440{ 427{
441 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, 428 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
442 burst_size); 429 burst_size);
@@ -444,11 +431,9 @@ mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
444 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, 431 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
445 pi->sdma_base + SDMA_SDC); 432 pi->sdma_base + SDMA_SDC);
446 mpsc_sdma_burstsize(pi, burst_size); 433 mpsc_sdma_burstsize(pi, burst_size);
447 return;
448} 434}
449 435
450static inline u32 436static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
451mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
452{ 437{
453 u32 old, v; 438 u32 old, v;
454 439
@@ -471,15 +456,14 @@ mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
471 return old & 0xf; 456 return old & 0xf;
472} 457}
473 458
474static inline void 459static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
475mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
476{ 460{
477 u32 v; 461 u32 v;
478 462
479 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); 463 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
480 464
481 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : 465 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
482 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); 466 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
483 467
484 mask &= 0xf; 468 mask &= 0xf;
485 if (pi->port.line) 469 if (pi->port.line)
@@ -489,41 +473,35 @@ mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
489 if (pi->mirror_regs) 473 if (pi->mirror_regs)
490 pi->shared_regs->SDMA_INTR_MASK_m = v; 474 pi->shared_regs->SDMA_INTR_MASK_m = v;
491 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); 475 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
492 return;
493} 476}
494 477
495static inline void 478static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
496mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
497{ 479{
498 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); 480 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
499 481
500 if (pi->mirror_regs) 482 if (pi->mirror_regs)
501 pi->shared_regs->SDMA_INTR_CAUSE_m = 0; 483 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
502 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE + 484 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
503 pi->port.line); 485 + pi->port.line);
504 return;
505} 486}
506 487
507static inline void 488static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
508mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p) 489 struct mpsc_rx_desc *rxre_p)
509{ 490{
510 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n", 491 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
511 pi->port.line, (u32) rxre_p); 492 pi->port.line, (u32)rxre_p);
512 493
513 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); 494 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
514 return;
515} 495}
516 496
517static inline void 497static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
518mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p) 498 struct mpsc_tx_desc *txre_p)
519{ 499{
520 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); 500 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
521 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); 501 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
522 return;
523} 502}
524 503
525static inline void 504static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
526mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
527{ 505{
528 u32 v; 506 u32 v;
529 507
@@ -535,46 +513,40 @@ mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
535 wmb(); 513 wmb();
536 writel(v, pi->sdma_base + SDMA_SDCM); 514 writel(v, pi->sdma_base + SDMA_SDCM);
537 wmb(); 515 wmb();
538 return;
539} 516}
540 517
541static inline uint 518static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
542mpsc_sdma_tx_active(struct mpsc_port_info *pi)
543{ 519{
544 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; 520 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
545} 521}
546 522
547static inline void 523static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
548mpsc_sdma_start_tx(struct mpsc_port_info *pi)
549{ 524{
550 struct mpsc_tx_desc *txre, *txre_p; 525 struct mpsc_tx_desc *txre, *txre_p;
551 526
552 /* If tx isn't running & there's a desc ready to go, start it */ 527 /* If tx isn't running & there's a desc ready to go, start it */
553 if (!mpsc_sdma_tx_active(pi)) { 528 if (!mpsc_sdma_tx_active(pi)) {
554 txre = (struct mpsc_tx_desc *)(pi->txr + 529 txre = (struct mpsc_tx_desc *)(pi->txr
555 (pi->txr_tail * MPSC_TXRE_SIZE)); 530 + (pi->txr_tail * MPSC_TXRE_SIZE));
556 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); 531 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
532 DMA_FROM_DEVICE);
557#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 533#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
558 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 534 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
559 invalidate_dcache_range((ulong)txre, 535 invalidate_dcache_range((ulong)txre,
560 (ulong)txre + MPSC_TXRE_SIZE); 536 (ulong)txre + MPSC_TXRE_SIZE);
561#endif 537#endif
562 538
563 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) { 539 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
564 txre_p = (struct mpsc_tx_desc *)(pi->txr_p + 540 txre_p = (struct mpsc_tx_desc *)
565 (pi->txr_tail * 541 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
566 MPSC_TXRE_SIZE));
567 542
568 mpsc_sdma_set_tx_ring(pi, txre_p); 543 mpsc_sdma_set_tx_ring(pi, txre_p);
569 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); 544 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
570 } 545 }
571 } 546 }
572
573 return;
574} 547}
575 548
576static inline void 549static void mpsc_sdma_stop(struct mpsc_port_info *pi)
577mpsc_sdma_stop(struct mpsc_port_info *pi)
578{ 550{
579 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); 551 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
580 552
@@ -589,8 +561,6 @@ mpsc_sdma_stop(struct mpsc_port_info *pi)
589 /* Disable interrupts */ 561 /* Disable interrupts */
590 mpsc_sdma_intr_mask(pi, 0xf); 562 mpsc_sdma_intr_mask(pi, 0xf);
591 mpsc_sdma_intr_ack(pi); 563 mpsc_sdma_intr_ack(pi);
592
593 return;
594} 564}
595 565
596/* 566/*
@@ -601,8 +571,7 @@ mpsc_sdma_stop(struct mpsc_port_info *pi)
601 ****************************************************************************** 571 ******************************************************************************
602 */ 572 */
603 573
604static void 574static void mpsc_hw_init(struct mpsc_port_info *pi)
605mpsc_hw_init(struct mpsc_port_info *pi)
606{ 575{
607 u32 v; 576 u32 v;
608 577
@@ -624,8 +593,7 @@ mpsc_hw_init(struct mpsc_port_info *pi)
624 v = (v & ~0xf0f) | 0x100; 593 v = (v & ~0xf0f) | 0x100;
625 pi->shared_regs->MPSC_TCRR_m = v; 594 pi->shared_regs->MPSC_TCRR_m = v;
626 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); 595 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
627 } 596 } else {
628 else {
629 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); 597 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
630 v &= ~0x1c7; 598 v &= ~0x1c7;
631 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); 599 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
@@ -642,7 +610,7 @@ mpsc_hw_init(struct mpsc_port_info *pi)
642 /* Put MPSC in UART mode & enabel Tx/Rx egines */ 610 /* Put MPSC in UART mode & enabel Tx/Rx egines */
643 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); 611 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
644 612
645 /* No preamble, 16x divider, low-latency, */ 613 /* No preamble, 16x divider, low-latency, */
646 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); 614 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
647 615
648 if (pi->mirror_regs) { 616 if (pi->mirror_regs) {
@@ -659,12 +627,9 @@ mpsc_hw_init(struct mpsc_port_info *pi)
659 writel(0, pi->mpsc_base + MPSC_CHR_8); 627 writel(0, pi->mpsc_base + MPSC_CHR_8);
660 writel(0, pi->mpsc_base + MPSC_CHR_9); 628 writel(0, pi->mpsc_base + MPSC_CHR_9);
661 writel(0, pi->mpsc_base + MPSC_CHR_10); 629 writel(0, pi->mpsc_base + MPSC_CHR_10);
662
663 return;
664} 630}
665 631
666static inline void 632static void mpsc_enter_hunt(struct mpsc_port_info *pi)
667mpsc_enter_hunt(struct mpsc_port_info *pi)
668{ 633{
669 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); 634 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
670 635
@@ -673,20 +638,16 @@ mpsc_enter_hunt(struct mpsc_port_info *pi)
673 pi->mpsc_base + MPSC_CHR_2); 638 pi->mpsc_base + MPSC_CHR_2);
674 /* Erratum prevents reading CHR_2 so just delay for a while */ 639 /* Erratum prevents reading CHR_2 so just delay for a while */
675 udelay(100); 640 udelay(100);
676 } 641 } else {
677 else {
678 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, 642 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
679 pi->mpsc_base + MPSC_CHR_2); 643 pi->mpsc_base + MPSC_CHR_2);
680 644
681 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) 645 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
682 udelay(10); 646 udelay(10);
683 } 647 }
684
685 return;
686} 648}
687 649
688static inline void 650static void mpsc_freeze(struct mpsc_port_info *pi)
689mpsc_freeze(struct mpsc_port_info *pi)
690{ 651{
691 u32 v; 652 u32 v;
692 653
@@ -699,11 +660,9 @@ mpsc_freeze(struct mpsc_port_info *pi)
699 if (pi->mirror_regs) 660 if (pi->mirror_regs)
700 pi->MPSC_MPCR_m = v; 661 pi->MPSC_MPCR_m = v;
701 writel(v, pi->mpsc_base + MPSC_MPCR); 662 writel(v, pi->mpsc_base + MPSC_MPCR);
702 return;
703} 663}
704 664
705static inline void 665static void mpsc_unfreeze(struct mpsc_port_info *pi)
706mpsc_unfreeze(struct mpsc_port_info *pi)
707{ 666{
708 u32 v; 667 u32 v;
709 668
@@ -716,11 +675,9 @@ mpsc_unfreeze(struct mpsc_port_info *pi)
716 writel(v, pi->mpsc_base + MPSC_MPCR); 675 writel(v, pi->mpsc_base + MPSC_MPCR);
717 676
718 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); 677 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
719 return;
720} 678}
721 679
722static inline void 680static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
723mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
724{ 681{
725 u32 v; 682 u32 v;
726 683
@@ -733,11 +690,9 @@ mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
733 if (pi->mirror_regs) 690 if (pi->mirror_regs)
734 pi->MPSC_MPCR_m = v; 691 pi->MPSC_MPCR_m = v;
735 writel(v, pi->mpsc_base + MPSC_MPCR); 692 writel(v, pi->mpsc_base + MPSC_MPCR);
736 return;
737} 693}
738 694
739static inline void 695static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
740mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
741{ 696{
742 u32 v; 697 u32 v;
743 698
@@ -752,11 +707,9 @@ mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
752 if (pi->mirror_regs) 707 if (pi->mirror_regs)
753 pi->MPSC_MPCR_m = v; 708 pi->MPSC_MPCR_m = v;
754 writel(v, pi->mpsc_base + MPSC_MPCR); 709 writel(v, pi->mpsc_base + MPSC_MPCR);
755 return;
756} 710}
757 711
758static inline void 712static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
759mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
760{ 713{
761 u32 v; 714 u32 v;
762 715
@@ -771,7 +724,6 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
771 if (pi->mirror_regs) 724 if (pi->mirror_regs)
772 pi->MPSC_CHR_2_m = v; 725 pi->MPSC_CHR_2_m = v;
773 writel(v, pi->mpsc_base + MPSC_CHR_2); 726 writel(v, pi->mpsc_base + MPSC_CHR_2);
774 return;
775} 727}
776 728
777/* 729/*
@@ -782,8 +734,7 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
782 ****************************************************************************** 734 ******************************************************************************
783 */ 735 */
784 736
785static void 737static void mpsc_init_hw(struct mpsc_port_info *pi)
786mpsc_init_hw(struct mpsc_port_info *pi)
787{ 738{
788 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); 739 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
789 740
@@ -792,12 +743,9 @@ mpsc_init_hw(struct mpsc_port_info *pi)
792 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ 743 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
793 mpsc_sdma_stop(pi); 744 mpsc_sdma_stop(pi);
794 mpsc_hw_init(pi); 745 mpsc_hw_init(pi);
795
796 return;
797} 746}
798 747
799static int 748static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
800mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
801{ 749{
802 int rc = 0; 750 int rc = 0;
803 751
@@ -808,11 +756,10 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
808 if (!dma_supported(pi->port.dev, 0xffffffff)) { 756 if (!dma_supported(pi->port.dev, 0xffffffff)) {
809 printk(KERN_ERR "MPSC: Inadequate DMA support\n"); 757 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
810 rc = -ENXIO; 758 rc = -ENXIO;
811 } 759 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
812 else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, 760 MPSC_DMA_ALLOC_SIZE,
813 MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL)) 761 &pi->dma_region_p, GFP_KERNEL))
814 == NULL) { 762 == NULL) {
815
816 printk(KERN_ERR "MPSC: Can't alloc Desc region\n"); 763 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
817 rc = -ENOMEM; 764 rc = -ENOMEM;
818 } 765 }
@@ -821,23 +768,19 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
821 return rc; 768 return rc;
822} 769}
823 770
824static void 771static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
825mpsc_free_ring_mem(struct mpsc_port_info *pi)
826{ 772{
827 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); 773 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
828 774
829 if (pi->dma_region) { 775 if (pi->dma_region) {
830 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, 776 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
831 pi->dma_region, pi->dma_region_p); 777 pi->dma_region, pi->dma_region_p);
832 pi->dma_region = NULL; 778 pi->dma_region = NULL;
833 pi->dma_region_p = (dma_addr_t) NULL; 779 pi->dma_region_p = (dma_addr_t)NULL;
834 } 780 }
835
836 return;
837} 781}
838 782
839static void 783static void mpsc_init_rings(struct mpsc_port_info *pi)
840mpsc_init_rings(struct mpsc_port_info *pi)
841{ 784{
842 struct mpsc_rx_desc *rxre; 785 struct mpsc_rx_desc *rxre;
843 struct mpsc_tx_desc *txre; 786 struct mpsc_tx_desc *txre;
@@ -855,8 +798,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
855 * Descriptors & buffers are multiples of cacheline size and must be 798 * Descriptors & buffers are multiples of cacheline size and must be
856 * cacheline aligned. 799 * cacheline aligned.
857 */ 800 */
858 dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment()); 801 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
859 dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment()); 802 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
860 803
861 /* 804 /*
862 * Partition dma region into rx ring descriptor, rx buffers, 805 * Partition dma region into rx ring descriptor, rx buffers,
@@ -867,8 +810,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
867 dp += MPSC_RXR_SIZE; 810 dp += MPSC_RXR_SIZE;
868 dp_p += MPSC_RXR_SIZE; 811 dp_p += MPSC_RXR_SIZE;
869 812
870 pi->rxb = (u8 *) dp; 813 pi->rxb = (u8 *)dp;
871 pi->rxb_p = (u8 *) dp_p; 814 pi->rxb_p = (u8 *)dp_p;
872 dp += MPSC_RXB_SIZE; 815 dp += MPSC_RXB_SIZE;
873 dp_p += MPSC_RXB_SIZE; 816 dp_p += MPSC_RXB_SIZE;
874 817
@@ -879,8 +822,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
879 dp += MPSC_TXR_SIZE; 822 dp += MPSC_TXR_SIZE;
880 dp_p += MPSC_TXR_SIZE; 823 dp_p += MPSC_TXR_SIZE;
881 824
882 pi->txb = (u8 *) dp; 825 pi->txb = (u8 *)dp;
883 pi->txb_p = (u8 *) dp_p; 826 pi->txb_p = (u8 *)dp_p;
884 827
885 pi->txr_head = 0; 828 pi->txr_head = 0;
886 pi->txr_tail = 0; 829 pi->txr_tail = 0;
@@ -896,10 +839,9 @@ mpsc_init_rings(struct mpsc_port_info *pi)
896 839
897 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE); 840 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
898 rxre->bytecnt = cpu_to_be16(0); 841 rxre->bytecnt = cpu_to_be16(0);
899 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | 842 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
900 SDMA_DESC_CMDSTAT_EI | 843 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
901 SDMA_DESC_CMDSTAT_F | 844 | SDMA_DESC_CMDSTAT_L);
902 SDMA_DESC_CMDSTAT_L);
903 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE); 845 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
904 rxre->buf_ptr = cpu_to_be32(bp_p); 846 rxre->buf_ptr = cpu_to_be32(bp_p);
905 847
@@ -929,19 +871,19 @@ mpsc_init_rings(struct mpsc_port_info *pi)
929 } 871 }
930 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ 872 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
931 873
932 dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE, 874 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
933 DMA_BIDIRECTIONAL); 875 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
934#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 876#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
935 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 877 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
936 flush_dcache_range((ulong)pi->dma_region, 878 flush_dcache_range((ulong)pi->dma_region,
937 (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE); 879 (ulong)pi->dma_region
880 + MPSC_DMA_ALLOC_SIZE);
938#endif 881#endif
939 882
940 return; 883 return;
941} 884}
942 885
943static void 886static void mpsc_uninit_rings(struct mpsc_port_info *pi)
944mpsc_uninit_rings(struct mpsc_port_info *pi)
945{ 887{
946 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); 888 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
947 889
@@ -959,12 +901,9 @@ mpsc_uninit_rings(struct mpsc_port_info *pi)
959 pi->txb_p = NULL; 901 pi->txb_p = NULL;
960 pi->txr_head = 0; 902 pi->txr_head = 0;
961 pi->txr_tail = 0; 903 pi->txr_tail = 0;
962
963 return;
964} 904}
965 905
966static int 906static int mpsc_make_ready(struct mpsc_port_info *pi)
967mpsc_make_ready(struct mpsc_port_info *pi)
968{ 907{
969 int rc; 908 int rc;
970 909
@@ -989,8 +928,7 @@ mpsc_make_ready(struct mpsc_port_info *pi)
989 ****************************************************************************** 928 ******************************************************************************
990 */ 929 */
991 930
992static inline int 931static int mpsc_rx_intr(struct mpsc_port_info *pi)
993mpsc_rx_intr(struct mpsc_port_info *pi)
994{ 932{
995 struct mpsc_rx_desc *rxre; 933 struct mpsc_rx_desc *rxre;
996 struct tty_struct *tty = pi->port.info->tty; 934 struct tty_struct *tty = pi->port.info->tty;
@@ -1003,21 +941,24 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
1003 941
1004 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); 942 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
1005 943
1006 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); 944 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
945 DMA_FROM_DEVICE);
1007#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 946#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1008 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 947 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1009 invalidate_dcache_range((ulong)rxre, 948 invalidate_dcache_range((ulong)rxre,
1010 (ulong)rxre + MPSC_RXRE_SIZE); 949 (ulong)rxre + MPSC_RXRE_SIZE);
1011#endif 950#endif
1012 951
1013 /* 952 /*
1014 * Loop through Rx descriptors handling ones that have been completed. 953 * Loop through Rx descriptors handling ones that have been completed.
1015 */ 954 */
1016 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){ 955 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
956 & SDMA_DESC_CMDSTAT_O)) {
1017 bytes_in = be16_to_cpu(rxre->bytecnt); 957 bytes_in = be16_to_cpu(rxre->bytecnt);
1018 958
1019 /* Following use of tty struct directly is deprecated */ 959 /* Following use of tty struct directly is deprecated */
1020 if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) { 960 if (unlikely(tty_buffer_request_room(tty, bytes_in)
961 < bytes_in)) {
1021 if (tty->low_latency) 962 if (tty->low_latency)
1022 tty_flip_buffer_push(tty); 963 tty_flip_buffer_push(tty);
1023 /* 964 /*
@@ -1027,11 +968,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
1027 } 968 }
1028 969
1029 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); 970 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1030 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE); 971 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
972 DMA_FROM_DEVICE);
1031#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 973#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1032 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 974 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1033 invalidate_dcache_range((ulong)bp, 975 invalidate_dcache_range((ulong)bp,
1034 (ulong)bp + MPSC_RXBE_SIZE); 976 (ulong)bp + MPSC_RXBE_SIZE);
1035#endif 977#endif
1036 978
1037 /* 979 /*
@@ -1042,8 +984,9 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
1042 * we'll assume there is no data in the buffer. 984 * we'll assume there is no data in the buffer.
1043 * If there is...it gets lost. 985 * If there is...it gets lost.
1044 */ 986 */
1045 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | 987 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1046 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) { 988 | SDMA_DESC_CMDSTAT_FR
989 | SDMA_DESC_CMDSTAT_OR))) {
1047 990
1048 pi->port.icount.rx++; 991 pi->port.icount.rx++;
1049 992
@@ -1052,11 +995,11 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
1052 995
1053 if (uart_handle_break(&pi->port)) 996 if (uart_handle_break(&pi->port))
1054 goto next_frame; 997 goto next_frame;
1055 } 998 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1056 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
1057 pi->port.icount.frame++; 999 pi->port.icount.frame++;
1058 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */ 1000 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1059 pi->port.icount.overrun++; 1001 pi->port.icount.overrun++;
1002 }
1060 1003
1061 cmdstat &= pi->port.read_status_mask; 1004 cmdstat &= pi->port.read_status_mask;
1062 1005
@@ -1076,12 +1019,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
1076 goto next_frame; 1019 goto next_frame;
1077 } 1020 }
1078 1021
1079 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | 1022 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1080 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) && 1023 | SDMA_DESC_CMDSTAT_FR
1081 !(cmdstat & pi->port.ignore_status_mask)) 1024 | SDMA_DESC_CMDSTAT_OR)))
1082 1025 && !(cmdstat & pi->port.ignore_status_mask)) {
1083 tty_insert_flip_char(tty, *bp, flag); 1026 tty_insert_flip_char(tty, *bp, flag);
1084 else { 1027 } else {
1085 for (i=0; i<bytes_in; i++) 1028 for (i=0; i<bytes_in; i++)
1086 tty_insert_flip_char(tty, *bp++, TTY_NORMAL); 1029 tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
1087 1030
@@ -1091,29 +1034,29 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
1091next_frame: 1034next_frame:
1092 rxre->bytecnt = cpu_to_be16(0); 1035 rxre->bytecnt = cpu_to_be16(0);
1093 wmb(); 1036 wmb();
1094 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | 1037 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1095 SDMA_DESC_CMDSTAT_EI | 1038 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1096 SDMA_DESC_CMDSTAT_F | 1039 | SDMA_DESC_CMDSTAT_L);
1097 SDMA_DESC_CMDSTAT_L);
1098 wmb(); 1040 wmb();
1099 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL); 1041 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1042 DMA_BIDIRECTIONAL);
1100#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1043#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1101 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1044 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1102 flush_dcache_range((ulong)rxre, 1045 flush_dcache_range((ulong)rxre,
1103 (ulong)rxre + MPSC_RXRE_SIZE); 1046 (ulong)rxre + MPSC_RXRE_SIZE);
1104#endif 1047#endif
1105 1048
1106 /* Advance to next descriptor */ 1049 /* Advance to next descriptor */
1107 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); 1050 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1108 rxre = (struct mpsc_rx_desc *)(pi->rxr + 1051 rxre = (struct mpsc_rx_desc *)
1109 (pi->rxr_posn * MPSC_RXRE_SIZE)); 1052 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1110 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); 1053 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1054 DMA_FROM_DEVICE);
1111#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1055#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1112 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1056 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1113 invalidate_dcache_range((ulong)rxre, 1057 invalidate_dcache_range((ulong)rxre,
1114 (ulong)rxre + MPSC_RXRE_SIZE); 1058 (ulong)rxre + MPSC_RXRE_SIZE);
1115#endif 1059#endif
1116
1117 rc = 1; 1060 rc = 1;
1118 } 1061 }
1119 1062
@@ -1125,42 +1068,38 @@ next_frame:
1125 return rc; 1068 return rc;
1126} 1069}
1127 1070
1128static inline void 1071static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1129mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1130{ 1072{
1131 struct mpsc_tx_desc *txre; 1073 struct mpsc_tx_desc *txre;
1132 1074
1133 txre = (struct mpsc_tx_desc *)(pi->txr + 1075 txre = (struct mpsc_tx_desc *)(pi->txr
1134 (pi->txr_head * MPSC_TXRE_SIZE)); 1076 + (pi->txr_head * MPSC_TXRE_SIZE));
1135 1077
1136 txre->bytecnt = cpu_to_be16(count); 1078 txre->bytecnt = cpu_to_be16(count);
1137 txre->shadow = txre->bytecnt; 1079 txre->shadow = txre->bytecnt;
1138 wmb(); /* ensure cmdstat is last field updated */ 1080 wmb(); /* ensure cmdstat is last field updated */
1139 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F | 1081 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1140 SDMA_DESC_CMDSTAT_L | ((intr) ? 1082 | SDMA_DESC_CMDSTAT_L
1141 SDMA_DESC_CMDSTAT_EI 1083 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1142 : 0));
1143 wmb(); 1084 wmb();
1144 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL); 1085 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1086 DMA_BIDIRECTIONAL);
1145#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1087#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1146 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1088 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1147 flush_dcache_range((ulong)txre, 1089 flush_dcache_range((ulong)txre,
1148 (ulong)txre + MPSC_TXRE_SIZE); 1090 (ulong)txre + MPSC_TXRE_SIZE);
1149#endif 1091#endif
1150
1151 return;
1152} 1092}
1153 1093
1154static inline void 1094static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1155mpsc_copy_tx_data(struct mpsc_port_info *pi)
1156{ 1095{
1157 struct circ_buf *xmit = &pi->port.info->xmit; 1096 struct circ_buf *xmit = &pi->port.info->xmit;
1158 u8 *bp; 1097 u8 *bp;
1159 u32 i; 1098 u32 i;
1160 1099
1161 /* Make sure the desc ring isn't full */ 1100 /* Make sure the desc ring isn't full */
1162 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) < 1101 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1163 (MPSC_TXR_ENTRIES - 1)) { 1102 < (MPSC_TXR_ENTRIES - 1)) {
1164 if (pi->port.x_char) { 1103 if (pi->port.x_char) {
1165 /* 1104 /*
1166 * Ideally, we should use the TCS field in 1105 * Ideally, we should use the TCS field in
@@ -1174,11 +1113,11 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi)
1174 *bp = pi->port.x_char; 1113 *bp = pi->port.x_char;
1175 pi->port.x_char = 0; 1114 pi->port.x_char = 0;
1176 i = 1; 1115 i = 1;
1177 } 1116 } else if (!uart_circ_empty(xmit)
1178 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){ 1117 && !uart_tx_stopped(&pi->port)) {
1179 i = min((u32) MPSC_TXBE_SIZE, 1118 i = min((u32)MPSC_TXBE_SIZE,
1180 (u32) uart_circ_chars_pending(xmit)); 1119 (u32)uart_circ_chars_pending(xmit));
1181 i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail, 1120 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1182 UART_XMIT_SIZE)); 1121 UART_XMIT_SIZE));
1183 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); 1122 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1184 memcpy(bp, &xmit->buf[xmit->tail], i); 1123 memcpy(bp, &xmit->buf[xmit->tail], i);
@@ -1186,27 +1125,25 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi)
1186 1125
1187 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1126 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1188 uart_write_wakeup(&pi->port); 1127 uart_write_wakeup(&pi->port);
1189 } 1128 } else { /* All tx data copied into ring bufs */
1190 else /* All tx data copied into ring bufs */
1191 return; 1129 return;
1130 }
1192 1131
1193 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); 1132 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1133 DMA_BIDIRECTIONAL);
1194#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1134#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1195 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1135 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1196 flush_dcache_range((ulong)bp, 1136 flush_dcache_range((ulong)bp,
1197 (ulong)bp + MPSC_TXBE_SIZE); 1137 (ulong)bp + MPSC_TXBE_SIZE);
1198#endif 1138#endif
1199 mpsc_setup_tx_desc(pi, i, 1); 1139 mpsc_setup_tx_desc(pi, i, 1);
1200 1140
1201 /* Advance to next descriptor */ 1141 /* Advance to next descriptor */
1202 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); 1142 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1203 } 1143 }
1204
1205 return;
1206} 1144}
1207 1145
1208static inline int 1146static int mpsc_tx_intr(struct mpsc_port_info *pi)
1209mpsc_tx_intr(struct mpsc_port_info *pi)
1210{ 1147{
1211 struct mpsc_tx_desc *txre; 1148 struct mpsc_tx_desc *txre;
1212 int rc = 0; 1149 int rc = 0;
@@ -1215,14 +1152,15 @@ mpsc_tx_intr(struct mpsc_port_info *pi)
1215 spin_lock_irqsave(&pi->tx_lock, iflags); 1152 spin_lock_irqsave(&pi->tx_lock, iflags);
1216 1153
1217 if (!mpsc_sdma_tx_active(pi)) { 1154 if (!mpsc_sdma_tx_active(pi)) {
1218 txre = (struct mpsc_tx_desc *)(pi->txr + 1155 txre = (struct mpsc_tx_desc *)(pi->txr
1219 (pi->txr_tail * MPSC_TXRE_SIZE)); 1156 + (pi->txr_tail * MPSC_TXRE_SIZE));
1220 1157
1221 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); 1158 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1159 DMA_FROM_DEVICE);
1222#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1160#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1223 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1161 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1224 invalidate_dcache_range((ulong)txre, 1162 invalidate_dcache_range((ulong)txre,
1225 (ulong)txre + MPSC_TXRE_SIZE); 1163 (ulong)txre + MPSC_TXRE_SIZE);
1226#endif 1164#endif
1227 1165
1228 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) { 1166 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
@@ -1234,14 +1172,14 @@ mpsc_tx_intr(struct mpsc_port_info *pi)
1234 if (pi->txr_head == pi->txr_tail) 1172 if (pi->txr_head == pi->txr_tail)
1235 break; 1173 break;
1236 1174
1237 txre = (struct mpsc_tx_desc *)(pi->txr + 1175 txre = (struct mpsc_tx_desc *)(pi->txr
1238 (pi->txr_tail * MPSC_TXRE_SIZE)); 1176 + (pi->txr_tail * MPSC_TXRE_SIZE));
1239 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, 1177 dma_cache_sync(pi->port.dev, (void *)txre,
1240 DMA_FROM_DEVICE); 1178 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1241#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1179#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1242 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1180 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1243 invalidate_dcache_range((ulong)txre, 1181 invalidate_dcache_range((ulong)txre,
1244 (ulong)txre + MPSC_TXRE_SIZE); 1182 (ulong)txre + MPSC_TXRE_SIZE);
1245#endif 1183#endif
1246 } 1184 }
1247 1185
@@ -1258,8 +1196,7 @@ mpsc_tx_intr(struct mpsc_port_info *pi)
1258 * the interrupt, then handle any completed Rx/Tx descriptors. When done 1196 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1259 * handling those descriptors, we restart the Rx/Tx engines if they're stopped. 1197 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1260 */ 1198 */
1261static irqreturn_t 1199static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1262mpsc_sdma_intr(int irq, void *dev_id)
1263{ 1200{
1264 struct mpsc_port_info *pi = dev_id; 1201 struct mpsc_port_info *pi = dev_id;
1265 ulong iflags; 1202 ulong iflags;
@@ -1286,8 +1223,7 @@ mpsc_sdma_intr(int irq, void *dev_id)
1286 * 1223 *
1287 ****************************************************************************** 1224 ******************************************************************************
1288 */ 1225 */
1289static uint 1226static uint mpsc_tx_empty(struct uart_port *port)
1290mpsc_tx_empty(struct uart_port *port)
1291{ 1227{
1292 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1228 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1293 ulong iflags; 1229 ulong iflags;
@@ -1300,21 +1236,18 @@ mpsc_tx_empty(struct uart_port *port)
1300 return rc; 1236 return rc;
1301} 1237}
1302 1238
1303static void 1239static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1304mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1305{ 1240{
1306 /* Have no way to set modem control lines AFAICT */ 1241 /* Have no way to set modem control lines AFAICT */
1307 return;
1308} 1242}
1309 1243
1310static uint 1244static uint mpsc_get_mctrl(struct uart_port *port)
1311mpsc_get_mctrl(struct uart_port *port)
1312{ 1245{
1313 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1246 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1314 u32 mflags, status; 1247 u32 mflags, status;
1315 1248
1316 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m : 1249 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1317 readl(pi->mpsc_base + MPSC_CHR_10); 1250 : readl(pi->mpsc_base + MPSC_CHR_10);
1318 1251
1319 mflags = 0; 1252 mflags = 0;
1320 if (status & 0x1) 1253 if (status & 0x1)
@@ -1325,19 +1258,16 @@ mpsc_get_mctrl(struct uart_port *port)
1325 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */ 1258 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1326} 1259}
1327 1260
1328static void 1261static void mpsc_stop_tx(struct uart_port *port)
1329mpsc_stop_tx(struct uart_port *port)
1330{ 1262{
1331 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1263 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1332 1264
1333 pr_debug("mpsc_stop_tx[%d]\n", port->line); 1265 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1334 1266
1335 mpsc_freeze(pi); 1267 mpsc_freeze(pi);
1336 return;
1337} 1268}
1338 1269
1339static void 1270static void mpsc_start_tx(struct uart_port *port)
1340mpsc_start_tx(struct uart_port *port)
1341{ 1271{
1342 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1272 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1343 unsigned long iflags; 1273 unsigned long iflags;
@@ -1351,11 +1281,9 @@ mpsc_start_tx(struct uart_port *port)
1351 spin_unlock_irqrestore(&pi->tx_lock, iflags); 1281 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1352 1282
1353 pr_debug("mpsc_start_tx[%d]\n", port->line); 1283 pr_debug("mpsc_start_tx[%d]\n", port->line);
1354 return;
1355} 1284}
1356 1285
1357static void 1286static void mpsc_start_rx(struct mpsc_port_info *pi)
1358mpsc_start_rx(struct mpsc_port_info *pi)
1359{ 1287{
1360 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); 1288 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1361 1289
@@ -1363,11 +1291,9 @@ mpsc_start_rx(struct mpsc_port_info *pi)
1363 mpsc_enter_hunt(pi); 1291 mpsc_enter_hunt(pi);
1364 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); 1292 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1365 } 1293 }
1366 return;
1367} 1294}
1368 1295
1369static void 1296static void mpsc_stop_rx(struct uart_port *port)
1370mpsc_stop_rx(struct uart_port *port)
1371{ 1297{
1372 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1298 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1373 1299
@@ -1378,27 +1304,22 @@ mpsc_stop_rx(struct uart_port *port)
1378 pi->mpsc_base + MPSC_CHR_2); 1304 pi->mpsc_base + MPSC_CHR_2);
1379 /* Erratum prevents reading CHR_2 so just delay for a while */ 1305 /* Erratum prevents reading CHR_2 so just delay for a while */
1380 udelay(100); 1306 udelay(100);
1381 } 1307 } else {
1382 else {
1383 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA, 1308 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
1384 pi->mpsc_base + MPSC_CHR_2); 1309 pi->mpsc_base + MPSC_CHR_2);
1385 1310
1386 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA) 1311 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1387 udelay(10); 1312 udelay(10);
1388 } 1313 }
1389 1314
1390 mpsc_sdma_cmd(pi, SDMA_SDCM_AR); 1315 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1391 return;
1392} 1316}
1393 1317
1394static void 1318static void mpsc_enable_ms(struct uart_port *port)
1395mpsc_enable_ms(struct uart_port *port)
1396{ 1319{
1397 return; /* Not supported */
1398} 1320}
1399 1321
1400static void 1322static void mpsc_break_ctl(struct uart_port *port, int ctl)
1401mpsc_break_ctl(struct uart_port *port, int ctl)
1402{ 1323{
1403 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1324 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1404 ulong flags; 1325 ulong flags;
@@ -1411,12 +1332,9 @@ mpsc_break_ctl(struct uart_port *port, int ctl)
1411 pi->MPSC_CHR_1_m = v; 1332 pi->MPSC_CHR_1_m = v;
1412 writel(v, pi->mpsc_base + MPSC_CHR_1); 1333 writel(v, pi->mpsc_base + MPSC_CHR_1);
1413 spin_unlock_irqrestore(&pi->port.lock, flags); 1334 spin_unlock_irqrestore(&pi->port.lock, flags);
1414
1415 return;
1416} 1335}
1417 1336
1418static int 1337static int mpsc_startup(struct uart_port *port)
1419mpsc_startup(struct uart_port *port)
1420{ 1338{
1421 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1339 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1422 u32 flag = 0; 1340 u32 flag = 0;
@@ -1434,20 +1352,19 @@ mpsc_startup(struct uart_port *port)
1434 flag = IRQF_SHARED; 1352 flag = IRQF_SHARED;
1435 1353
1436 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, 1354 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1437 "mpsc-sdma", pi)) 1355 "mpsc-sdma", pi))
1438 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", 1356 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1439 pi->port.irq); 1357 pi->port.irq);
1440 1358
1441 mpsc_sdma_intr_unmask(pi, 0xf); 1359 mpsc_sdma_intr_unmask(pi, 0xf);
1442 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p + 1360 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1443 (pi->rxr_posn * MPSC_RXRE_SIZE))); 1361 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1444 } 1362 }
1445 1363
1446 return rc; 1364 return rc;
1447} 1365}
1448 1366
1449static void 1367static void mpsc_shutdown(struct uart_port *port)
1450mpsc_shutdown(struct uart_port *port)
1451{ 1368{
1452 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1369 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1453 1370
@@ -1455,11 +1372,9 @@ mpsc_shutdown(struct uart_port *port)
1455 1372
1456 mpsc_sdma_stop(pi); 1373 mpsc_sdma_stop(pi);
1457 free_irq(pi->port.irq, pi); 1374 free_irq(pi->port.irq, pi);
1458 return;
1459} 1375}
1460 1376
1461static void 1377static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1462mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1463 struct ktermios *old) 1378 struct ktermios *old)
1464{ 1379{
1465 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1380 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
@@ -1519,8 +1434,8 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1519 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; 1434 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1520 1435
1521 if (termios->c_iflag & INPCK) 1436 if (termios->c_iflag & INPCK)
1522 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE | 1437 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1523 SDMA_DESC_CMDSTAT_FR; 1438 | SDMA_DESC_CMDSTAT_FR;
1524 1439
1525 if (termios->c_iflag & (BRKINT | PARMRK)) 1440 if (termios->c_iflag & (BRKINT | PARMRK))
1526 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; 1441 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
@@ -1529,8 +1444,8 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1529 pi->port.ignore_status_mask = 0; 1444 pi->port.ignore_status_mask = 0;
1530 1445
1531 if (termios->c_iflag & IGNPAR) 1446 if (termios->c_iflag & IGNPAR)
1532 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE | 1447 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1533 SDMA_DESC_CMDSTAT_FR; 1448 | SDMA_DESC_CMDSTAT_FR;
1534 1449
1535 if (termios->c_iflag & IGNBRK) { 1450 if (termios->c_iflag & IGNBRK) {
1536 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; 1451 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
@@ -1550,25 +1465,21 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1550 } 1465 }
1551 1466
1552 spin_unlock_irqrestore(&pi->port.lock, flags); 1467 spin_unlock_irqrestore(&pi->port.lock, flags);
1553 return;
1554} 1468}
1555 1469
1556static const char * 1470static const char *mpsc_type(struct uart_port *port)
1557mpsc_type(struct uart_port *port)
1558{ 1471{
1559 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME); 1472 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1560 return MPSC_DRIVER_NAME; 1473 return MPSC_DRIVER_NAME;
1561} 1474}
1562 1475
1563static int 1476static int mpsc_request_port(struct uart_port *port)
1564mpsc_request_port(struct uart_port *port)
1565{ 1477{
1566 /* Should make chip/platform specific call */ 1478 /* Should make chip/platform specific call */
1567 return 0; 1479 return 0;
1568} 1480}
1569 1481
1570static void 1482static void mpsc_release_port(struct uart_port *port)
1571mpsc_release_port(struct uart_port *port)
1572{ 1483{
1573 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1484 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1574 1485
@@ -1577,18 +1488,13 @@ mpsc_release_port(struct uart_port *port)
1577 mpsc_free_ring_mem(pi); 1488 mpsc_free_ring_mem(pi);
1578 pi->ready = 0; 1489 pi->ready = 0;
1579 } 1490 }
1580
1581 return;
1582} 1491}
1583 1492
1584static void 1493static void mpsc_config_port(struct uart_port *port, int flags)
1585mpsc_config_port(struct uart_port *port, int flags)
1586{ 1494{
1587 return;
1588} 1495}
1589 1496
1590static int 1497static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1591mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1592{ 1498{
1593 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1499 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1594 int rc = 0; 1500 int rc = 0;
@@ -1614,22 +1520,22 @@ mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1614} 1520}
1615 1521
1616static struct uart_ops mpsc_pops = { 1522static struct uart_ops mpsc_pops = {
1617 .tx_empty = mpsc_tx_empty, 1523 .tx_empty = mpsc_tx_empty,
1618 .set_mctrl = mpsc_set_mctrl, 1524 .set_mctrl = mpsc_set_mctrl,
1619 .get_mctrl = mpsc_get_mctrl, 1525 .get_mctrl = mpsc_get_mctrl,
1620 .stop_tx = mpsc_stop_tx, 1526 .stop_tx = mpsc_stop_tx,
1621 .start_tx = mpsc_start_tx, 1527 .start_tx = mpsc_start_tx,
1622 .stop_rx = mpsc_stop_rx, 1528 .stop_rx = mpsc_stop_rx,
1623 .enable_ms = mpsc_enable_ms, 1529 .enable_ms = mpsc_enable_ms,
1624 .break_ctl = mpsc_break_ctl, 1530 .break_ctl = mpsc_break_ctl,
1625 .startup = mpsc_startup, 1531 .startup = mpsc_startup,
1626 .shutdown = mpsc_shutdown, 1532 .shutdown = mpsc_shutdown,
1627 .set_termios = mpsc_set_termios, 1533 .set_termios = mpsc_set_termios,
1628 .type = mpsc_type, 1534 .type = mpsc_type,
1629 .release_port = mpsc_release_port, 1535 .release_port = mpsc_release_port,
1630 .request_port = mpsc_request_port, 1536 .request_port = mpsc_request_port,
1631 .config_port = mpsc_config_port, 1537 .config_port = mpsc_config_port,
1632 .verify_port = mpsc_verify_port, 1538 .verify_port = mpsc_verify_port,
1633}; 1539};
1634 1540
1635/* 1541/*
@@ -1641,8 +1547,7 @@ static struct uart_ops mpsc_pops = {
1641 */ 1547 */
1642 1548
1643#ifdef CONFIG_SERIAL_MPSC_CONSOLE 1549#ifdef CONFIG_SERIAL_MPSC_CONSOLE
1644static void 1550static void mpsc_console_write(struct console *co, const char *s, uint count)
1645mpsc_console_write(struct console *co, const char *s, uint count)
1646{ 1551{
1647 struct mpsc_port_info *pi = &mpsc_ports[co->index]; 1552 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1648 u8 *bp, *dp, add_cr = 0; 1553 u8 *bp, *dp, add_cr = 0;
@@ -1671,8 +1576,7 @@ mpsc_console_write(struct console *co, const char *s, uint count)
1671 if (add_cr) { 1576 if (add_cr) {
1672 *(dp++) = '\r'; 1577 *(dp++) = '\r';
1673 add_cr = 0; 1578 add_cr = 0;
1674 } 1579 } else {
1675 else {
1676 *(dp++) = *s; 1580 *(dp++) = *s;
1677 1581
1678 if (*(s++) == '\n') { /* add '\r' after '\n' */ 1582 if (*(s++) == '\n') { /* add '\r' after '\n' */
@@ -1684,11 +1588,12 @@ mpsc_console_write(struct console *co, const char *s, uint count)
1684 count--; 1588 count--;
1685 } 1589 }
1686 1590
1687 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); 1591 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1592 DMA_BIDIRECTIONAL);
1688#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1593#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1689 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1594 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1690 flush_dcache_range((ulong)bp, 1595 flush_dcache_range((ulong)bp,
1691 (ulong)bp + MPSC_TXBE_SIZE); 1596 (ulong)bp + MPSC_TXBE_SIZE);
1692#endif 1597#endif
1693 mpsc_setup_tx_desc(pi, i, 0); 1598 mpsc_setup_tx_desc(pi, i, 0);
1694 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); 1599 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
@@ -1701,11 +1606,9 @@ mpsc_console_write(struct console *co, const char *s, uint count)
1701 } 1606 }
1702 1607
1703 spin_unlock_irqrestore(&pi->tx_lock, iflags); 1608 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1704 return;
1705} 1609}
1706 1610
1707static int __init 1611static int __init mpsc_console_setup(struct console *co, char *options)
1708mpsc_console_setup(struct console *co, char *options)
1709{ 1612{
1710 struct mpsc_port_info *pi; 1613 struct mpsc_port_info *pi;
1711 int baud, bits, parity, flow; 1614 int baud, bits, parity, flow;
@@ -1734,17 +1637,16 @@ mpsc_console_setup(struct console *co, char *options)
1734} 1637}
1735 1638
1736static struct console mpsc_console = { 1639static struct console mpsc_console = {
1737 .name = MPSC_DEV_NAME, 1640 .name = MPSC_DEV_NAME,
1738 .write = mpsc_console_write, 1641 .write = mpsc_console_write,
1739 .device = uart_console_device, 1642 .device = uart_console_device,
1740 .setup = mpsc_console_setup, 1643 .setup = mpsc_console_setup,
1741 .flags = CON_PRINTBUFFER, 1644 .flags = CON_PRINTBUFFER,
1742 .index = -1, 1645 .index = -1,
1743 .data = &mpsc_reg, 1646 .data = &mpsc_reg,
1744}; 1647};
1745 1648
1746static int __init 1649static int __init mpsc_late_console_init(void)
1747mpsc_late_console_init(void)
1748{ 1650{
1749 pr_debug("mpsc_late_console_init: Enter\n"); 1651 pr_debug("mpsc_late_console_init: Enter\n");
1750 1652
@@ -1766,43 +1668,40 @@ late_initcall(mpsc_late_console_init);
1766 * 1668 *
1767 ****************************************************************************** 1669 ******************************************************************************
1768 */ 1670 */
1769static void 1671static void mpsc_resource_err(char *s)
1770mpsc_resource_err(char *s)
1771{ 1672{
1772 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s); 1673 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1773 return;
1774} 1674}
1775 1675
1776static int 1676static int mpsc_shared_map_regs(struct platform_device *pd)
1777mpsc_shared_map_regs(struct platform_device *pd)
1778{ 1677{
1779 struct resource *r; 1678 struct resource *r;
1780 1679
1781 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 1680 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1782 MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start, 1681 MPSC_ROUTING_BASE_ORDER))
1783 MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) { 1682 && request_mem_region(r->start,
1784 1683 MPSC_ROUTING_REG_BLOCK_SIZE,
1684 "mpsc_routing_regs")) {
1785 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start, 1685 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1786 MPSC_ROUTING_REG_BLOCK_SIZE); 1686 MPSC_ROUTING_REG_BLOCK_SIZE);
1787 mpsc_shared_regs.mpsc_routing_base_p = r->start; 1687 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1788 } 1688 } else {
1789 else {
1790 mpsc_resource_err("MPSC routing base"); 1689 mpsc_resource_err("MPSC routing base");
1791 return -ENOMEM; 1690 return -ENOMEM;
1792 } 1691 }
1793 1692
1794 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 1693 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1795 MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start, 1694 MPSC_SDMA_INTR_BASE_ORDER))
1796 MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) { 1695 && request_mem_region(r->start,
1797 1696 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1697 "sdma_intr_regs")) {
1798 mpsc_shared_regs.sdma_intr_base = ioremap(r->start, 1698 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1799 MPSC_SDMA_INTR_REG_BLOCK_SIZE); 1699 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1800 mpsc_shared_regs.sdma_intr_base_p = r->start; 1700 mpsc_shared_regs.sdma_intr_base_p = r->start;
1801 } 1701 } else {
1802 else {
1803 iounmap(mpsc_shared_regs.mpsc_routing_base); 1702 iounmap(mpsc_shared_regs.mpsc_routing_base);
1804 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, 1703 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1805 MPSC_ROUTING_REG_BLOCK_SIZE); 1704 MPSC_ROUTING_REG_BLOCK_SIZE);
1806 mpsc_resource_err("SDMA intr base"); 1705 mpsc_resource_err("SDMA intr base");
1807 return -ENOMEM; 1706 return -ENOMEM;
1808 } 1707 }
@@ -1810,18 +1709,17 @@ mpsc_shared_map_regs(struct platform_device *pd)
1810 return 0; 1709 return 0;
1811} 1710}
1812 1711
1813static void 1712static void mpsc_shared_unmap_regs(void)
1814mpsc_shared_unmap_regs(void)
1815{ 1713{
1816 if (!mpsc_shared_regs.mpsc_routing_base) { 1714 if (!mpsc_shared_regs.mpsc_routing_base) {
1817 iounmap(mpsc_shared_regs.mpsc_routing_base); 1715 iounmap(mpsc_shared_regs.mpsc_routing_base);
1818 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, 1716 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1819 MPSC_ROUTING_REG_BLOCK_SIZE); 1717 MPSC_ROUTING_REG_BLOCK_SIZE);
1820 } 1718 }
1821 if (!mpsc_shared_regs.sdma_intr_base) { 1719 if (!mpsc_shared_regs.sdma_intr_base) {
1822 iounmap(mpsc_shared_regs.sdma_intr_base); 1720 iounmap(mpsc_shared_regs.sdma_intr_base);
1823 release_mem_region(mpsc_shared_regs.sdma_intr_base_p, 1721 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1824 MPSC_SDMA_INTR_REG_BLOCK_SIZE); 1722 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1825 } 1723 }
1826 1724
1827 mpsc_shared_regs.mpsc_routing_base = NULL; 1725 mpsc_shared_regs.mpsc_routing_base = NULL;
@@ -1829,19 +1727,17 @@ mpsc_shared_unmap_regs(void)
1829 1727
1830 mpsc_shared_regs.mpsc_routing_base_p = 0; 1728 mpsc_shared_regs.mpsc_routing_base_p = 0;
1831 mpsc_shared_regs.sdma_intr_base_p = 0; 1729 mpsc_shared_regs.sdma_intr_base_p = 0;
1832
1833 return;
1834} 1730}
1835 1731
1836static int 1732static int mpsc_shared_drv_probe(struct platform_device *dev)
1837mpsc_shared_drv_probe(struct platform_device *dev)
1838{ 1733{
1839 struct mpsc_shared_pdata *pdata; 1734 struct mpsc_shared_pdata *pdata;
1840 int rc = -ENODEV; 1735 int rc = -ENODEV;
1841 1736
1842 if (dev->id == 0) { 1737 if (dev->id == 0) {
1843 if (!(rc = mpsc_shared_map_regs(dev))) { 1738 if (!(rc = mpsc_shared_map_regs(dev))) {
1844 pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data; 1739 pdata = (struct mpsc_shared_pdata *)
1740 dev->dev.platform_data;
1845 1741
1846 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val; 1742 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1847 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val; 1743 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
@@ -1858,8 +1754,7 @@ mpsc_shared_drv_probe(struct platform_device *dev)
1858 return rc; 1754 return rc;
1859} 1755}
1860 1756
1861static int 1757static int mpsc_shared_drv_remove(struct platform_device *dev)
1862mpsc_shared_drv_remove(struct platform_device *dev)
1863{ 1758{
1864 int rc = -ENODEV; 1759 int rc = -ENODEV;
1865 1760
@@ -1880,7 +1775,7 @@ static struct platform_driver mpsc_shared_driver = {
1880 .probe = mpsc_shared_drv_probe, 1775 .probe = mpsc_shared_drv_probe,
1881 .remove = mpsc_shared_drv_remove, 1776 .remove = mpsc_shared_drv_remove,
1882 .driver = { 1777 .driver = {
1883 .name = MPSC_SHARED_NAME, 1778 .name = MPSC_SHARED_NAME,
1884 }, 1779 },
1885}; 1780};
1886 1781
@@ -1892,55 +1787,51 @@ static struct platform_driver mpsc_shared_driver = {
1892 ****************************************************************************** 1787 ******************************************************************************
1893 */ 1788 */
1894static struct uart_driver mpsc_reg = { 1789static struct uart_driver mpsc_reg = {
1895 .owner = THIS_MODULE, 1790 .owner = THIS_MODULE,
1896 .driver_name = MPSC_DRIVER_NAME, 1791 .driver_name = MPSC_DRIVER_NAME,
1897 .dev_name = MPSC_DEV_NAME, 1792 .dev_name = MPSC_DEV_NAME,
1898 .major = MPSC_MAJOR, 1793 .major = MPSC_MAJOR,
1899 .minor = MPSC_MINOR_START, 1794 .minor = MPSC_MINOR_START,
1900 .nr = MPSC_NUM_CTLRS, 1795 .nr = MPSC_NUM_CTLRS,
1901 .cons = MPSC_CONSOLE, 1796 .cons = MPSC_CONSOLE,
1902}; 1797};
1903 1798
1904static int 1799static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1905mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd) 1800 struct platform_device *pd)
1906{ 1801{
1907 struct resource *r; 1802 struct resource *r;
1908 1803
1909 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) && 1804 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1910 request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){ 1805 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1911 1806 "mpsc_regs")) {
1912 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); 1807 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1913 pi->mpsc_base_p = r->start; 1808 pi->mpsc_base_p = r->start;
1914 } 1809 } else {
1915 else {
1916 mpsc_resource_err("MPSC base"); 1810 mpsc_resource_err("MPSC base");
1917 return -ENOMEM; 1811 goto err;
1918 } 1812 }
1919 1813
1920 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 1814 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1921 MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start, 1815 MPSC_SDMA_BASE_ORDER))
1922 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) { 1816 && request_mem_region(r->start,
1923 1817 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1924 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); 1818 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1925 pi->sdma_base_p = r->start; 1819 pi->sdma_base_p = r->start;
1926 } 1820 } else {
1927 else {
1928 mpsc_resource_err("SDMA base"); 1821 mpsc_resource_err("SDMA base");
1929 if (pi->mpsc_base) { 1822 if (pi->mpsc_base) {
1930 iounmap(pi->mpsc_base); 1823 iounmap(pi->mpsc_base);
1931 pi->mpsc_base = NULL; 1824 pi->mpsc_base = NULL;
1932 } 1825 }
1933 return -ENOMEM; 1826 goto err;
1934 } 1827 }
1935 1828
1936 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER)) 1829 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1937 && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE, 1830 && request_mem_region(r->start,
1938 "brg_regs")) { 1831 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1939
1940 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); 1832 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1941 pi->brg_base_p = r->start; 1833 pi->brg_base_p = r->start;
1942 } 1834 } else {
1943 else {
1944 mpsc_resource_err("BRG base"); 1835 mpsc_resource_err("BRG base");
1945 if (pi->mpsc_base) { 1836 if (pi->mpsc_base) {
1946 iounmap(pi->mpsc_base); 1837 iounmap(pi->mpsc_base);
@@ -1950,14 +1841,15 @@ mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
1950 iounmap(pi->sdma_base); 1841 iounmap(pi->sdma_base);
1951 pi->sdma_base = NULL; 1842 pi->sdma_base = NULL;
1952 } 1843 }
1953 return -ENOMEM; 1844 goto err;
1954 } 1845 }
1955
1956 return 0; 1846 return 0;
1847
1848err:
1849 return -ENOMEM;
1957} 1850}
1958 1851
1959static void 1852static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1960mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1961{ 1853{
1962 if (!pi->mpsc_base) { 1854 if (!pi->mpsc_base) {
1963 iounmap(pi->mpsc_base); 1855 iounmap(pi->mpsc_base);
@@ -1979,13 +1871,10 @@ mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1979 pi->mpsc_base_p = 0; 1871 pi->mpsc_base_p = 0;
1980 pi->sdma_base_p = 0; 1872 pi->sdma_base_p = 0;
1981 pi->brg_base_p = 0; 1873 pi->brg_base_p = 0;
1982
1983 return;
1984} 1874}
1985 1875
1986static void 1876static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
1987mpsc_drv_get_platform_data(struct mpsc_port_info *pi, 1877 struct platform_device *pd, int num)
1988 struct platform_device *pd, int num)
1989{ 1878{
1990 struct mpsc_pdata *pdata; 1879 struct mpsc_pdata *pdata;
1991 1880
@@ -2020,12 +1909,9 @@ mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2020 pi->shared_regs = &mpsc_shared_regs; 1909 pi->shared_regs = &mpsc_shared_regs;
2021 1910
2022 pi->port.irq = platform_get_irq(pd, 0); 1911 pi->port.irq = platform_get_irq(pd, 0);
2023
2024 return;
2025} 1912}
2026 1913
2027static int 1914static int mpsc_drv_probe(struct platform_device *dev)
2028mpsc_drv_probe(struct platform_device *dev)
2029{ 1915{
2030 struct mpsc_port_info *pi; 1916 struct mpsc_port_info *pi;
2031 int rc = -ENODEV; 1917 int rc = -ENODEV;
@@ -2041,47 +1927,46 @@ mpsc_drv_probe(struct platform_device *dev)
2041 if (!(rc = mpsc_make_ready(pi))) { 1927 if (!(rc = mpsc_make_ready(pi))) {
2042 spin_lock_init(&pi->tx_lock); 1928 spin_lock_init(&pi->tx_lock);
2043 if (!(rc = uart_add_one_port(&mpsc_reg, 1929 if (!(rc = uart_add_one_port(&mpsc_reg,
2044 &pi->port))) 1930 &pi->port))) {
2045 rc = 0; 1931 rc = 0;
2046 else { 1932 } else {
2047 mpsc_release_port( 1933 mpsc_release_port((struct uart_port *)
2048 (struct uart_port *)pi); 1934 pi);
2049 mpsc_drv_unmap_regs(pi); 1935 mpsc_drv_unmap_regs(pi);
2050 } 1936 }
2051 } 1937 } else {
2052 else
2053 mpsc_drv_unmap_regs(pi); 1938 mpsc_drv_unmap_regs(pi);
1939 }
2054 } 1940 }
2055 } 1941 }
2056 1942
2057 return rc; 1943 return rc;
2058} 1944}
2059 1945
2060static int 1946static int mpsc_drv_remove(struct platform_device *dev)
2061mpsc_drv_remove(struct platform_device *dev)
2062{ 1947{
2063 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id); 1948 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2064 1949
2065 if (dev->id < MPSC_NUM_CTLRS) { 1950 if (dev->id < MPSC_NUM_CTLRS) {
2066 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port); 1951 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2067 mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port); 1952 mpsc_release_port((struct uart_port *)
1953 &mpsc_ports[dev->id].port);
2068 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]); 1954 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2069 return 0; 1955 return 0;
2070 } 1956 } else {
2071 else
2072 return -ENODEV; 1957 return -ENODEV;
1958 }
2073} 1959}
2074 1960
2075static struct platform_driver mpsc_driver = { 1961static struct platform_driver mpsc_driver = {
2076 .probe = mpsc_drv_probe, 1962 .probe = mpsc_drv_probe,
2077 .remove = mpsc_drv_remove, 1963 .remove = mpsc_drv_remove,
2078 .driver = { 1964 .driver = {
2079 .name = MPSC_CTLR_NAME, 1965 .name = MPSC_CTLR_NAME,
2080 }, 1966 },
2081}; 1967};
2082 1968
2083static int __init 1969static int __init mpsc_drv_init(void)
2084mpsc_drv_init(void)
2085{ 1970{
2086 int rc; 1971 int rc;
2087 1972
@@ -2096,24 +1981,21 @@ mpsc_drv_init(void)
2096 platform_driver_unregister(&mpsc_shared_driver); 1981 platform_driver_unregister(&mpsc_shared_driver);
2097 uart_unregister_driver(&mpsc_reg); 1982 uart_unregister_driver(&mpsc_reg);
2098 } 1983 }
2099 } 1984 } else {
2100 else
2101 uart_unregister_driver(&mpsc_reg); 1985 uart_unregister_driver(&mpsc_reg);
1986 }
2102 } 1987 }
2103 1988
2104 return rc; 1989 return rc;
2105
2106} 1990}
2107 1991
2108static void __exit 1992static void __exit mpsc_drv_exit(void)
2109mpsc_drv_exit(void)
2110{ 1993{
2111 platform_driver_unregister(&mpsc_driver); 1994 platform_driver_unregister(&mpsc_driver);
2112 platform_driver_unregister(&mpsc_shared_driver); 1995 platform_driver_unregister(&mpsc_shared_driver);
2113 uart_unregister_driver(&mpsc_reg); 1996 uart_unregister_driver(&mpsc_reg);
2114 memset(mpsc_ports, 0, sizeof(mpsc_ports)); 1997 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2115 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); 1998 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2116 return;
2117} 1999}
2118 2000
2119module_init(mpsc_drv_init); 2001module_init(mpsc_drv_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 04:36:41 -0400