diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2007-04-22 06:55:59 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-04-22 06:55:59 -0400 |
commit | 1b0646a033c370d6c7f5390f2cb452cc1884bb5b (patch) | |
tree | 184b94140fe78452ce69d05c968ae829d028597e /drivers/serial | |
parent | 7531a1c2c4477f63688871c1648d828f55313d42 (diff) |
[ARM] Convert AMBA PL010 driver to use 'uart_amba_port'
Use a pointer to struct uart_amba_port throughout the driver
rather than a mixture of that and struct uart_port.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/amba-pl010.c | 258 |
1 files changed, 134 insertions, 124 deletions
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c index f69bd097166e..ea49aafd66bf 100644 --- a/drivers/serial/amba-pl010.c +++ b/drivers/serial/amba-pl010.c | |||
@@ -77,73 +77,77 @@ struct uart_amba_port { | |||
77 | 77 | ||
78 | static void pl010_stop_tx(struct uart_port *port) | 78 | static void pl010_stop_tx(struct uart_port *port) |
79 | { | 79 | { |
80 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
80 | unsigned int cr; | 81 | unsigned int cr; |
81 | 82 | ||
82 | cr = readb(port->membase + UART010_CR); | 83 | cr = readb(uap->port.membase + UART010_CR); |
83 | cr &= ~UART010_CR_TIE; | 84 | cr &= ~UART010_CR_TIE; |
84 | writel(cr, port->membase + UART010_CR); | 85 | writel(cr, uap->port.membase + UART010_CR); |
85 | } | 86 | } |
86 | 87 | ||
87 | static void pl010_start_tx(struct uart_port *port) | 88 | static void pl010_start_tx(struct uart_port *port) |
88 | { | 89 | { |
90 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
89 | unsigned int cr; | 91 | unsigned int cr; |
90 | 92 | ||
91 | cr = readb(port->membase + UART010_CR); | 93 | cr = readb(uap->port.membase + UART010_CR); |
92 | cr |= UART010_CR_TIE; | 94 | cr |= UART010_CR_TIE; |
93 | writel(cr, port->membase + UART010_CR); | 95 | writel(cr, uap->port.membase + UART010_CR); |
94 | } | 96 | } |
95 | 97 | ||
96 | static void pl010_stop_rx(struct uart_port *port) | 98 | static void pl010_stop_rx(struct uart_port *port) |
97 | { | 99 | { |
100 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
98 | unsigned int cr; | 101 | unsigned int cr; |
99 | 102 | ||
100 | cr = readb(port->membase + UART010_CR); | 103 | cr = readb(uap->port.membase + UART010_CR); |
101 | cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); | 104 | cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); |
102 | writel(cr, port->membase + UART010_CR); | 105 | writel(cr, uap->port.membase + UART010_CR); |
103 | } | 106 | } |
104 | 107 | ||
105 | static void pl010_enable_ms(struct uart_port *port) | 108 | static void pl010_enable_ms(struct uart_port *port) |
106 | { | 109 | { |
110 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
107 | unsigned int cr; | 111 | unsigned int cr; |
108 | 112 | ||
109 | cr = readb(port->membase + UART010_CR); | 113 | cr = readb(uap->port.membase + UART010_CR); |
110 | cr |= UART010_CR_MSIE; | 114 | cr |= UART010_CR_MSIE; |
111 | writel(cr, port->membase + UART010_CR); | 115 | writel(cr, uap->port.membase + UART010_CR); |
112 | } | 116 | } |
113 | 117 | ||
114 | static void pl010_rx_chars(struct uart_port *port) | 118 | static void pl010_rx_chars(struct uart_amba_port *uap) |
115 | { | 119 | { |
116 | struct tty_struct *tty = port->info->tty; | 120 | struct tty_struct *tty = uap->port.info->tty; |
117 | unsigned int status, ch, flag, rsr, max_count = 256; | 121 | unsigned int status, ch, flag, rsr, max_count = 256; |
118 | 122 | ||
119 | status = readb(port->membase + UART01x_FR); | 123 | status = readb(uap->port.membase + UART01x_FR); |
120 | while (UART_RX_DATA(status) && max_count--) { | 124 | while (UART_RX_DATA(status) && max_count--) { |
121 | ch = readb(port->membase + UART01x_DR); | 125 | ch = readb(uap->port.membase + UART01x_DR); |
122 | flag = TTY_NORMAL; | 126 | flag = TTY_NORMAL; |
123 | 127 | ||
124 | port->icount.rx++; | 128 | uap->port.icount.rx++; |
125 | 129 | ||
126 | /* | 130 | /* |
127 | * Note that the error handling code is | 131 | * Note that the error handling code is |
128 | * out of the main execution path | 132 | * out of the main execution path |
129 | */ | 133 | */ |
130 | rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX; | 134 | rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; |
131 | if (unlikely(rsr & UART01x_RSR_ANY)) { | 135 | if (unlikely(rsr & UART01x_RSR_ANY)) { |
132 | writel(0, port->membase + UART01x_ECR); | 136 | writel(0, uap->port.membase + UART01x_ECR); |
133 | 137 | ||
134 | if (rsr & UART01x_RSR_BE) { | 138 | if (rsr & UART01x_RSR_BE) { |
135 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); | 139 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); |
136 | port->icount.brk++; | 140 | uap->port.icount.brk++; |
137 | if (uart_handle_break(port)) | 141 | if (uart_handle_break(&uap->port)) |
138 | goto ignore_char; | 142 | goto ignore_char; |
139 | } else if (rsr & UART01x_RSR_PE) | 143 | } else if (rsr & UART01x_RSR_PE) |
140 | port->icount.parity++; | 144 | uap->port.icount.parity++; |
141 | else if (rsr & UART01x_RSR_FE) | 145 | else if (rsr & UART01x_RSR_FE) |
142 | port->icount.frame++; | 146 | uap->port.icount.frame++; |
143 | if (rsr & UART01x_RSR_OE) | 147 | if (rsr & UART01x_RSR_OE) |
144 | port->icount.overrun++; | 148 | uap->port.icount.overrun++; |
145 | 149 | ||
146 | rsr &= port->read_status_mask; | 150 | rsr &= uap->port.read_status_mask; |
147 | 151 | ||
148 | if (rsr & UART01x_RSR_BE) | 152 | if (rsr & UART01x_RSR_BE) |
149 | flag = TTY_BREAK; | 153 | flag = TTY_BREAK; |
@@ -153,53 +157,52 @@ static void pl010_rx_chars(struct uart_port *port) | |||
153 | flag = TTY_FRAME; | 157 | flag = TTY_FRAME; |
154 | } | 158 | } |
155 | 159 | ||
156 | if (uart_handle_sysrq_char(port, ch)) | 160 | if (uart_handle_sysrq_char(&uap->port, ch)) |
157 | goto ignore_char; | 161 | goto ignore_char; |
158 | 162 | ||
159 | uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag); | 163 | uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); |
160 | 164 | ||
161 | ignore_char: | 165 | ignore_char: |
162 | status = readb(port->membase + UART01x_FR); | 166 | status = readb(uap->port.membase + UART01x_FR); |
163 | } | 167 | } |
164 | tty_flip_buffer_push(tty); | 168 | tty_flip_buffer_push(tty); |
165 | return; | 169 | return; |
166 | } | 170 | } |
167 | 171 | ||
168 | static void pl010_tx_chars(struct uart_port *port) | 172 | static void pl010_tx_chars(struct uart_amba_port *uap) |
169 | { | 173 | { |
170 | struct circ_buf *xmit = &port->info->xmit; | 174 | struct circ_buf *xmit = &uap->port.info->xmit; |
171 | int count; | 175 | int count; |
172 | 176 | ||
173 | if (port->x_char) { | 177 | if (uap->port.x_char) { |
174 | writel(port->x_char, port->membase + UART01x_DR); | 178 | writel(uap->port.x_char, uap->port.membase + UART01x_DR); |
175 | port->icount.tx++; | 179 | uap->port.icount.tx++; |
176 | port->x_char = 0; | 180 | uap->port.x_char = 0; |
177 | return; | 181 | return; |
178 | } | 182 | } |
179 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | 183 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
180 | pl010_stop_tx(port); | 184 | pl010_stop_tx(&uap->port); |
181 | return; | 185 | return; |
182 | } | 186 | } |
183 | 187 | ||
184 | count = port->fifosize >> 1; | 188 | count = uap->port.fifosize >> 1; |
185 | do { | 189 | do { |
186 | writel(xmit->buf[xmit->tail], port->membase + UART01x_DR); | 190 | writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); |
187 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | 191 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
188 | port->icount.tx++; | 192 | uap->port.icount.tx++; |
189 | if (uart_circ_empty(xmit)) | 193 | if (uart_circ_empty(xmit)) |
190 | break; | 194 | break; |
191 | } while (--count > 0); | 195 | } while (--count > 0); |
192 | 196 | ||
193 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | 197 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
194 | uart_write_wakeup(port); | 198 | uart_write_wakeup(&uap->port); |
195 | 199 | ||
196 | if (uart_circ_empty(xmit)) | 200 | if (uart_circ_empty(xmit)) |
197 | pl010_stop_tx(port); | 201 | pl010_stop_tx(&uap->port); |
198 | } | 202 | } |
199 | 203 | ||
200 | static void pl010_modem_status(struct uart_port *port) | 204 | static void pl010_modem_status(struct uart_amba_port *uap) |
201 | { | 205 | { |
202 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
203 | unsigned int status, delta; | 206 | unsigned int status, delta; |
204 | 207 | ||
205 | writel(0, uap->port.membase + UART010_ICR); | 208 | writel(0, uap->port.membase + UART010_ICR); |
@@ -226,47 +229,50 @@ static void pl010_modem_status(struct uart_port *port) | |||
226 | 229 | ||
227 | static irqreturn_t pl010_int(int irq, void *dev_id) | 230 | static irqreturn_t pl010_int(int irq, void *dev_id) |
228 | { | 231 | { |
229 | struct uart_port *port = dev_id; | 232 | struct uart_amba_port *uap = dev_id; |
230 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; | 233 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
231 | int handled = 0; | 234 | int handled = 0; |
232 | 235 | ||
233 | spin_lock(&port->lock); | 236 | spin_lock(&uap->port.lock); |
234 | 237 | ||
235 | status = readb(port->membase + UART010_IIR); | 238 | status = readb(uap->port.membase + UART010_IIR); |
236 | if (status) { | 239 | if (status) { |
237 | do { | 240 | do { |
238 | if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) | 241 | if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) |
239 | pl010_rx_chars(port); | 242 | pl010_rx_chars(uap); |
240 | if (status & UART010_IIR_MIS) | 243 | if (status & UART010_IIR_MIS) |
241 | pl010_modem_status(port); | 244 | pl010_modem_status(uap); |
242 | if (status & UART010_IIR_TIS) | 245 | if (status & UART010_IIR_TIS) |
243 | pl010_tx_chars(port); | 246 | pl010_tx_chars(uap); |
244 | 247 | ||
245 | if (pass_counter-- == 0) | 248 | if (pass_counter-- == 0) |
246 | break; | 249 | break; |
247 | 250 | ||
248 | status = readb(port->membase + UART010_IIR); | 251 | status = readb(uap->port.membase + UART010_IIR); |
249 | } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | | 252 | } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | |
250 | UART010_IIR_TIS)); | 253 | UART010_IIR_TIS)); |
251 | handled = 1; | 254 | handled = 1; |
252 | } | 255 | } |
253 | 256 | ||
254 | spin_unlock(&port->lock); | 257 | spin_unlock(&uap->port.lock); |
255 | 258 | ||
256 | return IRQ_RETVAL(handled); | 259 | return IRQ_RETVAL(handled); |
257 | } | 260 | } |
258 | 261 | ||
259 | static unsigned int pl010_tx_empty(struct uart_port *port) | 262 | static unsigned int pl010_tx_empty(struct uart_port *port) |
260 | { | 263 | { |
261 | return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; | 264 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
265 | unsigned int status = readb(uap->port.membase + UART01x_FR); | ||
266 | return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; | ||
262 | } | 267 | } |
263 | 268 | ||
264 | static unsigned int pl010_get_mctrl(struct uart_port *port) | 269 | static unsigned int pl010_get_mctrl(struct uart_port *port) |
265 | { | 270 | { |
271 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
266 | unsigned int result = 0; | 272 | unsigned int result = 0; |
267 | unsigned int status; | 273 | unsigned int status; |
268 | 274 | ||
269 | status = readb(port->membase + UART01x_FR); | 275 | status = readb(uap->port.membase + UART01x_FR); |
270 | if (status & UART01x_FR_DCD) | 276 | if (status & UART01x_FR_DCD) |
271 | result |= TIOCM_CAR; | 277 | result |= TIOCM_CAR; |
272 | if (status & UART01x_FR_DSR) | 278 | if (status & UART01x_FR_DSR) |
@@ -287,17 +293,18 @@ static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
287 | 293 | ||
288 | static void pl010_break_ctl(struct uart_port *port, int break_state) | 294 | static void pl010_break_ctl(struct uart_port *port, int break_state) |
289 | { | 295 | { |
296 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
290 | unsigned long flags; | 297 | unsigned long flags; |
291 | unsigned int lcr_h; | 298 | unsigned int lcr_h; |
292 | 299 | ||
293 | spin_lock_irqsave(&port->lock, flags); | 300 | spin_lock_irqsave(&uap->port.lock, flags); |
294 | lcr_h = readb(port->membase + UART010_LCRH); | 301 | lcr_h = readb(uap->port.membase + UART010_LCRH); |
295 | if (break_state == -1) | 302 | if (break_state == -1) |
296 | lcr_h |= UART01x_LCRH_BRK; | 303 | lcr_h |= UART01x_LCRH_BRK; |
297 | else | 304 | else |
298 | lcr_h &= ~UART01x_LCRH_BRK; | 305 | lcr_h &= ~UART01x_LCRH_BRK; |
299 | writel(lcr_h, port->membase + UART010_LCRH); | 306 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
300 | spin_unlock_irqrestore(&port->lock, flags); | 307 | spin_unlock_irqrestore(&uap->port.lock, flags); |
301 | } | 308 | } |
302 | 309 | ||
303 | static int pl010_startup(struct uart_port *port) | 310 | static int pl010_startup(struct uart_port *port) |
@@ -308,46 +315,49 @@ static int pl010_startup(struct uart_port *port) | |||
308 | /* | 315 | /* |
309 | * Allocate the IRQ | 316 | * Allocate the IRQ |
310 | */ | 317 | */ |
311 | retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port); | 318 | retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); |
312 | if (retval) | 319 | if (retval) |
313 | return retval; | 320 | return retval; |
314 | 321 | ||
315 | /* | 322 | /* |
316 | * initialise the old status of the modem signals | 323 | * initialise the old status of the modem signals |
317 | */ | 324 | */ |
318 | uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | 325 | uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
319 | 326 | ||
320 | /* | 327 | /* |
321 | * Finally, enable interrupts | 328 | * Finally, enable interrupts |
322 | */ | 329 | */ |
323 | writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, | 330 | writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, |
324 | port->membase + UART010_CR); | 331 | uap->port.membase + UART010_CR); |
325 | 332 | ||
326 | return 0; | 333 | return 0; |
327 | } | 334 | } |
328 | 335 | ||
329 | static void pl010_shutdown(struct uart_port *port) | 336 | static void pl010_shutdown(struct uart_port *port) |
330 | { | 337 | { |
338 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
339 | |||
331 | /* | 340 | /* |
332 | * Free the interrupt | 341 | * Free the interrupt |
333 | */ | 342 | */ |
334 | free_irq(port->irq, port); | 343 | free_irq(uap->port.irq, uap); |
335 | 344 | ||
336 | /* | 345 | /* |
337 | * disable all interrupts, disable the port | 346 | * disable all interrupts, disable the port |
338 | */ | 347 | */ |
339 | writel(0, port->membase + UART010_CR); | 348 | writel(0, uap->port.membase + UART010_CR); |
340 | 349 | ||
341 | /* disable break condition and fifos */ | 350 | /* disable break condition and fifos */ |
342 | writel(readb(port->membase + UART010_LCRH) & | 351 | writel(readb(uap->port.membase + UART010_LCRH) & |
343 | ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), | 352 | ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), |
344 | port->membase + UART010_LCRH); | 353 | uap->port.membase + UART010_LCRH); |
345 | } | 354 | } |
346 | 355 | ||
347 | static void | 356 | static void |
348 | pl010_set_termios(struct uart_port *port, struct ktermios *termios, | 357 | pl010_set_termios(struct uart_port *port, struct ktermios *termios, |
349 | struct ktermios *old) | 358 | struct ktermios *old) |
350 | { | 359 | { |
360 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
351 | unsigned int lcr_h, old_cr; | 361 | unsigned int lcr_h, old_cr; |
352 | unsigned long flags; | 362 | unsigned long flags; |
353 | unsigned int baud, quot; | 363 | unsigned int baud, quot; |
@@ -355,7 +365,7 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios, | |||
355 | /* | 365 | /* |
356 | * Ask the core to calculate the divisor for us. | 366 | * Ask the core to calculate the divisor for us. |
357 | */ | 367 | */ |
358 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | 368 | baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); |
359 | quot = uart_get_divisor(port, baud); | 369 | quot = uart_get_divisor(port, baud); |
360 | 370 | ||
361 | switch (termios->c_cflag & CSIZE) { | 371 | switch (termios->c_cflag & CSIZE) { |
@@ -379,66 +389,66 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios, | |||
379 | if (!(termios->c_cflag & PARODD)) | 389 | if (!(termios->c_cflag & PARODD)) |
380 | lcr_h |= UART01x_LCRH_EPS; | 390 | lcr_h |= UART01x_LCRH_EPS; |
381 | } | 391 | } |
382 | if (port->fifosize > 1) | 392 | if (uap->port.fifosize > 1) |
383 | lcr_h |= UART01x_LCRH_FEN; | 393 | lcr_h |= UART01x_LCRH_FEN; |
384 | 394 | ||
385 | spin_lock_irqsave(&port->lock, flags); | 395 | spin_lock_irqsave(&uap->port.lock, flags); |
386 | 396 | ||
387 | /* | 397 | /* |
388 | * Update the per-port timeout. | 398 | * Update the per-port timeout. |
389 | */ | 399 | */ |
390 | uart_update_timeout(port, termios->c_cflag, baud); | 400 | uart_update_timeout(port, termios->c_cflag, baud); |
391 | 401 | ||
392 | port->read_status_mask = UART01x_RSR_OE; | 402 | uap->port.read_status_mask = UART01x_RSR_OE; |
393 | if (termios->c_iflag & INPCK) | 403 | if (termios->c_iflag & INPCK) |
394 | port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | 404 | uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
395 | if (termios->c_iflag & (BRKINT | PARMRK)) | 405 | if (termios->c_iflag & (BRKINT | PARMRK)) |
396 | port->read_status_mask |= UART01x_RSR_BE; | 406 | uap->port.read_status_mask |= UART01x_RSR_BE; |
397 | 407 | ||
398 | /* | 408 | /* |
399 | * Characters to ignore | 409 | * Characters to ignore |
400 | */ | 410 | */ |
401 | port->ignore_status_mask = 0; | 411 | uap->port.ignore_status_mask = 0; |
402 | if (termios->c_iflag & IGNPAR) | 412 | if (termios->c_iflag & IGNPAR) |
403 | port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | 413 | uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
404 | if (termios->c_iflag & IGNBRK) { | 414 | if (termios->c_iflag & IGNBRK) { |
405 | port->ignore_status_mask |= UART01x_RSR_BE; | 415 | uap->port.ignore_status_mask |= UART01x_RSR_BE; |
406 | /* | 416 | /* |
407 | * If we're ignoring parity and break indicators, | 417 | * If we're ignoring parity and break indicators, |
408 | * ignore overruns too (for real raw support). | 418 | * ignore overruns too (for real raw support). |
409 | */ | 419 | */ |
410 | if (termios->c_iflag & IGNPAR) | 420 | if (termios->c_iflag & IGNPAR) |
411 | port->ignore_status_mask |= UART01x_RSR_OE; | 421 | uap->port.ignore_status_mask |= UART01x_RSR_OE; |
412 | } | 422 | } |
413 | 423 | ||
414 | /* | 424 | /* |
415 | * Ignore all characters if CREAD is not set. | 425 | * Ignore all characters if CREAD is not set. |
416 | */ | 426 | */ |
417 | if ((termios->c_cflag & CREAD) == 0) | 427 | if ((termios->c_cflag & CREAD) == 0) |
418 | port->ignore_status_mask |= UART_DUMMY_RSR_RX; | 428 | uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; |
419 | 429 | ||
420 | /* first, disable everything */ | 430 | /* first, disable everything */ |
421 | old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE; | 431 | old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; |
422 | 432 | ||
423 | if (UART_ENABLE_MS(port, termios->c_cflag)) | 433 | if (UART_ENABLE_MS(port, termios->c_cflag)) |
424 | old_cr |= UART010_CR_MSIE; | 434 | old_cr |= UART010_CR_MSIE; |
425 | 435 | ||
426 | writel(0, port->membase + UART010_CR); | 436 | writel(0, uap->port.membase + UART010_CR); |
427 | 437 | ||
428 | /* Set baud rate */ | 438 | /* Set baud rate */ |
429 | quot -= 1; | 439 | quot -= 1; |
430 | writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM); | 440 | writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); |
431 | writel(quot & 0xff, port->membase + UART010_LCRL); | 441 | writel(quot & 0xff, uap->port.membase + UART010_LCRL); |
432 | 442 | ||
433 | /* | 443 | /* |
434 | * ----------v----------v----------v----------v----- | 444 | * ----------v----------v----------v----------v----- |
435 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | 445 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L |
436 | * ----------^----------^----------^----------^----- | 446 | * ----------^----------^----------^----------^----- |
437 | */ | 447 | */ |
438 | writel(lcr_h, port->membase + UART010_LCRH); | 448 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
439 | writel(old_cr, port->membase + UART010_CR); | 449 | writel(old_cr, uap->port.membase + UART010_CR); |
440 | 450 | ||
441 | spin_unlock_irqrestore(&port->lock, flags); | 451 | spin_unlock_irqrestore(&uap->port.lock, flags); |
442 | } | 452 | } |
443 | 453 | ||
444 | static const char *pl010_type(struct uart_port *port) | 454 | static const char *pl010_type(struct uart_port *port) |
@@ -514,47 +524,48 @@ static struct uart_amba_port *amba_ports[UART_NR]; | |||
514 | 524 | ||
515 | static void pl010_console_putchar(struct uart_port *port, int ch) | 525 | static void pl010_console_putchar(struct uart_port *port, int ch) |
516 | { | 526 | { |
527 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
517 | unsigned int status; | 528 | unsigned int status; |
518 | 529 | ||
519 | do { | 530 | do { |
520 | status = readb(port->membase + UART01x_FR); | 531 | status = readb(uap->port.membase + UART01x_FR); |
521 | barrier(); | 532 | barrier(); |
522 | } while (!UART_TX_READY(status)); | 533 | } while (!UART_TX_READY(status)); |
523 | writel(ch, port->membase + UART01x_DR); | 534 | writel(ch, uap->port.membase + UART01x_DR); |
524 | } | 535 | } |
525 | 536 | ||
526 | static void | 537 | static void |
527 | pl010_console_write(struct console *co, const char *s, unsigned int count) | 538 | pl010_console_write(struct console *co, const char *s, unsigned int count) |
528 | { | 539 | { |
529 | struct uart_port *port = &amba_ports[co->index]->port; | 540 | struct uart_amba_port *uap = amba_ports[co->index]; |
530 | unsigned int status, old_cr; | 541 | unsigned int status, old_cr; |
531 | 542 | ||
532 | /* | 543 | /* |
533 | * First save the CR then disable the interrupts | 544 | * First save the CR then disable the interrupts |
534 | */ | 545 | */ |
535 | old_cr = readb(port->membase + UART010_CR); | 546 | old_cr = readb(uap->port.membase + UART010_CR); |
536 | writel(UART01x_CR_UARTEN, port->membase + UART010_CR); | 547 | writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); |
537 | 548 | ||
538 | uart_console_write(port, s, count, pl010_console_putchar); | 549 | uart_console_write(&uap->port, s, count, pl010_console_putchar); |
539 | 550 | ||
540 | /* | 551 | /* |
541 | * Finally, wait for transmitter to become empty | 552 | * Finally, wait for transmitter to become empty |
542 | * and restore the TCR | 553 | * and restore the TCR |
543 | */ | 554 | */ |
544 | do { | 555 | do { |
545 | status = readb(port->membase + UART01x_FR); | 556 | status = readb(uap->port.membase + UART01x_FR); |
546 | barrier(); | 557 | barrier(); |
547 | } while (status & UART01x_FR_BUSY); | 558 | } while (status & UART01x_FR_BUSY); |
548 | writel(old_cr, port->membase + UART010_CR); | 559 | writel(old_cr, uap->port.membase + UART010_CR); |
549 | } | 560 | } |
550 | 561 | ||
551 | static void __init | 562 | static void __init |
552 | pl010_console_get_options(struct uart_port *port, int *baud, | 563 | pl010_console_get_options(struct uart_amba_port *uap, int *baud, |
553 | int *parity, int *bits) | 564 | int *parity, int *bits) |
554 | { | 565 | { |
555 | if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) { | 566 | if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { |
556 | unsigned int lcr_h, quot; | 567 | unsigned int lcr_h, quot; |
557 | lcr_h = readb(port->membase + UART010_LCRH); | 568 | lcr_h = readb(uap->port.membase + UART010_LCRH); |
558 | 569 | ||
559 | *parity = 'n'; | 570 | *parity = 'n'; |
560 | if (lcr_h & UART01x_LCRH_PEN) { | 571 | if (lcr_h & UART01x_LCRH_PEN) { |
@@ -569,14 +580,15 @@ pl010_console_get_options(struct uart_port *port, int *baud, | |||
569 | else | 580 | else |
570 | *bits = 8; | 581 | *bits = 8; |
571 | 582 | ||
572 | quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8; | 583 | quot = readb(uap->port.membase + UART010_LCRL) | |
573 | *baud = port->uartclk / (16 * (quot + 1)); | 584 | readb(uap->port.membase + UART010_LCRM) << 8; |
585 | *baud = uap->port.uartclk / (16 * (quot + 1)); | ||
574 | } | 586 | } |
575 | } | 587 | } |
576 | 588 | ||
577 | static int __init pl010_console_setup(struct console *co, char *options) | 589 | static int __init pl010_console_setup(struct console *co, char *options) |
578 | { | 590 | { |
579 | struct uart_port *port; | 591 | struct uart_amba_port *uap; |
580 | int baud = 38400; | 592 | int baud = 38400; |
581 | int bits = 8; | 593 | int bits = 8; |
582 | int parity = 'n'; | 594 | int parity = 'n'; |
@@ -589,16 +601,16 @@ static int __init pl010_console_setup(struct console *co, char *options) | |||
589 | */ | 601 | */ |
590 | if (co->index >= UART_NR) | 602 | if (co->index >= UART_NR) |
591 | co->index = 0; | 603 | co->index = 0; |
592 | if (!amba_ports[co->index]) | 604 | uap = amba_ports[co->index]; |
605 | if (!uap) | ||
593 | return -ENODEV; | 606 | return -ENODEV; |
594 | port = &amba_ports[co->index]->port; | ||
595 | 607 | ||
596 | if (options) | 608 | if (options) |
597 | uart_parse_options(options, &baud, &parity, &bits, &flow); | 609 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
598 | else | 610 | else |
599 | pl010_console_get_options(port, &baud, &parity, &bits); | 611 | pl010_console_get_options(uap, &baud, &parity, &bits); |
600 | 612 | ||
601 | return uart_set_options(port, co, baud, parity, bits, flow); | 613 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); |
602 | } | 614 | } |
603 | 615 | ||
604 | static struct uart_driver amba_reg; | 616 | static struct uart_driver amba_reg; |
@@ -629,7 +641,7 @@ static struct uart_driver amba_reg = { | |||
629 | 641 | ||
630 | static int pl010_probe(struct amba_device *dev, void *id) | 642 | static int pl010_probe(struct amba_device *dev, void *id) |
631 | { | 643 | { |
632 | struct uart_amba_port *port; | 644 | struct uart_amba_port *uap; |
633 | void __iomem *base; | 645 | void __iomem *base; |
634 | int i, ret; | 646 | int i, ret; |
635 | 647 | ||
@@ -642,8 +654,8 @@ static int pl010_probe(struct amba_device *dev, void *id) | |||
642 | goto out; | 654 | goto out; |
643 | } | 655 | } |
644 | 656 | ||
645 | port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); | 657 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
646 | if (!port) { | 658 | if (!uap) { |
647 | ret = -ENOMEM; | 659 | ret = -ENOMEM; |
648 | goto out; | 660 | goto out; |
649 | } | 661 | } |
@@ -654,51 +666,49 @@ static int pl010_probe(struct amba_device *dev, void *id) | |||
654 | goto free; | 666 | goto free; |
655 | } | 667 | } |
656 | 668 | ||
657 | port->port.dev = &dev->dev; | 669 | uap->port.dev = &dev->dev; |
658 | port->port.mapbase = dev->res.start; | 670 | uap->port.mapbase = dev->res.start; |
659 | port->port.membase = base; | 671 | uap->port.membase = base; |
660 | port->port.iotype = UPIO_MEM; | 672 | uap->port.iotype = UPIO_MEM; |
661 | port->port.irq = dev->irq[0]; | 673 | uap->port.irq = dev->irq[0]; |
662 | port->port.uartclk = 14745600; | 674 | uap->port.uartclk = 14745600; |
663 | port->port.fifosize = 16; | 675 | uap->port.fifosize = 16; |
664 | port->port.ops = &amba_pl010_pops; | 676 | uap->port.ops = &amba_pl010_pops; |
665 | port->port.flags = UPF_BOOT_AUTOCONF; | 677 | uap->port.flags = UPF_BOOT_AUTOCONF; |
666 | port->port.line = i; | 678 | uap->port.line = i; |
667 | port->dev = dev; | 679 | uap->dev = dev; |
668 | port->data = dev->dev.platform_data; | 680 | uap->data = dev->dev.platform_data; |
669 | 681 | ||
670 | amba_ports[i] = port; | 682 | amba_ports[i] = uap; |
671 | 683 | ||
672 | amba_set_drvdata(dev, port); | 684 | amba_set_drvdata(dev, uap); |
673 | ret = uart_add_one_port(&amba_reg, &port->port); | 685 | ret = uart_add_one_port(&amba_reg, &uap->port); |
674 | if (ret) { | 686 | if (ret) { |
675 | amba_set_drvdata(dev, NULL); | 687 | amba_set_drvdata(dev, NULL); |
676 | amba_ports[i] = NULL; | 688 | amba_ports[i] = NULL; |
677 | iounmap(base); | 689 | iounmap(base); |
678 | free: | 690 | free: |
679 | kfree(port); | 691 | kfree(uap); |
680 | } | 692 | } |
681 | |||
682 | out: | 693 | out: |
683 | return ret; | 694 | return ret; |
684 | } | 695 | } |
685 | 696 | ||
686 | static int pl010_remove(struct amba_device *dev) | 697 | static int pl010_remove(struct amba_device *dev) |
687 | { | 698 | { |
688 | struct uart_amba_port *port = amba_get_drvdata(dev); | 699 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
689 | int i; | 700 | int i; |
690 | 701 | ||
691 | amba_set_drvdata(dev, NULL); | 702 | amba_set_drvdata(dev, NULL); |
692 | 703 | ||
693 | uart_remove_one_port(&amba_reg, &port->port); | 704 | uart_remove_one_port(&amba_reg, &uap->port); |
694 | 705 | ||
695 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | 706 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
696 | if (amba_ports[i] == port) | 707 | if (amba_ports[i] == uap) |
697 | amba_ports[i] = NULL; | 708 | amba_ports[i] = NULL; |
698 | 709 | ||
699 | iounmap(port->port.membase); | 710 | iounmap(uap->port.membase); |
700 | kfree(port); | 711 | kfree(uap); |
701 | |||
702 | return 0; | 712 | return 0; |
703 | } | 713 | } |
704 | 714 | ||