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authorjianwei.yang <jianwei.yang@intel.com>2010-06-30 12:57:12 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-08-10 16:47:44 -0400
commit44318feb93327e36108b2a9cf94ac9f7ccabf047 (patch)
treebd39b37ae88595f5eef16795361500a05940944c /drivers/serial
parent11dbf203922dc70a340417c895c95fb96f6b7068 (diff)
serial: max3107: introduce a max3107 driver
This device is used by some of the Intel MID platforms. It's not similar enough to the MAX3100 to use the same driver. At this point the driver is specific to the platform and not generalised. We will fix that later. Signed-off-by: jianwei.yang <jianwei.yang@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/Kconfig8
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/max3107.c1442
-rw-r--r--drivers/serial/max3107.h358
4 files changed, 1809 insertions, 0 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 964634e79c16..fd406273cb71 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -542,6 +542,14 @@ config SERIAL_S5PV210
542 help 542 help
543 Serial port support for Samsung's S5P Family of SoC's 543 Serial port support for Samsung's S5P Family of SoC's
544 544
545config SERIAL_MAX3107
546 tristate "MAX3107 support"
547 depends on SPI && GPIOLIB
548 select SERIAL_CORE
549 default y
550 help
551 MAX3107 chip support
552
545config SERIAL_MAX3100 553config SERIAL_MAX3100
546 tristate "MAX3100 support" 554 tristate "MAX3100 support"
547 depends on SPI 555 depends on SPI
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index a5edb49c7303..4cd0c0694917 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
46obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o 46obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
47obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o 47obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o
48obj-$(CONFIG_SERIAL_MAX3100) += max3100.o 48obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
49obj-$(CONFIG_SERIAL_MAX3107) += max3107.o
49obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 50obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
50obj-$(CONFIG_SERIAL_MUX) += mux.o 51obj-$(CONFIG_SERIAL_MUX) += mux.o
51obj-$(CONFIG_SERIAL_68328) += 68328serial.o 52obj-$(CONFIG_SERIAL_68328) += 68328serial.o
diff --git a/drivers/serial/max3107.c b/drivers/serial/max3107.c
new file mode 100644
index 000000000000..a96ddd388ffd
--- /dev/null
+++ b/drivers/serial/max3107.c
@@ -0,0 +1,1442 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/spi/spi.h>
35#include <linux/freezer.h>
36#include <linux/platform_device.h>
37#include <linux/gpio.h>
38#include <linux/sfi.h>
39#include <asm/mrst.h>
40#include "max3107.h"
41
42struct baud_table {
43 int baud;
44 u32 new_brg;
45};
46
47struct max3107_port {
48 /* UART port structure */
49 struct uart_port port;
50
51 /* SPI device structure */
52 struct spi_device *spi;
53
54 /* GPIO chip stucture */
55 struct gpio_chip chip;
56
57 /* Workqueue that does all the magic */
58 struct workqueue_struct *workqueue;
59 struct work_struct work;
60
61 /* Lock for shared data */
62 spinlock_t data_lock;
63
64 /* Device configuration */
65 int ext_clk; /* 1 if external clock used */
66 int loopback; /* Current loopback mode state */
67 int baud; /* Current baud rate */
68
69 /* State flags */
70 int suspended; /* Indicates suspend mode */
71 int tx_fifo_empty; /* Flag for TX FIFO state */
72 int rx_enabled; /* Flag for receiver state */
73 int tx_enabled; /* Flag for transmitter state */
74
75 u16 irqen_reg; /* Current IRQ enable register value */
76 /* Shared data */
77 u16 mode1_reg; /* Current mode1 register value*/
78 int mode1_commit; /* Flag for setting new mode1 register value */
79 u16 lcr_reg; /* Current LCR register value */
80 int lcr_commit; /* Flag for setting new LCR register value */
81 u32 brg_cfg; /* Current Baud rate generator config */
82 int brg_commit; /* Flag for setting new baud rate generator
83 * config
84 */
85 struct baud_table *baud_tbl;
86 int handle_irq; /* Indicates that IRQ should be handled */
87
88 /* Rx buffer and str*/
89 u16 *rxbuf;
90 u8 *rxstr;
91 /* Tx buffer*/
92 u16 *txbuf;
93};
94
95/* Platform data structure */
96struct max3107_plat {
97 /* Loopback mode enable */
98 int loopback;
99 /* External clock enable */
100 int ext_clk;
101 /* HW suspend function */
102 void (*max3107_hw_suspend) (struct max3107_port *s, int suspend);
103 /* Polling mode enable */
104 int polled_mode;
105 /* Polling period if polling mode enabled */
106 int poll_time;
107};
108
109static struct baud_table brg13_ext[] = {
110 { 300, MAX3107_BRG13_B300 },
111 { 600, MAX3107_BRG13_B600 },
112 { 1200, MAX3107_BRG13_B1200 },
113 { 2400, MAX3107_BRG13_B2400 },
114 { 4800, MAX3107_BRG13_B4800 },
115 { 9600, MAX3107_BRG13_B9600 },
116 { 19200, MAX3107_BRG13_B19200 },
117 { 57600, MAX3107_BRG13_B57600 },
118 { 115200, MAX3107_BRG13_B115200 },
119 { 230400, MAX3107_BRG13_B230400 },
120 { 460800, MAX3107_BRG13_B460800 },
121 { 921600, MAX3107_BRG13_B921600 },
122 { 0, 0 }
123};
124
125static struct baud_table brg26_ext[] = {
126 { 300, MAX3107_BRG26_B300 },
127 { 600, MAX3107_BRG26_B600 },
128 { 1200, MAX3107_BRG26_B1200 },
129 { 2400, MAX3107_BRG26_B2400 },
130 { 4800, MAX3107_BRG26_B4800 },
131 { 9600, MAX3107_BRG26_B9600 },
132 { 19200, MAX3107_BRG26_B19200 },
133 { 57600, MAX3107_BRG26_B57600 },
134 { 115200, MAX3107_BRG26_B115200 },
135 { 230400, MAX3107_BRG26_B230400 },
136 { 460800, MAX3107_BRG26_B460800 },
137 { 921600, MAX3107_BRG26_B921600 },
138 { 0, 0 }
139};
140
141static struct baud_table brg13_int[] = {
142 { 300, MAX3107_BRG13_IB300 },
143 { 600, MAX3107_BRG13_IB600 },
144 { 1200, MAX3107_BRG13_IB1200 },
145 { 2400, MAX3107_BRG13_IB2400 },
146 { 4800, MAX3107_BRG13_IB4800 },
147 { 9600, MAX3107_BRG13_IB9600 },
148 { 19200, MAX3107_BRG13_IB19200 },
149 { 57600, MAX3107_BRG13_IB57600 },
150 { 115200, MAX3107_BRG13_IB115200 },
151 { 230400, MAX3107_BRG13_IB230400 },
152 { 460800, MAX3107_BRG13_IB460800 },
153 { 921600, MAX3107_BRG13_IB921600 },
154 { 0, 0 }
155};
156
157static u32 get_new_brg(int baud, struct max3107_port *s)
158{
159 int i;
160 struct baud_table *baud_tbl = s->baud_tbl;
161
162 for (i = 0; i < 13; i++) {
163 if (baud == baud_tbl[i].baud)
164 return baud_tbl[i].new_brg;
165 }
166
167 return 0;
168}
169
170/* Perform SPI transfer for write/read of device register(s) */
171static int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
172{
173 struct spi_message spi_msg;
174 struct spi_transfer spi_xfer;
175
176 /* Initialize SPI ,message */
177 spi_message_init(&spi_msg);
178
179 /* Initialize SPI transfer */
180 memset(&spi_xfer, 0, sizeof spi_xfer);
181 spi_xfer.len = len;
182 spi_xfer.tx_buf = tx;
183 spi_xfer.rx_buf = rx;
184 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
185
186 /* Add SPI transfer to SPI message */
187 spi_message_add_tail(&spi_xfer, &spi_msg);
188
189#ifdef DBG_TRACE_SPI_DATA
190 {
191 int i;
192 pr_info("tx len %d:\n", spi_xfer.len);
193 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
194 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
195 pr_info("\n");
196 }
197#endif
198
199 /* Perform synchronous SPI transfer */
200 if (spi_sync(s->spi, &spi_msg)) {
201 dev_err(&s->spi->dev, "spi_sync failure\n");
202 return -EIO;
203 }
204
205#ifdef DBG_TRACE_SPI_DATA
206 if (spi_xfer.rx_buf) {
207 int i;
208 pr_info("rx len %d:\n", spi_xfer.len);
209 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
210 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
211 pr_info("\n");
212 }
213#endif
214 return 0;
215}
216
217/* Puts received data to circular buffer */
218static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
219 int len)
220{
221 struct uart_port *port = &s->port;
222 struct tty_struct *tty;
223
224 if (!port->state)
225 return;
226
227 tty = port->state->port.tty;
228 if (!tty)
229 return;
230
231 /* Insert received data */
232 tty_insert_flip_string(tty, data, len);
233 /* Update RX counter */
234 port->icount.rx += len;
235}
236
237/* Handle data receiving */
238static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
239{
240 int i;
241 int j;
242 int len; /* SPI transfer buffer length */
243 u16 *buf;
244 u8 *valid_str;
245
246 if (!s->rx_enabled)
247 /* RX is disabled */
248 return;
249
250 if (rxlvl == 0) {
251 /* RX fifo is empty */
252 return;
253 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
254 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
255 /* Ensure sanity of RX level */
256 rxlvl = MAX3107_RX_FIFO_SIZE;
257 }
258 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
259 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
260 return;
261 }
262 buf = s->rxbuf;
263 valid_str = s->rxstr;
264 while (rxlvl) {
265 pr_debug("rxlvl %d\n", rxlvl);
266 /* Clear buffer */
267 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
268 len = 0;
269 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
270 /* First disable RX FIFO interrupt */
271 pr_debug("Disabling RX INT\n");
272 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
273 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
274 buf[0] |= s->irqen_reg;
275 len++;
276 }
277 /* Just increase the length by amount of words in FIFO since
278 * buffer was zeroed and SPI transfer of 0x0000 means reading
279 * from RX FIFO
280 */
281 len += rxlvl;
282 /* Append RX level query */
283 buf[len] = MAX3107_RXFIFOLVL_REG;
284 len++;
285
286 /* Perform the SPI transfer */
287 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
288 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
289 return;
290 }
291
292 /* Skip RX FIFO interrupt disabling word if it was added */
293 j = ((len - 1) - rxlvl);
294 /* Read received words */
295 for (i = 0; i < rxlvl; i++, j++)
296 valid_str[i] = (u8)buf[j];
297 put_data_to_circ_buf(s, valid_str, rxlvl);
298 /* Get new RX level */
299 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
300 }
301
302 if (s->rx_enabled) {
303 /* RX still enabled, re-enable RX FIFO interrupt */
304 pr_debug("Enabling RX INT\n");
305 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
306 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
307 buf[0] |= s->irqen_reg;
308 if (max3107_rw(s, (u8 *)buf, NULL, 2))
309 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
310 }
311
312 /* Push the received data to receivers */
313 if (s->port.state->port.tty)
314 tty_flip_buffer_push(s->port.state->port.tty);
315}
316
317
318/* Handle data sending */
319static void max3107_handletx(struct max3107_port *s)
320{
321 struct circ_buf *xmit = &s->port.state->xmit;
322 int i;
323 unsigned long flags;
324 int len; /* SPI transfer buffer length */
325 u16 *buf;
326
327 if (!s->tx_fifo_empty)
328 /* Don't send more data before previous data is sent */
329 return;
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
332 /* No data to send or TX is stopped */
333 return;
334
335 if (!s->txbuf) {
336 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
337 return;
338 }
339 buf = s->txbuf;
340 /* Get length of data pending in circular buffer */
341 len = uart_circ_chars_pending(xmit);
342 if (len) {
343 /* Limit to size of TX FIFO */
344 if (len > MAX3107_TX_FIFO_SIZE)
345 len = MAX3107_TX_FIFO_SIZE;
346
347 pr_debug("txlen %d\n", len);
348
349 /* Update TX counter */
350 s->port.icount.tx += len;
351
352 /* TX FIFO will no longer be empty */
353 s->tx_fifo_empty = 0;
354
355 i = 0;
356 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
357 /* First disable TX empty interrupt */
358 pr_debug("Disabling TE INT\n");
359 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
360 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
361 buf[i] |= s->irqen_reg;
362 i++;
363 len++;
364 }
365 /* Add data to send */
366 spin_lock_irqsave(&s->port.lock, flags);
367 for ( ; i < len ; i++) {
368 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
369 buf[i] |= ((u16)xmit->buf[xmit->tail] &
370 MAX3107_SPI_TX_DATA_MASK);
371 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
372 }
373 spin_unlock_irqrestore(&s->port.lock, flags);
374 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
375 /* Enable TX empty interrupt */
376 pr_debug("Enabling TE INT\n");
377 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
378 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
379 buf[i] |= s->irqen_reg;
380 i++;
381 len++;
382 }
383 if (!s->tx_enabled) {
384 /* Enable TX */
385 pr_debug("Enable TX\n");
386 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
387 spin_lock_irqsave(&s->data_lock, flags);
388 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
389 buf[i] |= s->mode1_reg;
390 spin_unlock_irqrestore(&s->data_lock, flags);
391 s->tx_enabled = 1;
392 i++;
393 len++;
394 }
395
396 /* Perform the SPI transfer */
397 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
398 dev_err(&s->spi->dev,
399 "SPI transfer TX handling failed\n");
400 return;
401 }
402 }
403
404 /* Indicate wake up if circular buffer is getting low on data */
405 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
406 uart_write_wakeup(&s->port);
407
408}
409
410/* Handle interrupts
411 * Also reads and returns current RX FIFO level
412 */
413static u16 handle_interrupt(struct max3107_port *s)
414{
415 u16 buf[4]; /* Buffer for SPI transfers */
416 u8 irq_status;
417 u16 rx_level;
418 unsigned long flags;
419
420 /* Read IRQ status register */
421 buf[0] = MAX3107_IRQSTS_REG;
422 /* Read status IRQ status register */
423 buf[1] = MAX3107_STS_IRQSTS_REG;
424 /* Read LSR IRQ status register */
425 buf[2] = MAX3107_LSR_IRQSTS_REG;
426 /* Query RX level */
427 buf[3] = MAX3107_RXFIFOLVL_REG;
428
429 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
430 dev_err(&s->spi->dev,
431 "SPI transfer for INTR handling failed\n");
432 return 0;
433 }
434
435 irq_status = (u8)buf[0];
436 pr_debug("IRQSTS %x\n", irq_status);
437 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
438
439 if (irq_status & MAX3107_IRQ_LSR_BIT) {
440 /* LSR interrupt */
441 if (buf[2] & MAX3107_LSR_RXTO_BIT)
442 /* RX timeout interrupt,
443 * handled by normal RX handling
444 */
445 pr_debug("RX TO INT\n");
446 }
447
448 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
449 /* Tx empty interrupt,
450 * disable TX and set tx_fifo_empty flag
451 */
452 pr_debug("TE INT, disabling TX\n");
453 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
454 spin_lock_irqsave(&s->data_lock, flags);
455 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
456 buf[0] |= s->mode1_reg;
457 spin_unlock_irqrestore(&s->data_lock, flags);
458 if (max3107_rw(s, (u8 *)buf, NULL, 2))
459 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
460 s->tx_enabled = 0;
461 s->tx_fifo_empty = 1;
462 }
463
464 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
465 /* RX FIFO interrupt,
466 * handled by normal RX handling
467 */
468 pr_debug("RFIFO INT\n");
469
470 /* Return RX level */
471 return rx_level;
472}
473
474/* Trigger work thread*/
475static void max3107_dowork(struct max3107_port *s)
476{
477 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
478 queue_work(s->workqueue, &s->work);
479 else
480 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
481}
482
483/* Work thread */
484static void max3107_work(struct work_struct *w)
485{
486 struct max3107_port *s = container_of(w, struct max3107_port, work);
487 u16 rxlvl = 0;
488 int len; /* SPI transfer buffer length */
489 u16 buf[5]; /* Buffer for SPI transfers */
490 unsigned long flags;
491
492 /* Start by reading current RX FIFO level */
493 buf[0] = MAX3107_RXFIFOLVL_REG;
494 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
495 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
496 rxlvl = 0;
497 } else {
498 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
499 }
500
501 do {
502 pr_debug("rxlvl %d\n", rxlvl);
503
504 /* Handle RX */
505 max3107_handlerx(s, rxlvl);
506 rxlvl = 0;
507
508 if (s->handle_irq) {
509 /* Handle pending interrupts
510 * We also get new RX FIFO level since new data may
511 * have been received while pushing received data to
512 * receivers
513 */
514 s->handle_irq = 0;
515 rxlvl = handle_interrupt(s);
516 }
517
518 /* Handle TX */
519 max3107_handletx(s);
520
521 /* Handle configuration changes */
522 len = 0;
523 spin_lock_irqsave(&s->data_lock, flags);
524 if (s->mode1_commit) {
525 pr_debug("mode1_commit\n");
526 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
527 buf[len++] |= s->mode1_reg;
528 s->mode1_commit = 0;
529 }
530 if (s->lcr_commit) {
531 pr_debug("lcr_commit\n");
532 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
533 buf[len++] |= s->lcr_reg;
534 s->lcr_commit = 0;
535 }
536 if (s->brg_commit) {
537 pr_debug("brg_commit\n");
538 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
539 buf[len++] |= ((s->brg_cfg >> 16) &
540 MAX3107_SPI_TX_DATA_MASK);
541 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
542 buf[len++] |= ((s->brg_cfg >> 8) &
543 MAX3107_SPI_TX_DATA_MASK);
544 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
545 buf[len++] |= ((s->brg_cfg) & 0xff);
546 s->brg_commit = 0;
547 }
548 spin_unlock_irqrestore(&s->data_lock, flags);
549
550 if (len > 0) {
551 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
552 dev_err(&s->spi->dev,
553 "SPI transfer config failed\n");
554 }
555
556 /* Reloop if interrupt handling indicated data in RX FIFO */
557 } while (rxlvl);
558
559}
560
561/* Set sleep mode */
562static void max3107_set_sleep(struct max3107_port *s, int mode)
563{
564 u16 buf[1]; /* Buffer for SPI transfer */
565 unsigned long flags;
566 pr_debug("enter, mode %d\n", mode);
567
568 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
569 spin_lock_irqsave(&s->data_lock, flags);
570 switch (mode) {
571 case MAX3107_DISABLE_FORCED_SLEEP:
572 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
573 break;
574 case MAX3107_ENABLE_FORCED_SLEEP:
575 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
576 break;
577 case MAX3107_DISABLE_AUTOSLEEP:
578 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
579 break;
580 case MAX3107_ENABLE_AUTOSLEEP:
581 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
582 break;
583 default:
584 spin_unlock_irqrestore(&s->data_lock, flags);
585 dev_warn(&s->spi->dev, "invalid sleep mode\n");
586 return;
587 }
588 buf[0] |= s->mode1_reg;
589 spin_unlock_irqrestore(&s->data_lock, flags);
590
591 if (max3107_rw(s, (u8 *)buf, NULL, 2))
592 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
593
594 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
595 mode == MAX3107_DISABLE_FORCED_SLEEP)
596 msleep(MAX3107_WAKEUP_DELAY);
597}
598
599/* Perform full register initialization */
600static void max3107_register_init(struct max3107_port *s)
601{
602 u16 buf[11]; /* Buffer for SPI transfers */
603
604 /* 1. Configure baud rate, 9600 as default */
605 s->baud = 9600;
606 /* the below is default*/
607 if (s->ext_clk) {
608 s->brg_cfg = MAX3107_BRG26_B9600;
609 s->baud_tbl = (struct baud_table *)brg26_ext;
610 } else {
611 s->brg_cfg = MAX3107_BRG13_IB9600;
612 s->baud_tbl = (struct baud_table *)brg13_int;
613 }
614#if 0
615 /*override for AAVA SC specific*/
616 if (mrst_platform_id() == MRST_PLATFORM_AAVA_SC) {
617 if (get_koski_build_id() <= KOSKI_EV2)
618 if (s->ext_clk) {
619 s->brg_cfg = MAX3107_BRG13_B9600;
620 s->baud_tbl = (struct baud_table *)brg13_ext;
621 }
622 }
623#endif
624 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
625 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
626 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
627 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
628 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
629 | ((s->brg_cfg) & 0xff);
630
631 /* 2. Configure LCR register, 8N1 mode by default */
632 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
633 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
634 | s->lcr_reg;
635
636 /* 3. Configure MODE 1 register */
637 s->mode1_reg = 0;
638 /* Enable IRQ pin */
639 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
640 /* Disable TX */
641 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
642 s->tx_enabled = 0;
643 /* RX is enabled */
644 s->rx_enabled = 1;
645 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
646 | s->mode1_reg;
647
648 /* 4. Configure MODE 2 register */
649 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
650 if (s->loopback) {
651 /* Enable loopback */
652 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
653 }
654 /* Reset FIFOs */
655 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
656 s->tx_fifo_empty = 1;
657
658 /* 5. Configure FIFO trigger level register */
659 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
660 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
661 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
662
663 /* 6. Configure flow control levels */
664 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
665 /* Flow control halt level 96, resume level 48 */
666 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
667
668 /* 7. Configure flow control */
669 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
670 /* Enable auto CTS and auto RTS flow control */
671 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
672
673 /* 8. Configure RX timeout register */
674 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
675 /* Timeout after 48 character intervals */
676 buf[9] |= 0x0030;
677
678 /* 9. Configure LSR interrupt enable register */
679 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
680 /* Enable RX timeout interrupt */
681 buf[10] |= MAX3107_LSR_RXTO_BIT;
682
683 /* Perform SPI transfer */
684 if (max3107_rw(s, (u8 *)buf, NULL, 22))
685 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
686
687 /* 10. Clear IRQ status register by reading it */
688 buf[0] = MAX3107_IRQSTS_REG;
689
690 /* 11. Configure interrupt enable register */
691 /* Enable LSR interrupt */
692 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
693 /* Enable RX FIFO interrupt */
694 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
695 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
696 | s->irqen_reg;
697
698 /* 12. Clear FIFO reset that was set in step 6 */
699 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
700 if (s->loopback) {
701 /* Keep loopback enabled */
702 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
703 }
704
705 /* Perform SPI transfer */
706 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
707 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
708
709}
710
711/* IRQ handler */
712static irqreturn_t max3107_irq(int irqno, void *dev_id)
713{
714 struct max3107_port *s = dev_id;
715
716 if (irqno != s->spi->irq) {
717 /* Unexpected IRQ */
718 return IRQ_NONE;
719 }
720
721 /* Indicate irq */
722 s->handle_irq = 1;
723
724 /* Trigger work thread */
725 max3107_dowork(s);
726
727 return IRQ_HANDLED;
728}
729
730/* HW suspension function
731 *
732 * Currently autosleep is used to decrease current consumption, alternative
733 * approach would be to set the chip to reset mode if UART is not being
734 * used but that would mess the GPIOs
735 *
736 */
737static void max3107_hw_susp(struct max3107_port *s, int suspend)
738{
739 pr_debug("enter, suspend %d\n", suspend);
740
741 if (suspend) {
742 /* Suspend requested,
743 * enable autosleep to decrease current consumption
744 */
745 s->suspended = 1;
746 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
747 } else {
748 /* Resume requested,
749 * disable autosleep
750 */
751 s->suspended = 0;
752 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
753 }
754}
755
756/* Modem status IRQ enabling */
757static void max3107_enable_ms(struct uart_port *port)
758{
759 /* Modem status not supported */
760}
761
762/* Data send function */
763static void max3107_start_tx(struct uart_port *port)
764{
765 struct max3107_port *s = container_of(port, struct max3107_port, port);
766
767 /* Trigger work thread for sending data */
768 max3107_dowork(s);
769}
770
771/* Function for checking that there is no pending transfers */
772static unsigned int max3107_tx_empty(struct uart_port *port)
773{
774 struct max3107_port *s = container_of(port, struct max3107_port, port);
775
776 pr_debug("returning %d\n",
777 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
778 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
779}
780
781/* Function for stopping RX */
782static void max3107_stop_rx(struct uart_port *port)
783{
784 struct max3107_port *s = container_of(port, struct max3107_port, port);
785 unsigned long flags;
786
787 /* Set RX disabled in MODE 1 register */
788 spin_lock_irqsave(&s->data_lock, flags);
789 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
790 s->mode1_commit = 1;
791 spin_unlock_irqrestore(&s->data_lock, flags);
792 /* Set RX disabled */
793 s->rx_enabled = 0;
794 /* Trigger work thread for doing the actual configuration change */
795 max3107_dowork(s);
796}
797
798/* Function for returning control pin states */
799static unsigned int max3107_get_mctrl(struct uart_port *port)
800{
801 /* DCD and DSR are not wired and CTS/RTS is handled automatically
802 * so just indicate DSR and CAR asserted
803 */
804 return TIOCM_DSR | TIOCM_CAR;
805}
806
807/* Function for setting control pin states */
808static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
809{
810 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
811 * so do nothing
812 */
813}
814
815/* Function for configuring UART parameters */
816static void max3107_set_termios(struct uart_port *port,
817 struct ktermios *termios,
818 struct ktermios *old)
819{
820 struct max3107_port *s = container_of(port, struct max3107_port, port);
821 struct tty_struct *tty;
822 int baud;
823 u16 new_lcr = 0;
824 u32 new_brg = 0;
825 unsigned long flags;
826
827 if (!port->state)
828 return;
829
830 tty = port->state->port.tty;
831 if (!tty)
832 return;
833
834 /* Get new LCR register values */
835 /* Word size */
836 if ((termios->c_cflag & CSIZE) == CS7)
837 new_lcr |= MAX3107_LCR_WORD_LEN_7;
838 else
839 new_lcr |= MAX3107_LCR_WORD_LEN_8;
840
841 /* Parity */
842 if (termios->c_cflag & PARENB) {
843 new_lcr |= MAX3107_LCR_PARITY_BIT;
844 if (!(termios->c_cflag & PARODD))
845 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
846 }
847
848 /* Stop bits */
849 if (termios->c_cflag & CSTOPB) {
850 /* 2 stop bits */
851 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
852 }
853
854 /* Mask termios capabilities we don't support */
855 termios->c_cflag &= ~CMSPAR;
856
857 /* Set status ignore mask */
858 s->port.ignore_status_mask = 0;
859 if (termios->c_iflag & IGNPAR)
860 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
861
862 /* Set low latency to immediately handle pushed data */
863 s->port.state->port.tty->low_latency = 1;
864
865 /* Get new baud rate generator configuration */
866 baud = tty_get_baud_rate(tty);
867
868 spin_lock_irqsave(&s->data_lock, flags);
869 new_brg = get_new_brg(baud, s);
870 /* if can't find the corrent config, use previous */
871 if (!new_brg) {
872 baud = s->baud;
873 new_brg = s->brg_cfg;
874 }
875 spin_unlock_irqrestore(&s->data_lock, flags);
876 tty_termios_encode_baud_rate(termios, baud, baud);
877 s->baud = baud;
878
879 /* Update timeout according to new baud rate */
880 uart_update_timeout(port, termios->c_cflag, baud);
881
882 spin_lock_irqsave(&s->data_lock, flags);
883 if (s->lcr_reg != new_lcr) {
884 s->lcr_reg = new_lcr;
885 s->lcr_commit = 1;
886 }
887 if (s->brg_cfg != new_brg) {
888 s->brg_cfg = new_brg;
889 s->brg_commit = 1;
890 }
891 spin_unlock_irqrestore(&s->data_lock, flags);
892
893 /* Trigger work thread for doing the actual configuration change */
894 max3107_dowork(s);
895}
896
897/* Port shutdown function */
898static void max3107_shutdown(struct uart_port *port)
899{
900 struct max3107_port *s = container_of(port, struct max3107_port, port);
901
902 if (s->suspended) {
903 /* Resume HW */
904 max3107_hw_susp(s, 0);
905 }
906
907 /* Free the interrupt */
908 free_irq(s->spi->irq, s);
909
910 if (s->workqueue) {
911 /* Flush and destroy work queue */
912 flush_workqueue(s->workqueue);
913 destroy_workqueue(s->workqueue);
914 s->workqueue = NULL;
915 }
916
917 /* Suspend HW */
918 max3107_hw_susp(s, 1);
919}
920
921/* Port startup function */
922static int max3107_startup(struct uart_port *port)
923{
924 struct max3107_port *s = container_of(port, struct max3107_port, port);
925
926 /* Initialize work queue */
927 s->workqueue = create_freezeable_workqueue("max3107");
928 if (!s->workqueue) {
929 dev_err(&s->spi->dev, "Workqueue creation failed\n");
930 return -EBUSY;
931 }
932 INIT_WORK(&s->work, max3107_work);
933
934 /* Setup IRQ */
935 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
936 "max3107", s)) {
937 dev_err(&s->spi->dev, "IRQ reguest failed\n");
938 destroy_workqueue(s->workqueue);
939 s->workqueue = NULL;
940 return -EBUSY;
941 }
942
943 /* Resume HW */
944 max3107_hw_susp(s, 0);
945
946 /* Init registers */
947 max3107_register_init(s);
948
949 return 0;
950}
951
952/* Port type function */
953static const char *max3107_type(struct uart_port *port)
954{
955 struct max3107_port *s = container_of(port, struct max3107_port, port);
956 return s->spi->modalias;
957}
958
959/* Port release function */
960static void max3107_release_port(struct uart_port *port)
961{
962 /* Do nothing */
963}
964
965/* Port request function */
966static int max3107_request_port(struct uart_port *port)
967{
968 /* Do nothing */
969 return 0;
970}
971
972/* Port config function */
973static void max3107_config_port(struct uart_port *port, int flags)
974{
975 struct max3107_port *s = container_of(port, struct max3107_port, port);
976
977 /* Use PORT_MAX3100 since we are at least int the same series */
978 s->port.type = PORT_MAX3100;
979}
980
981/* Port verify function */
982static int max3107_verify_port(struct uart_port *port,
983 struct serial_struct *ser)
984{
985 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
986 return 0;
987
988 return -EINVAL;
989}
990
991/* Port stop TX function */
992static void max3107_stop_tx(struct uart_port *port)
993{
994 /* Do nothing */
995}
996
997/* Port break control function */
998static void max3107_break_ctl(struct uart_port *port, int break_state)
999{
1000 /* We don't support break control, do nothing */
1001}
1002
1003/* GPIO direction to input function */
1004static int max3107_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1005{
1006 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1007 u16 buf[1]; /* Buffer for SPI transfer */
1008
1009 if (offset >= MAX3107_GPIO_COUNT) {
1010 dev_err(&s->spi->dev, "Invalid GPIO\n");
1011 return -EINVAL;
1012 }
1013
1014 /* Read current GPIO configuration register */
1015 buf[0] = MAX3107_GPIOCFG_REG;
1016 /* Perform SPI transfer */
1017 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1018 dev_err(&s->spi->dev, "SPI transfer GPIO read failed\n");
1019 return -EIO;
1020 }
1021 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1022
1023 /* Set GPIO to input */
1024 buf[0] &= ~(0x0001 << offset);
1025
1026 /* Write new GPIO configuration register value */
1027 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
1028 /* Perform SPI transfer */
1029 if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
1030 dev_err(&s->spi->dev, "SPI transfer GPIO write failed\n");
1031 return -EIO;
1032 }
1033 return 0;
1034}
1035
1036/* GPIO direction to output function */
1037static int max3107_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
1038 int value)
1039{
1040 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1041 u16 buf[2]; /* Buffer for SPI transfers */
1042
1043 if (offset >= MAX3107_GPIO_COUNT) {
1044 dev_err(&s->spi->dev, "Invalid GPIO\n");
1045 return -EINVAL;
1046 }
1047
1048 /* Read current GPIO configuration and data registers */
1049 buf[0] = MAX3107_GPIOCFG_REG;
1050 buf[1] = MAX3107_GPIODATA_REG;
1051 /* Perform SPI transfer */
1052 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
1053 dev_err(&s->spi->dev, "SPI transfer gpio failed\n");
1054 return -EIO;
1055 }
1056 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1057 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
1058
1059 /* Set GPIO to output */
1060 buf[0] |= (0x0001 << offset);
1061 /* Set value */
1062 if (value)
1063 buf[1] |= (0x0001 << offset);
1064 else
1065 buf[1] &= ~(0x0001 << offset);
1066
1067 /* Write new GPIO configuration and data register values */
1068 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
1069 buf[1] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
1070 /* Perform SPI transfer */
1071 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1072 dev_err(&s->spi->dev,
1073 "SPI transfer for GPIO conf data w failed\n");
1074 return -EIO;
1075 }
1076 return 0;
1077}
1078
1079/* GPIO value query function */
1080static int max3107_gpio_get(struct gpio_chip *chip, unsigned offset)
1081{
1082 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1083 u16 buf[1]; /* Buffer for SPI transfer */
1084
1085 if (offset >= MAX3107_GPIO_COUNT) {
1086 dev_err(&s->spi->dev, "Invalid GPIO\n");
1087 return -EINVAL;
1088 }
1089
1090 /* Read current GPIO data register */
1091 buf[0] = MAX3107_GPIODATA_REG;
1092 /* Perform SPI transfer */
1093 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1094 dev_err(&s->spi->dev, "SPI transfer GPIO data r failed\n");
1095 return -EIO;
1096 }
1097 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1098
1099 /* Return value */
1100 return buf[0] & (0x0001 << offset);
1101}
1102
1103/* GPIO value set function */
1104static void max3107_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1105{
1106 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1107 u16 buf[2]; /* Buffer for SPI transfers */
1108
1109 if (offset >= MAX3107_GPIO_COUNT) {
1110 dev_err(&s->spi->dev, "Invalid GPIO\n");
1111 return;
1112 }
1113
1114 /* Read current GPIO configuration registers*/
1115 buf[0] = MAX3107_GPIODATA_REG;
1116 buf[1] = MAX3107_GPIOCFG_REG;
1117 /* Perform SPI transfer */
1118 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
1119 dev_err(&s->spi->dev,
1120 "SPI transfer for GPIO data and config read failed\n");
1121 return;
1122 }
1123 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1124 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
1125
1126 if (!(buf[1] & (0x0001 << offset))) {
1127 /* Configured as input, can't set value */
1128 dev_warn(&s->spi->dev,
1129 "Trying to set value for input GPIO\n");
1130 return;
1131 }
1132
1133 /* Set value */
1134 if (value)
1135 buf[0] |= (0x0001 << offset);
1136 else
1137 buf[0] &= ~(0x0001 << offset);
1138
1139 /* Write new GPIO data register value */
1140 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
1141 /* Perform SPI transfer */
1142 if (max3107_rw(s, (u8 *)buf, NULL, 2))
1143 dev_err(&s->spi->dev, "SPI transfer GPIO data w failed\n");
1144}
1145
1146/* Platform data */
1147static struct max3107_plat max3107_plat_data = {
1148 .loopback = 0,
1149 .ext_clk = 1,
1150 .max3107_hw_suspend = &max3107_hw_susp,
1151 .polled_mode = 0,
1152 .poll_time = 0,
1153};
1154
1155/* Port functions */
1156static struct uart_ops max3107_ops = {
1157 .tx_empty = max3107_tx_empty,
1158 .set_mctrl = max3107_set_mctrl,
1159 .get_mctrl = max3107_get_mctrl,
1160 .stop_tx = max3107_stop_tx,
1161 .start_tx = max3107_start_tx,
1162 .stop_rx = max3107_stop_rx,
1163 .enable_ms = max3107_enable_ms,
1164 .break_ctl = max3107_break_ctl,
1165 .startup = max3107_startup,
1166 .shutdown = max3107_shutdown,
1167 .set_termios = max3107_set_termios,
1168 .type = max3107_type,
1169 .release_port = max3107_release_port,
1170 .request_port = max3107_request_port,
1171 .config_port = max3107_config_port,
1172 .verify_port = max3107_verify_port,
1173};
1174
1175/* UART driver data */
1176static struct uart_driver max3107_uart_driver = {
1177 .owner = THIS_MODULE,
1178 .driver_name = "ttyMAX",
1179 .dev_name = "ttyMAX",
1180 .nr = 1,
1181};
1182
1183/* GPIO chip data */
1184static struct gpio_chip max3107_gpio_chip = {
1185 .owner = THIS_MODULE,
1186 .direction_input = max3107_gpio_direction_in,
1187 .direction_output = max3107_gpio_direction_out,
1188 .get = max3107_gpio_get,
1189 .set = max3107_gpio_set,
1190 .can_sleep = 1,
1191 .base = MAX3107_GPIO_BASE,
1192 .ngpio = MAX3107_GPIO_COUNT,
1193};
1194/* Device probe function */
1195static int __devinit max3107_probe(struct spi_device *spi)
1196{
1197 struct max3107_port *s;
1198 struct max3107_plat *pdata = &max3107_plat_data;
1199 u16 buf[2]; /* Buffer for SPI transfers */
1200 int retval;
1201
1202 pr_info("enter max3107 probe\n");
1203
1204 /* Reset the chip */
1205 if (gpio_request(MAX3107_RESET_GPIO, "max3107")) {
1206 pr_err("Requesting RESET GPIO failed\n");
1207 return -EIO;
1208 }
1209 if (gpio_direction_output(MAX3107_RESET_GPIO, 0)) {
1210 pr_err("Setting RESET GPIO to 0 failed\n");
1211 gpio_free(MAX3107_RESET_GPIO);
1212 return -EIO;
1213 }
1214 msleep(MAX3107_RESET_DELAY);
1215 if (gpio_direction_output(MAX3107_RESET_GPIO, 1)) {
1216 pr_err("Setting RESET GPIO to 1 failed\n");
1217 gpio_free(MAX3107_RESET_GPIO);
1218 return -EIO;
1219 }
1220 gpio_free(MAX3107_RESET_GPIO);
1221 msleep(MAX3107_WAKEUP_DELAY);
1222
1223 /* Allocate port structure */
1224 s = kzalloc(sizeof(*s), GFP_KERNEL);
1225 if (!s) {
1226 pr_err("Allocating port structure failed\n");
1227 return -ENOMEM;
1228 }
1229 /* SPI Rx buffer
1230 * +2 for RX FIFO interrupt
1231 * disabling and RX level query
1232 */
1233 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
1234 if (!s->rxbuf) {
1235 pr_err("Allocating RX buffer failed\n");
1236 return -ENOMEM;
1237 }
1238 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
1239 if (!s->rxstr) {
1240 pr_err("Allocating RX buffer failed\n");
1241 return -ENOMEM;
1242 }
1243 /* SPI Tx buffer
1244 * SPI transfer buffer
1245 * +3 for TX FIFO empty
1246 * interrupt disabling and
1247 * enabling and TX enabling
1248 */
1249 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1250 if (!s->txbuf) {
1251 pr_err("Allocating TX buffer failed\n");
1252 return -ENOMEM;
1253 }
1254 /* Initialize shared data lock */
1255 spin_lock_init(&s->data_lock);
1256
1257 /* SPI intializations */
1258 dev_set_drvdata(&spi->dev, s);
1259 spi->mode = SPI_MODE_0;
1260 spi->dev.platform_data = pdata;
1261 spi->bits_per_word = 16;
1262 s->ext_clk = pdata->ext_clk;
1263 s->loopback = pdata->loopback;
1264 spi_setup(spi);
1265 s->spi = spi;
1266
1267 /* Check REV ID to ensure we are talking to what we expect */
1268 buf[0] = MAX3107_REVID_REG;
1269 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1270 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1271 return -EIO;
1272 }
1273 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1274 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1275 dev_err(&s->spi->dev, "REVID %x does not match\n",
1276 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1277 return -ENODEV;
1278 }
1279
1280 /* Disable all interrupts */
1281 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1282 buf[0] |= 0x0000;
1283
1284 /* Configure clock source */
1285 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1286 if (s->ext_clk) {
1287 /* External clock */
1288 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1289 }
1290
1291 /* PLL bypass ON */
1292 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1293
1294 /* Perform SPI transfer */
1295 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1296 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1297 return -EIO;
1298 }
1299
1300 /* Register UART driver */
1301 retval = uart_register_driver(&max3107_uart_driver);
1302 if (retval) {
1303 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1304 return retval;
1305 }
1306
1307 /* Initialize UART port data */
1308 s->port.fifosize = 128;
1309 s->port.ops = &max3107_ops;
1310 s->port.line = 0;
1311 s->port.dev = &spi->dev;
1312 s->port.uartclk = 9600;
1313 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1314 s->port.irq = s->spi->irq;
1315 /* Use PORT_MAX3100 since we are at least in the same series */
1316 s->port.type = PORT_MAX3100;
1317
1318 /* Add UART port */
1319 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1320 if (retval < 0) {
1321 dev_err(&s->spi->dev, "Adding UART port failed\n");
1322 return retval;
1323 }
1324
1325 /* Initialize GPIO chip data */
1326 s->chip = max3107_gpio_chip;
1327 s->chip.label = spi->modalias;
1328 s->chip.dev = &spi->dev;
1329
1330 /* Add GPIO chip */
1331 retval = gpiochip_add(&s->chip);
1332 if (retval) {
1333 dev_err(&s->spi->dev, "Adding GPIO chip failed\n");
1334 return retval;
1335 }
1336
1337 /* Temporary fix for EV2 boot problems, set modem reset to 0 */
1338 max3107_gpio_direction_out(&s->chip, 3, 0);
1339
1340 /* Go to suspend mode */
1341 max3107_hw_susp(s, 1);
1342
1343 return 0;
1344}
1345
1346/* Driver remove function */
1347static int __devexit max3107_remove(struct spi_device *spi)
1348{
1349 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1350
1351 pr_info("enter max3107 remove\n");
1352
1353 /* Remove GPIO chip */
1354 if (gpiochip_remove(&s->chip))
1355 dev_warn(&s->spi->dev, "Removing GPIO chip failed\n");
1356
1357 /* Remove port */
1358 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1359 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1360
1361 /* Unregister UART driver */
1362 uart_unregister_driver(&max3107_uart_driver);
1363
1364 /* Free TxRx buffer */
1365 kfree(s->rxbuf);
1366 kfree(s->rxstr);
1367 kfree(s->txbuf);
1368
1369 /* Free port structure */
1370 kfree(s);
1371
1372 return 0;
1373}
1374
1375/* Driver suspend function */
1376static int max3107_suspend(struct spi_device *spi, pm_message_t state)
1377{
1378#ifdef CONFIG_PM
1379 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1380
1381 pr_debug("enter suspend\n");
1382
1383 /* Suspend UART port */
1384 uart_suspend_port(&max3107_uart_driver, &s->port);
1385
1386 /* Go to suspend mode */
1387 max3107_hw_susp(s, 1);
1388#endif /* CONFIG_PM */
1389 return 0;
1390}
1391
1392/* Driver resume function */
1393static int max3107_resume(struct spi_device *spi)
1394{
1395#ifdef CONFIG_PM
1396 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1397
1398 pr_debug("enter resume\n");
1399
1400 /* Resume from suspend */
1401 max3107_hw_susp(s, 0);
1402
1403 /* Resume UART port */
1404 uart_resume_port(&max3107_uart_driver, &s->port);
1405#endif /* CONFIG_PM */
1406 return 0;
1407}
1408
1409/* Spi driver data */
1410static struct spi_driver max3107_driver = {
1411 .driver = {
1412 .name = "max3107",
1413 .bus = &spi_bus_type,
1414 .owner = THIS_MODULE,
1415 },
1416 .probe = max3107_probe,
1417 .remove = __devexit_p(max3107_remove),
1418 .suspend = max3107_suspend,
1419 .resume = max3107_resume,
1420};
1421
1422/* Driver init function */
1423static int __init max3107_init(void)
1424{
1425 pr_info("enter max3107 init\n");
1426 return spi_register_driver(&max3107_driver);
1427}
1428
1429/* Driver exit function */
1430static void __exit max3107_exit(void)
1431{
1432 pr_info("enter max3107 exit\n");
1433 spi_unregister_driver(&max3107_driver);
1434}
1435
1436module_init(max3107_init);
1437module_exit(max3107_exit);
1438
1439MODULE_DESCRIPTION("MAX3107 driver");
1440MODULE_AUTHOR("Aavamobile");
1441MODULE_ALIAS("max3107-spi-uart");
1442MODULE_LICENSE("GPLv2");
diff --git a/drivers/serial/max3107.h b/drivers/serial/max3107.h
new file mode 100644
index 000000000000..a5625d1f263d
--- /dev/null
+++ b/drivers/serial/max3107.h
@@ -0,0 +1,358 @@
1/*
2 * max3107.h - spi uart protocol driver header for Maxim 3107
3 *
4 * Copyright (C) Aavamobile 2009
5 * Based on serial_max3100.h by Christian Pellegrin
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _LINUX_SERIAL_MAX3107_H
14#define _LINUX_SERIAL_MAX3107_H
15
16/* Serial error status definitions */
17#define MAX3107_PARITY_ERROR 1
18#define MAX3107_FRAME_ERROR 2
19#define MAX3107_OVERRUN_ERROR 4
20#define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \
21 MAX3107_FRAME_ERROR | \
22 MAX3107_OVERRUN_ERROR)
23
24/* GPIO definitions */
25#define MAX3107_GPIO_BASE 88
26#define MAX3107_GPIO_COUNT 4
27
28
29/* GPIO connected to chip's reset pin */
30#define MAX3107_RESET_GPIO 87
31
32
33/* Chip reset delay */
34#define MAX3107_RESET_DELAY 10
35
36/* Chip wakeup delay */
37#define MAX3107_WAKEUP_DELAY 50
38
39
40/* Sleep mode definitions */
41#define MAX3107_DISABLE_FORCED_SLEEP 0
42#define MAX3107_ENABLE_FORCED_SLEEP 1
43#define MAX3107_DISABLE_AUTOSLEEP 2
44#define MAX3107_ENABLE_AUTOSLEEP 3
45
46
47/* Definitions for register access with SPI transfers
48 *
49 * SPI transfer format:
50 *
51 * Master to slave bits xzzzzzzzyyyyyyyy
52 * Slave to master bits aaaaaaaabbbbbbbb
53 *
54 * where:
55 * x = 0 for reads, 1 for writes
56 * z = register address
57 * y = new register value if write, 0 if read
58 * a = unspecified
59 * b = register value if read, unspecified if write
60 */
61
62/* SPI speed */
63#define MAX3107_SPI_SPEED (3125000 * 2)
64
65/* Write bit */
66#define MAX3107_WRITE_BIT (1 << 15)
67
68/* SPI TX data mask */
69#define MAX3107_SPI_RX_DATA_MASK (0x00ff)
70
71/* SPI RX data mask */
72#define MAX3107_SPI_TX_DATA_MASK (0x00ff)
73
74/* Register access masks */
75#define MAX3107_RHR_REG (0x0000) /* RX FIFO */
76#define MAX3107_THR_REG (0x0000) /* TX FIFO */
77#define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */
78#define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */
79#define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */
80#define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */
81#define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */
82#define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */
83#define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */
84#define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */
85#define MAX3107_MODE1_REG (0x0900) /* MODE1 */
86#define MAX3107_MODE2_REG (0x0a00) /* MODE2 */
87#define MAX3107_LCR_REG (0x0b00) /* LCR */
88#define MAX3107_RXTO_REG (0x0c00) /* RX timeout */
89#define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */
90#define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */
91#define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */
92#define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */
93#define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */
94#define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */
95#define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */
96#define MAX3107_XON1_REG (0x1400) /* XON1 character */
97#define MAX3107_XON2_REG (0x1500) /* XON2 character */
98#define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */
99#define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */
100#define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */
101#define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */
102#define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */
103#define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */
104#define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */
105#define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */
106#define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */
107#define MAX3107_REVID_REG (0x1f00) /* Revision identification */
108
109/* IRQ register bits */
110#define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
111#define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
112#define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */
113#define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
114#define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
115#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
116#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
117#define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
118
119/* LSR register bits */
120#define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */
121#define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
122#define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
123#define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */
124#define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */
125#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
126#define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
127#define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */
128
129/* Special character register bits */
130#define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
131#define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
132#define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
133#define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
134#define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */
135#define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
136#define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
137#define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */
138
139/* Status register bits */
140#define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
141#define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
142#define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
143#define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
144#define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */
145#define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
146#define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
147#define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */
148
149/* MODE1 register bits */
150#define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
151#define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
152#define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
153#define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
154#define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
155#define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
156#define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
157#define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
158
159/* MODE2 register bits */
160#define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */
161#define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
162#define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
163#define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
164#define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
165#define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
166#define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
167#define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
168
169/* LCR register bits */
170#define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
171#define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
172 *
173 * Word length bits table:
174 * 00 -> 5 bit words
175 * 01 -> 6 bit words
176 * 10 -> 7 bit words
177 * 11 -> 8 bit words
178 */
179#define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
180 *
181 * STOP length bit table:
182 * 0 -> 1 stop bit
183 * 1 -> 1-1.5 stop bits if
184 * word length is 5,
185 * 2 stop bits otherwise
186 */
187#define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
188#define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
189#define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
190#define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
191#define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */
192#define MAX3107_LCR_WORD_LEN_5 (0x0000)
193#define MAX3107_LCR_WORD_LEN_6 (0x0001)
194#define MAX3107_LCR_WORD_LEN_7 (0x0002)
195#define MAX3107_LCR_WORD_LEN_8 (0x0003)
196
197
198/* IRDA register bits */
199#define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
200#define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
201#define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
202#define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
203#define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
204#define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
205#define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */
206#define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */
207
208/* Flow control trigger level register masks */
209#define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
210#define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
211#define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f)
212#define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4)
213
214/* FIFO interrupt trigger level register masks */
215#define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */
216#define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */
217#define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f)
218#define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4)
219
220/* Flow control register bits */
221#define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
222#define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
223#define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
224 * are used in conjunction with
225 * XOFF2 for definition of
226 * special character */
227#define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
228#define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
229#define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
230 *
231 * SWFLOW bits 1 & 0 table:
232 * 00 -> no transmitter flow
233 * control
234 * 01 -> receiver compares
235 * XON2 and XOFF2
236 * and controls
237 * transmitter
238 * 10 -> receiver compares
239 * XON1 and XOFF1
240 * and controls
241 * transmitter
242 * 11 -> receiver compares
243 * XON1, XON2, XOFF1 and
244 * XOFF2 and controls
245 * transmitter
246 */
247#define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
248#define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
249 *
250 * SWFLOW bits 3 & 2 table:
251 * 00 -> no received flow
252 * control
253 * 01 -> transmitter generates
254 * XON2 and XOFF2
255 * 10 -> transmitter generates
256 * XON1 and XOFF1
257 * 11 -> transmitter generates
258 * XON1, XON2, XOFF1 and
259 * XOFF2
260 */
261
262/* GPIO configuration register bits */
263#define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
264#define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
265#define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
266#define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
267#define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
268#define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
269#define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
270#define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
271
272/* GPIO DATA register bits */
273#define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
274#define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
275#define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
276#define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
277#define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
278#define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
279#define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
280#define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
281
282/* PLL configuration register masks */
283#define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */
284#define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */
285
286/* Baud rate generator configuration register masks and bits */
287#define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of
288 * Baud rate generator divisor
289 */
290#define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
291#define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
292#define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */
293#define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */
294
295/* Clock source register bits */
296#define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */
297#define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
298#define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
299#define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
300#define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
301#define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */
302#define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */
303#define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
304
305
306/* HW definitions */
307#define MAX3107_RX_FIFO_SIZE 128
308#define MAX3107_TX_FIFO_SIZE 128
309#define MAX3107_REVID1 0x00a0
310#define MAX3107_REVID2 0x00a1
311
312
313/* Baud rate generator configuration values for external clock 13MHz */
314#define MAX3107_BRG13_B300 (0x0A9400 | 0x05)
315#define MAX3107_BRG13_B600 (0x054A00 | 0x03)
316#define MAX3107_BRG13_B1200 (0x02A500 | 0x01)
317#define MAX3107_BRG13_B2400 (0x015200 | 0x09)
318#define MAX3107_BRG13_B4800 (0x00A900 | 0x04)
319#define MAX3107_BRG13_B9600 (0x005400 | 0x0A)
320#define MAX3107_BRG13_B19200 (0x002A00 | 0x05)
321#define MAX3107_BRG13_B38400 (0x001500 | 0x03)
322#define MAX3107_BRG13_B57600 (0x000E00 | 0x02)
323#define MAX3107_BRG13_B115200 (0x000700 | 0x01)
324#define MAX3107_BRG13_B230400 (0x000300 | 0x08)
325#define MAX3107_BRG13_B460800 (0x000100 | 0x0c)
326#define MAX3107_BRG13_B921600 (0x000100 | 0x1c)
327
328/* Baud rate generator configuration values for external clock 26MHz */
329#define MAX3107_BRG26_B300 (0x152800 | 0x0A)
330#define MAX3107_BRG26_B600 (0x0A9400 | 0x05)
331#define MAX3107_BRG26_B1200 (0x054A00 | 0x03)
332#define MAX3107_BRG26_B2400 (0x02A500 | 0x01)
333#define MAX3107_BRG26_B4800 (0x015200 | 0x09)
334#define MAX3107_BRG26_B9600 (0x00A900 | 0x04)
335#define MAX3107_BRG26_B19200 (0x005400 | 0x0A)
336#define MAX3107_BRG26_B38400 (0x002A00 | 0x05)
337#define MAX3107_BRG26_B57600 (0x001C00 | 0x03)
338#define MAX3107_BRG26_B115200 (0x000E00 | 0x02)
339#define MAX3107_BRG26_B230400 (0x000700 | 0x01)
340#define MAX3107_BRG26_B460800 (0x000300 | 0x08)
341#define MAX3107_BRG26_B921600 (0x000100 | 0x0C)
342
343/* Baud rate generator configuration values for internal clock */
344#define MAX3107_BRG13_IB300 (0x008000 | 0x00)
345#define MAX3107_BRG13_IB600 (0x004000 | 0x00)
346#define MAX3107_BRG13_IB1200 (0x002000 | 0x00)
347#define MAX3107_BRG13_IB2400 (0x001000 | 0x00)
348#define MAX3107_BRG13_IB4800 (0x000800 | 0x00)
349#define MAX3107_BRG13_IB9600 (0x000400 | 0x00)
350#define MAX3107_BRG13_IB19200 (0x000200 | 0x00)
351#define MAX3107_BRG13_IB38400 (0x000100 | 0x00)
352#define MAX3107_BRG13_IB57600 (0x000000 | 0x0B)
353#define MAX3107_BRG13_IB115200 (0x000000 | 0x05)
354#define MAX3107_BRG13_IB230400 (0x000000 | 0x03)
355#define MAX3107_BRG13_IB460800 (0x000000 | 0x00)
356#define MAX3107_BRG13_IB921600 (0x000000 | 0x00)
357
358#endif /* _LINUX_SERIAL_MAX3107_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 05:34:31 -0500