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authorWill Page <will.page@ni.com>2009-04-06 12:32:15 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-06 17:36:28 -0400
commit04bf7e745b841619d2f14f2f8b6f2c97f1c6757e (patch)
tree46372d66552fa2945ba8dbf1a4692d280123a66e /drivers/serial
parent46a0fac9438764533245928b78d35fbaa5d7adf4 (diff)
8250_pci: add support for National Instruments legacy 8420 RS232 boards
Signed-off-by: Will Page <will.page@ni.com> Signed-off-by: Shawn Bohrer <shawn.bohrer@ni.com> Signed-off-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/8250_pci.c218
1 files changed, 218 insertions, 0 deletions
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 2f570c761faf..5b0e80da1c44 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -306,6 +306,33 @@ static void __devexit pci_plx9050_exit(struct pci_dev *dev)
306 } 306 }
307} 307}
308 308
309#define NI8420_INT_ENABLE_REG 0x38
310#define NI8420_INT_ENABLE_BIT 0x2000
311
312static void __devexit pci_ni8420_exit(struct pci_dev *dev)
313{
314 void __iomem *p;
315 unsigned long base, len;
316 unsigned int bar = 0;
317
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
320 return;
321 }
322
323 base = pci_resource_start(dev, bar);
324 len = pci_resource_len(dev, bar);
325 p = ioremap_nocache(base, len);
326 if (p == NULL)
327 return;
328
329 /* Disable the CPU Interrupt */
330 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
331 p + NI8420_INT_ENABLE_REG);
332 iounmap(p);
333}
334
335
309/* MITE registers */ 336/* MITE registers */
310#define MITE_IOWBSR1 0xc4 337#define MITE_IOWBSR1 0xc4
311#define MITE_IOWCR1 0xf4 338#define MITE_IOWCR1 0xf4
@@ -627,6 +654,31 @@ static int pci_xircom_init(struct pci_dev *dev)
627 return 0; 654 return 0;
628} 655}
629 656
657static int pci_ni8420_init(struct pci_dev *dev)
658{
659 void __iomem *p;
660 unsigned long base, len;
661 unsigned int bar = 0;
662
663 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
664 moan_device("no memory in bar", dev);
665 return 0;
666 }
667
668 base = pci_resource_start(dev, bar);
669 len = pci_resource_len(dev, bar);
670 p = ioremap_nocache(base, len);
671 if (p == NULL)
672 return -ENOMEM;
673
674 /* Enable CPU Interrupt */
675 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
676 p + NI8420_INT_ENABLE_REG);
677
678 iounmap(p);
679 return 0;
680}
681
630#define MITE_IOWBSR1_WSIZE 0xa 682#define MITE_IOWBSR1_WSIZE 0xa
631#define MITE_IOWBSR1_WIN_OFFSET 0x800 683#define MITE_IOWBSR1_WIN_OFFSET 0x800
632#define MITE_IOWBSR1_WENAB (1 << 7) 684#define MITE_IOWBSR1_WENAB (1 << 7)
@@ -1023,6 +1075,114 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1023 */ 1075 */
1024 { 1076 {
1025 .vendor = PCI_VENDOR_ID_NI, 1077 .vendor = PCI_VENDOR_ID_NI,
1078 .device = PCI_DEVICE_ID_NI_PCI23216,
1079 .subvendor = PCI_ANY_ID,
1080 .subdevice = PCI_ANY_ID,
1081 .init = pci_ni8420_init,
1082 .setup = pci_default_setup,
1083 .exit = __devexit_p(pci_ni8420_exit),
1084 },
1085 {
1086 .vendor = PCI_VENDOR_ID_NI,
1087 .device = PCI_DEVICE_ID_NI_PCI2328,
1088 .subvendor = PCI_ANY_ID,
1089 .subdevice = PCI_ANY_ID,
1090 .init = pci_ni8420_init,
1091 .setup = pci_default_setup,
1092 .exit = __devexit_p(pci_ni8420_exit),
1093 },
1094 {
1095 .vendor = PCI_VENDOR_ID_NI,
1096 .device = PCI_DEVICE_ID_NI_PCI2324,
1097 .subvendor = PCI_ANY_ID,
1098 .subdevice = PCI_ANY_ID,
1099 .init = pci_ni8420_init,
1100 .setup = pci_default_setup,
1101 .exit = __devexit_p(pci_ni8420_exit),
1102 },
1103 {
1104 .vendor = PCI_VENDOR_ID_NI,
1105 .device = PCI_DEVICE_ID_NI_PCI2322,
1106 .subvendor = PCI_ANY_ID,
1107 .subdevice = PCI_ANY_ID,
1108 .init = pci_ni8420_init,
1109 .setup = pci_default_setup,
1110 .exit = __devexit_p(pci_ni8420_exit),
1111 },
1112 {
1113 .vendor = PCI_VENDOR_ID_NI,
1114 .device = PCI_DEVICE_ID_NI_PCI2324I,
1115 .subvendor = PCI_ANY_ID,
1116 .subdevice = PCI_ANY_ID,
1117 .init = pci_ni8420_init,
1118 .setup = pci_default_setup,
1119 .exit = __devexit_p(pci_ni8420_exit),
1120 },
1121 {
1122 .vendor = PCI_VENDOR_ID_NI,
1123 .device = PCI_DEVICE_ID_NI_PCI2322I,
1124 .subvendor = PCI_ANY_ID,
1125 .subdevice = PCI_ANY_ID,
1126 .init = pci_ni8420_init,
1127 .setup = pci_default_setup,
1128 .exit = __devexit_p(pci_ni8420_exit),
1129 },
1130 {
1131 .vendor = PCI_VENDOR_ID_NI,
1132 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1133 .subvendor = PCI_ANY_ID,
1134 .subdevice = PCI_ANY_ID,
1135 .init = pci_ni8420_init,
1136 .setup = pci_default_setup,
1137 .exit = __devexit_p(pci_ni8420_exit),
1138 },
1139 {
1140 .vendor = PCI_VENDOR_ID_NI,
1141 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1142 .subvendor = PCI_ANY_ID,
1143 .subdevice = PCI_ANY_ID,
1144 .init = pci_ni8420_init,
1145 .setup = pci_default_setup,
1146 .exit = __devexit_p(pci_ni8420_exit),
1147 },
1148 {
1149 .vendor = PCI_VENDOR_ID_NI,
1150 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1151 .subvendor = PCI_ANY_ID,
1152 .subdevice = PCI_ANY_ID,
1153 .init = pci_ni8420_init,
1154 .setup = pci_default_setup,
1155 .exit = __devexit_p(pci_ni8420_exit),
1156 },
1157 {
1158 .vendor = PCI_VENDOR_ID_NI,
1159 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1160 .subvendor = PCI_ANY_ID,
1161 .subdevice = PCI_ANY_ID,
1162 .init = pci_ni8420_init,
1163 .setup = pci_default_setup,
1164 .exit = __devexit_p(pci_ni8420_exit),
1165 },
1166 {
1167 .vendor = PCI_VENDOR_ID_NI,
1168 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1169 .subvendor = PCI_ANY_ID,
1170 .subdevice = PCI_ANY_ID,
1171 .init = pci_ni8420_init,
1172 .setup = pci_default_setup,
1173 .exit = __devexit_p(pci_ni8420_exit),
1174 },
1175 {
1176 .vendor = PCI_VENDOR_ID_NI,
1177 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1178 .subvendor = PCI_ANY_ID,
1179 .subdevice = PCI_ANY_ID,
1180 .init = pci_ni8420_init,
1181 .setup = pci_default_setup,
1182 .exit = __devexit_p(pci_ni8420_exit),
1183 },
1184 {
1185 .vendor = PCI_VENDOR_ID_NI,
1026 .device = PCI_ANY_ID, 1186 .device = PCI_ANY_ID,
1027 .subvendor = PCI_ANY_ID, 1187 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID, 1188 .subdevice = PCI_ANY_ID,
@@ -1334,6 +1494,7 @@ enum pci_board_num_t {
1334 pbn_b1_2_115200, 1494 pbn_b1_2_115200,
1335 pbn_b1_4_115200, 1495 pbn_b1_4_115200,
1336 pbn_b1_8_115200, 1496 pbn_b1_8_115200,
1497 pbn_b1_16_115200,
1337 1498
1338 pbn_b1_1_921600, 1499 pbn_b1_1_921600,
1339 pbn_b1_2_921600, 1500 pbn_b1_2_921600,
@@ -1343,6 +1504,9 @@ enum pci_board_num_t {
1343 pbn_b1_2_1250000, 1504 pbn_b1_2_1250000,
1344 1505
1345 pbn_b1_bt_1_115200, 1506 pbn_b1_bt_1_115200,
1507 pbn_b1_bt_2_115200,
1508 pbn_b1_bt_4_115200,
1509
1346 pbn_b1_bt_2_921600, 1510 pbn_b1_bt_2_921600,
1347 1511
1348 pbn_b1_1_1382400, 1512 pbn_b1_1_1382400,
@@ -1609,6 +1773,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1609 .base_baud = 115200, 1773 .base_baud = 115200,
1610 .uart_offset = 8, 1774 .uart_offset = 8,
1611 }, 1775 },
1776 [pbn_b1_16_115200] = {
1777 .flags = FL_BASE1,
1778 .num_ports = 16,
1779 .base_baud = 115200,
1780 .uart_offset = 8,
1781 },
1612 1782
1613 [pbn_b1_1_921600] = { 1783 [pbn_b1_1_921600] = {
1614 .flags = FL_BASE1, 1784 .flags = FL_BASE1,
@@ -1647,6 +1817,18 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1647 .base_baud = 115200, 1817 .base_baud = 115200,
1648 .uart_offset = 8, 1818 .uart_offset = 8,
1649 }, 1819 },
1820 [pbn_b1_bt_2_115200] = {
1821 .flags = FL_BASE1|FL_BASE_BARS,
1822 .num_ports = 2,
1823 .base_baud = 115200,
1824 .uart_offset = 8,
1825 },
1826 [pbn_b1_bt_4_115200] = {
1827 .flags = FL_BASE1|FL_BASE_BARS,
1828 .num_ports = 4,
1829 .base_baud = 115200,
1830 .uart_offset = 8,
1831 },
1650 1832
1651 [pbn_b1_bt_2_921600] = { 1833 [pbn_b1_bt_2_921600] = {
1652 .flags = FL_BASE1|FL_BASE_BARS, 1834 .flags = FL_BASE1|FL_BASE_BARS,
@@ -3207,6 +3389,42 @@ static struct pci_device_id serial_pci_tbl[] = {
3207 /* 3389 /*
3208 * National Instruments 3390 * National Instruments
3209 */ 3391 */
3392 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3394 pbn_b1_16_115200 },
3395 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397 pbn_b1_8_115200 },
3398 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400 pbn_b1_bt_4_115200 },
3401 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403 pbn_b1_bt_2_115200 },
3404 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406 pbn_b1_bt_4_115200 },
3407 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409 pbn_b1_bt_2_115200 },
3410 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412 pbn_b1_16_115200 },
3413 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415 pbn_b1_8_115200 },
3416 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418 pbn_b1_bt_4_115200 },
3419 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421 pbn_b1_bt_2_115200 },
3422 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424 pbn_b1_bt_4_115200 },
3425 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427 pbn_b1_bt_2_115200 },
3210 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 3428 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_ni8430_2 }, 3430 pbn_ni8430_2 },
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 23:11:53 -0500