diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-02-05 05:48:10 -0500 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-02-05 05:48:10 -0500 |
commit | 9b4a1617772d6d5ab5eeda0cd95302fae119e359 (patch) | |
tree | 5104ea63a01c995036947998016e3205cff3a61d /drivers/serial/sunzilog.c | |
parent | 53ea68ecea11bcbb3451c2758ce181bd97b569a9 (diff) |
[SERIAL] uart_port iotype member should use UPIO_*
Convert usage of SERIAL_IO_* to UPIO_*.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/serial/sunzilog.c')
-rw-r--r-- | drivers/serial/sunzilog.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/serial/sunzilog.c b/drivers/serial/sunzilog.c index 3c72484adea7..5cc4d4c2935c 100644 --- a/drivers/serial/sunzilog.c +++ b/drivers/serial/sunzilog.c | |||
@@ -1487,7 +1487,7 @@ static void __init sunzilog_prepare(void) | |||
1487 | up[(chip * 2) + 1].port.membase = (void __iomem *)&rp->channelB; | 1487 | up[(chip * 2) + 1].port.membase = (void __iomem *)&rp->channelB; |
1488 | 1488 | ||
1489 | /* Channel A */ | 1489 | /* Channel A */ |
1490 | up[(chip * 2) + 0].port.iotype = SERIAL_IO_MEM; | 1490 | up[(chip * 2) + 0].port.iotype = UPIO_MEM; |
1491 | up[(chip * 2) + 0].port.irq = zilog_irq; | 1491 | up[(chip * 2) + 0].port.irq = zilog_irq; |
1492 | up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; | 1492 | up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; |
1493 | up[(chip * 2) + 0].port.fifosize = 1; | 1493 | up[(chip * 2) + 0].port.fifosize = 1; |
@@ -1498,7 +1498,7 @@ static void __init sunzilog_prepare(void) | |||
1498 | up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A; | 1498 | up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A; |
1499 | 1499 | ||
1500 | /* Channel B */ | 1500 | /* Channel B */ |
1501 | up[(chip * 2) + 1].port.iotype = SERIAL_IO_MEM; | 1501 | up[(chip * 2) + 1].port.iotype = UPIO_MEM; |
1502 | up[(chip * 2) + 1].port.irq = zilog_irq; | 1502 | up[(chip * 2) + 1].port.irq = zilog_irq; |
1503 | up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; | 1503 | up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; |
1504 | up[(chip * 2) + 1].port.fifosize = 1; | 1504 | up[(chip * 2) + 1].port.fifosize = 1; |