diff options
author | Magnus Damm <damm@opensource.se> | 2010-02-05 06:15:33 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-02-07 22:49:01 -0500 |
commit | 8a77b8d0744ab21b59a9413c41c6a3d6cb9b0b4f (patch) | |
tree | 8bac6436e4068190f60b0fa950082cfa9b8543d9 /drivers/serial/sh-sci.h | |
parent | 65a5b28f0af00dddd785b516914739460562638f (diff) |
serial: sh-sci: Support ARM-based SH-Mobile CPUs.
Add support for ARM-based SH-Mobile CPUs to the sh-sci driver.
Also remove the SCLSR register that is missing on sh772x, sh7705 and
SH-Mobile.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r-- | drivers/serial/sh-sci.h | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index f7d2589926d2..fad67d33b0bd 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -30,7 +30,8 @@ | |||
30 | */ | 30 | */ |
31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | 31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 |
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
33 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
34 | defined(CONFIG_ARCH_SHMOBILE) | ||
34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | 35 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
35 | # define PORT_PTCR 0xA405011EUL | 36 | # define PORT_PTCR 0xA405011EUL |
36 | # define PORT_PVCR 0xA4050122UL | 37 | # define PORT_PVCR 0xA4050122UL |
@@ -228,7 +229,8 @@ | |||
228 | 229 | ||
229 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 230 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
230 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 231 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
231 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 232 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
233 | defined(CONFIG_ARCH_SHMOBILE) | ||
232 | # define SCIF_ORER 0x0200 | 234 | # define SCIF_ORER 0x0200 |
233 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | 235 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) |
234 | # define SCIF_RFDC_MASK 0x007f | 236 | # define SCIF_RFDC_MASK 0x007f |
@@ -261,7 +263,8 @@ | |||
261 | 263 | ||
262 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 264 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
263 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 265 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
264 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 266 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
267 | defined(CONFIG_ARCH_SHMOBILE) | ||
265 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) | 268 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
266 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | 269 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) |
267 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | 270 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) |
@@ -356,7 +359,7 @@ | |||
356 | SCI_OUT(sci_size, sci_offset, value); \ | 359 | SCI_OUT(sci_size, sci_offset, value); \ |
357 | } | 360 | } |
358 | 361 | ||
359 | #ifdef CONFIG_CPU_SH3 | 362 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) |
360 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 363 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
361 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | 364 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ |
362 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | 365 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ |
@@ -366,7 +369,8 @@ | |||
366 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | 369 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) |
367 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 370 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
368 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 371 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
369 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 372 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
373 | defined(CONFIG_ARCH_SHMOBILE) | ||
370 | #define SCIF_FNS(name, scif_offset, scif_size) \ | 374 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
371 | CPU_SCIF_FNS(name, scif_offset, scif_size) | 375 | CPU_SCIF_FNS(name, scif_offset, scif_size) |
372 | #else | 376 | #else |
@@ -401,7 +405,8 @@ | |||
401 | 405 | ||
402 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 406 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
403 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 407 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
404 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 408 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
409 | defined(CONFIG_ARCH_SHMOBILE) | ||
405 | 410 | ||
406 | SCIF_FNS(SCSMR, 0x00, 16) | 411 | SCIF_FNS(SCSMR, 0x00, 16) |
407 | SCIF_FNS(SCBRR, 0x04, 8) | 412 | SCIF_FNS(SCBRR, 0x04, 8) |
@@ -413,7 +418,7 @@ SCIF_FNS(SCFCR, 0x18, 16) | |||
413 | SCIF_FNS(SCFDR, 0x1c, 16) | 418 | SCIF_FNS(SCFDR, 0x1c, 16) |
414 | SCIF_FNS(SCxTDR, 0x20, 8) | 419 | SCIF_FNS(SCxTDR, 0x20, 8) |
415 | SCIF_FNS(SCxRDR, 0x24, 8) | 420 | SCIF_FNS(SCxRDR, 0x24, 8) |
416 | SCIF_FNS(SCLSR, 0x24, 16) | 421 | SCIF_FNS(SCLSR, 0x00, 0) |
417 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | 422 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
418 | defined(CONFIG_CPU_SUBTYPE_SH7724) | 423 | defined(CONFIG_CPU_SUBTYPE_SH7724) |
419 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | 424 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) |
@@ -583,7 +588,8 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
583 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) | 588 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
584 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 589 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
585 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 590 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
586 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 591 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
592 | defined(CONFIG_ARCH_SHMOBILE) | ||
587 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) | 593 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
588 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | 594 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
589 | defined(CONFIG_CPU_SUBTYPE_SH7724) | 595 | defined(CONFIG_CPU_SUBTYPE_SH7724) |