diff options
author | Paul Mundt <lethal@linux-sh.org> | 2008-10-02 06:09:13 -0400 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-10-02 06:09:13 -0400 |
commit | a2159b52219870553fd67e6456f41cd5225c46c6 (patch) | |
tree | 103c2750b618ca1b91aa0a0e6fad28dffb41a484 /drivers/serial/sh-sci.h | |
parent | bdeb3be7cc6911477b7169dad62a427d7a263d02 (diff) |
serial: sh-sci: Dynamic clock management depends on HAVE_CLK.
Presently this is conditionalized on sh, and disabled for sh64.
Now that SH-5 ties in to the clock framework, the sh64 exception
can be dropped. Additionally, ARM will want to use the same hooks
once SH-Mobile G3 grows clock framework support, so switch these
paths over to HAVE_CLK now.
Once the H8 and ARM sh-sci users hook up HAVE_CLK, the driver can
be switched over to having an outright dependency on it and the
ifdefs can go away.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r-- | drivers/serial/sh-sci.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 8a0749e34ca3..b3d906bfbd87 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -793,9 +793,7 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
793 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | 793 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
794 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1) | 794 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1) |
795 | #elif defined(__H8300H__) || defined(__H8300S__) | 795 | #elif defined(__H8300H__) || defined(__H8300S__) |
796 | #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) | 796 | #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
797 | #elif defined(CONFIG_SUPERH64) | ||
798 | #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1) | ||
799 | #else /* Generic SH */ | 797 | #else /* Generic SH */ |
800 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | 798 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) |
801 | #endif | 799 | #endif |