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authorPaul Mundt <lethal@linux-sh.org>2006-02-01 06:06:06 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-02-01 11:53:20 -0500
commitb7a76e4b4e212ec0829f3a7243064511d62cb6da (patch)
tree37a4be476a1a85a119131f88bc637e2628b1a75d /drivers/serial/sh-sci.h
parent37cc7943788c841b03a48c00751dfac0ad9f5b12 (diff)
[PATCH] sh: sh-sci clock framework updates
A couple of updates for the sh-sci serial driver: - Update for clock framework on sh. - Fix a compile error introduced by some h8300 changes. - Add SH7770/SH7780 subtype support. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r--drivers/serial/sh-sci.h114
1 files changed, 66 insertions, 48 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 2892169eff05..1f14bb4382f6 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -46,14 +46,17 @@
46#define H8S_SCI_IRQS1 {92, 93, 94, 0 } 46#define H8S_SCI_IRQS1 {92, 93, 94, 0 }
47#define H8S_SCI_IRQS2 {96, 97, 98, 0 } 47#define H8S_SCI_IRQS2 {96, 97, 98, 0 }
48#define SH5_SCIF_IRQS {39, 40, 42, 0 } 48#define SH5_SCIF_IRQS {39, 40, 42, 0 }
49#define SH7770_SCIF0_IRQS {61, 61, 61, 61 }
50#define SH7770_SCIF1_IRQS {62, 62, 62, 62 }
51#define SH7770_SCIF2_IRQS {63, 63, 63, 63 }
52#define SH7780_SCIF0_IRQS {40, 41, 43, 42 }
53#define SH7780_SCIF1_IRQS {76, 77, 79, 78 }
49 54
50#if defined(CONFIG_CPU_SUBTYPE_SH7708) 55#if defined(CONFIG_CPU_SUBTYPE_SH7708)
51# define SCI_NPORTS 1
52# define SCSPTR 0xffffff7c /* 8 bit */ 56# define SCSPTR 0xffffff7c /* 8 bit */
53# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 57# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
54# define SCI_ONLY 58# define SCI_ONLY
55#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 59#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
56# define SCI_NPORTS 3
57# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 60# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
58# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 61# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
59# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 62# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -61,9 +64,8 @@
61#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 64#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
62# define SCIF0 0xA4400000 65# define SCIF0 0xA4400000
63# define SCIF2 0xA4410000 66# define SCIF2 0xA4410000
64# define SCSMR_Ir 0xA44A0000 67# define SCSMR_Ir 0xA44A0000
65# define IRDA_SCIF SCIF0 68# define IRDA_SCIF SCIF0
66# define SCI_NPORTS 2
67# define SCPCR 0xA4000116 69# define SCPCR 0xA4000116
68# define SCPDR 0xA4000136 70# define SCPDR 0xA4000136
69 71
@@ -74,14 +76,11 @@
74# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 76# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
75# define SCIF_ONLY 77# define SCIF_ONLY
76#elif defined(CONFIG_SH_RTS7751R2D) 78#elif defined(CONFIG_SH_RTS7751R2D)
77# define SCI_NPORTS 1
78# define SCSPTR1 0xffe0001c /* 8 bit SCI */
79# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 79# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
80# define SCIF_ORER 0x0001 /* overrun error bit */ 80# define SCIF_ORER 0x0001 /* overrun error bit */
81# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 81# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
82# define SCIF_ONLY 82# define SCIF_ONLY
83#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) 83#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
84# define SCI_NPORTS 2
85# define SCSPTR1 0xffe0001c /* 8 bit SCI */ 84# define SCSPTR1 0xffe0001c /* 8 bit SCI */
86# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 85# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
87# define SCIF_ORER 0x0001 /* overrun error bit */ 86# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -90,34 +89,29 @@
90 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 89 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
91# define SCI_AND_SCIF 90# define SCI_AND_SCIF
92#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 91#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
93# define SCI_NPORTS 3 92# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
94# define SCSPTR0 0xfe600000 /* 16 bit SCIF */ 93# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
95# define SCSPTR1 0xfe610000 /* 16 bit SCIF */ 94# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
96# define SCSPTR2 0xfe620000 /* 16 bit SCIF */
97# define SCIF_ORER 0x0001 /* overrun error bit */ 95# define SCIF_ORER 0x0001 /* overrun error bit */
98# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
99# define SCIF_ONLY 97# define SCIF_ONLY
100#elif defined(CONFIG_CPU_SUBTYPE_SH7300) 98#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
101# define SCI_NPORTS 1
102# define SCPCR 0xA4050116 /* 16 bit SCIF */ 99# define SCPCR 0xA4050116 /* 16 bit SCIF */
103# define SCPDR 0xA4050136 /* 16 bit SCIF */ 100# define SCPDR 0xA4050136 /* 16 bit SCIF */
104# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 101# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
105# define SCIF_ONLY 102# define SCIF_ONLY
106#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 103#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
107# define SCI_NPORTS 1
108# define SCPDR 0xA4050138 /* 16 bit SCIF */ 104# define SCPDR 0xA4050138 /* 16 bit SCIF */
109# define SCSPTR2 SCPDR 105# define SCSPTR2 SCPDR
110# define SCIF_ORER 0x0001 /* overrun error bit */ 106# define SCIF_ORER 0x0001 /* overrun error bit */
111# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ 107# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
112# define SCIF_ONLY 108# define SCIF_ONLY
113#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 109#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
114# define SCI_NPORTS 1
115# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 110# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
116# define SCIF_ORER 0x0001 /* overrun error bit */ 111# define SCIF_ORER 0x0001 /* overrun error bit */
117# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 112# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
118# define SCIF_ONLY 113# define SCIF_ONLY
119#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 114#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
120# define SCI_NPORTS 2
121# define SCSPTR1 0xffe00020 /* 16 bit SCIF */ 115# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
122# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 116# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
123# define SCIF_ORER 0x0001 /* overrun error bit */ 117# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -129,26 +123,32 @@
129# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR 123# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
130# define SCIF_PTR2_OFFS 0x0000020 124# define SCIF_PTR2_OFFS 0x0000020
131# define SCIF_LSR2_OFFS 0x0000024 125# define SCIF_LSR2_OFFS 0x0000024
132# define SCI_NPORTS 1
133# define SCI_INIT { \
134 { {}, PORT_SCIF, 0, \
135 SH5_SCIF_IRQS, sci_init_pins_scif } \
136}
137# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 126# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
138# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 127# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
139# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, 128# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
140 TE=1,RE=1,REIE=1 */ 129 TE=1,RE=1,REIE=1 */
141# define SCIF_ONLY 130# define SCIF_ONLY
142#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 131#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
143# define SCI_NPORTS 3
144# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 132# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
145# define SCI_ONLY 133# define SCI_ONLY
146# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 134# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
147#elif defined(CONFIG_H8S2678) 135#elif defined(CONFIG_H8S2678)
148# define SCI_NPORTS 3
149# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 136# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
150# define SCI_ONLY 137# define SCI_ONLY
151# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 138# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
139#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
140# define SCSPTR0 0xff923020 /* 16 bit SCIF */
141# define SCSPTR1 0xff924020 /* 16 bit SCIF */
142# define SCSPTR2 0xff925020 /* 16 bit SCIF */
143# define SCIF_ORER 0x0001 /* overrun error bit */
144# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
145# define SCIF_ONLY
146#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
147# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
148# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
149# define SCIF_OPER 0x0001 /* Overrun error bit */
150# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
151# define SCIF_ONLY
152#else 152#else
153# error CPU subtype not defined 153# error CPU subtype not defined
154#endif 154#endif
@@ -158,7 +158,7 @@
158#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 158#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
159#define SCI_CTRL_FLAGS_TE 0x20 /* all */ 159#define SCI_CTRL_FLAGS_TE 0x20 /* all */
160#define SCI_CTRL_FLAGS_RE 0x10 /* all */ 160#define SCI_CTRL_FLAGS_RE 0x10 /* all */
161#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) 161#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
162#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 162#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
163#else 163#else
164#define SCI_CTRL_FLAGS_REIE 0 164#define SCI_CTRL_FLAGS_REIE 0
@@ -213,7 +213,7 @@
213# define SCxSR_RDxF_CLEAR(port) 0xbc 213# define SCxSR_RDxF_CLEAR(port) 0xbc
214# define SCxSR_ERROR_CLEAR(port) 0xc4 214# define SCxSR_ERROR_CLEAR(port) 0xc4
215# define SCxSR_TDxE_CLEAR(port) 0x78 215# define SCxSR_TDxE_CLEAR(port) 0x78
216# define SCxSR_BREAK_CLEAR(port) 0xc4 216# define SCxSR_BREAK_CLEAR(port) 0xc4
217#elif defined(SCIF_ONLY) 217#elif defined(SCIF_ONLY)
218# define SCxSR_TEND(port) SCIF_TEND 218# define SCxSR_TEND(port) SCIF_TEND
219# define SCxSR_ERRORS(port) SCIF_ERRORS 219# define SCxSR_ERRORS(port) SCIF_ERRORS
@@ -237,7 +237,7 @@
237# define SCxSR_RDxF_CLEAR(port) 0x00fc 237# define SCxSR_RDxF_CLEAR(port) 0x00fc
238# define SCxSR_ERROR_CLEAR(port) 0x0073 238# define SCxSR_ERROR_CLEAR(port) 0x0073
239# define SCxSR_TDxE_CLEAR(port) 0x00df 239# define SCxSR_TDxE_CLEAR(port) 0x00df
240# define SCxSR_BREAK_CLEAR(port) 0x00e3 240# define SCxSR_BREAK_CLEAR(port) 0x00e3
241#endif 241#endif
242#else 242#else
243# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 243# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
@@ -285,14 +285,14 @@ struct sci_port {
285 285
286#define SCI_IN(size, offset) \ 286#define SCI_IN(size, offset) \
287 unsigned int addr = port->mapbase + (offset); \ 287 unsigned int addr = port->mapbase + (offset); \
288 if ((size) == 8) { \ 288 if ((size) == 8) { \
289 return ctrl_inb(addr); \ 289 return ctrl_inb(addr); \
290 } else { \ 290 } else { \
291 return ctrl_inw(addr); \ 291 return ctrl_inw(addr); \
292 } 292 }
293#define SCI_OUT(size, offset, value) \ 293#define SCI_OUT(size, offset, value) \
294 unsigned int addr = port->mapbase + (offset); \ 294 unsigned int addr = port->mapbase + (offset); \
295 if ((size) == 8) { \ 295 if ((size) == 8) { \
296 ctrl_outb(value, addr); \ 296 ctrl_outb(value, addr); \
297 } else { \ 297 } else { \
298 ctrl_outw(value, addr); \ 298 ctrl_outw(value, addr); \
@@ -301,10 +301,10 @@ struct sci_port {
301#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 301#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
302 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 302 static inline unsigned int sci_##name##_in(struct uart_port *port) \
303 { \ 303 { \
304 if (port->type == PORT_SCI) { \ 304 if (port->type == PORT_SCI) { \
305 SCI_IN(sci_size, sci_offset) \ 305 SCI_IN(sci_size, sci_offset) \
306 } else { \ 306 } else { \
307 SCI_IN(scif_size, scif_offset); \ 307 SCI_IN(scif_size, scif_offset); \
308 } \ 308 } \
309 } \ 309 } \
310 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 310 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
@@ -319,7 +319,7 @@ struct sci_port {
319#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 319#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
320 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 320 static inline unsigned int sci_##name##_in(struct uart_port *port) \
321 { \ 321 { \
322 SCI_IN(scif_size, scif_offset); \ 322 SCI_IN(scif_size, scif_offset); \
323 } \ 323 } \
324 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 324 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
325 { \ 325 { \
@@ -329,7 +329,7 @@ struct sci_port {
329#define CPU_SCI_FNS(name, sci_offset, sci_size) \ 329#define CPU_SCI_FNS(name, sci_offset, sci_size) \
330 static inline unsigned int sci_##name##_in(struct uart_port* port) \ 330 static inline unsigned int sci_##name##_in(struct uart_port* port) \
331 { \ 331 { \
332 SCI_IN(sci_size, sci_offset); \ 332 SCI_IN(sci_size, sci_offset); \
333 } \ 333 } \
334 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ 334 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
335 { \ 335 { \
@@ -385,10 +385,17 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
385SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 385SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
386SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 386SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
387SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 387SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
388#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
389SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
390SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
391SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
392SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
393#else
388SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 394SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
389SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 395SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
390SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 396SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
391#endif 397#endif
398#endif
392#define sci_in(port, reg) sci_##reg##_in(port) 399#define sci_in(port, reg) sci_##reg##_in(port)
393#define sci_out(port, reg, value) sci_##reg##_out(port, value) 400#define sci_out(port, reg, value) sci_##reg##_out(port, value)
394 401
@@ -518,6 +525,24 @@ static inline int sci_rxd_in(struct uart_port *port)
518 int ch = (port->mapbase - SMR0) >> 3; 525 int ch = (port->mapbase - SMR0) >> 3;
519 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 526 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
520} 527}
528#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
529static inline int sci_rxd_in(struct uart_port *port)
530{
531 if (port->mapbase == 0xff923000)
532 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
533 if (port->mapbase == 0xff924000)
534 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
535 if (port->mapbase == 0xff925000)
536 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
537}
538#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
539static inline int sci_rxd_in(struct uart_port *port)
540{
541 if (port->mapbase == 0xffe00000)
542 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
543 if (port->mapbase == 0xffe10000)
544 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
545}
521#endif 546#endif
522 547
523/* 548/*
@@ -552,22 +577,15 @@ static inline int sci_rxd_in(struct uart_port *port)
552 * -- Mitch Davis - 15 Jul 2000 577 * -- Mitch Davis - 15 Jul 2000
553 */ 578 */
554 579
555#define PCLK (current_cpu_data.module_clock) 580#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
556 581#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
557#if defined(CONFIG_CPU_SUBTYPE_SH7300)
558#define SCBRR_VALUE(bps) ((PCLK+16*bps)/(16*bps)-1)
559#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 582#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
560#define SCBRR_VALUE(bps) (((PCLK*2)+16*bps)/(32*bps)-1) 583#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
561#elif !defined(__H8300H__) && !defined(__H8300S__) 584#elif defined(__H8300H__) || defined(__H8300S__)
562#define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
563#else
564#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) 585#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
586#elif defined(CONFIG_SUPERH64)
587#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
588#else /* Generic SH */
589#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
565#endif 590#endif
566#define BPS_2400 SCBRR_VALUE(2400)
567#define BPS_4800 SCBRR_VALUE(4800)
568#define BPS_9600 SCBRR_VALUE(9600)
569#define BPS_19200 SCBRR_VALUE(19200)
570#define BPS_38400 SCBRR_VALUE(38400)
571#define BPS_57600 SCBRR_VALUE(57600)
572#define BPS_115200 SCBRR_VALUE(115200)
573 591