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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2007-12-25 21:45:06 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:19:02 -0500
commit31a49c4bf8f964b7a9897baa889916d71b51d9c1 (patch)
treee6c900dfbdf51d97d4c189a712a8c4e1aa059cf4 /drivers/serial/sh-sci.h
parent52e8b118ecd17185ce514cd3f955094c1d8f4288 (diff)
sh: Add support for SH7721 CPU subtype.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r--drivers/serial/sh-sci.h21
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 0187dccfe8c1..85562040a6d3 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -46,7 +46,8 @@
46 */ 46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY 48# define SCIF_ONLY
49#elif defined(CONFIG_CPU_SUBTYPE_SH7720) 49#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
50 defined(CONFIG_CPU_SUBTYPE_SH7721)
50# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 51# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51# define SCIF_ONLY 52# define SCIF_ONLY
52#define SCIF_ORER 0x0200 /* overrun error bit */ 53#define SCIF_ORER 0x0200 /* overrun error bit */
@@ -216,7 +217,8 @@
216#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 217#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 218
218#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 219#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
219 defined(CONFIG_CPU_SUBTYPE_SH7720) 220 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
221 defined(CONFIG_CPU_SUBTYPE_SH7721)
220#define SCIF_ORER 0x0200 222#define SCIF_ORER 0x0200
221#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 223#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
222#define SCIF_RFDC_MASK 0x007f 224#define SCIF_RFDC_MASK 0x007f
@@ -254,7 +256,8 @@
254# define SCxSR_PER(port) SCIF_PER 256# define SCxSR_PER(port) SCIF_PER
255# define SCxSR_BRK(port) SCIF_BRK 257# define SCxSR_BRK(port) SCIF_BRK
256#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 258#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7720) 259 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7721)
258# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 261# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
259# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 262# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
260# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 263# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
@@ -363,7 +366,8 @@
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 366#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 367 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
365#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 368#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7720) 369 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
370 defined(CONFIG_CPU_SUBTYPE_SH7721)
367#define SCIF_FNS(name, scif_offset, scif_size) \ 371#define SCIF_FNS(name, scif_offset, scif_size) \
368 CPU_SCIF_FNS(name, scif_offset, scif_size) 372 CPU_SCIF_FNS(name, scif_offset, scif_size)
369#else 373#else
@@ -390,7 +394,8 @@
390#endif 394#endif
391 395
392#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 396#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
393 defined(CONFIG_CPU_SUBTYPE_SH7720) 397 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
398 defined(CONFIG_CPU_SUBTYPE_SH7721)
394 399
395SCIF_FNS(SCSMR, 0x00, 16) 400SCIF_FNS(SCSMR, 0x00, 16)
396SCIF_FNS(SCBRR, 0x04, 8) 401SCIF_FNS(SCBRR, 0x04, 8)
@@ -512,7 +517,8 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
512 return; 517 return;
513 } 518 }
514} 519}
515#elif defined(CONFIG_CPU_SUBTYPE_SH7720) 520#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
521 defined(CONFIG_CPU_SUBTYPE_SH7721)
516static inline int sci_rxd_in(struct uart_port *port) 522static inline int sci_rxd_in(struct uart_port *port)
517{ 523{
518 if (port->mapbase == 0xa4430000) 524 if (port->mapbase == 0xa4430000)
@@ -696,7 +702,8 @@ static inline int sci_rxd_in(struct uart_port *port)
696 defined(CONFIG_CPU_SUBTYPE_SH7785) 702 defined(CONFIG_CPU_SUBTYPE_SH7785)
697#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 703#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
698#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 704#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
699 defined(CONFIG_CPU_SUBTYPE_SH7720) 705 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
706 defined(CONFIG_CPU_SUBTYPE_SH7721)
700#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 707#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
701#elif defined(__H8300H__) || defined(__H8300S__) 708#elif defined(__H8300H__) || defined(__H8300S__)
702#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) 709#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)