diff options
author | David S. Miller <davem@davemloft.net> | 2008-11-07 01:43:03 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-11-07 01:43:03 -0500 |
commit | 9eeda9abd1faf489f3df9a1f557975f4c8650363 (patch) | |
tree | 3e0a58e25b776cfbee193195460324dccb1886c7 /drivers/serial/sh-sci.h | |
parent | 61c9eaf90081cbe6dc4f389e0056bff76eca19ec (diff) | |
parent | 4bab0ea1d42dd1927af9df6fbf0003fc00617c50 (diff) |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
drivers/net/wireless/ath5k/base.c
net/8021q/vlan_core.c
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r-- | drivers/serial/sh-sci.h | 96 |
1 files changed, 26 insertions, 70 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 7cd28b226800..6163a45f968f 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -16,7 +16,6 @@ | |||
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ | 16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | 17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ |
18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
19 | # define SCI_AND_SCIF | ||
20 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | 19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
21 | # define SCIF0 0xA4400000 | 20 | # define SCIF0 0xA4400000 |
22 | # define SCIF2 0xA4410000 | 21 | # define SCIF2 0xA4410000 |
@@ -30,17 +29,15 @@ | |||
30 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | 29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output |
31 | */ | 30 | */ |
32 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | 31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 |
33 | # define SCIF_ONLY | ||
34 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
35 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) |
36 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | 34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
37 | # define SCIF_ONLY | ||
38 | #define SCIF_ORER 0x0200 /* overrun error bit */ | 35 | #define SCIF_ORER 0x0200 /* overrun error bit */ |
39 | #elif defined(CONFIG_SH_RTS7751R2D) | 36 | #elif defined(CONFIG_SH_RTS7751R2D) |
37 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ | ||
40 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | 38 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
41 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 39 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
42 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 40 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
43 | # define SCIF_ONLY | ||
44 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 41 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
45 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 42 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
46 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 43 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
@@ -53,28 +50,24 @@ | |||
53 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | 50 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ |
54 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | 51 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ |
55 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | 52 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) |
56 | # define SCI_AND_SCIF | ||
57 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | 53 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
58 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ | 54 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
59 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | 55 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ |
60 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | 56 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ |
61 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 57 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
62 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 58 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
63 | # define SCIF_ONLY | ||
64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 59 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
65 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | 60 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
66 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 61 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
67 | # define PACR 0xa4050100 | 62 | # define PACR 0xa4050100 |
68 | # define PBCR 0xa4050102 | 63 | # define PBCR 0xa4050102 |
69 | # define SCSCR_INIT(port) 0x3B | 64 | # define SCSCR_INIT(port) 0x3B |
70 | # define SCIF_ONLY | ||
71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) | 65 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
72 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | 66 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ |
73 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | 67 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ |
74 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | 68 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ |
75 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | 69 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ |
76 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | 70 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ |
77 | # define SCIF_ONLY | ||
78 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) | 71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
79 | # define PADR 0xA4050120 | 72 | # define PADR 0xA4050120 |
80 | # define PSDR 0xA405013e | 73 | # define PSDR 0xA405013e |
@@ -82,7 +75,6 @@ | |||
82 | # define PSCR 0xA405011E | 75 | # define PSCR 0xA405011E |
83 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 76 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
84 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 77 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
85 | # define SCIF_ONLY | ||
86 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) | 78 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
87 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | 79 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ |
88 | # define SCSPTR0 SCPDR0 | 80 | # define SCSPTR0 SCPDR0 |
@@ -97,12 +89,10 @@ | |||
97 | # define SCSPTR5 0xa4050128 | 89 | # define SCSPTR5 0xa4050128 |
98 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 90 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
99 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 91 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
100 | # define SCIF_ONLY | ||
101 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | 92 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
102 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | 93 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
103 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 94 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
104 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 95 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
105 | # define SCIF_ONLY | ||
106 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 96 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
107 | # define SCIF_BASE_ADDR 0x01030000 | 97 | # define SCIF_BASE_ADDR 0x01030000 |
108 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | 98 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR |
@@ -111,14 +101,11 @@ | |||
111 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ | 101 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
112 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | 102 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ |
113 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ | 103 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
114 | # define SCIF_ONLY | ||
115 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | 104 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
116 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 105 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
117 | # define SCI_ONLY | ||
118 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 106 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
119 | #elif defined(CONFIG_H8S2678) | 107 | #elif defined(CONFIG_H8S2678) |
120 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 108 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
121 | # define SCI_ONLY | ||
122 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 109 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
123 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | 110 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
124 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 111 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
@@ -126,20 +113,17 @@ | |||
126 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ | 113 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
127 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 114 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
128 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 115 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
129 | # define SCIF_ONLY | ||
130 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) | 116 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
131 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | 117 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ |
132 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | 118 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ |
133 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | 119 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ |
134 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 120 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
135 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | 121 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ |
136 | # define SCIF_ONLY | ||
137 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | 122 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
138 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 123 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
139 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | 124 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ |
140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 125 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 126 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
142 | # define SCIF_ONLY | ||
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) | 127 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
144 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | 128 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
145 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | 129 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ |
@@ -149,7 +133,6 @@ | |||
149 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | 133 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ |
150 | # define SCIF_OPER 0x0001 /* Overrun error bit */ | 134 | # define SCIF_OPER 0x0001 /* Overrun error bit */ |
151 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 135 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
152 | # define SCIF_ONLY | ||
153 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | 136 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
154 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | 137 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
155 | defined(CONFIG_CPU_SUBTYPE_SH7263) | 138 | defined(CONFIG_CPU_SUBTYPE_SH7263) |
@@ -158,14 +141,12 @@ | |||
158 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | 141 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ |
159 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | 142 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ |
160 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 143 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
161 | # define SCIF_ONLY | ||
162 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | 144 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
163 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | 145 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ |
164 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | 146 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |
165 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | 147 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ |
166 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 148 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
167 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 149 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
168 | # define SCIF_ONLY | ||
169 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) | 150 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
170 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | 151 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ |
171 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | 152 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ |
@@ -173,7 +154,6 @@ | |||
173 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | 154 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ |
174 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 155 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
175 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 156 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
176 | # define SCIF_ONLY | ||
177 | #else | 157 | #else |
178 | # error CPU subtype not defined | 158 | # error CPU subtype not defined |
179 | #endif | 159 | #endif |
@@ -186,6 +166,7 @@ | |||
186 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 166 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
187 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | 167 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ |
188 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 168 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
169 | defined(CONFIG_CPU_SUBTYPE_SH7722) || \ | ||
189 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 170 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
190 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 171 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
191 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | 172 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ |
@@ -244,55 +225,28 @@ | |||
244 | # define SCIF_TXROOM_MAX 16 | 225 | # define SCIF_TXROOM_MAX 16 |
245 | #endif | 226 | #endif |
246 | 227 | ||
247 | #if defined(SCI_ONLY) | 228 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
248 | # define SCxSR_TEND(port) SCI_TEND | 229 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) |
249 | # define SCxSR_ERRORS(port) SCI_ERRORS | 230 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) |
250 | # define SCxSR_RDxF(port) SCI_RDRF | 231 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) |
251 | # define SCxSR_TDxE(port) SCI_TDRE | 232 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) |
252 | # define SCxSR_ORER(port) SCI_ORER | 233 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) |
253 | # define SCxSR_FER(port) SCI_FER | 234 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) |
254 | # define SCxSR_PER(port) SCI_PER | 235 | |
255 | # define SCxSR_BRK(port) 0x00 | ||
256 | # define SCxSR_RDxF_CLEAR(port) 0xbc | ||
257 | # define SCxSR_ERROR_CLEAR(port) 0xc4 | ||
258 | # define SCxSR_TDxE_CLEAR(port) 0x78 | ||
259 | # define SCxSR_BREAK_CLEAR(port) 0xc4 | ||
260 | #elif defined(SCIF_ONLY) | ||
261 | # define SCxSR_TEND(port) SCIF_TEND | ||
262 | # define SCxSR_ERRORS(port) SCIF_ERRORS | ||
263 | # define SCxSR_RDxF(port) SCIF_RDF | ||
264 | # define SCxSR_TDxE(port) SCIF_TDFE | ||
265 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) | 236 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
266 | # define SCxSR_ORER(port) SCIF_ORER | 237 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
267 | #else | 238 | #else |
268 | # define SCxSR_ORER(port) 0x0000 | 239 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) |
269 | #endif | 240 | #endif |
270 | # define SCxSR_FER(port) SCIF_FER | 241 | |
271 | # define SCxSR_PER(port) SCIF_PER | ||
272 | # define SCxSR_BRK(port) SCIF_BRK | ||
273 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 242 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
274 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 243 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
275 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 244 | defined(CONFIG_CPU_SUBTYPE_SH7721) |
276 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) | 245 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
277 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) | 246 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) |
278 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) | 247 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) |
279 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) | 248 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) |
280 | #else | ||
281 | /* SH7705 can also use this, clearing is same between 7705 and 7709 */ | ||
282 | # define SCxSR_RDxF_CLEAR(port) 0x00fc | ||
283 | # define SCxSR_ERROR_CLEAR(port) 0x0073 | ||
284 | # define SCxSR_TDxE_CLEAR(port) 0x00df | ||
285 | # define SCxSR_BREAK_CLEAR(port) 0x00e3 | ||
286 | #endif | ||
287 | #else | 249 | #else |
288 | # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | ||
289 | # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | ||
290 | # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | ||
291 | # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | ||
292 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) | ||
293 | # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | ||
294 | # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | ||
295 | # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | ||
296 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | 250 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
297 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | 251 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) |
298 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | 252 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) |
@@ -574,18 +528,20 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
574 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | 528 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ |
575 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 529 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
576 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 530 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
577 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | 531 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
578 | defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
579 | static inline int sci_rxd_in(struct uart_port *port) | 532 | static inline int sci_rxd_in(struct uart_port *port) |
580 | { | 533 | { |
581 | #ifndef SCIF_ONLY | ||
582 | if (port->mapbase == 0xffe00000) | 534 | if (port->mapbase == 0xffe00000) |
583 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | 535 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
584 | #endif | ||
585 | #ifndef SCI_ONLY | ||
586 | if (port->mapbase == 0xffe80000) | 536 | if (port->mapbase == 0xffe80000) |
587 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | 537 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
588 | #endif | 538 | return 1; |
539 | } | ||
540 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
541 | static inline int sci_rxd_in(struct uart_port *port) | ||
542 | { | ||
543 | if (port->mapbase == 0xffe80000) | ||
544 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
589 | return 1; | 545 | return 1; |
590 | } | 546 | } |
591 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | 547 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
@@ -651,7 +607,7 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
651 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 607 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
652 | static inline int sci_rxd_in(struct uart_port *port) | 608 | static inline int sci_rxd_in(struct uart_port *port) |
653 | { | 609 | { |
654 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | 610 | return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
655 | } | 611 | } |
656 | #elif defined(__H8300H__) || defined(__H8300S__) | 612 | #elif defined(__H8300H__) || defined(__H8300S__) |
657 | static inline int sci_rxd_in(struct uart_port *port) | 613 | static inline int sci_rxd_in(struct uart_port *port) |