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authorLinus Torvalds <torvalds@g5.osdl.org>2006-03-21 11:52:18 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-21 11:52:18 -0500
commitb05005772f34497eb2b7415a651fe785cbe70e16 (patch)
treeb176aeb7fa9baf69e77ddd83e844727490bfcf28 /drivers/serial/sh-sci.c
parent044f324f6ea5d55391db62fca6a295b2651cb946 (diff)
parent7705a8792b0fc82fd7d4dd923724606bbfd9fb20 (diff)
Merge branch 'origin'
Conflicts: Documentation/video4linux/CARDLIST.cx88 drivers/media/video/cx88/Kconfig drivers/media/video/em28xx/em28xx-video.c drivers/media/video/saa7134/saa7134-dvb.c Resolved as in the original merge by Mauro Carvalho Chehab
Diffstat (limited to 'drivers/serial/sh-sci.c')
-rw-r--r--drivers/serial/sh-sci.c317
1 files changed, 203 insertions, 114 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index a9e070759628..44f6bf79bbe1 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -42,6 +42,7 @@
42#include <linux/delay.h> 42#include <linux/delay.h>
43#include <linux/console.h> 43#include <linux/console.h>
44#include <linux/bitops.h> 44#include <linux/bitops.h>
45#include <linux/generic_serial.h>
45 46
46#ifdef CONFIG_CPU_FREQ 47#ifdef CONFIG_CPU_FREQ
47#include <linux/notifier.h> 48#include <linux/notifier.h>
@@ -53,7 +54,9 @@
53#include <asm/irq.h> 54#include <asm/irq.h>
54#include <asm/uaccess.h> 55#include <asm/uaccess.h>
55 56
56#include <linux/generic_serial.h> 57#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
58#include <asm/clock.h>
59#endif
57 60
58#ifdef CONFIG_SH_STANDARD_BIOS 61#ifdef CONFIG_SH_STANDARD_BIOS
59#include <asm/sh_bios.h> 62#include <asm/sh_bios.h>
@@ -86,9 +89,11 @@ static void sci_stop_rx(struct uart_port *port);
86static int sci_request_irq(struct sci_port *port); 89static int sci_request_irq(struct sci_port *port);
87static void sci_free_irq(struct sci_port *port); 90static void sci_free_irq(struct sci_port *port);
88 91
89static struct sci_port sci_ports[SCI_NPORTS]; 92static struct sci_port sci_ports[];
90static struct uart_driver sci_uart_driver; 93static struct uart_driver sci_uart_driver;
91 94
95#define SCI_NPORTS sci_uart_driver.nr
96
92#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) 97#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
93 98
94static void handle_error(struct uart_port *port) 99static void handle_error(struct uart_port *port)
@@ -168,7 +173,7 @@ static void put_string(struct sci_port *sci_port, const char *buffer, int count)
168 int usegdb=0; 173 int usegdb=0;
169 174
170#ifdef CONFIG_SH_STANDARD_BIOS 175#ifdef CONFIG_SH_STANDARD_BIOS
171 /* This call only does a trap the first time it is 176 /* This call only does a trap the first time it is
172 * called, and so is safe to do here unconditionally 177 * called, and so is safe to do here unconditionally
173 */ 178 */
174 usegdb |= sh_bios_in_gdb_mode(); 179 usegdb |= sh_bios_in_gdb_mode();
@@ -324,47 +329,46 @@ static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
324 /* tx mark output*/ 329 /* tx mark output*/
325 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; 330 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
326} 331}
327#else
328static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
329{
330}
331#endif 332#endif
332#endif 333#endif
333 334
334#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 335#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
335#if defined(CONFIG_CPU_SH3) 336#if defined(CONFIG_CPU_SUBTYPE_SH7300)
336/* For SH7705, SH7707, SH7709, SH7709A, SH7729, SH7300*/ 337/* SH7300 doesn't use RTS/CTS */
338static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339{
340 sci_out(port, SCFCR, 0);
341}
342#elif defined(CONFIG_CPU_SH3)
343/* For SH7705, SH7707, SH7709, SH7709A, SH7729 */
337static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 344static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338{ 345{
339 unsigned int fcr_val = 0; 346 unsigned int fcr_val = 0;
340#if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */ 347 unsigned short data;
341 { 348
342 unsigned short data; 349 /* We need to set SCPCR to enable RTS/CTS */
350 data = ctrl_inw(SCPCR);
351 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
352 ctrl_outw(data & 0x0fcf, SCPCR);
343 353
344 /* We need to set SCPCR to enable RTS/CTS */
345 data = ctrl_inw(SCPCR);
346 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
347 ctrl_outw(data&0x0fcf, SCPCR);
348 }
349 if (cflag & CRTSCTS) 354 if (cflag & CRTSCTS)
350 fcr_val |= SCFCR_MCE; 355 fcr_val |= SCFCR_MCE;
351 else { 356 else {
352 unsigned short data;
353
354 /* We need to set SCPCR to enable RTS/CTS */ 357 /* We need to set SCPCR to enable RTS/CTS */
355 data = ctrl_inw(SCPCR); 358 data = ctrl_inw(SCPCR);
356 /* Clear out SCP7MD1,0, SCP4MD1,0, 359 /* Clear out SCP7MD1,0, SCP4MD1,0,
357 Set SCP6MD1,0 = {01} (output) */ 360 Set SCP6MD1,0 = {01} (output) */
358 ctrl_outw((data&0x0fcf)|0x1000, SCPCR); 361 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
359 362
360 data = ctrl_inb(SCPDR); 363 data = ctrl_inb(SCPDR);
361 /* Set /RTS2 (bit6) = 0 */ 364 /* Set /RTS2 (bit6) = 0 */
362 ctrl_outb(data&0xbf, SCPDR); 365 ctrl_outb(data & 0xbf, SCPDR);
363 } 366 }
364#endif 367
365 sci_out(port, SCFCR, fcr_val); 368 sci_out(port, SCFCR, fcr_val);
366} 369}
367 370
371#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
368static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) 372static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
369{ 373{
370 unsigned int fcr_val = 0; 374 unsigned int fcr_val = 0;
@@ -374,7 +378,7 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
374 378
375 sci_out(port, SCFCR, fcr_val); 379 sci_out(port, SCFCR, fcr_val);
376} 380}
377 381#endif
378#else 382#else
379 383
380/* For SH7750 */ 384/* For SH7750 */
@@ -385,7 +389,11 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
385 if (cflag & CRTSCTS) { 389 if (cflag & CRTSCTS) {
386 fcr_val |= SCFCR_MCE; 390 fcr_val |= SCFCR_MCE;
387 } else { 391 } else {
392#ifdef CONFIG_CPU_SUBTYPE_SH7780
393 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
394#else
388 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ 395 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
396#endif
389 } 397 }
390 sci_out(port, SCFCR, fcr_val); 398 sci_out(port, SCFCR, fcr_val);
391} 399}
@@ -422,7 +430,11 @@ static void sci_transmit_chars(struct uart_port *port)
422 430
423#if !defined(SCI_ONLY) 431#if !defined(SCI_ONLY)
424 if (port->type == PORT_SCIF) { 432 if (port->type == PORT_SCIF) {
433#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
434 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
435#else
425 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8); 436 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
437#endif
426 } else { 438 } else {
427 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0; 439 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
428 } 440 }
@@ -491,7 +503,11 @@ static inline void sci_receive_chars(struct uart_port *port,
491 while (1) { 503 while (1) {
492#if !defined(SCI_ONLY) 504#if !defined(SCI_ONLY)
493 if (port->type == PORT_SCIF) { 505 if (port->type == PORT_SCIF) {
506#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
507 count = sci_in(port, SCRFDR) & 0x7f;
508#else
494 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ; 509 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
510#endif
495 } else { 511 } else {
496 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0; 512 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
497 } 513 }
@@ -652,7 +668,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
652 struct tty_struct *tty = port->info->tty; 668 struct tty_struct *tty = port->info->tty;
653 struct sci_port *s = &sci_ports[port->line]; 669 struct sci_port *s = &sci_ports[port->line];
654 670
655 if (!s->break_flag && status & SCxSR_BRK(port)) 671 if (!s->break_flag && status & SCxSR_BRK(port)) {
656#if defined(CONFIG_CPU_SH3) 672#if defined(CONFIG_CPU_SH3)
657 /* Debounce break */ 673 /* Debounce break */
658 s->break_flag = 1; 674 s->break_flag = 1;
@@ -783,6 +799,7 @@ static int sci_notifier(struct notifier_block *self, unsigned long phase, void *
783 (phase == CPUFREQ_RESUMECHANGE)){ 799 (phase == CPUFREQ_RESUMECHANGE)){
784 for (i = 0; i < SCI_NPORTS; i++) { 800 for (i = 0; i < SCI_NPORTS; i++) {
785 struct uart_port *port = &sci_ports[i].port; 801 struct uart_port *port = &sci_ports[i].port;
802 struct clk *clk;
786 803
787 /* 804 /*
788 * Update the uartclk per-port if frequency has 805 * Update the uartclk per-port if frequency has
@@ -795,7 +812,9 @@ static int sci_notifier(struct notifier_block *self, unsigned long phase, void *
795 * 812 *
796 * Clean this up later.. 813 * Clean this up later..
797 */ 814 */
798 port->uartclk = current_cpu_data.module_clock * 16; 815 clk = clk_get("module_clk");
816 port->uartclk = clk_get_rate(clk) * 16;
817 clk_put(clk);
799 } 818 }
800 819
801 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n", 820 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
@@ -1008,15 +1027,20 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1008 sci_out(port, SCSMR, smr_val); 1027 sci_out(port, SCSMR, smr_val);
1009 1028
1010 switch (baud) { 1029 switch (baud) {
1011 case 0: t = -1; break; 1030 case 0:
1012 case 2400: t = BPS_2400; break; 1031 t = -1;
1013 case 4800: t = BPS_4800; break; 1032 break;
1014 case 9600: t = BPS_9600; break; 1033 default:
1015 case 19200: t = BPS_19200; break; 1034 {
1016 case 38400: t = BPS_38400; break; 1035#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1017 case 57600: t = BPS_57600; break; 1036 struct clk *clk = clk_get("module_clk");
1018 case 115200: t = BPS_115200; break; 1037 t = SCBRR_VALUE(baud, clk_get_rate(clk));
1019 default: t = SCBRR_VALUE(baud); break; 1038 clk_put(clk);
1039#else
1040 t = SCBRR_VALUE(baud);
1041#endif
1042 }
1043 break;
1020 } 1044 }
1021 1045
1022 if (t > 0) { 1046 if (t > 0) {
@@ -1030,7 +1054,9 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1030 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1054 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1031 } 1055 }
1032 1056
1033 s->init_pins(port, termios->c_cflag); 1057 if (likely(s->init_pins))
1058 s->init_pins(port, termios->c_cflag);
1059
1034 sci_out(port, SCSCR, SCSCR_INIT(port)); 1060 sci_out(port, SCSCR, SCSCR_INIT(port));
1035 1061
1036 if ((termios->c_cflag & CREAD) != 0) 1062 if ((termios->c_cflag & CREAD) != 0)
@@ -1107,31 +1133,30 @@ static struct uart_ops sci_uart_ops = {
1107 .verify_port = sci_verify_port, 1133 .verify_port = sci_verify_port,
1108}; 1134};
1109 1135
1110static struct sci_port sci_ports[SCI_NPORTS] = { 1136static struct sci_port sci_ports[] = {
1111#if defined(CONFIG_CPU_SUBTYPE_SH7708) 1137#if defined(CONFIG_CPU_SUBTYPE_SH7708)
1112 { 1138 {
1113 .port = { 1139 .port = {
1114 .membase = (void *)0xfffffe80, 1140 .membase = (void *)0xfffffe80,
1115 .mapbase = 0xfffffe80, 1141 .mapbase = 0xfffffe80,
1116 .iotype = SERIAL_IO_MEM, 1142 .iotype = UPIO_MEM,
1117 .irq = 25, 1143 .irq = 25,
1118 .ops = &sci_uart_ops, 1144 .ops = &sci_uart_ops,
1119 .flags = ASYNC_BOOT_AUTOCONF, 1145 .flags = UPF_BOOT_AUTOCONF,
1120 .line = 0, 1146 .line = 0,
1121 }, 1147 },
1122 .type = PORT_SCI, 1148 .type = PORT_SCI,
1123 .irqs = SCI_IRQS, 1149 .irqs = SCI_IRQS,
1124 .init_pins = sci_init_pins_sci,
1125 }, 1150 },
1126#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 1151#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
1127 { 1152 {
1128 .port = { 1153 .port = {
1129 .membase = (void *)SCIF0, 1154 .membase = (void *)SCIF0,
1130 .mapbase = SCIF0, 1155 .mapbase = SCIF0,
1131 .iotype = SERIAL_IO_MEM, 1156 .iotype = UPIO_MEM,
1132 .irq = 55, 1157 .irq = 55,
1133 .ops = &sci_uart_ops, 1158 .ops = &sci_uart_ops,
1134 .flags = ASYNC_BOOT_AUTOCONF, 1159 .flags = UPF_BOOT_AUTOCONF,
1135 .line = 0, 1160 .line = 0,
1136 }, 1161 },
1137 .type = PORT_SCIF, 1162 .type = PORT_SCIF,
@@ -1142,10 +1167,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1142 .port = { 1167 .port = {
1143 .membase = (void *)SCIF2, 1168 .membase = (void *)SCIF2,
1144 .mapbase = SCIF2, 1169 .mapbase = SCIF2,
1145 .iotype = SERIAL_IO_MEM, 1170 .iotype = UPIO_MEM,
1146 .irq = 59, 1171 .irq = 59,
1147 .ops = &sci_uart_ops, 1172 .ops = &sci_uart_ops,
1148 .flags = ASYNC_BOOT_AUTOCONF, 1173 .flags = UPF_BOOT_AUTOCONF,
1149 .line = 1, 1174 .line = 1,
1150 }, 1175 },
1151 .type = PORT_SCIF, 1176 .type = PORT_SCIF,
@@ -1157,24 +1182,23 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1157 .port = { 1182 .port = {
1158 .membase = (void *)0xfffffe80, 1183 .membase = (void *)0xfffffe80,
1159 .mapbase = 0xfffffe80, 1184 .mapbase = 0xfffffe80,
1160 .iotype = SERIAL_IO_MEM, 1185 .iotype = UPIO_MEM,
1161 .irq = 25, 1186 .irq = 25,
1162 .ops = &sci_uart_ops, 1187 .ops = &sci_uart_ops,
1163 .flags = ASYNC_BOOT_AUTOCONF, 1188 .flags = UPF_BOOT_AUTOCONF,
1164 .line = 0, 1189 .line = 0,
1165 }, 1190 },
1166 .type = PORT_SCI, 1191 .type = PORT_SCI,
1167 .irqs = SCI_IRQS, 1192 .irqs = SCI_IRQS,
1168 .init_pins = sci_init_pins_sci,
1169 }, 1193 },
1170 { 1194 {
1171 .port = { 1195 .port = {
1172 .membase = (void *)0xa4000150, 1196 .membase = (void *)0xa4000150,
1173 .mapbase = 0xa4000150, 1197 .mapbase = 0xa4000150,
1174 .iotype = SERIAL_IO_MEM, 1198 .iotype = UPIO_MEM,
1175 .irq = 59, 1199 .irq = 59,
1176 .ops = &sci_uart_ops, 1200 .ops = &sci_uart_ops,
1177 .flags = ASYNC_BOOT_AUTOCONF, 1201 .flags = UPF_BOOT_AUTOCONF,
1178 .line = 1, 1202 .line = 1,
1179 }, 1203 },
1180 .type = PORT_SCIF, 1204 .type = PORT_SCIF,
@@ -1185,10 +1209,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1185 .port = { 1209 .port = {
1186 .membase = (void *)0xa4000140, 1210 .membase = (void *)0xa4000140,
1187 .mapbase = 0xa4000140, 1211 .mapbase = 0xa4000140,
1188 .iotype = SERIAL_IO_MEM, 1212 .iotype = UPIO_MEM,
1189 .irq = 55, 1213 .irq = 55,
1190 .ops = &sci_uart_ops, 1214 .ops = &sci_uart_ops,
1191 .flags = ASYNC_BOOT_AUTOCONF, 1215 .flags = UPF_BOOT_AUTOCONF,
1192 .line = 2, 1216 .line = 2,
1193 }, 1217 },
1194 .type = PORT_IRDA, 1218 .type = PORT_IRDA,
@@ -1200,10 +1224,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1200 .port = { 1224 .port = {
1201 .membase = (void *)0xA4430000, 1225 .membase = (void *)0xA4430000,
1202 .mapbase = 0xA4430000, 1226 .mapbase = 0xA4430000,
1203 .iotype = SERIAL_IO_MEM, 1227 .iotype = UPIO_MEM,
1204 .irq = 25, 1228 .irq = 25,
1205 .ops = &sci_uart_ops, 1229 .ops = &sci_uart_ops,
1206 .flags = ASYNC_BOOT_AUTOCONF, 1230 .flags = UPF_BOOT_AUTOCONF,
1207 .line = 0, 1231 .line = 0,
1208 }, 1232 },
1209 .type = PORT_SCIF, 1233 .type = PORT_SCIF,
@@ -1215,25 +1239,25 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1215 .port = { 1239 .port = {
1216 .membase = (void *)0xffe00000, 1240 .membase = (void *)0xffe00000,
1217 .mapbase = 0xffe00000, 1241 .mapbase = 0xffe00000,
1218 .iotype = SERIAL_IO_MEM, 1242 .iotype = UPIO_MEM,
1219 .irq = 25, 1243 .irq = 25,
1220 .ops = &sci_uart_ops, 1244 .ops = &sci_uart_ops,
1221 .flags = ASYNC_BOOT_AUTOCONF, 1245 .flags = UPF_BOOT_AUTOCONF,
1222 .line = 0, 1246 .line = 0,
1223 }, 1247 },
1224 .type = PORT_SCIF, 1248 .type = PORT_SCIF,
1225 .irqs = SH73180_SCIF_IRQS, 1249 .irqs = SH73180_SCIF_IRQS,
1226 .init_pins = sci_init_pins_scif, 1250 .init_pins = sci_init_pins_scif,
1227 }, 1251 },
1228#elif defined(CONFIG_SH_RTS7751R2D) 1252#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1229 { 1253 {
1230 .port = { 1254 .port = {
1231 .membase = (void *)0xffe80000, 1255 .membase = (void *)0xffe80000,
1232 .mapbase = 0xffe80000, 1256 .mapbase = 0xffe80000,
1233 .iotype = SERIAL_IO_MEM, 1257 .iotype = UPIO_MEM,
1234 .irq = 43, 1258 .irq = 43,
1235 .ops = &sci_uart_ops, 1259 .ops = &sci_uart_ops,
1236 .flags = ASYNC_BOOT_AUTOCONF, 1260 .flags = UPF_BOOT_AUTOCONF,
1237 .line = 0, 1261 .line = 0,
1238 }, 1262 },
1239 .type = PORT_SCIF, 1263 .type = PORT_SCIF,
@@ -1245,24 +1269,23 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1245 .port = { 1269 .port = {
1246 .membase = (void *)0xffe00000, 1270 .membase = (void *)0xffe00000,
1247 .mapbase = 0xffe00000, 1271 .mapbase = 0xffe00000,
1248 .iotype = SERIAL_IO_MEM, 1272 .iotype = UPIO_MEM,
1249 .irq = 25, 1273 .irq = 25,
1250 .ops = &sci_uart_ops, 1274 .ops = &sci_uart_ops,
1251 .flags = ASYNC_BOOT_AUTOCONF, 1275 .flags = UPF_BOOT_AUTOCONF,
1252 .line = 0, 1276 .line = 0,
1253 }, 1277 },
1254 .type = PORT_SCI, 1278 .type = PORT_SCI,
1255 .irqs = SCI_IRQS, 1279 .irqs = SCI_IRQS,
1256 .init_pins = sci_init_pins_sci,
1257 }, 1280 },
1258 { 1281 {
1259 .port = { 1282 .port = {
1260 .membase = (void *)0xffe80000, 1283 .membase = (void *)0xffe80000,
1261 .mapbase = 0xffe80000, 1284 .mapbase = 0xffe80000,
1262 .iotype = SERIAL_IO_MEM, 1285 .iotype = UPIO_MEM,
1263 .irq = 43, 1286 .irq = 43,
1264 .ops = &sci_uart_ops, 1287 .ops = &sci_uart_ops,
1265 .flags = ASYNC_BOOT_AUTOCONF, 1288 .flags = UPF_BOOT_AUTOCONF,
1266 .line = 1, 1289 .line = 1,
1267 }, 1290 },
1268 .type = PORT_SCIF, 1291 .type = PORT_SCIF,
@@ -1274,10 +1297,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1274 .port = { 1297 .port = {
1275 .membase = (void *)0xfe600000, 1298 .membase = (void *)0xfe600000,
1276 .mapbase = 0xfe600000, 1299 .mapbase = 0xfe600000,
1277 .iotype = SERIAL_IO_MEM, 1300 .iotype = UPIO_MEM,
1278 .irq = 55, 1301 .irq = 55,
1279 .ops = &sci_uart_ops, 1302 .ops = &sci_uart_ops,
1280 .flags = ASYNC_BOOT_AUTOCONF, 1303 .flags = UPF_BOOT_AUTOCONF,
1281 .line = 0, 1304 .line = 0,
1282 }, 1305 },
1283 .type = PORT_SCIF, 1306 .type = PORT_SCIF,
@@ -1288,10 +1311,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1288 .port = { 1311 .port = {
1289 .membase = (void *)0xfe610000, 1312 .membase = (void *)0xfe610000,
1290 .mapbase = 0xfe610000, 1313 .mapbase = 0xfe610000,
1291 .iotype = SERIAL_IO_MEM, 1314 .iotype = UPIO_MEM,
1292 .irq = 75, 1315 .irq = 75,
1293 .ops = &sci_uart_ops, 1316 .ops = &sci_uart_ops,
1294 .flags = ASYNC_BOOT_AUTOCONF, 1317 .flags = UPF_BOOT_AUTOCONF,
1295 .line = 1, 1318 .line = 1,
1296 }, 1319 },
1297 .type = PORT_SCIF, 1320 .type = PORT_SCIF,
@@ -1302,40 +1325,25 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1302 .port = { 1325 .port = {
1303 .membase = (void *)0xfe620000, 1326 .membase = (void *)0xfe620000,
1304 .mapbase = 0xfe620000, 1327 .mapbase = 0xfe620000,
1305 .iotype = SERIAL_IO_MEM, 1328 .iotype = UPIO_MEM,
1306 .irq = 79, 1329 .irq = 79,
1307 .ops = &sci_uart_ops, 1330 .ops = &sci_uart_ops,
1308 .flags = ASYNC_BOOT_AUTOCONF, 1331 .flags = UPF_BOOT_AUTOCONF,
1309 .line = 2, 1332 .line = 2,
1310 }, 1333 },
1311 .type = PORT_SCIF, 1334 .type = PORT_SCIF,
1312 .irqs = SH7760_SCIF2_IRQS, 1335 .irqs = SH7760_SCIF2_IRQS,
1313 .init_pins = sci_init_pins_scif, 1336 .init_pins = sci_init_pins_scif,
1314 }, 1337 },
1315#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1316 {
1317 .port = {
1318 .membase = (void *)0xffe80000,
1319 .mapbase = 0xffe80000,
1320 .iotype = SERIAL_IO_MEM,
1321 .irq = 43,
1322 .ops = &sci_uart_ops,
1323 .flags = ASYNC_BOOT_AUTOCONF,
1324 .line = 0,
1325 },
1326 .type = PORT_SCIF,
1327 .irqs = SH4_SCIF_IRQS,
1328 .init_pins = sci_init_pins_scif,
1329 },
1330#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 1338#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1331 { 1339 {
1332 .port = { 1340 .port = {
1333 .membase = (void *)0xffe00000, 1341 .membase = (void *)0xffe00000,
1334 .mapbase = 0xffe00000, 1342 .mapbase = 0xffe00000,
1335 .iotype = SERIAL_IO_MEM, 1343 .iotype = UPIO_MEM,
1336 .irq = 26, 1344 .irq = 26,
1337 .ops = &sci_uart_ops, 1345 .ops = &sci_uart_ops,
1338 .flags = ASYNC_BOOT_AUTOCONF, 1346 .flags = UPF_BOOT_AUTOCONF,
1339 .line = 0, 1347 .line = 0,
1340 }, 1348 },
1341 .type = PORT_SCIF, 1349 .type = PORT_SCIF,
@@ -1346,10 +1354,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1346 .port = { 1354 .port = {
1347 .membase = (void *)0xffe80000, 1355 .membase = (void *)0xffe80000,
1348 .mapbase = 0xffe80000, 1356 .mapbase = 0xffe80000,
1349 .iotype = SERIAL_IO_MEM, 1357 .iotype = UPIO_MEM,
1350 .irq = 43, 1358 .irq = 43,
1351 .ops = &sci_uart_ops, 1359 .ops = &sci_uart_ops,
1352 .flags = ASYNC_BOOT_AUTOCONF, 1360 .flags = UPF_BOOT_AUTOCONF,
1353 .line = 1, 1361 .line = 1,
1354 }, 1362 },
1355 .type = PORT_SCIF, 1363 .type = PORT_SCIF,
@@ -1359,10 +1367,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1359#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 1367#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1360 { 1368 {
1361 .port = { 1369 .port = {
1362 .iotype = SERIAL_IO_MEM, 1370 .iotype = UPIO_MEM,
1363 .irq = 42, 1371 .irq = 42,
1364 .ops = &sci_uart_ops, 1372 .ops = &sci_uart_ops,
1365 .flags = ASYNC_BOOT_AUTOCONF, 1373 .flags = UPF_BOOT_AUTOCONF,
1366 .line = 0, 1374 .line = 0,
1367 }, 1375 },
1368 .type = PORT_SCIF, 1376 .type = PORT_SCIF,
@@ -1374,10 +1382,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1374 .port = { 1382 .port = {
1375 .membase = (void *)0x00ffffb0, 1383 .membase = (void *)0x00ffffb0,
1376 .mapbase = 0x00ffffb0, 1384 .mapbase = 0x00ffffb0,
1377 .iotype = SERIAL_IO_MEM, 1385 .iotype = UPIO_MEM,
1378 .irq = 54, 1386 .irq = 54,
1379 .ops = &sci_uart_ops, 1387 .ops = &sci_uart_ops,
1380 .flags = ASYNC_BOOT_AUTOCONF, 1388 .flags = UPF_BOOT_AUTOCONF,
1381 .line = 0, 1389 .line = 0,
1382 }, 1390 },
1383 .type = PORT_SCI, 1391 .type = PORT_SCI,
@@ -1388,10 +1396,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1388 .port = { 1396 .port = {
1389 .membase = (void *)0x00ffffb8, 1397 .membase = (void *)0x00ffffb8,
1390 .mapbase = 0x00ffffb8, 1398 .mapbase = 0x00ffffb8,
1391 .iotype = SERIAL_IO_MEM, 1399 .iotype = UPIO_MEM,
1392 .irq = 58, 1400 .irq = 58,
1393 .ops = &sci_uart_ops, 1401 .ops = &sci_uart_ops,
1394 .flags = ASYNC_BOOT_AUTOCONF, 1402 .flags = UPF_BOOT_AUTOCONF,
1395 .line = 1, 1403 .line = 1,
1396 }, 1404 },
1397 .type = PORT_SCI, 1405 .type = PORT_SCI,
@@ -1402,10 +1410,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1402 .port = { 1410 .port = {
1403 .membase = (void *)0x00ffffc0, 1411 .membase = (void *)0x00ffffc0,
1404 .mapbase = 0x00ffffc0, 1412 .mapbase = 0x00ffffc0,
1405 .iotype = SERIAL_IO_MEM, 1413 .iotype = UPIO_MEM,
1406 .irq = 62, 1414 .irq = 62,
1407 .ops = &sci_uart_ops, 1415 .ops = &sci_uart_ops,
1408 .flags = ASYNC_BOOT_AUTOCONF, 1416 .flags = UPF_BOOT_AUTOCONF,
1409 .line = 2, 1417 .line = 2,
1410 }, 1418 },
1411 .type = PORT_SCI, 1419 .type = PORT_SCI,
@@ -1417,10 +1425,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1417 .port = { 1425 .port = {
1418 .membase = (void *)0x00ffff78, 1426 .membase = (void *)0x00ffff78,
1419 .mapbase = 0x00ffff78, 1427 .mapbase = 0x00ffff78,
1420 .iotype = SERIAL_IO_MEM, 1428 .iotype = UPIO_MEM,
1421 .irq = 90, 1429 .irq = 90,
1422 .ops = &sci_uart_ops, 1430 .ops = &sci_uart_ops,
1423 .flags = ASYNC_BOOT_AUTOCONF, 1431 .flags = UPF_BOOT_AUTOCONF,
1424 .line = 0, 1432 .line = 0,
1425 }, 1433 },
1426 .type = PORT_SCI, 1434 .type = PORT_SCI,
@@ -1431,10 +1439,10 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1431 .port = { 1439 .port = {
1432 .membase = (void *)0x00ffff80, 1440 .membase = (void *)0x00ffff80,
1433 .mapbase = 0x00ffff80, 1441 .mapbase = 0x00ffff80,
1434 .iotype = SERIAL_IO_MEM, 1442 .iotype = UPIO_MEM,
1435 .irq = 94, 1443 .irq = 94,
1436 .ops = &sci_uart_ops, 1444 .ops = &sci_uart_ops,
1437 .flags = ASYNC_BOOT_AUTOCONF, 1445 .flags = UPF_BOOT_AUTOCONF,
1438 .line = 1, 1446 .line = 1,
1439 }, 1447 },
1440 .type = PORT_SCI, 1448 .type = PORT_SCI,
@@ -1445,16 +1453,88 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
1445 .port = { 1453 .port = {
1446 .membase = (void *)0x00ffff88, 1454 .membase = (void *)0x00ffff88,
1447 .mapbase = 0x00ffff88, 1455 .mapbase = 0x00ffff88,
1448 .iotype = SERIAL_IO_MEM, 1456 .iotype = UPIO_MEM,
1449 .irq = 98, 1457 .irq = 98,
1450 .ops = &sci_uart_ops, 1458 .ops = &sci_uart_ops,
1451 .flags = ASYNC_BOOT_AUTOCONF, 1459 .flags = UPF_BOOT_AUTOCONF,
1452 .line = 2, 1460 .line = 2,
1453 }, 1461 },
1454 .type = PORT_SCI, 1462 .type = PORT_SCI,
1455 .irqs = H8S_SCI_IRQS2, 1463 .irqs = H8S_SCI_IRQS2,
1456 .init_pins = sci_init_pins_sci, 1464 .init_pins = sci_init_pins_sci,
1457 }, 1465 },
1466#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
1467 {
1468 .port = {
1469 .membase = (void *)0xff923000,
1470 .mapbase = 0xff923000,
1471 .iotype = UPIO_MEM,
1472 .irq = 61,
1473 .ops = &sci_uart_ops,
1474 .flags = UPF_BOOT_AUTOCONF,
1475 .line = 0,
1476 },
1477 .type = PORT_SCIF,
1478 .irqs = SH7770_SCIF0_IRQS,
1479 .init_pins = sci_init_pins_scif,
1480 },
1481 {
1482 .port = {
1483 .membase = (void *)0xff924000,
1484 .mapbase = 0xff924000,
1485 .iotype = UPIO_MEM,
1486 .irq = 62,
1487 .ops = &sci_uart_ops,
1488 .flags = UPF_BOOT_AUTOCONF,
1489 .line = 1,
1490 },
1491 .type = PORT_SCIF,
1492 .irqs = SH7770_SCIF1_IRQS,
1493 .init_pins = sci_init_pins_scif,
1494 },
1495 {
1496 .port = {
1497 .membase = (void *)0xff925000,
1498 .mapbase = 0xff925000,
1499 .iotype = UPIO_MEM,
1500 .irq = 63,
1501 .ops = &sci_uart_ops,
1502 .flags = UPF_BOOT_AUTOCONF,
1503 .line = 2,
1504 },
1505 .type = PORT_SCIF,
1506 .irqs = SH7770_SCIF2_IRQS,
1507 .init_pins = sci_init_pins_scif,
1508 },
1509#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
1510 {
1511 .port = {
1512 .membase = (void *)0xffe00000,
1513 .mapbase = 0xffe00000,
1514 .iotype = UPIO_MEM,
1515 .irq = 43,
1516 .ops = &sci_uart_ops,
1517 .flags = UPF_BOOT_AUTOCONF,
1518 .line = 0,
1519 },
1520 .type = PORT_SCIF,
1521 .irqs = SH7780_SCIF0_IRQS,
1522 .init_pins = sci_init_pins_scif,
1523 },
1524 {
1525 .port = {
1526 .membase = (void *)0xffe10000,
1527 .mapbase = 0xffe10000,
1528 .iotype = UPIO_MEM,
1529 .irq = 79,
1530 .ops = &sci_uart_ops,
1531 .flags = UPF_BOOT_AUTOCONF,
1532 .line = 1,
1533 },
1534 .type = PORT_SCIF,
1535 .irqs = SH7780_SCIF1_IRQS,
1536 .init_pins = sci_init_pins_scif,
1537 },
1458#else 1538#else
1459#error "CPU subtype not defined" 1539#error "CPU subtype not defined"
1460#endif 1540#endif
@@ -1480,9 +1560,6 @@ static int __init serial_console_setup(struct console *co, char *options)
1480 int flow = 'n'; 1560 int flow = 'n';
1481 int ret; 1561 int ret;
1482 1562
1483 if (co->index >= SCI_NPORTS)
1484 co->index = 0;
1485
1486 serial_console_port = &sci_ports[co->index]; 1563 serial_console_port = &sci_ports[co->index];
1487 port = &serial_console_port->port; 1564 port = &serial_console_port->port;
1488 port->type = serial_console_port->type; 1565 port->type = serial_console_port->type;
@@ -1496,14 +1573,21 @@ static int __init serial_console_setup(struct console *co, char *options)
1496 * We need to set the initial uartclk here, since otherwise it will 1573 * We need to set the initial uartclk here, since otherwise it will
1497 * only ever be setup at sci_init() time. 1574 * only ever be setup at sci_init() time.
1498 */ 1575 */
1499#if !defined(__H8300H__) && !defined(__H8300S__) 1576#if defined(__H8300H__) || defined(__H8300S__)
1500 port->uartclk = current_cpu_data.module_clock * 16;
1501#else
1502 port->uartclk = CONFIG_CPU_CLOCK; 1577 port->uartclk = CONFIG_CPU_CLOCK;
1503#endif 1578
1504#if defined(__H8300S__) 1579#if defined(__H8300S__)
1505 h8300_sci_enable(port, sci_enable); 1580 h8300_sci_enable(port, sci_enable);
1506#endif 1581#endif
1582#elif defined(CONFIG_SUPERH64)
1583 port->uartclk = current_cpu_info.module_clock * 16;
1584#else
1585 {
1586 struct clk *clk = clk_get("module_clk");
1587 port->uartclk = clk_get_rate(clk) * 16;
1588 clk_put(clk);
1589 }
1590#endif
1507 if (options) 1591 if (options)
1508 uart_parse_options(options, &baud, &parity, &bits, &flow); 1592 uart_parse_options(options, &baud, &parity, &bits, &flow);
1509 1593
@@ -1566,7 +1650,7 @@ int __init kgdb_console_setup(struct console *co, char *options)
1566 int parity = 'n'; 1650 int parity = 'n';
1567 int flow = 'n'; 1651 int flow = 'n';
1568 1652
1569 if (co->index >= SCI_NPORTS || co->index != kgdb_portnum) 1653 if (co->index != kgdb_portnum)
1570 co->index = kgdb_portnum; 1654 co->index = kgdb_portnum;
1571 1655
1572 if (options) 1656 if (options)
@@ -1606,7 +1690,7 @@ console_initcall(kgdb_console_init);
1606#elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 1690#elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1607#define SCI_CONSOLE &serial_console 1691#define SCI_CONSOLE &serial_console
1608#else 1692#else
1609#define SCI_CONSOLE 0 1693#define SCI_CONSOLE 0
1610#endif 1694#endif
1611 1695
1612static char banner[] __initdata = 1696static char banner[] __initdata =
@@ -1621,7 +1705,6 @@ static struct uart_driver sci_uart_driver = {
1621 .dev_name = "ttySC", 1705 .dev_name = "ttySC",
1622 .major = SCI_MAJOR, 1706 .major = SCI_MAJOR,
1623 .minor = SCI_MINOR_START, 1707 .minor = SCI_MINOR_START,
1624 .nr = SCI_NPORTS,
1625 .cons = SCI_CONSOLE, 1708 .cons = SCI_CONSOLE,
1626}; 1709};
1627 1710
@@ -1631,15 +1714,21 @@ static int __init sci_init(void)
1631 1714
1632 printk("%s", banner); 1715 printk("%s", banner);
1633 1716
1717 sci_uart_driver.nr = ARRAY_SIZE(sci_ports);
1718
1634 ret = uart_register_driver(&sci_uart_driver); 1719 ret = uart_register_driver(&sci_uart_driver);
1635 if (ret == 0) { 1720 if (ret == 0) {
1636 for (chan = 0; chan < SCI_NPORTS; chan++) { 1721 for (chan = 0; chan < SCI_NPORTS; chan++) {
1637 struct sci_port *sciport = &sci_ports[chan]; 1722 struct sci_port *sciport = &sci_ports[chan];
1638 1723
1639#if !defined(__H8300H__) && !defined(__H8300S__) 1724#if defined(__H8300H__) || defined(__H8300S__)
1640 sciport->port.uartclk = (current_cpu_data.module_clock * 16);
1641#else
1642 sciport->port.uartclk = CONFIG_CPU_CLOCK; 1725 sciport->port.uartclk = CONFIG_CPU_CLOCK;
1726#elif defined(CONFIG_SUPERH64)
1727 sciport->port.uartclk = current_cpu_info.module_clock * 16;
1728#else
1729 struct clk *clk = clk_get("module_clk");
1730 sciport->port.uartclk = clk_get_rate(clk) * 16;
1731 clk_put(clk);
1643#endif 1732#endif
1644 uart_add_one_port(&sci_uart_driver, &sciport->port); 1733 uart_add_one_port(&sci_uart_driver, &sciport->port);
1645 sciport->break_timer.data = (unsigned long)sciport; 1734 sciport->break_timer.data = (unsigned long)sciport;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 13:34:11 -0500