diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/serial/sa1100.c |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'drivers/serial/sa1100.c')
-rw-r--r-- | drivers/serial/sa1100.c | 952 |
1 files changed, 952 insertions, 0 deletions
diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c new file mode 100644 index 000000000000..85f0af452f95 --- /dev/null +++ b/drivers/serial/sa1100.c | |||
@@ -0,0 +1,952 @@ | |||
1 | /* | ||
2 | * linux/drivers/char/sa1100.c | ||
3 | * | ||
4 | * Driver for SA11x0 serial ports | ||
5 | * | ||
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | ||
7 | * | ||
8 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $ | ||
25 | * | ||
26 | */ | ||
27 | #include <linux/config.h> | ||
28 | |||
29 | #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
30 | #define SUPPORT_SYSRQ | ||
31 | #endif | ||
32 | |||
33 | #include <linux/module.h> | ||
34 | #include <linux/ioport.h> | ||
35 | #include <linux/init.h> | ||
36 | #include <linux/console.h> | ||
37 | #include <linux/sysrq.h> | ||
38 | #include <linux/device.h> | ||
39 | #include <linux/tty.h> | ||
40 | #include <linux/tty_flip.h> | ||
41 | #include <linux/serial_core.h> | ||
42 | #include <linux/serial.h> | ||
43 | |||
44 | #include <asm/io.h> | ||
45 | #include <asm/irq.h> | ||
46 | #include <asm/hardware.h> | ||
47 | #include <asm/mach/serial_sa1100.h> | ||
48 | |||
49 | /* We've been assigned a range on the "Low-density serial ports" major */ | ||
50 | #define SERIAL_SA1100_MAJOR 204 | ||
51 | #define MINOR_START 5 | ||
52 | |||
53 | #define NR_PORTS 3 | ||
54 | |||
55 | #define SA1100_ISR_PASS_LIMIT 256 | ||
56 | |||
57 | /* | ||
58 | * Convert from ignore_status_mask or read_status_mask to UTSR[01] | ||
59 | */ | ||
60 | #define SM_TO_UTSR0(x) ((x) & 0xff) | ||
61 | #define SM_TO_UTSR1(x) ((x) >> 8) | ||
62 | #define UTSR0_TO_SM(x) ((x)) | ||
63 | #define UTSR1_TO_SM(x) ((x) << 8) | ||
64 | |||
65 | #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) | ||
66 | #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) | ||
67 | #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) | ||
68 | #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) | ||
69 | #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) | ||
70 | #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) | ||
71 | #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) | ||
72 | |||
73 | #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0) | ||
74 | #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1) | ||
75 | #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2) | ||
76 | #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3) | ||
77 | #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0) | ||
78 | #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1) | ||
79 | #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR) | ||
80 | |||
81 | /* | ||
82 | * This is the size of our serial port register set. | ||
83 | */ | ||
84 | #define UART_PORT_SIZE 0x24 | ||
85 | |||
86 | /* | ||
87 | * This determines how often we check the modem status signals | ||
88 | * for any change. They generally aren't connected to an IRQ | ||
89 | * so we have to poll them. We also check immediately before | ||
90 | * filling the TX fifo incase CTS has been dropped. | ||
91 | */ | ||
92 | #define MCTRL_TIMEOUT (250*HZ/1000) | ||
93 | |||
94 | struct sa1100_port { | ||
95 | struct uart_port port; | ||
96 | struct timer_list timer; | ||
97 | unsigned int old_status; | ||
98 | }; | ||
99 | |||
100 | /* | ||
101 | * Handle any change of modem status signal since we were last called. | ||
102 | */ | ||
103 | static void sa1100_mctrl_check(struct sa1100_port *sport) | ||
104 | { | ||
105 | unsigned int status, changed; | ||
106 | |||
107 | status = sport->port.ops->get_mctrl(&sport->port); | ||
108 | changed = status ^ sport->old_status; | ||
109 | |||
110 | if (changed == 0) | ||
111 | return; | ||
112 | |||
113 | sport->old_status = status; | ||
114 | |||
115 | if (changed & TIOCM_RI) | ||
116 | sport->port.icount.rng++; | ||
117 | if (changed & TIOCM_DSR) | ||
118 | sport->port.icount.dsr++; | ||
119 | if (changed & TIOCM_CAR) | ||
120 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | ||
121 | if (changed & TIOCM_CTS) | ||
122 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | ||
123 | |||
124 | wake_up_interruptible(&sport->port.info->delta_msr_wait); | ||
125 | } | ||
126 | |||
127 | /* | ||
128 | * This is our per-port timeout handler, for checking the | ||
129 | * modem status signals. | ||
130 | */ | ||
131 | static void sa1100_timeout(unsigned long data) | ||
132 | { | ||
133 | struct sa1100_port *sport = (struct sa1100_port *)data; | ||
134 | unsigned long flags; | ||
135 | |||
136 | if (sport->port.info) { | ||
137 | spin_lock_irqsave(&sport->port.lock, flags); | ||
138 | sa1100_mctrl_check(sport); | ||
139 | spin_unlock_irqrestore(&sport->port.lock, flags); | ||
140 | |||
141 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | ||
142 | } | ||
143 | } | ||
144 | |||
145 | /* | ||
146 | * interrupts disabled on entry | ||
147 | */ | ||
148 | static void sa1100_stop_tx(struct uart_port *port, unsigned int tty_stop) | ||
149 | { | ||
150 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
151 | u32 utcr3; | ||
152 | |||
153 | utcr3 = UART_GET_UTCR3(sport); | ||
154 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE); | ||
155 | sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS); | ||
156 | } | ||
157 | |||
158 | /* | ||
159 | * interrupts may not be disabled on entry | ||
160 | */ | ||
161 | static void sa1100_start_tx(struct uart_port *port, unsigned int tty_start) | ||
162 | { | ||
163 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
164 | unsigned long flags; | ||
165 | u32 utcr3; | ||
166 | |||
167 | spin_lock_irqsave(&sport->port.lock, flags); | ||
168 | utcr3 = UART_GET_UTCR3(sport); | ||
169 | sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS); | ||
170 | UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE); | ||
171 | spin_unlock_irqrestore(&sport->port.lock, flags); | ||
172 | } | ||
173 | |||
174 | /* | ||
175 | * Interrupts enabled | ||
176 | */ | ||
177 | static void sa1100_stop_rx(struct uart_port *port) | ||
178 | { | ||
179 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
180 | u32 utcr3; | ||
181 | |||
182 | utcr3 = UART_GET_UTCR3(sport); | ||
183 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE); | ||
184 | } | ||
185 | |||
186 | /* | ||
187 | * Set the modem control timer to fire immediately. | ||
188 | */ | ||
189 | static void sa1100_enable_ms(struct uart_port *port) | ||
190 | { | ||
191 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
192 | |||
193 | mod_timer(&sport->timer, jiffies); | ||
194 | } | ||
195 | |||
196 | static void | ||
197 | sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs) | ||
198 | { | ||
199 | struct tty_struct *tty = sport->port.info->tty; | ||
200 | unsigned int status, ch, flg, ignored = 0; | ||
201 | |||
202 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | ||
203 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | ||
204 | while (status & UTSR1_TO_SM(UTSR1_RNE)) { | ||
205 | ch = UART_GET_CHAR(sport); | ||
206 | |||
207 | if (tty->flip.count >= TTY_FLIPBUF_SIZE) | ||
208 | goto ignore_char; | ||
209 | sport->port.icount.rx++; | ||
210 | |||
211 | flg = TTY_NORMAL; | ||
212 | |||
213 | /* | ||
214 | * note that the error handling code is | ||
215 | * out of the main execution path | ||
216 | */ | ||
217 | if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) | ||
218 | goto handle_error; | ||
219 | |||
220 | if (uart_handle_sysrq_char(&sport->port, ch, regs)) | ||
221 | goto ignore_char; | ||
222 | |||
223 | error_return: | ||
224 | tty_insert_flip_char(tty, ch, flg); | ||
225 | ignore_char: | ||
226 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | ||
227 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | ||
228 | } | ||
229 | out: | ||
230 | tty_flip_buffer_push(tty); | ||
231 | return; | ||
232 | |||
233 | handle_error: | ||
234 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | ||
235 | sport->port.icount.parity++; | ||
236 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | ||
237 | sport->port.icount.frame++; | ||
238 | if (status & UTSR1_TO_SM(UTSR1_ROR)) | ||
239 | sport->port.icount.overrun++; | ||
240 | |||
241 | if (status & sport->port.ignore_status_mask) { | ||
242 | if (++ignored > 100) | ||
243 | goto out; | ||
244 | goto ignore_char; | ||
245 | } | ||
246 | |||
247 | status &= sport->port.read_status_mask; | ||
248 | |||
249 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | ||
250 | flg = TTY_PARITY; | ||
251 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | ||
252 | flg = TTY_FRAME; | ||
253 | |||
254 | if (status & UTSR1_TO_SM(UTSR1_ROR)) { | ||
255 | /* | ||
256 | * overrun does *not* affect the character | ||
257 | * we read from the FIFO | ||
258 | */ | ||
259 | tty_insert_flip_char(tty, ch, flg); | ||
260 | ch = 0; | ||
261 | flg = TTY_OVERRUN; | ||
262 | } | ||
263 | #ifdef SUPPORT_SYSRQ | ||
264 | sport->port.sysrq = 0; | ||
265 | #endif | ||
266 | goto error_return; | ||
267 | } | ||
268 | |||
269 | static void sa1100_tx_chars(struct sa1100_port *sport) | ||
270 | { | ||
271 | struct circ_buf *xmit = &sport->port.info->xmit; | ||
272 | |||
273 | if (sport->port.x_char) { | ||
274 | UART_PUT_CHAR(sport, sport->port.x_char); | ||
275 | sport->port.icount.tx++; | ||
276 | sport->port.x_char = 0; | ||
277 | return; | ||
278 | } | ||
279 | |||
280 | /* | ||
281 | * Check the modem control lines before | ||
282 | * transmitting anything. | ||
283 | */ | ||
284 | sa1100_mctrl_check(sport); | ||
285 | |||
286 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | ||
287 | sa1100_stop_tx(&sport->port, 0); | ||
288 | return; | ||
289 | } | ||
290 | |||
291 | /* | ||
292 | * Tried using FIFO (not checking TNF) for fifo fill: | ||
293 | * still had the '4 bytes repeated' problem. | ||
294 | */ | ||
295 | while (UART_GET_UTSR1(sport) & UTSR1_TNF) { | ||
296 | UART_PUT_CHAR(sport, xmit->buf[xmit->tail]); | ||
297 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | ||
298 | sport->port.icount.tx++; | ||
299 | if (uart_circ_empty(xmit)) | ||
300 | break; | ||
301 | } | ||
302 | |||
303 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
304 | uart_write_wakeup(&sport->port); | ||
305 | |||
306 | if (uart_circ_empty(xmit)) | ||
307 | sa1100_stop_tx(&sport->port, 0); | ||
308 | } | ||
309 | |||
310 | static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs) | ||
311 | { | ||
312 | struct sa1100_port *sport = dev_id; | ||
313 | unsigned int status, pass_counter = 0; | ||
314 | |||
315 | spin_lock(&sport->port.lock); | ||
316 | status = UART_GET_UTSR0(sport); | ||
317 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; | ||
318 | do { | ||
319 | if (status & (UTSR0_RFS | UTSR0_RID)) { | ||
320 | /* Clear the receiver idle bit, if set */ | ||
321 | if (status & UTSR0_RID) | ||
322 | UART_PUT_UTSR0(sport, UTSR0_RID); | ||
323 | sa1100_rx_chars(sport, regs); | ||
324 | } | ||
325 | |||
326 | /* Clear the relevant break bits */ | ||
327 | if (status & (UTSR0_RBB | UTSR0_REB)) | ||
328 | UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB)); | ||
329 | |||
330 | if (status & UTSR0_RBB) | ||
331 | sport->port.icount.brk++; | ||
332 | |||
333 | if (status & UTSR0_REB) | ||
334 | uart_handle_break(&sport->port); | ||
335 | |||
336 | if (status & UTSR0_TFS) | ||
337 | sa1100_tx_chars(sport); | ||
338 | if (pass_counter++ > SA1100_ISR_PASS_LIMIT) | ||
339 | break; | ||
340 | status = UART_GET_UTSR0(sport); | ||
341 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | | ||
342 | ~UTSR0_TFS; | ||
343 | } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); | ||
344 | spin_unlock(&sport->port.lock); | ||
345 | |||
346 | return IRQ_HANDLED; | ||
347 | } | ||
348 | |||
349 | /* | ||
350 | * Return TIOCSER_TEMT when transmitter is not busy. | ||
351 | */ | ||
352 | static unsigned int sa1100_tx_empty(struct uart_port *port) | ||
353 | { | ||
354 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
355 | |||
356 | return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT; | ||
357 | } | ||
358 | |||
359 | static unsigned int sa1100_get_mctrl(struct uart_port *port) | ||
360 | { | ||
361 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | ||
362 | } | ||
363 | |||
364 | static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl) | ||
365 | { | ||
366 | } | ||
367 | |||
368 | /* | ||
369 | * Interrupts always disabled. | ||
370 | */ | ||
371 | static void sa1100_break_ctl(struct uart_port *port, int break_state) | ||
372 | { | ||
373 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
374 | unsigned long flags; | ||
375 | unsigned int utcr3; | ||
376 | |||
377 | spin_lock_irqsave(&sport->port.lock, flags); | ||
378 | utcr3 = UART_GET_UTCR3(sport); | ||
379 | if (break_state == -1) | ||
380 | utcr3 |= UTCR3_BRK; | ||
381 | else | ||
382 | utcr3 &= ~UTCR3_BRK; | ||
383 | UART_PUT_UTCR3(sport, utcr3); | ||
384 | spin_unlock_irqrestore(&sport->port.lock, flags); | ||
385 | } | ||
386 | |||
387 | static int sa1100_startup(struct uart_port *port) | ||
388 | { | ||
389 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
390 | int retval; | ||
391 | |||
392 | /* | ||
393 | * Allocate the IRQ | ||
394 | */ | ||
395 | retval = request_irq(sport->port.irq, sa1100_int, 0, | ||
396 | "sa11x0-uart", sport); | ||
397 | if (retval) | ||
398 | return retval; | ||
399 | |||
400 | /* | ||
401 | * Finally, clear and enable interrupts | ||
402 | */ | ||
403 | UART_PUT_UTSR0(sport, -1); | ||
404 | UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE); | ||
405 | |||
406 | /* | ||
407 | * Enable modem status interrupts | ||
408 | */ | ||
409 | spin_lock_irq(&sport->port.lock); | ||
410 | sa1100_enable_ms(&sport->port); | ||
411 | spin_unlock_irq(&sport->port.lock); | ||
412 | |||
413 | return 0; | ||
414 | } | ||
415 | |||
416 | static void sa1100_shutdown(struct uart_port *port) | ||
417 | { | ||
418 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
419 | |||
420 | /* | ||
421 | * Stop our timer. | ||
422 | */ | ||
423 | del_timer_sync(&sport->timer); | ||
424 | |||
425 | /* | ||
426 | * Free the interrupt | ||
427 | */ | ||
428 | free_irq(sport->port.irq, sport); | ||
429 | |||
430 | /* | ||
431 | * Disable all interrupts, port and break condition. | ||
432 | */ | ||
433 | UART_PUT_UTCR3(sport, 0); | ||
434 | } | ||
435 | |||
436 | static void | ||
437 | sa1100_set_termios(struct uart_port *port, struct termios *termios, | ||
438 | struct termios *old) | ||
439 | { | ||
440 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
441 | unsigned long flags; | ||
442 | unsigned int utcr0, old_utcr3, baud, quot; | ||
443 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | ||
444 | |||
445 | /* | ||
446 | * We only support CS7 and CS8. | ||
447 | */ | ||
448 | while ((termios->c_cflag & CSIZE) != CS7 && | ||
449 | (termios->c_cflag & CSIZE) != CS8) { | ||
450 | termios->c_cflag &= ~CSIZE; | ||
451 | termios->c_cflag |= old_csize; | ||
452 | old_csize = CS8; | ||
453 | } | ||
454 | |||
455 | if ((termios->c_cflag & CSIZE) == CS8) | ||
456 | utcr0 = UTCR0_DSS; | ||
457 | else | ||
458 | utcr0 = 0; | ||
459 | |||
460 | if (termios->c_cflag & CSTOPB) | ||
461 | utcr0 |= UTCR0_SBS; | ||
462 | if (termios->c_cflag & PARENB) { | ||
463 | utcr0 |= UTCR0_PE; | ||
464 | if (!(termios->c_cflag & PARODD)) | ||
465 | utcr0 |= UTCR0_OES; | ||
466 | } | ||
467 | |||
468 | /* | ||
469 | * Ask the core to calculate the divisor for us. | ||
470 | */ | ||
471 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | ||
472 | quot = uart_get_divisor(port, baud); | ||
473 | |||
474 | spin_lock_irqsave(&sport->port.lock, flags); | ||
475 | |||
476 | sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); | ||
477 | sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); | ||
478 | if (termios->c_iflag & INPCK) | ||
479 | sport->port.read_status_mask |= | ||
480 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | ||
481 | if (termios->c_iflag & (BRKINT | PARMRK)) | ||
482 | sport->port.read_status_mask |= | ||
483 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | ||
484 | |||
485 | /* | ||
486 | * Characters to ignore | ||
487 | */ | ||
488 | sport->port.ignore_status_mask = 0; | ||
489 | if (termios->c_iflag & IGNPAR) | ||
490 | sport->port.ignore_status_mask |= | ||
491 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | ||
492 | if (termios->c_iflag & IGNBRK) { | ||
493 | sport->port.ignore_status_mask |= | ||
494 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | ||
495 | /* | ||
496 | * If we're ignoring parity and break indicators, | ||
497 | * ignore overruns too (for real raw support). | ||
498 | */ | ||
499 | if (termios->c_iflag & IGNPAR) | ||
500 | sport->port.ignore_status_mask |= | ||
501 | UTSR1_TO_SM(UTSR1_ROR); | ||
502 | } | ||
503 | |||
504 | del_timer_sync(&sport->timer); | ||
505 | |||
506 | /* | ||
507 | * Update the per-port timeout. | ||
508 | */ | ||
509 | uart_update_timeout(port, termios->c_cflag, baud); | ||
510 | |||
511 | /* | ||
512 | * disable interrupts and drain transmitter | ||
513 | */ | ||
514 | old_utcr3 = UART_GET_UTCR3(sport); | ||
515 | UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)); | ||
516 | |||
517 | while (UART_GET_UTSR1(sport) & UTSR1_TBY) | ||
518 | barrier(); | ||
519 | |||
520 | /* then, disable everything */ | ||
521 | UART_PUT_UTCR3(sport, 0); | ||
522 | |||
523 | /* set the parity, stop bits and data size */ | ||
524 | UART_PUT_UTCR0(sport, utcr0); | ||
525 | |||
526 | /* set the baud rate */ | ||
527 | quot -= 1; | ||
528 | UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8)); | ||
529 | UART_PUT_UTCR2(sport, (quot & 0xff)); | ||
530 | |||
531 | UART_PUT_UTSR0(sport, -1); | ||
532 | |||
533 | UART_PUT_UTCR3(sport, old_utcr3); | ||
534 | |||
535 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | ||
536 | sa1100_enable_ms(&sport->port); | ||
537 | |||
538 | spin_unlock_irqrestore(&sport->port.lock, flags); | ||
539 | } | ||
540 | |||
541 | static const char *sa1100_type(struct uart_port *port) | ||
542 | { | ||
543 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
544 | |||
545 | return sport->port.type == PORT_SA1100 ? "SA1100" : NULL; | ||
546 | } | ||
547 | |||
548 | /* | ||
549 | * Release the memory region(s) being used by 'port'. | ||
550 | */ | ||
551 | static void sa1100_release_port(struct uart_port *port) | ||
552 | { | ||
553 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
554 | |||
555 | release_mem_region(sport->port.mapbase, UART_PORT_SIZE); | ||
556 | } | ||
557 | |||
558 | /* | ||
559 | * Request the memory region(s) being used by 'port'. | ||
560 | */ | ||
561 | static int sa1100_request_port(struct uart_port *port) | ||
562 | { | ||
563 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
564 | |||
565 | return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, | ||
566 | "sa11x0-uart") != NULL ? 0 : -EBUSY; | ||
567 | } | ||
568 | |||
569 | /* | ||
570 | * Configure/autoconfigure the port. | ||
571 | */ | ||
572 | static void sa1100_config_port(struct uart_port *port, int flags) | ||
573 | { | ||
574 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
575 | |||
576 | if (flags & UART_CONFIG_TYPE && | ||
577 | sa1100_request_port(&sport->port) == 0) | ||
578 | sport->port.type = PORT_SA1100; | ||
579 | } | ||
580 | |||
581 | /* | ||
582 | * Verify the new serial_struct (for TIOCSSERIAL). | ||
583 | * The only change we allow are to the flags and type, and | ||
584 | * even then only between PORT_SA1100 and PORT_UNKNOWN | ||
585 | */ | ||
586 | static int | ||
587 | sa1100_verify_port(struct uart_port *port, struct serial_struct *ser) | ||
588 | { | ||
589 | struct sa1100_port *sport = (struct sa1100_port *)port; | ||
590 | int ret = 0; | ||
591 | |||
592 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100) | ||
593 | ret = -EINVAL; | ||
594 | if (sport->port.irq != ser->irq) | ||
595 | ret = -EINVAL; | ||
596 | if (ser->io_type != SERIAL_IO_MEM) | ||
597 | ret = -EINVAL; | ||
598 | if (sport->port.uartclk / 16 != ser->baud_base) | ||
599 | ret = -EINVAL; | ||
600 | if ((void *)sport->port.mapbase != ser->iomem_base) | ||
601 | ret = -EINVAL; | ||
602 | if (sport->port.iobase != ser->port) | ||
603 | ret = -EINVAL; | ||
604 | if (ser->hub6 != 0) | ||
605 | ret = -EINVAL; | ||
606 | return ret; | ||
607 | } | ||
608 | |||
609 | static struct uart_ops sa1100_pops = { | ||
610 | .tx_empty = sa1100_tx_empty, | ||
611 | .set_mctrl = sa1100_set_mctrl, | ||
612 | .get_mctrl = sa1100_get_mctrl, | ||
613 | .stop_tx = sa1100_stop_tx, | ||
614 | .start_tx = sa1100_start_tx, | ||
615 | .stop_rx = sa1100_stop_rx, | ||
616 | .enable_ms = sa1100_enable_ms, | ||
617 | .break_ctl = sa1100_break_ctl, | ||
618 | .startup = sa1100_startup, | ||
619 | .shutdown = sa1100_shutdown, | ||
620 | .set_termios = sa1100_set_termios, | ||
621 | .type = sa1100_type, | ||
622 | .release_port = sa1100_release_port, | ||
623 | .request_port = sa1100_request_port, | ||
624 | .config_port = sa1100_config_port, | ||
625 | .verify_port = sa1100_verify_port, | ||
626 | }; | ||
627 | |||
628 | static struct sa1100_port sa1100_ports[NR_PORTS]; | ||
629 | |||
630 | /* | ||
631 | * Setup the SA1100 serial ports. Note that we don't include the IrDA | ||
632 | * port here since we have our own SIR/FIR driver (see drivers/net/irda) | ||
633 | * | ||
634 | * Note also that we support "console=ttySAx" where "x" is either 0 or 1. | ||
635 | * Which serial port this ends up being depends on the machine you're | ||
636 | * running this kernel on. I'm not convinced that this is a good idea, | ||
637 | * but that's the way it traditionally works. | ||
638 | * | ||
639 | * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer | ||
640 | * used here. | ||
641 | */ | ||
642 | static void __init sa1100_init_ports(void) | ||
643 | { | ||
644 | static int first = 1; | ||
645 | int i; | ||
646 | |||
647 | if (!first) | ||
648 | return; | ||
649 | first = 0; | ||
650 | |||
651 | for (i = 0; i < NR_PORTS; i++) { | ||
652 | sa1100_ports[i].port.uartclk = 3686400; | ||
653 | sa1100_ports[i].port.ops = &sa1100_pops; | ||
654 | sa1100_ports[i].port.fifosize = 8; | ||
655 | sa1100_ports[i].port.line = i; | ||
656 | sa1100_ports[i].port.iotype = SERIAL_IO_MEM; | ||
657 | init_timer(&sa1100_ports[i].timer); | ||
658 | sa1100_ports[i].timer.function = sa1100_timeout; | ||
659 | sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i]; | ||
660 | } | ||
661 | |||
662 | /* | ||
663 | * make transmit lines outputs, so that when the port | ||
664 | * is closed, the output is in the MARK state. | ||
665 | */ | ||
666 | PPDR |= PPC_TXD1 | PPC_TXD3; | ||
667 | PPSR |= PPC_TXD1 | PPC_TXD3; | ||
668 | } | ||
669 | |||
670 | void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns) | ||
671 | { | ||
672 | if (fns->get_mctrl) | ||
673 | sa1100_pops.get_mctrl = fns->get_mctrl; | ||
674 | if (fns->set_mctrl) | ||
675 | sa1100_pops.set_mctrl = fns->set_mctrl; | ||
676 | |||
677 | sa1100_pops.pm = fns->pm; | ||
678 | sa1100_pops.set_wake = fns->set_wake; | ||
679 | } | ||
680 | |||
681 | void __init sa1100_register_uart(int idx, int port) | ||
682 | { | ||
683 | if (idx >= NR_PORTS) { | ||
684 | printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx); | ||
685 | return; | ||
686 | } | ||
687 | |||
688 | switch (port) { | ||
689 | case 1: | ||
690 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; | ||
691 | sa1100_ports[idx].port.mapbase = _Ser1UTCR0; | ||
692 | sa1100_ports[idx].port.irq = IRQ_Ser1UART; | ||
693 | sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF; | ||
694 | break; | ||
695 | |||
696 | case 2: | ||
697 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; | ||
698 | sa1100_ports[idx].port.mapbase = _Ser2UTCR0; | ||
699 | sa1100_ports[idx].port.irq = IRQ_Ser2ICP; | ||
700 | sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF; | ||
701 | break; | ||
702 | |||
703 | case 3: | ||
704 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; | ||
705 | sa1100_ports[idx].port.mapbase = _Ser3UTCR0; | ||
706 | sa1100_ports[idx].port.irq = IRQ_Ser3UART; | ||
707 | sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF; | ||
708 | break; | ||
709 | |||
710 | default: | ||
711 | printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port); | ||
712 | } | ||
713 | } | ||
714 | |||
715 | |||
716 | #ifdef CONFIG_SERIAL_SA1100_CONSOLE | ||
717 | |||
718 | /* | ||
719 | * Interrupts are disabled on entering | ||
720 | */ | ||
721 | static void | ||
722 | sa1100_console_write(struct console *co, const char *s, unsigned int count) | ||
723 | { | ||
724 | struct sa1100_port *sport = &sa1100_ports[co->index]; | ||
725 | unsigned int old_utcr3, status, i; | ||
726 | |||
727 | /* | ||
728 | * First, save UTCR3 and then disable interrupts | ||
729 | */ | ||
730 | old_utcr3 = UART_GET_UTCR3(sport); | ||
731 | UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) | | ||
732 | UTCR3_TXE); | ||
733 | |||
734 | /* | ||
735 | * Now, do each character | ||
736 | */ | ||
737 | for (i = 0; i < count; i++) { | ||
738 | do { | ||
739 | status = UART_GET_UTSR1(sport); | ||
740 | } while (!(status & UTSR1_TNF)); | ||
741 | UART_PUT_CHAR(sport, s[i]); | ||
742 | if (s[i] == '\n') { | ||
743 | do { | ||
744 | status = UART_GET_UTSR1(sport); | ||
745 | } while (!(status & UTSR1_TNF)); | ||
746 | UART_PUT_CHAR(sport, '\r'); | ||
747 | } | ||
748 | } | ||
749 | |||
750 | /* | ||
751 | * Finally, wait for transmitter to become empty | ||
752 | * and restore UTCR3 | ||
753 | */ | ||
754 | do { | ||
755 | status = UART_GET_UTSR1(sport); | ||
756 | } while (status & UTSR1_TBY); | ||
757 | UART_PUT_UTCR3(sport, old_utcr3); | ||
758 | } | ||
759 | |||
760 | /* | ||
761 | * If the port was already initialised (eg, by a boot loader), | ||
762 | * try to determine the current setup. | ||
763 | */ | ||
764 | static void __init | ||
765 | sa1100_console_get_options(struct sa1100_port *sport, int *baud, | ||
766 | int *parity, int *bits) | ||
767 | { | ||
768 | unsigned int utcr3; | ||
769 | |||
770 | utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE); | ||
771 | if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) { | ||
772 | /* ok, the port was enabled */ | ||
773 | unsigned int utcr0, quot; | ||
774 | |||
775 | utcr0 = UART_GET_UTCR0(sport); | ||
776 | |||
777 | *parity = 'n'; | ||
778 | if (utcr0 & UTCR0_PE) { | ||
779 | if (utcr0 & UTCR0_OES) | ||
780 | *parity = 'e'; | ||
781 | else | ||
782 | *parity = 'o'; | ||
783 | } | ||
784 | |||
785 | if (utcr0 & UTCR0_DSS) | ||
786 | *bits = 8; | ||
787 | else | ||
788 | *bits = 7; | ||
789 | |||
790 | quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8; | ||
791 | quot &= 0xfff; | ||
792 | *baud = sport->port.uartclk / (16 * (quot + 1)); | ||
793 | } | ||
794 | } | ||
795 | |||
796 | static int __init | ||
797 | sa1100_console_setup(struct console *co, char *options) | ||
798 | { | ||
799 | struct sa1100_port *sport; | ||
800 | int baud = 9600; | ||
801 | int bits = 8; | ||
802 | int parity = 'n'; | ||
803 | int flow = 'n'; | ||
804 | |||
805 | /* | ||
806 | * Check whether an invalid uart number has been specified, and | ||
807 | * if so, search for the first available port that does have | ||
808 | * console support. | ||
809 | */ | ||
810 | if (co->index == -1 || co->index >= NR_PORTS) | ||
811 | co->index = 0; | ||
812 | sport = &sa1100_ports[co->index]; | ||
813 | |||
814 | if (options) | ||
815 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
816 | else | ||
817 | sa1100_console_get_options(sport, &baud, &parity, &bits); | ||
818 | |||
819 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | ||
820 | } | ||
821 | |||
822 | extern struct uart_driver sa1100_reg; | ||
823 | static struct console sa1100_console = { | ||
824 | .name = "ttySA", | ||
825 | .write = sa1100_console_write, | ||
826 | .device = uart_console_device, | ||
827 | .setup = sa1100_console_setup, | ||
828 | .flags = CON_PRINTBUFFER, | ||
829 | .index = -1, | ||
830 | .data = &sa1100_reg, | ||
831 | }; | ||
832 | |||
833 | static int __init sa1100_rs_console_init(void) | ||
834 | { | ||
835 | sa1100_init_ports(); | ||
836 | register_console(&sa1100_console); | ||
837 | return 0; | ||
838 | } | ||
839 | console_initcall(sa1100_rs_console_init); | ||
840 | |||
841 | #define SA1100_CONSOLE &sa1100_console | ||
842 | #else | ||
843 | #define SA1100_CONSOLE NULL | ||
844 | #endif | ||
845 | |||
846 | static struct uart_driver sa1100_reg = { | ||
847 | .owner = THIS_MODULE, | ||
848 | .driver_name = "ttySA", | ||
849 | .dev_name = "ttySA", | ||
850 | .devfs_name = "ttySA", | ||
851 | .major = SERIAL_SA1100_MAJOR, | ||
852 | .minor = MINOR_START, | ||
853 | .nr = NR_PORTS, | ||
854 | .cons = SA1100_CONSOLE, | ||
855 | }; | ||
856 | |||
857 | static int sa1100_serial_suspend(struct device *_dev, u32 state, u32 level) | ||
858 | { | ||
859 | struct sa1100_port *sport = dev_get_drvdata(_dev); | ||
860 | |||
861 | if (sport && level == SUSPEND_DISABLE) | ||
862 | uart_suspend_port(&sa1100_reg, &sport->port); | ||
863 | |||
864 | return 0; | ||
865 | } | ||
866 | |||
867 | static int sa1100_serial_resume(struct device *_dev, u32 level) | ||
868 | { | ||
869 | struct sa1100_port *sport = dev_get_drvdata(_dev); | ||
870 | |||
871 | if (sport && level == RESUME_ENABLE) | ||
872 | uart_resume_port(&sa1100_reg, &sport->port); | ||
873 | |||
874 | return 0; | ||
875 | } | ||
876 | |||
877 | static int sa1100_serial_probe(struct device *_dev) | ||
878 | { | ||
879 | struct platform_device *dev = to_platform_device(_dev); | ||
880 | struct resource *res = dev->resource; | ||
881 | int i; | ||
882 | |||
883 | for (i = 0; i < dev->num_resources; i++, res++) | ||
884 | if (res->flags & IORESOURCE_MEM) | ||
885 | break; | ||
886 | |||
887 | if (i < dev->num_resources) { | ||
888 | for (i = 0; i < NR_PORTS; i++) { | ||
889 | if (sa1100_ports[i].port.mapbase != res->start) | ||
890 | continue; | ||
891 | |||
892 | sa1100_ports[i].port.dev = _dev; | ||
893 | uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port); | ||
894 | dev_set_drvdata(_dev, &sa1100_ports[i]); | ||
895 | break; | ||
896 | } | ||
897 | } | ||
898 | |||
899 | return 0; | ||
900 | } | ||
901 | |||
902 | static int sa1100_serial_remove(struct device *_dev) | ||
903 | { | ||
904 | struct sa1100_port *sport = dev_get_drvdata(_dev); | ||
905 | |||
906 | dev_set_drvdata(_dev, NULL); | ||
907 | |||
908 | if (sport) | ||
909 | uart_remove_one_port(&sa1100_reg, &sport->port); | ||
910 | |||
911 | return 0; | ||
912 | } | ||
913 | |||
914 | static struct device_driver sa11x0_serial_driver = { | ||
915 | .name = "sa11x0-uart", | ||
916 | .bus = &platform_bus_type, | ||
917 | .probe = sa1100_serial_probe, | ||
918 | .remove = sa1100_serial_remove, | ||
919 | .suspend = sa1100_serial_suspend, | ||
920 | .resume = sa1100_serial_resume, | ||
921 | }; | ||
922 | |||
923 | static int __init sa1100_serial_init(void) | ||
924 | { | ||
925 | int ret; | ||
926 | |||
927 | printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n"); | ||
928 | |||
929 | sa1100_init_ports(); | ||
930 | |||
931 | ret = uart_register_driver(&sa1100_reg); | ||
932 | if (ret == 0) { | ||
933 | ret = driver_register(&sa11x0_serial_driver); | ||
934 | if (ret) | ||
935 | uart_unregister_driver(&sa1100_reg); | ||
936 | } | ||
937 | return ret; | ||
938 | } | ||
939 | |||
940 | static void __exit sa1100_serial_exit(void) | ||
941 | { | ||
942 | driver_unregister(&sa11x0_serial_driver); | ||
943 | uart_unregister_driver(&sa1100_reg); | ||
944 | } | ||
945 | |||
946 | module_init(sa1100_serial_init); | ||
947 | module_exit(sa1100_serial_exit); | ||
948 | |||
949 | MODULE_AUTHOR("Deep Blue Solutions Ltd"); | ||
950 | MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $"); | ||
951 | MODULE_LICENSE("GPL"); | ||
952 | MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR); | ||