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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/serial/s3c2410.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/serial/s3c2410.c')
-rw-r--r--drivers/serial/s3c2410.c1831
1 files changed, 1831 insertions, 0 deletions
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
new file mode 100644
index 000000000000..ffc61389614b
--- /dev/null
+++ b/drivers/serial/s3c2410.c
@@ -0,0 +1,1831 @@
1/*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34*/
35
36/* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41*/
42
43/* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56*/
57
58#include <linux/config.h>
59
60#if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61#define SUPPORT_SYSRQ
62#endif
63
64#include <linux/module.h>
65#include <linux/ioport.h>
66#include <linux/device.h>
67#include <linux/init.h>
68#include <linux/sysrq.h>
69#include <linux/console.h>
70#include <linux/tty.h>
71#include <linux/tty_flip.h>
72#include <linux/serial_core.h>
73#include <linux/serial.h>
74#include <linux/delay.h>
75
76#include <asm/io.h>
77#include <asm/irq.h>
78
79#include <asm/hardware.h>
80#include <asm/hardware/clock.h>
81
82#include <asm/arch/regs-serial.h>
83#include <asm/arch/regs-gpio.h>
84
85#include <asm/mach-types.h>
86
87/* structures */
88
89struct s3c24xx_uart_info {
90 char *name;
91 unsigned int type;
92 unsigned int fifosize;
93 unsigned long rx_fifomask;
94 unsigned long rx_fifoshift;
95 unsigned long rx_fifofull;
96 unsigned long tx_fifomask;
97 unsigned long tx_fifoshift;
98 unsigned long tx_fifofull;
99
100 /* clock source control */
101
102 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
103 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
104
105 /* uart controls */
106 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
107};
108
109struct s3c24xx_uart_port {
110 unsigned char rx_claimed;
111 unsigned char tx_claimed;
112
113 struct s3c24xx_uart_info *info;
114 struct s3c24xx_uart_clksrc *clksrc;
115 struct clk *clk;
116 struct clk *baudclk;
117 struct uart_port port;
118};
119
120
121/* configuration defines */
122
123#if 0
124#if 1
125/* send debug to the low-level output routines */
126
127extern void printascii(const char *);
128
129static void
130s3c24xx_serial_dbg(const char *fmt, ...)
131{
132 va_list va;
133 char buff[256];
134
135 va_start(va, fmt);
136 vsprintf(buff, fmt, va);
137 va_end(va);
138
139 printascii(buff);
140}
141
142#define dbg(x...) s3c24xx_serial_dbg(x)
143
144#else
145#define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
146#endif
147#else /* no debug */
148#define dbg(x...) do {} while(0)
149#endif
150
151/* UART name and device definitions */
152
153#define S3C24XX_SERIAL_NAME "ttySAC"
154#define S3C24XX_SERIAL_DEVFS "tts/"
155#define S3C24XX_SERIAL_MAJOR 204
156#define S3C24XX_SERIAL_MINOR 64
157
158
159/* conversion functions */
160
161#define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
162#define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
163
164/* we can support 3 uarts, but not always use them */
165
166#define NR_PORTS (3)
167
168/* port irq numbers */
169
170#define TX_IRQ(port) ((port)->irq + 1)
171#define RX_IRQ(port) ((port)->irq)
172
173/* register access controls */
174
175#define portaddr(port, reg) ((port)->membase + (reg))
176
177#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
178#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
179
180#define wr_regb(port, reg, val) \
181 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
182
183#define wr_regl(port, reg, val) \
184 do { __raw_writel(val, portaddr(port, reg)); } while(0)
185
186/* macros to change one thing to another */
187
188#define tx_enabled(port) ((port)->unused[0])
189#define rx_enabled(port) ((port)->unused[1])
190
191/* flag to ignore all characters comming in */
192#define RXSTAT_DUMMY_READ (0x10000000)
193
194static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
195{
196 return container_of(port, struct s3c24xx_uart_port, port);
197}
198
199/* translate a port to the device name */
200
201static inline char *s3c24xx_serial_portname(struct uart_port *port)
202{
203 return to_platform_device(port->dev)->name;
204}
205
206static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
207{
208 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
209}
210
211static void s3c24xx_serial_rx_enable(struct uart_port *port)
212{
213 unsigned long flags;
214 unsigned int ucon, ufcon;
215 int count = 10000;
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 while (--count && !s3c24xx_serial_txempty_nofifo(port))
220 udelay(100);
221
222 ufcon = rd_regl(port, S3C2410_UFCON);
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
225
226 ucon = rd_regl(port, S3C2410_UCON);
227 ucon |= S3C2410_UCON_RXIRQMODE;
228 wr_regl(port, S3C2410_UCON, ucon);
229
230 rx_enabled(port) = 1;
231 spin_unlock_irqrestore(&port->lock, flags);
232}
233
234static void s3c24xx_serial_rx_disable(struct uart_port *port)
235{
236 unsigned long flags;
237 unsigned int ucon;
238
239 spin_lock_irqsave(&port->lock, flags);
240
241 ucon = rd_regl(port, S3C2410_UCON);
242 ucon &= ~S3C2410_UCON_RXIRQMODE;
243 wr_regl(port, S3C2410_UCON, ucon);
244
245 rx_enabled(port) = 0;
246 spin_unlock_irqrestore(&port->lock, flags);
247}
248
249static void
250s3c24xx_serial_stop_tx(struct uart_port *port, unsigned int tty_stop)
251{
252 if (tx_enabled(port)) {
253 disable_irq(TX_IRQ(port));
254 tx_enabled(port) = 0;
255 if (port->flags & UPF_CONS_FLOW)
256 s3c24xx_serial_rx_enable(port);
257 }
258}
259
260static void
261s3c24xx_serial_start_tx(struct uart_port *port, unsigned int tty_start)
262{
263 if (!tx_enabled(port)) {
264 if (port->flags & UPF_CONS_FLOW)
265 s3c24xx_serial_rx_disable(port);
266
267 enable_irq(TX_IRQ(port));
268 tx_enabled(port) = 1;
269 }
270}
271
272
273static void s3c24xx_serial_stop_rx(struct uart_port *port)
274{
275 if (rx_enabled(port)) {
276 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
277 disable_irq(RX_IRQ(port));
278 rx_enabled(port) = 0;
279 }
280}
281
282static void s3c24xx_serial_enable_ms(struct uart_port *port)
283{
284}
285
286static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
287{
288 return to_ourport(port)->info;
289}
290
291static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
292{
293 if (port->dev == NULL)
294 return NULL;
295
296 return (struct s3c2410_uartcfg *)port->dev->platform_data;
297}
298
299static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
300 unsigned long ufstat)
301{
302 struct s3c24xx_uart_info *info = ourport->info;
303
304 if (ufstat & info->rx_fifofull)
305 return info->fifosize;
306
307 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
308}
309
310
311/* ? - where has parity gone?? */
312#define S3C2410_UERSTAT_PARITY (0x1000)
313
314static irqreturn_t
315s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
316{
317 struct s3c24xx_uart_port *ourport = dev_id;
318 struct uart_port *port = &ourport->port;
319 struct tty_struct *tty = port->info->tty;
320 unsigned int ufcon, ch, flag, ufstat, uerstat;
321 int max_count = 64;
322
323 while (max_count-- > 0) {
324 ufcon = rd_regl(port, S3C2410_UFCON);
325 ufstat = rd_regl(port, S3C2410_UFSTAT);
326
327 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
328 break;
329
330 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
331 if (tty->low_latency)
332 tty_flip_buffer_push(tty);
333
334 /*
335 * If this failed then we will throw away the
336 * bytes but must do so to clear interrupts
337 */
338 }
339
340 uerstat = rd_regl(port, S3C2410_UERSTAT);
341 ch = rd_regb(port, S3C2410_URXH);
342
343 if (port->flags & UPF_CONS_FLOW) {
344 int txe = s3c24xx_serial_txempty_nofifo(port);
345
346 if (rx_enabled(port)) {
347 if (!txe) {
348 rx_enabled(port) = 0;
349 continue;
350 }
351 } else {
352 if (txe) {
353 ufcon |= S3C2410_UFCON_RESETRX;
354 wr_regl(port, S3C2410_UFCON, ufcon);
355 rx_enabled(port) = 1;
356 goto out;
357 }
358 continue;
359 }
360 }
361
362 /* insert the character into the buffer */
363
364 flag = TTY_NORMAL;
365 port->icount.rx++;
366
367 if (uerstat & S3C2410_UERSTAT_ANY) {
368 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
369 ch, uerstat);
370
371 /* check for break */
372 if (uerstat & S3C2410_UERSTAT_BREAK) {
373 dbg("break!\n");
374 port->icount.brk++;
375 if (uart_handle_break(port))
376 goto ignore_char;
377 }
378
379 if (uerstat & S3C2410_UERSTAT_FRAME)
380 port->icount.frame++;
381 if (uerstat & S3C2410_UERSTAT_OVERRUN)
382 port->icount.overrun++;
383
384 uerstat &= port->read_status_mask;
385
386 if (uerstat & S3C2410_UERSTAT_BREAK)
387 flag = TTY_BREAK;
388 else if (uerstat & S3C2410_UERSTAT_PARITY)
389 flag = TTY_PARITY;
390 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
391 flag = TTY_FRAME;
392 }
393
394 if (uart_handle_sysrq_char(port, ch, regs))
395 goto ignore_char;
396
397 if ((uerstat & port->ignore_status_mask) == 0) {
398 tty_insert_flip_char(tty, ch, flag);
399 }
400
401 if ((uerstat & S3C2410_UERSTAT_OVERRUN) &&
402 tty->flip.count < TTY_FLIPBUF_SIZE) {
403 /*
404 * Overrun is special, since it's reported
405 * immediately, and doesn't affect the current
406 * character.
407 */
408
409 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
410 }
411
412 ignore_char:
413 continue;
414 }
415 tty_flip_buffer_push(tty);
416
417 out:
418 return IRQ_HANDLED;
419}
420
421static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
422{
423 struct s3c24xx_uart_port *ourport = id;
424 struct uart_port *port = &ourport->port;
425 struct circ_buf *xmit = &port->info->xmit;
426 int count = 256;
427
428 if (port->x_char) {
429 wr_regb(port, S3C2410_UTXH, port->x_char);
430 port->icount.tx++;
431 port->x_char = 0;
432 goto out;
433 }
434
435 /* if there isnt anything more to transmit, or the uart is now
436 * stopped, disable the uart and exit
437 */
438
439 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
440 s3c24xx_serial_stop_tx(port, 0);
441 goto out;
442 }
443
444 /* try and drain the buffer... */
445
446 while (!uart_circ_empty(xmit) && count-- > 0) {
447 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
448 break;
449
450 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
452 port->icount.tx++;
453 }
454
455 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456 uart_write_wakeup(port);
457
458 if (uart_circ_empty(xmit))
459 s3c24xx_serial_stop_tx(port, 0);
460
461 out:
462 return IRQ_HANDLED;
463}
464
465static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
466{
467 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
468 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
469 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
470
471 if (ufcon & S3C2410_UFCON_FIFOMODE) {
472 if ((ufstat & info->tx_fifomask) != 0 ||
473 (ufstat & info->tx_fifofull))
474 return 0;
475
476 return 1;
477 }
478
479 return s3c24xx_serial_txempty_nofifo(port);
480}
481
482/* no modem control lines */
483static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
484{
485 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
486
487 if (umstat & S3C2410_UMSTAT_CTS)
488 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
489 else
490 return TIOCM_CAR | TIOCM_DSR;
491}
492
493static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
494{
495 /* todo - possibly remove AFC and do manual CTS */
496}
497
498static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
499{
500 unsigned long flags;
501 unsigned int ucon;
502
503 spin_lock_irqsave(&port->lock, flags);
504
505 ucon = rd_regl(port, S3C2410_UCON);
506
507 if (break_state)
508 ucon |= S3C2410_UCON_SBREAK;
509 else
510 ucon &= ~S3C2410_UCON_SBREAK;
511
512 wr_regl(port, S3C2410_UCON, ucon);
513
514 spin_unlock_irqrestore(&port->lock, flags);
515}
516
517static void s3c24xx_serial_shutdown(struct uart_port *port)
518{
519 struct s3c24xx_uart_port *ourport = to_ourport(port);
520
521 if (ourport->tx_claimed) {
522 free_irq(TX_IRQ(port), ourport);
523 tx_enabled(port) = 0;
524 ourport->tx_claimed = 0;
525 }
526
527 if (ourport->rx_claimed) {
528 free_irq(RX_IRQ(port), ourport);
529 ourport->rx_claimed = 0;
530 rx_enabled(port) = 0;
531 }
532}
533
534
535static int s3c24xx_serial_startup(struct uart_port *port)
536{
537 struct s3c24xx_uart_port *ourport = to_ourport(port);
538 unsigned long flags;
539 int ret;
540
541 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
542 port->mapbase, port->membase);
543
544 local_irq_save(flags);
545
546 rx_enabled(port) = 1;
547
548 ret = request_irq(RX_IRQ(port),
549 s3c24xx_serial_rx_chars, 0,
550 s3c24xx_serial_portname(port), ourport);
551
552 if (ret != 0) {
553 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
554 return ret;
555 }
556
557 ourport->rx_claimed = 1;
558
559 dbg("requesting tx irq...\n");
560
561 tx_enabled(port) = 1;
562
563 ret = request_irq(TX_IRQ(port),
564 s3c24xx_serial_tx_chars, 0,
565 s3c24xx_serial_portname(port), ourport);
566
567 if (ret) {
568 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
569 goto err;
570 }
571
572 ourport->tx_claimed = 1;
573
574 dbg("s3c24xx_serial_startup ok\n");
575
576 /* the port reset code should have done the correct
577 * register setup for the port controls */
578
579 local_irq_restore(flags);
580 return ret;
581
582 err:
583 s3c24xx_serial_shutdown(port);
584 local_irq_restore(flags);
585 return ret;
586}
587
588/* power power management control */
589
590static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
591 unsigned int old)
592{
593 struct s3c24xx_uart_port *ourport = to_ourport(port);
594
595 switch (level) {
596 case 3:
597 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
598 clk_disable(ourport->baudclk);
599
600 clk_disable(ourport->clk);
601 break;
602
603 case 0:
604 clk_enable(ourport->clk);
605
606 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
607 clk_enable(ourport->baudclk);
608
609 break;
610 default:
611 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
612 }
613}
614
615/* baud rate calculation
616 *
617 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
618 * of different sources, including the peripheral clock ("pclk") and an
619 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
620 * with a programmable extra divisor.
621 *
622 * The following code goes through the clock sources, and calculates the
623 * baud clocks (and the resultant actual baud rates) and then tries to
624 * pick the closest one and select that.
625 *
626*/
627
628
629#define MAX_CLKS (8)
630
631static struct s3c24xx_uart_clksrc tmp_clksrc = {
632 .name = "pclk",
633 .min_baud = 0,
634 .max_baud = 0,
635 .divisor = 1,
636};
637
638static inline int
639s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
640{
641 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
642
643 return (info->get_clksrc)(port, c);
644}
645
646static inline int
647s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
648{
649 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
650
651 return (info->set_clksrc)(port, c);
652}
653
654struct baud_calc {
655 struct s3c24xx_uart_clksrc *clksrc;
656 unsigned int calc;
657 unsigned int quot;
658 struct clk *src;
659};
660
661static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
662 struct uart_port *port,
663 struct s3c24xx_uart_clksrc *clksrc,
664 unsigned int baud)
665{
666 unsigned long rate;
667
668 calc->src = clk_get(port->dev, clksrc->name);
669 if (calc->src == NULL || IS_ERR(calc->src))
670 return 0;
671
672 rate = clk_get_rate(calc->src);
673 rate /= clksrc->divisor;
674
675 calc->clksrc = clksrc;
676 calc->quot = (rate + (8 * baud)) / (16 * baud);
677 calc->calc = (rate / (calc->quot * 16));
678
679 calc->quot--;
680 return 1;
681}
682
683static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
684 struct s3c24xx_uart_clksrc **clksrc,
685 struct clk **clk,
686 unsigned int baud)
687{
688 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
689 struct s3c24xx_uart_clksrc *clkp;
690 struct baud_calc res[MAX_CLKS];
691 struct baud_calc *resptr, *best, *sptr;
692 int i;
693
694 clkp = cfg->clocks;
695 best = NULL;
696
697 if (cfg->clocks_size < 2) {
698 if (cfg->clocks_size == 0)
699 clkp = &tmp_clksrc;
700
701 /* check to see if we're sourcing fclk, and if so we're
702 * going to have to update the clock source
703 */
704
705 if (strcmp(clkp->name, "fclk") == 0) {
706 struct s3c24xx_uart_clksrc src;
707
708 s3c24xx_serial_getsource(port, &src);
709
710 /* check that the port already using fclk, and if
711 * not, then re-select fclk
712 */
713
714 if (strcmp(src.name, clkp->name) == 0) {
715 s3c24xx_serial_setsource(port, clkp);
716 s3c24xx_serial_getsource(port, &src);
717 }
718
719 clkp->divisor = src.divisor;
720 }
721
722 s3c24xx_serial_calcbaud(res, port, clkp, baud);
723 best = res;
724 resptr = best + 1;
725 } else {
726 resptr = res;
727
728 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
729 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
730 resptr++;
731 }
732 }
733
734 /* ok, we now need to select the best clock we found */
735
736 if (!best) {
737 unsigned int deviation = (1<<30)|((1<<30)-1);
738 int calc_deviation;
739
740 for (sptr = res; sptr < resptr; sptr++) {
741 printk(KERN_DEBUG
742 "found clk %p (%s) quot %d, calc %d\n",
743 sptr->clksrc, sptr->clksrc->name,
744 sptr->quot, sptr->calc);
745
746 calc_deviation = baud - sptr->calc;
747 if (calc_deviation < 0)
748 calc_deviation = -calc_deviation;
749
750 if (calc_deviation < deviation) {
751 best = sptr;
752 deviation = calc_deviation;
753 }
754 }
755
756 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
757 }
758
759 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
760 best->clksrc, best->clksrc->name, best->quot, best->calc);
761
762 /* store results to pass back */
763
764 *clksrc = best->clksrc;
765 *clk = best->src;
766
767 return best->quot;
768}
769
770static void s3c24xx_serial_set_termios(struct uart_port *port,
771 struct termios *termios,
772 struct termios *old)
773{
774 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
775 struct s3c24xx_uart_port *ourport = to_ourport(port);
776 struct s3c24xx_uart_clksrc *clksrc;
777 struct clk *clk;
778 unsigned long flags;
779 unsigned int baud, quot;
780 unsigned int ulcon;
781 unsigned int umcon;
782
783 /*
784 * We don't support modem control lines.
785 */
786 termios->c_cflag &= ~(HUPCL | CMSPAR);
787 termios->c_cflag |= CLOCAL;
788
789 /*
790 * Ask the core to calculate the divisor for us.
791 */
792
793 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
794
795 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
796 quot = port->custom_divisor;
797 else
798 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
799
800 /* check to see if we need to change clock source */
801
802 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
803 s3c24xx_serial_setsource(port, clksrc);
804
805 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
806 clk_disable(ourport->baudclk);
807 clk_unuse(ourport->baudclk);
808 ourport->baudclk = NULL;
809 }
810
811 clk_use(clk);
812 clk_enable(clk);
813
814 ourport->clksrc = clksrc;
815 ourport->baudclk = clk;
816 }
817
818 switch (termios->c_cflag & CSIZE) {
819 case CS5:
820 dbg("config: 5bits/char\n");
821 ulcon = S3C2410_LCON_CS5;
822 break;
823 case CS6:
824 dbg("config: 6bits/char\n");
825 ulcon = S3C2410_LCON_CS6;
826 break;
827 case CS7:
828 dbg("config: 7bits/char\n");
829 ulcon = S3C2410_LCON_CS7;
830 break;
831 case CS8:
832 default:
833 dbg("config: 8bits/char\n");
834 ulcon = S3C2410_LCON_CS8;
835 break;
836 }
837
838 /* preserve original lcon IR settings */
839 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
840
841 if (termios->c_cflag & CSTOPB)
842 ulcon |= S3C2410_LCON_STOPB;
843
844 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
845
846 if (termios->c_cflag & PARENB) {
847 if (termios->c_cflag & PARODD)
848 ulcon |= S3C2410_LCON_PODD;
849 else
850 ulcon |= S3C2410_LCON_PEVEN;
851 } else {
852 ulcon |= S3C2410_LCON_PNONE;
853 }
854
855 spin_lock_irqsave(&port->lock, flags);
856
857 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
858
859 wr_regl(port, S3C2410_ULCON, ulcon);
860 wr_regl(port, S3C2410_UBRDIV, quot);
861 wr_regl(port, S3C2410_UMCON, umcon);
862
863 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
864 rd_regl(port, S3C2410_ULCON),
865 rd_regl(port, S3C2410_UCON),
866 rd_regl(port, S3C2410_UFCON));
867
868 /*
869 * Update the per-port timeout.
870 */
871 uart_update_timeout(port, termios->c_cflag, baud);
872
873 /*
874 * Which character status flags are we interested in?
875 */
876 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
877 if (termios->c_iflag & INPCK)
878 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
879
880 /*
881 * Which character status flags should we ignore?
882 */
883 port->ignore_status_mask = 0;
884 if (termios->c_iflag & IGNPAR)
885 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
886 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
887 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
888
889 /*
890 * Ignore all characters if CREAD is not set.
891 */
892 if ((termios->c_cflag & CREAD) == 0)
893 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
894
895 spin_unlock_irqrestore(&port->lock, flags);
896}
897
898static const char *s3c24xx_serial_type(struct uart_port *port)
899{
900 switch (port->type) {
901 case PORT_S3C2410:
902 return "S3C2410";
903 case PORT_S3C2440:
904 return "S3C2440";
905 default:
906 return NULL;
907 }
908}
909
910#define MAP_SIZE (0x100)
911
912static void s3c24xx_serial_release_port(struct uart_port *port)
913{
914 release_mem_region(port->mapbase, MAP_SIZE);
915}
916
917static int s3c24xx_serial_request_port(struct uart_port *port)
918{
919 char *name = s3c24xx_serial_portname(port);
920 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
921}
922
923static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
924{
925 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
926
927 if (flags & UART_CONFIG_TYPE &&
928 s3c24xx_serial_request_port(port) == 0)
929 port->type = info->type;
930}
931
932/*
933 * verify the new serial_struct (for TIOCSSERIAL).
934 */
935static int
936s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
937{
938 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
939
940 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
941 return -EINVAL;
942
943 return 0;
944}
945
946
947#ifdef CONFIG_SERIAL_S3C2410_CONSOLE
948
949static struct console s3c24xx_serial_console;
950
951#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
952#else
953#define S3C24XX_SERIAL_CONSOLE NULL
954#endif
955
956static struct uart_ops s3c24xx_serial_ops = {
957 .pm = s3c24xx_serial_pm,
958 .tx_empty = s3c24xx_serial_tx_empty,
959 .get_mctrl = s3c24xx_serial_get_mctrl,
960 .set_mctrl = s3c24xx_serial_set_mctrl,
961 .stop_tx = s3c24xx_serial_stop_tx,
962 .start_tx = s3c24xx_serial_start_tx,
963 .stop_rx = s3c24xx_serial_stop_rx,
964 .enable_ms = s3c24xx_serial_enable_ms,
965 .break_ctl = s3c24xx_serial_break_ctl,
966 .startup = s3c24xx_serial_startup,
967 .shutdown = s3c24xx_serial_shutdown,
968 .set_termios = s3c24xx_serial_set_termios,
969 .type = s3c24xx_serial_type,
970 .release_port = s3c24xx_serial_release_port,
971 .request_port = s3c24xx_serial_request_port,
972 .config_port = s3c24xx_serial_config_port,
973 .verify_port = s3c24xx_serial_verify_port,
974};
975
976
977static struct uart_driver s3c24xx_uart_drv = {
978 .owner = THIS_MODULE,
979 .dev_name = "s3c2410_serial",
980 .nr = 3,
981 .cons = S3C24XX_SERIAL_CONSOLE,
982 .driver_name = S3C24XX_SERIAL_NAME,
983 .devfs_name = S3C24XX_SERIAL_DEVFS,
984 .major = S3C24XX_SERIAL_MAJOR,
985 .minor = S3C24XX_SERIAL_MINOR,
986};
987
988static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
989 [0] = {
990 .port = {
991 .lock = SPIN_LOCK_UNLOCKED,
992 .iotype = UPIO_MEM,
993 .irq = IRQ_S3CUART_RX0,
994 .uartclk = 0,
995 .fifosize = 16,
996 .ops = &s3c24xx_serial_ops,
997 .flags = UPF_BOOT_AUTOCONF,
998 .line = 0,
999 }
1000 },
1001 [1] = {
1002 .port = {
1003 .lock = SPIN_LOCK_UNLOCKED,
1004 .iotype = UPIO_MEM,
1005 .irq = IRQ_S3CUART_RX1,
1006 .uartclk = 0,
1007 .fifosize = 16,
1008 .ops = &s3c24xx_serial_ops,
1009 .flags = UPF_BOOT_AUTOCONF,
1010 .line = 1,
1011 }
1012 },
1013#if NR_PORTS > 2
1014
1015 [2] = {
1016 .port = {
1017 .lock = SPIN_LOCK_UNLOCKED,
1018 .iotype = UPIO_MEM,
1019 .irq = IRQ_S3CUART_RX2,
1020 .uartclk = 0,
1021 .fifosize = 16,
1022 .ops = &s3c24xx_serial_ops,
1023 .flags = UPF_BOOT_AUTOCONF,
1024 .line = 2,
1025 }
1026 }
1027#endif
1028};
1029
1030/* s3c24xx_serial_resetport
1031 *
1032 * wrapper to call the specific reset for this port (reset the fifos
1033 * and the settings)
1034*/
1035
1036static inline int s3c24xx_serial_resetport(struct uart_port * port,
1037 struct s3c2410_uartcfg *cfg)
1038{
1039 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1040
1041 return (info->reset_port)(port, cfg);
1042}
1043
1044/* s3c24xx_serial_init_port
1045 *
1046 * initialise a single serial port from the platform device given
1047 */
1048
1049static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1050 struct s3c24xx_uart_info *info,
1051 struct platform_device *platdev)
1052{
1053 struct uart_port *port = &ourport->port;
1054 struct s3c2410_uartcfg *cfg;
1055 struct resource *res;
1056
1057 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1058
1059 if (platdev == NULL)
1060 return -ENODEV;
1061
1062 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1063
1064 if (port->mapbase != 0)
1065 return 0;
1066
1067 if (cfg->hwport > 3)
1068 return -EINVAL;
1069
1070 /* setup info for port */
1071 port->dev = &platdev->dev;
1072 ourport->info = info;
1073
1074 /* copy the info in from provided structure */
1075 ourport->port.fifosize = info->fifosize;
1076
1077 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1078
1079 port->uartclk = 1;
1080
1081 if (cfg->uart_flags & UPF_CONS_FLOW) {
1082 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1083 port->flags |= UPF_CONS_FLOW;
1084 }
1085
1086 /* sort our the physical and virtual addresses for each UART */
1087
1088 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1089 if (res == NULL) {
1090 printk(KERN_ERR "failed to find memory resource for uart\n");
1091 return -EINVAL;
1092 }
1093
1094 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1095
1096 port->mapbase = res->start;
1097 port->membase = S3C24XX_VA_UART + (res->start - S3C2410_PA_UART);
1098 port->irq = platform_get_irq(platdev, 0);
1099
1100 ourport->clk = clk_get(&platdev->dev, "uart");
1101
1102 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1103 clk_use(ourport->clk);
1104
1105 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1106 port->mapbase, port->membase, port->irq, port->uartclk);
1107
1108 /* reset the fifos (and setup the uart) */
1109 s3c24xx_serial_resetport(port, cfg);
1110 return 0;
1111}
1112
1113/* Device driver serial port probe */
1114
1115static int probe_index = 0;
1116
1117int s3c24xx_serial_probe(struct device *_dev,
1118 struct s3c24xx_uart_info *info)
1119{
1120 struct s3c24xx_uart_port *ourport;
1121 struct platform_device *dev = to_platform_device(_dev);
1122 int ret;
1123
1124 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1125
1126 ourport = &s3c24xx_serial_ports[probe_index];
1127 probe_index++;
1128
1129 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1130
1131 ret = s3c24xx_serial_init_port(ourport, info, dev);
1132 if (ret < 0)
1133 goto probe_err;
1134
1135 dbg("%s: adding port\n", __FUNCTION__);
1136 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1137 dev_set_drvdata(_dev, &ourport->port);
1138
1139 return 0;
1140
1141 probe_err:
1142 return ret;
1143}
1144
1145int s3c24xx_serial_remove(struct device *_dev)
1146{
1147 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1148
1149 if (port)
1150 uart_remove_one_port(&s3c24xx_uart_drv, port);
1151
1152 return 0;
1153}
1154
1155/* UART power management code */
1156
1157#ifdef CONFIG_PM
1158
1159int s3c24xx_serial_suspend(struct device *dev, u32 state, u32 level)
1160{
1161 struct uart_port *port = s3c24xx_dev_to_port(dev);
1162
1163 if (port && level == SUSPEND_DISABLE)
1164 uart_suspend_port(&s3c24xx_uart_drv, port);
1165
1166 return 0;
1167}
1168
1169int s3c24xx_serial_resume(struct device *dev, u32 level)
1170{
1171 struct uart_port *port = s3c24xx_dev_to_port(dev);
1172 struct s3c24xx_uart_port *ourport = to_ourport(port);
1173
1174 if (port && level == RESUME_ENABLE) {
1175 clk_enable(ourport->clk);
1176 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1177 clk_disable(ourport->clk);
1178
1179 uart_resume_port(&s3c24xx_uart_drv, port);
1180 }
1181
1182 return 0;
1183}
1184
1185#else
1186#define s3c24xx_serial_suspend NULL
1187#define s3c24xx_serial_resume NULL
1188#endif
1189
1190int s3c24xx_serial_init(struct device_driver *drv,
1191 struct s3c24xx_uart_info *info)
1192{
1193 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1194 return driver_register(drv);
1195}
1196
1197
1198/* now comes the code to initialise either the s3c2410 or s3c2440 serial
1199 * port information
1200*/
1201
1202/* cpu specific variations on the serial port support */
1203
1204#ifdef CONFIG_CPU_S3C2400
1205
1206static int s3c2400_serial_getsource(struct uart_port *port,
1207 struct s3c24xx_uart_clksrc *clk)
1208{
1209 clk->divisor = 1;
1210 clk->name = "pclk";
1211
1212 return 0;
1213}
1214
1215static int s3c2400_serial_setsource(struct uart_port *port,
1216 struct s3c24xx_uart_clksrc *clk)
1217{
1218 return 0;
1219}
1220
1221static int s3c2400_serial_resetport(struct uart_port *port,
1222 struct s3c2410_uartcfg *cfg)
1223{
1224 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1225 port, port->mapbase, cfg);
1226
1227 wr_regl(port, S3C2410_UCON, cfg->ucon);
1228 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1229
1230 /* reset both fifos */
1231
1232 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1233 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1234
1235 return 0;
1236}
1237
1238static struct s3c24xx_uart_info s3c2400_uart_inf = {
1239 .name = "Samsung S3C2400 UART",
1240 .type = PORT_S3C2400,
1241 .fifosize = 16,
1242 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1243 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1244 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1245 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1246 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1247 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1248 .get_clksrc = s3c2400_serial_getsource,
1249 .set_clksrc = s3c2400_serial_setsource,
1250 .reset_port = s3c2400_serial_resetport,
1251};
1252
1253static int s3c2400_serial_probe(struct device *dev)
1254{
1255 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1256}
1257
1258static struct device_driver s3c2400_serial_drv = {
1259 .name = "s3c2400-uart",
1260 .bus = &platform_bus_type,
1261 .probe = s3c2400_serial_probe,
1262 .remove = s3c24xx_serial_remove,
1263 .suspend = s3c24xx_serial_suspend,
1264 .resume = s3c24xx_serial_resume,
1265};
1266
1267static inline int s3c2400_serial_init(void)
1268{
1269 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1270}
1271
1272static inline void s3c2400_serial_exit(void)
1273{
1274 driver_unregister(&s3c2400_serial_drv);
1275}
1276
1277#define s3c2400_uart_inf_at &s3c2400_uart_inf
1278#else
1279
1280static inline int s3c2400_serial_init(void)
1281{
1282 return 0;
1283}
1284
1285static inline void s3c2400_serial_exit(void)
1286{
1287}
1288
1289#define s3c2400_uart_inf_at NULL
1290
1291#endif /* CONFIG_CPU_S3C2400 */
1292
1293/* S3C2410 support */
1294
1295#ifdef CONFIG_CPU_S3C2410
1296
1297static int s3c2410_serial_setsource(struct uart_port *port,
1298 struct s3c24xx_uart_clksrc *clk)
1299{
1300 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1301
1302 if (strcmp(clk->name, "uclk") == 0)
1303 ucon |= S3C2410_UCON_UCLK;
1304 else
1305 ucon &= ~S3C2410_UCON_UCLK;
1306
1307 wr_regl(port, S3C2410_UCON, ucon);
1308 return 0;
1309}
1310
1311static int s3c2410_serial_getsource(struct uart_port *port,
1312 struct s3c24xx_uart_clksrc *clk)
1313{
1314 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1315
1316 clk->divisor = 1;
1317 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1318
1319 return 0;
1320}
1321
1322static int s3c2410_serial_resetport(struct uart_port *port,
1323 struct s3c2410_uartcfg *cfg)
1324{
1325 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1326 port, port->mapbase, cfg);
1327
1328 wr_regl(port, S3C2410_UCON, cfg->ucon);
1329 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1330
1331 /* reset both fifos */
1332
1333 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1334 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1335
1336 return 0;
1337}
1338
1339static struct s3c24xx_uart_info s3c2410_uart_inf = {
1340 .name = "Samsung S3C2410 UART",
1341 .type = PORT_S3C2410,
1342 .fifosize = 16,
1343 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1344 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1345 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1346 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1347 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1348 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1349 .get_clksrc = s3c2410_serial_getsource,
1350 .set_clksrc = s3c2410_serial_setsource,
1351 .reset_port = s3c2410_serial_resetport,
1352};
1353
1354/* device management */
1355
1356static int s3c2410_serial_probe(struct device *dev)
1357{
1358 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1359}
1360
1361static struct device_driver s3c2410_serial_drv = {
1362 .name = "s3c2410-uart",
1363 .bus = &platform_bus_type,
1364 .probe = s3c2410_serial_probe,
1365 .remove = s3c24xx_serial_remove,
1366 .suspend = s3c24xx_serial_suspend,
1367 .resume = s3c24xx_serial_resume,
1368};
1369
1370static inline int s3c2410_serial_init(void)
1371{
1372 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1373}
1374
1375static inline void s3c2410_serial_exit(void)
1376{
1377 driver_unregister(&s3c2410_serial_drv);
1378}
1379
1380#define s3c2410_uart_inf_at &s3c2410_uart_inf
1381#else
1382
1383static inline int s3c2410_serial_init(void)
1384{
1385 return 0;
1386}
1387
1388static inline void s3c2410_serial_exit(void)
1389{
1390}
1391
1392#define s3c2410_uart_inf_at NULL
1393
1394#endif /* CONFIG_CPU_S3C2410 */
1395
1396#ifdef CONFIG_CPU_S3C2440
1397
1398static int s3c2440_serial_setsource(struct uart_port *port,
1399 struct s3c24xx_uart_clksrc *clk)
1400{
1401 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1402
1403 // todo - proper fclk<>nonfclk switch //
1404
1405 ucon &= ~S3C2440_UCON_CLKMASK;
1406
1407 if (strcmp(clk->name, "uclk") == 0)
1408 ucon |= S3C2440_UCON_UCLK;
1409 else if (strcmp(clk->name, "pclk") == 0)
1410 ucon |= S3C2440_UCON_PCLK;
1411 else if (strcmp(clk->name, "fclk") == 0)
1412 ucon |= S3C2440_UCON_FCLK;
1413 else {
1414 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1415 return -EINVAL;
1416 }
1417
1418 wr_regl(port, S3C2410_UCON, ucon);
1419 return 0;
1420}
1421
1422
1423static int s3c2440_serial_getsource(struct uart_port *port,
1424 struct s3c24xx_uart_clksrc *clk)
1425{
1426 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1427 unsigned long ucon0, ucon1, ucon2;
1428
1429 switch (ucon & S3C2440_UCON_CLKMASK) {
1430 case S3C2440_UCON_UCLK:
1431 clk->divisor = 1;
1432 clk->name = "uclk";
1433 break;
1434
1435 case S3C2440_UCON_PCLK:
1436 case S3C2440_UCON_PCLK2:
1437 clk->divisor = 1;
1438 clk->name = "pclk";
1439 break;
1440
1441 case S3C2440_UCON_FCLK:
1442 /* the fun of calculating the uart divisors on
1443 * the s3c2440 */
1444
1445 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1446 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1447 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1448
1449 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1450
1451 ucon0 &= S3C2440_UCON0_DIVMASK;
1452 ucon1 &= S3C2440_UCON1_DIVMASK;
1453 ucon2 &= S3C2440_UCON2_DIVMASK;
1454
1455 if (ucon0 != 0) {
1456 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1457 clk->divisor += 6;
1458 } else if (ucon1 != 0) {
1459 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1460 clk->divisor += 21;
1461 } else if (ucon2 != 0) {
1462 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1463 clk->divisor += 36;
1464 } else {
1465 /* manual calims 44, seems to be 9 */
1466 clk->divisor = 9;
1467 }
1468
1469 clk->name = "fclk";
1470 break;
1471 }
1472
1473 return 0;
1474}
1475
1476static int s3c2440_serial_resetport(struct uart_port *port,
1477 struct s3c2410_uartcfg *cfg)
1478{
1479 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1480
1481 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1482 port, port->mapbase, cfg);
1483
1484 /* ensure we don't change the clock settings... */
1485
1486 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1487
1488 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1489 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1490
1491 /* reset both fifos */
1492
1493 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1494 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1495
1496 return 0;
1497}
1498
1499static struct s3c24xx_uart_info s3c2440_uart_inf = {
1500 .name = "Samsung S3C2440 UART",
1501 .type = PORT_S3C2440,
1502 .fifosize = 64,
1503 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1504 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1505 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1506 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1507 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1508 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1509 .get_clksrc = s3c2440_serial_getsource,
1510 .set_clksrc = s3c2440_serial_setsource,
1511 .reset_port = s3c2440_serial_resetport,
1512};
1513
1514/* device management */
1515
1516static int s3c2440_serial_probe(struct device *dev)
1517{
1518 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1519 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1520}
1521
1522static struct device_driver s3c2440_serial_drv = {
1523 .name = "s3c2440-uart",
1524 .bus = &platform_bus_type,
1525 .probe = s3c2440_serial_probe,
1526 .remove = s3c24xx_serial_remove,
1527 .suspend = s3c24xx_serial_suspend,
1528 .resume = s3c24xx_serial_resume,
1529};
1530
1531
1532static inline int s3c2440_serial_init(void)
1533{
1534 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1535}
1536
1537static inline void s3c2440_serial_exit(void)
1538{
1539 driver_unregister(&s3c2440_serial_drv);
1540}
1541
1542#define s3c2440_uart_inf_at &s3c2440_uart_inf
1543#else
1544
1545static inline int s3c2440_serial_init(void)
1546{
1547 return 0;
1548}
1549
1550static inline void s3c2440_serial_exit(void)
1551{
1552}
1553
1554#define s3c2440_uart_inf_at NULL
1555#endif /* CONFIG_CPU_S3C2440 */
1556
1557/* module initialisation code */
1558
1559static int __init s3c24xx_serial_modinit(void)
1560{
1561 int ret;
1562
1563 ret = uart_register_driver(&s3c24xx_uart_drv);
1564 if (ret < 0) {
1565 printk(KERN_ERR "failed to register UART driver\n");
1566 return -1;
1567 }
1568
1569 s3c2400_serial_init();
1570 s3c2410_serial_init();
1571 s3c2440_serial_init();
1572
1573 return 0;
1574}
1575
1576static void __exit s3c24xx_serial_modexit(void)
1577{
1578 s3c2400_serial_exit();
1579 s3c2410_serial_exit();
1580 s3c2440_serial_exit();
1581
1582 uart_unregister_driver(&s3c24xx_uart_drv);
1583}
1584
1585
1586module_init(s3c24xx_serial_modinit);
1587module_exit(s3c24xx_serial_modexit);
1588
1589/* Console code */
1590
1591#ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1592
1593static struct uart_port *cons_uart;
1594
1595static int
1596s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1597{
1598 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1599 unsigned long ufstat, utrstat;
1600
1601 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1602 /* fifo mode - check ammount of data in fifo registers... */
1603
1604 ufstat = rd_regl(port, S3C2410_UFSTAT);
1605 return (ufstat & info->tx_fifofull) ? 0 : 1;
1606 }
1607
1608 /* in non-fifo mode, we go and use the tx buffer empty */
1609
1610 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1611 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1612}
1613
1614static void
1615s3c24xx_serial_console_write(struct console *co, const char *s,
1616 unsigned int count)
1617{
1618 int i;
1619 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1620
1621 for (i = 0; i < count; i++) {
1622 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1623 barrier();
1624
1625 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1626
1627 if (s[i] == '\n') {
1628 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1629 barrier();
1630
1631 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1632 }
1633 }
1634}
1635
1636static void __init
1637s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1638 int *parity, int *bits)
1639{
1640 struct s3c24xx_uart_clksrc clksrc;
1641 struct clk *clk;
1642 unsigned int ulcon;
1643 unsigned int ucon;
1644 unsigned int ubrdiv;
1645 unsigned long rate;
1646
1647 ulcon = rd_regl(port, S3C2410_ULCON);
1648 ucon = rd_regl(port, S3C2410_UCON);
1649 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1650
1651 dbg("s3c24xx_serial_get_options: port=%p\n"
1652 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1653 port, ulcon, ucon, ubrdiv);
1654
1655 if ((ucon & 0xf) != 0) {
1656 /* consider the serial port configured if the tx/rx mode set */
1657
1658 switch (ulcon & S3C2410_LCON_CSMASK) {
1659 case S3C2410_LCON_CS5:
1660 *bits = 5;
1661 break;
1662 case S3C2410_LCON_CS6:
1663 *bits = 6;
1664 break;
1665 case S3C2410_LCON_CS7:
1666 *bits = 7;
1667 break;
1668 default:
1669 case S3C2410_LCON_CS8:
1670 *bits = 8;
1671 break;
1672 }
1673
1674 switch (ulcon & S3C2410_LCON_PMASK) {
1675 case S3C2410_LCON_PEVEN:
1676 *parity = 'e';
1677 break;
1678
1679 case S3C2410_LCON_PODD:
1680 *parity = 'o';
1681 break;
1682
1683 case S3C2410_LCON_PNONE:
1684 default:
1685 *parity = 'n';
1686 }
1687
1688 /* now calculate the baud rate */
1689
1690 s3c24xx_serial_getsource(port, &clksrc);
1691
1692 clk = clk_get(port->dev, clksrc.name);
1693 if (!IS_ERR(clk) && clk != NULL)
1694 rate = clk_get_rate(clk) / clksrc.divisor;
1695 else
1696 rate = 1;
1697
1698
1699 *baud = rate / ( 16 * (ubrdiv + 1));
1700 dbg("calculated baud %d\n", *baud);
1701 }
1702
1703}
1704
1705/* s3c24xx_serial_init_ports
1706 *
1707 * initialise the serial ports from the machine provided initialisation
1708 * data.
1709*/
1710
1711static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1712{
1713 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1714 struct platform_device **platdev_ptr;
1715 int i;
1716
1717 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1718
1719 platdev_ptr = s3c24xx_uart_devs;
1720
1721 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1722 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1723 }
1724
1725 return 0;
1726}
1727
1728static int __init
1729s3c24xx_serial_console_setup(struct console *co, char *options)
1730{
1731 struct uart_port *port;
1732 int baud = 9600;
1733 int bits = 8;
1734 int parity = 'n';
1735 int flow = 'n';
1736
1737 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1738 co, co->index, options);
1739
1740 /* is this a valid port */
1741
1742 if (co->index == -1 || co->index >= NR_PORTS)
1743 co->index = 0;
1744
1745 port = &s3c24xx_serial_ports[co->index].port;
1746
1747 /* is the port configured? */
1748
1749 if (port->mapbase == 0x0) {
1750 co->index = 0;
1751 port = &s3c24xx_serial_ports[co->index].port;
1752 }
1753
1754 cons_uart = port;
1755
1756 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1757
1758 /*
1759 * Check whether an invalid uart number has been specified, and
1760 * if so, search for the first available port that does have
1761 * console support.
1762 */
1763 if (options)
1764 uart_parse_options(options, &baud, &parity, &bits, &flow);
1765 else
1766 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1767
1768 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1769
1770 return uart_set_options(port, co, baud, parity, bits, flow);
1771}
1772
1773/* s3c24xx_serial_initconsole
1774 *
1775 * initialise the console from one of the uart drivers
1776*/
1777
1778static struct console s3c24xx_serial_console =
1779{
1780 .name = S3C24XX_SERIAL_NAME,
1781 .device = uart_console_device,
1782 .flags = CON_PRINTBUFFER,
1783 .index = -1,
1784 .write = s3c24xx_serial_console_write,
1785 .setup = s3c24xx_serial_console_setup
1786};
1787
1788static int s3c24xx_serial_initconsole(void)
1789{
1790 struct s3c24xx_uart_info *info;
1791 struct platform_device *dev = s3c24xx_uart_devs[0];
1792
1793 dbg("s3c24xx_serial_initconsole\n");
1794
1795 /* select driver based on the cpu */
1796
1797 if (dev == NULL) {
1798 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1799 return 0;
1800 }
1801
1802 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1803 info = s3c2400_uart_inf_at;
1804 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1805 info = s3c2410_uart_inf_at;
1806 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1807 info = s3c2440_uart_inf_at;
1808 } else {
1809 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1810 return 0;
1811 }
1812
1813 if (info == NULL) {
1814 printk(KERN_ERR "s3c24xx: no driver for console\n");
1815 return 0;
1816 }
1817
1818 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1819 s3c24xx_serial_init_ports(info);
1820
1821 register_console(&s3c24xx_serial_console);
1822 return 0;
1823}
1824
1825console_initcall(s3c24xx_serial_initconsole);
1826
1827#endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1828
1829MODULE_LICENSE("GPL");
1830MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1831MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 18:36:02 -0500