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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/serial/m32r_sio.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/serial/m32r_sio.c')
-rw-r--r--drivers/serial/m32r_sio.c1218
1 files changed, 1218 insertions, 0 deletions
diff --git a/drivers/serial/m32r_sio.c b/drivers/serial/m32r_sio.c
new file mode 100644
index 000000000000..08d61f13edc6
--- /dev/null
+++ b/drivers/serial/m32r_sio.c
@@ -0,0 +1,1218 @@
1/*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
28#include <linux/config.h>
29
30#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/tty.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/serial.h>
41#include <linux/serialP.h>
42#include <linux/delay.h>
43
44#include <asm/m32r.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#define PORT_M32R_BASE PORT_M32R_SIO
49#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
50#define BAUD_RATE 115200
51
52#include <linux/serial_core.h>
53#include "m32r_sio.h"
54#include "m32r_sio_reg.h"
55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
80#include <asm/serial.h>
81
82/* Standard COM flags */
83#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
84
85/*
86 * SERIAL_PORT_DFNS tells us about built-in ports that have no
87 * standard enumeration mechanism. Platforms that can find all
88 * serial ports via mechanisms like ACPI or PCI need not supply it.
89 */
90#undef SERIAL_PORT_DFNS
91#if defined(CONFIG_PLAT_USRV)
92
93#define SERIAL_PORT_DFNS \
94 /* UART CLK PORT IRQ FLAGS */ \
95 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
96 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
97
98#else /* !CONFIG_PLAT_USRV */
99
100#if defined(CONFIG_SERIAL_M32R_PLDSIO)
101#define SERIAL_PORT_DFNS \
102 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
103 STD_COM_FLAGS }, /* ttyS0 */
104#else
105#define SERIAL_PORT_DFNS \
106 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
107 STD_COM_FLAGS }, /* ttyS0 */
108#endif
109
110#endif /* !CONFIG_PLAT_USRV */
111
112static struct old_serial_port old_serial_port[] = {
113 SERIAL_PORT_DFNS /* defined in asm/serial.h */
114};
115
116#define UART_NR ARRAY_SIZE(old_serial_port)
117
118struct uart_sio_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
122 unsigned short rev;
123 unsigned char acr;
124 unsigned char ier;
125 unsigned char lcr;
126 unsigned char mcr_mask; /* mask of user bits */
127 unsigned char mcr_force; /* mask of forced bits */
128 unsigned char lsr_break_flag;
129
130 /*
131 * We provide a per-port pm hook.
132 */
133 void (*pm)(struct uart_port *port,
134 unsigned int state, unsigned int old);
135};
136
137struct irq_info {
138 spinlock_t lock;
139 struct list_head *head;
140};
141
142static struct irq_info irq_lists[NR_IRQS];
143
144/*
145 * Here we define the default xmit fifo size used for each type of UART.
146 */
147static const struct serial_uart_config uart_config[] = {
148 [PORT_UNKNOWN] = {
149 .name = "unknown",
150 .dfl_xmit_fifo_size = 1,
151 .flags = 0,
152 },
153 [PORT_INDEX(PORT_M32R_SIO)] = {
154 .name = "M32RSIO",
155 .dfl_xmit_fifo_size = 1,
156 .flags = 0,
157 },
158};
159
160#ifdef CONFIG_SERIAL_M32R_PLDSIO
161
162#define __sio_in(x) inw((unsigned long)(x))
163#define __sio_out(v,x) outw((v),(unsigned long)(x))
164
165static inline void sio_set_baud_rate(unsigned long baud)
166{
167 unsigned short sbaud;
168 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
169 __sio_out(sbaud, PLD_ESIO0BAUR);
170}
171
172static void sio_reset(void)
173{
174 unsigned short tmp;
175
176 tmp = __sio_in(PLD_ESIO0RXB);
177 tmp = __sio_in(PLD_ESIO0RXB);
178 tmp = __sio_in(PLD_ESIO0CR);
179 sio_set_baud_rate(BAUD_RATE);
180 __sio_out(0x0300, PLD_ESIO0CR);
181 __sio_out(0x0003, PLD_ESIO0CR);
182}
183
184static void sio_init(void)
185{
186 unsigned short tmp;
187
188 tmp = __sio_in(PLD_ESIO0RXB);
189 tmp = __sio_in(PLD_ESIO0RXB);
190 tmp = __sio_in(PLD_ESIO0CR);
191 __sio_out(0x0300, PLD_ESIO0CR);
192 __sio_out(0x0003, PLD_ESIO0CR);
193}
194
195static void sio_error(int *status)
196{
197 printk("SIO0 error[%04x]\n", *status);
198 do {
199 sio_init();
200 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
201}
202
203#else /* not CONFIG_SERIAL_M32R_PLDSIO */
204
205#define __sio_in(x) inl(x)
206#define __sio_out(v,x) outl((v),(x))
207
208static inline void sio_set_baud_rate(unsigned long baud)
209{
210 unsigned long i, j;
211
212 i = boot_cpu_data.bus_clock / (baud * 16);
213 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
214 i -= 1;
215 j = (j + 1) >> 1;
216
217 __sio_out(i, M32R_SIO0_BAUR_PORTL);
218 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
219}
220
221static void sio_reset(void)
222{
223 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
224 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
225 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
226 sio_set_baud_rate(BAUD_RATE);
227 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
228 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
229}
230
231static void sio_init(void)
232{
233 unsigned int tmp;
234
235 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
236 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
237 tmp = __sio_in(M32R_SIO0_STS_PORTL);
238 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
239}
240
241static void sio_error(int *status)
242{
243 printk("SIO0 error[%04x]\n", *status);
244 do {
245 sio_init();
246 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
247}
248
249#endif /* CONFIG_SERIAL_M32R_PLDSIO */
250
251static _INLINE_ unsigned int sio_in(struct uart_sio_port *up, int offset)
252{
253 return __sio_in(up->port.iobase + offset);
254}
255
256static _INLINE_ void sio_out(struct uart_sio_port *up, int offset, int value)
257{
258 __sio_out(value, up->port.iobase + offset);
259}
260
261static _INLINE_ unsigned int serial_in(struct uart_sio_port *up, int offset)
262{
263 if (!offset)
264 return 0;
265
266 return __sio_in(offset);
267}
268
269static _INLINE_ void
270serial_out(struct uart_sio_port *up, int offset, int value)
271{
272 if (!offset)
273 return;
274
275 __sio_out(value, offset);
276}
277
278static void m32r_sio_stop_tx(struct uart_port *port, unsigned int tty_stop)
279{
280 struct uart_sio_port *up = (struct uart_sio_port *)port;
281
282 if (up->ier & UART_IER_THRI) {
283 up->ier &= ~UART_IER_THRI;
284 serial_out(up, UART_IER, up->ier);
285 }
286}
287
288static void m32r_sio_start_tx(struct uart_port *port, unsigned int tty_start)
289{
290#ifdef CONFIG_SERIAL_M32R_PLDSIO
291 struct uart_sio_port *up = (struct uart_sio_port *)port;
292 struct circ_buf *xmit = &up->port.info->xmit;
293
294 if (!(up->ier & UART_IER_THRI)) {
295 up->ier |= UART_IER_THRI;
296 serial_out(up, UART_IER, up->ier);
297 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
298 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
299 up->port.icount.tx++;
300 }
301 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
302#else
303 struct uart_sio_port *up = (struct uart_sio_port *)port;
304
305 if (!(up->ier & UART_IER_THRI)) {
306 up->ier |= UART_IER_THRI;
307 serial_out(up, UART_IER, up->ier);
308 }
309#endif
310}
311
312static void m32r_sio_stop_rx(struct uart_port *port)
313{
314 struct uart_sio_port *up = (struct uart_sio_port *)port;
315
316 up->ier &= ~UART_IER_RLSI;
317 up->port.read_status_mask &= ~UART_LSR_DR;
318 serial_out(up, UART_IER, up->ier);
319}
320
321static void m32r_sio_enable_ms(struct uart_port *port)
322{
323 struct uart_sio_port *up = (struct uart_sio_port *)port;
324
325 up->ier |= UART_IER_MSI;
326 serial_out(up, UART_IER, up->ier);
327}
328
329static _INLINE_ void receive_chars(struct uart_sio_port *up, int *status,
330 struct pt_regs *regs)
331{
332 struct tty_struct *tty = up->port.info->tty;
333 unsigned char ch;
334 int max_count = 256;
335
336 do {
337 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
338 tty->flip.work.func((void *)tty);
339 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
340 return; // if TTY_DONT_FLIP is set
341 }
342 ch = sio_in(up, SIORXB);
343 *tty->flip.char_buf_ptr = ch;
344 *tty->flip.flag_buf_ptr = TTY_NORMAL;
345 up->port.icount.rx++;
346
347 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
348 UART_LSR_FE | UART_LSR_OE))) {
349 /*
350 * For statistics only
351 */
352 if (*status & UART_LSR_BI) {
353 *status &= ~(UART_LSR_FE | UART_LSR_PE);
354 up->port.icount.brk++;
355 /*
356 * We do the SysRQ and SAK checking
357 * here because otherwise the break
358 * may get masked by ignore_status_mask
359 * or read_status_mask.
360 */
361 if (uart_handle_break(&up->port))
362 goto ignore_char;
363 } else if (*status & UART_LSR_PE)
364 up->port.icount.parity++;
365 else if (*status & UART_LSR_FE)
366 up->port.icount.frame++;
367 if (*status & UART_LSR_OE)
368 up->port.icount.overrun++;
369
370 /*
371 * Mask off conditions which should be ingored.
372 */
373 *status &= up->port.read_status_mask;
374
375 if (up->port.line == up->port.cons->index) {
376 /* Recover the break flag from console xmit */
377 *status |= up->lsr_break_flag;
378 up->lsr_break_flag = 0;
379 }
380
381 if (*status & UART_LSR_BI) {
382 DEBUG_INTR("handling break....");
383 *tty->flip.flag_buf_ptr = TTY_BREAK;
384 } else if (*status & UART_LSR_PE)
385 *tty->flip.flag_buf_ptr = TTY_PARITY;
386 else if (*status & UART_LSR_FE)
387 *tty->flip.flag_buf_ptr = TTY_FRAME;
388 }
389 if (uart_handle_sysrq_char(&up->port, ch, regs))
390 goto ignore_char;
391 if ((*status & up->port.ignore_status_mask) == 0) {
392 tty->flip.flag_buf_ptr++;
393 tty->flip.char_buf_ptr++;
394 tty->flip.count++;
395 }
396 if ((*status & UART_LSR_OE) &&
397 tty->flip.count < TTY_FLIPBUF_SIZE) {
398 /*
399 * Overrun is special, since it's reported
400 * immediately, and doesn't affect the current
401 * character.
402 */
403 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
404 tty->flip.flag_buf_ptr++;
405 tty->flip.char_buf_ptr++;
406 tty->flip.count++;
407 }
408 ignore_char:
409 *status = serial_in(up, UART_LSR);
410 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
411 tty_flip_buffer_push(tty);
412}
413
414static _INLINE_ void transmit_chars(struct uart_sio_port *up)
415{
416 struct circ_buf *xmit = &up->port.info->xmit;
417 int count;
418
419 if (up->port.x_char) {
420#ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
421 serial_out(up, UART_TX, up->port.x_char);
422#endif
423 up->port.icount.tx++;
424 up->port.x_char = 0;
425 return;
426 }
427 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
428 m32r_sio_stop_tx(&up->port, 0);
429 return;
430 }
431
432 count = up->port.fifosize;
433 do {
434 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
435 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
436 up->port.icount.tx++;
437 if (uart_circ_empty(xmit))
438 break;
439 while (!serial_in(up, UART_LSR) & UART_LSR_THRE);
440
441 } while (--count > 0);
442
443 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
444 uart_write_wakeup(&up->port);
445
446 DEBUG_INTR("THRE...");
447
448 if (uart_circ_empty(xmit))
449 m32r_sio_stop_tx(&up->port, 0);
450}
451
452/*
453 * This handles the interrupt from one port.
454 */
455static inline void m32r_sio_handle_port(struct uart_sio_port *up,
456 unsigned int status, struct pt_regs *regs)
457{
458 DEBUG_INTR("status = %x...", status);
459
460 if (status & 0x04)
461 receive_chars(up, &status, regs);
462 if (status & 0x01)
463 transmit_chars(up);
464}
465
466/*
467 * This is the serial driver's interrupt routine.
468 *
469 * Arjan thinks the old way was overly complex, so it got simplified.
470 * Alan disagrees, saying that need the complexity to handle the weird
471 * nature of ISA shared interrupts. (This is a special exception.)
472 *
473 * In order to handle ISA shared interrupts properly, we need to check
474 * that all ports have been serviced, and therefore the ISA interrupt
475 * line has been de-asserted.
476 *
477 * This means we need to loop through all ports. checking that they
478 * don't have an interrupt pending.
479 */
480static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id,
481 struct pt_regs *regs)
482{
483 struct irq_info *i = dev_id;
484 struct list_head *l, *end = NULL;
485 int pass_counter = 0;
486
487 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
488
489#ifdef CONFIG_SERIAL_M32R_PLDSIO
490// if (irq == PLD_IRQ_SIO0_SND)
491// irq = PLD_IRQ_SIO0_RCV;
492#else
493 if (irq == M32R_IRQ_SIO0_S)
494 irq = M32R_IRQ_SIO0_R;
495#endif
496
497 spin_lock(&i->lock);
498
499 l = i->head;
500 do {
501 struct uart_sio_port *up;
502 unsigned int sts;
503
504 up = list_entry(l, struct uart_sio_port, list);
505
506 sts = sio_in(up, SIOSTS);
507 if (sts & 0x5) {
508 spin_lock(&up->port.lock);
509 m32r_sio_handle_port(up, sts, regs);
510 spin_unlock(&up->port.lock);
511
512 end = NULL;
513 } else if (end == NULL)
514 end = l;
515
516 l = l->next;
517
518 if (l == i->head && pass_counter++ > PASS_LIMIT) {
519 if (sts & 0xe0)
520 sio_error(&sts);
521 break;
522 }
523 } while (l != end);
524
525 spin_unlock(&i->lock);
526
527 DEBUG_INTR("end.\n");
528
529 return IRQ_HANDLED;
530}
531
532/*
533 * To support ISA shared interrupts, we need to have one interrupt
534 * handler that ensures that the IRQ line has been deasserted
535 * before returning. Failing to do this will result in the IRQ
536 * line being stuck active, and, since ISA irqs are edge triggered,
537 * no more IRQs will be seen.
538 */
539static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
540{
541 spin_lock_irq(&i->lock);
542
543 if (!list_empty(i->head)) {
544 if (i->head == &up->list)
545 i->head = i->head->next;
546 list_del(&up->list);
547 } else {
548 BUG_ON(i->head != &up->list);
549 i->head = NULL;
550 }
551
552 spin_unlock_irq(&i->lock);
553}
554
555static int serial_link_irq_chain(struct uart_sio_port *up)
556{
557 struct irq_info *i = irq_lists + up->port.irq;
558 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
559
560 spin_lock_irq(&i->lock);
561
562 if (i->head) {
563 list_add(&up->list, i->head);
564 spin_unlock_irq(&i->lock);
565
566 ret = 0;
567 } else {
568 INIT_LIST_HEAD(&up->list);
569 i->head = &up->list;
570 spin_unlock_irq(&i->lock);
571
572 ret = request_irq(up->port.irq, m32r_sio_interrupt,
573 irq_flags, "SIO0-RX", i);
574 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
575 irq_flags, "SIO0-TX", i);
576 if (ret < 0)
577 serial_do_unlink(i, up);
578 }
579
580 return ret;
581}
582
583static void serial_unlink_irq_chain(struct uart_sio_port *up)
584{
585 struct irq_info *i = irq_lists + up->port.irq;
586
587 BUG_ON(i->head == NULL);
588
589 if (list_empty(i->head)) {
590 free_irq(up->port.irq, i);
591 free_irq(up->port.irq + 1, i);
592 }
593
594 serial_do_unlink(i, up);
595}
596
597/*
598 * This function is used to handle ports that do not have an interrupt.
599 */
600static void m32r_sio_timeout(unsigned long data)
601{
602 struct uart_sio_port *up = (struct uart_sio_port *)data;
603 unsigned int timeout;
604 unsigned int sts;
605
606 sts = sio_in(up, SIOSTS);
607 if (sts & 0x5) {
608 spin_lock(&up->port.lock);
609 m32r_sio_handle_port(up, sts, NULL);
610 spin_unlock(&up->port.lock);
611 }
612
613 timeout = up->port.timeout;
614 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
615 mod_timer(&up->timer, jiffies + timeout);
616}
617
618static unsigned int m32r_sio_tx_empty(struct uart_port *port)
619{
620 struct uart_sio_port *up = (struct uart_sio_port *)port;
621 unsigned long flags;
622 unsigned int ret;
623
624 spin_lock_irqsave(&up->port.lock, flags);
625 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
626 spin_unlock_irqrestore(&up->port.lock, flags);
627
628 return ret;
629}
630
631static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
632{
633 return 0;
634}
635
636static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
637{
638
639}
640
641static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
642{
643
644}
645
646static int m32r_sio_startup(struct uart_port *port)
647{
648 struct uart_sio_port *up = (struct uart_sio_port *)port;
649 int retval;
650
651 sio_init();
652
653 /*
654 * If the "interrupt" for this port doesn't correspond with any
655 * hardware interrupt, we use a timer-based system. The original
656 * driver used to do this with IRQ0.
657 */
658 if (!is_real_interrupt(up->port.irq)) {
659 unsigned int timeout = up->port.timeout;
660
661 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
662
663 up->timer.data = (unsigned long)up;
664 mod_timer(&up->timer, jiffies + timeout);
665 } else {
666 retval = serial_link_irq_chain(up);
667 if (retval)
668 return retval;
669 }
670
671 /*
672 * Finally, enable interrupts. Note: Modem status interrupts
673 * are set via set_termios(), which will be occurring imminently
674 * anyway, so we don't enable them here.
675 * - M32R_SIO: 0x0c
676 * - M32R_PLDSIO: 0x04
677 */
678 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
679 sio_out(up, SIOTRCR, up->ier);
680
681 /*
682 * And clear the interrupt registers again for luck.
683 */
684 sio_reset();
685
686 return 0;
687}
688
689static void m32r_sio_shutdown(struct uart_port *port)
690{
691 struct uart_sio_port *up = (struct uart_sio_port *)port;
692
693 /*
694 * Disable interrupts from this port
695 */
696 up->ier = 0;
697 sio_out(up, SIOTRCR, 0);
698
699 /*
700 * Disable break condition and FIFOs
701 */
702
703 sio_init();
704
705 if (!is_real_interrupt(up->port.irq))
706 del_timer_sync(&up->timer);
707 else
708 serial_unlink_irq_chain(up);
709}
710
711static unsigned int m32r_sio_get_divisor(struct uart_port *port,
712 unsigned int baud)
713{
714 return uart_get_divisor(port, baud);
715}
716
717static void m32r_sio_set_termios(struct uart_port *port,
718 struct termios *termios, struct termios *old)
719{
720 struct uart_sio_port *up = (struct uart_sio_port *)port;
721 unsigned char cval = 0;
722 unsigned long flags;
723 unsigned int baud, quot;
724
725 switch (termios->c_cflag & CSIZE) {
726 case CS5:
727 cval = 0x00;
728 break;
729 case CS6:
730 cval = 0x01;
731 break;
732 case CS7:
733 cval = 0x02;
734 break;
735 default:
736 case CS8:
737 cval = 0x03;
738 break;
739 }
740
741 if (termios->c_cflag & CSTOPB)
742 cval |= 0x04;
743 if (termios->c_cflag & PARENB)
744 cval |= UART_LCR_PARITY;
745 if (!(termios->c_cflag & PARODD))
746 cval |= UART_LCR_EPAR;
747#ifdef CMSPAR
748 if (termios->c_cflag & CMSPAR)
749 cval |= UART_LCR_SPAR;
750#endif
751
752 /*
753 * Ask the core to calculate the divisor for us.
754 */
755#ifdef CONFIG_SERIAL_M32R_PLDSIO
756 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
757#else
758 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
759#endif
760 quot = m32r_sio_get_divisor(port, baud);
761
762 /*
763 * Ok, we're now changing the port state. Do it with
764 * interrupts disabled.
765 */
766 spin_lock_irqsave(&up->port.lock, flags);
767
768 sio_set_baud_rate(baud);
769
770 /*
771 * Update the per-port timeout.
772 */
773 uart_update_timeout(port, termios->c_cflag, baud);
774
775 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
776 if (termios->c_iflag & INPCK)
777 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
778 if (termios->c_iflag & (BRKINT | PARMRK))
779 up->port.read_status_mask |= UART_LSR_BI;
780
781 /*
782 * Characteres to ignore
783 */
784 up->port.ignore_status_mask = 0;
785 if (termios->c_iflag & IGNPAR)
786 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
787 if (termios->c_iflag & IGNBRK) {
788 up->port.ignore_status_mask |= UART_LSR_BI;
789 /*
790 * If we're ignoring parity and break indicators,
791 * ignore overruns too (for real raw support).
792 */
793 if (termios->c_iflag & IGNPAR)
794 up->port.ignore_status_mask |= UART_LSR_OE;
795 }
796
797 /*
798 * ignore all characters if CREAD is not set
799 */
800 if ((termios->c_cflag & CREAD) == 0)
801 up->port.ignore_status_mask |= UART_LSR_DR;
802
803 /*
804 * CTS flow control flag and modem status interrupts
805 */
806 up->ier &= ~UART_IER_MSI;
807 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
808 up->ier |= UART_IER_MSI;
809
810 serial_out(up, UART_IER, up->ier);
811
812 up->lcr = cval; /* Save LCR */
813 spin_unlock_irqrestore(&up->port.lock, flags);
814}
815
816static void m32r_sio_pm(struct uart_port *port, unsigned int state,
817 unsigned int oldstate)
818{
819 struct uart_sio_port *up = (struct uart_sio_port *)port;
820
821 if (up->pm)
822 up->pm(port, state, oldstate);
823}
824
825/*
826 * Resource handling. This is complicated by the fact that resources
827 * depend on the port type. Maybe we should be claiming the standard
828 * 8250 ports, and then trying to get other resources as necessary?
829 */
830static int
831m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
832{
833 unsigned int size = 8 << up->port.regshift;
834#ifndef CONFIG_SERIAL_M32R_PLDSIO
835 unsigned long start;
836#endif
837 int ret = 0;
838
839 switch (up->port.iotype) {
840 case UPIO_MEM:
841 if (up->port.mapbase) {
842#ifdef CONFIG_SERIAL_M32R_PLDSIO
843 *res = request_mem_region(up->port.mapbase, size, "serial");
844#else
845 start = up->port.mapbase;
846 *res = request_mem_region(start, size, "serial");
847#endif
848 if (!*res)
849 ret = -EBUSY;
850 }
851 break;
852
853 case UPIO_PORT:
854 *res = request_region(up->port.iobase, size, "serial");
855 if (!*res)
856 ret = -EBUSY;
857 break;
858 }
859 return ret;
860}
861
862static void m32r_sio_release_port(struct uart_port *port)
863{
864 struct uart_sio_port *up = (struct uart_sio_port *)port;
865 unsigned long start, offset = 0, size = 0;
866
867 size <<= up->port.regshift;
868
869 switch (up->port.iotype) {
870 case UPIO_MEM:
871 if (up->port.mapbase) {
872 /*
873 * Unmap the area.
874 */
875 iounmap(up->port.membase);
876 up->port.membase = NULL;
877
878 start = up->port.mapbase;
879
880 if (size)
881 release_mem_region(start + offset, size);
882 release_mem_region(start, 8 << up->port.regshift);
883 }
884 break;
885
886 case UPIO_PORT:
887 start = up->port.iobase;
888
889 if (size)
890 release_region(start + offset, size);
891 release_region(start + offset, 8 << up->port.regshift);
892 break;
893
894 default:
895 break;
896 }
897}
898
899static int m32r_sio_request_port(struct uart_port *port)
900{
901 struct uart_sio_port *up = (struct uart_sio_port *)port;
902 struct resource *res = NULL;
903 int ret = 0;
904
905 ret = m32r_sio_request_std_resource(up, &res);
906
907 /*
908 * If we have a mapbase, then request that as well.
909 */
910 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
911 int size = res->end - res->start + 1;
912
913 up->port.membase = ioremap(up->port.mapbase, size);
914 if (!up->port.membase)
915 ret = -ENOMEM;
916 }
917
918 if (ret < 0) {
919 if (res)
920 release_resource(res);
921 }
922
923 return ret;
924}
925
926static void m32r_sio_config_port(struct uart_port *port, int flags)
927{
928 struct uart_sio_port *up = (struct uart_sio_port *)port;
929
930 spin_lock_irqsave(&up->port.lock, flags);
931
932 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
933 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
934
935 spin_unlock_irqrestore(&up->port.lock, flags);
936}
937
938static int
939m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
940{
941 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
942 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
943 ser->type >= ARRAY_SIZE(uart_config))
944 return -EINVAL;
945 return 0;
946}
947
948static const char *
949m32r_sio_type(struct uart_port *port)
950{
951 int type = port->type;
952
953 if (type >= ARRAY_SIZE(uart_config))
954 type = 0;
955 return uart_config[type].name;
956}
957
958static struct uart_ops m32r_sio_pops = {
959 .tx_empty = m32r_sio_tx_empty,
960 .set_mctrl = m32r_sio_set_mctrl,
961 .get_mctrl = m32r_sio_get_mctrl,
962 .stop_tx = m32r_sio_stop_tx,
963 .start_tx = m32r_sio_start_tx,
964 .stop_rx = m32r_sio_stop_rx,
965 .enable_ms = m32r_sio_enable_ms,
966 .break_ctl = m32r_sio_break_ctl,
967 .startup = m32r_sio_startup,
968 .shutdown = m32r_sio_shutdown,
969 .set_termios = m32r_sio_set_termios,
970 .pm = m32r_sio_pm,
971 .type = m32r_sio_type,
972 .release_port = m32r_sio_release_port,
973 .request_port = m32r_sio_request_port,
974 .config_port = m32r_sio_config_port,
975 .verify_port = m32r_sio_verify_port,
976};
977
978static struct uart_sio_port m32r_sio_ports[UART_NR];
979
980static void __init m32r_sio_init_ports(void)
981{
982 struct uart_sio_port *up;
983 static int first = 1;
984 int i;
985
986 if (!first)
987 return;
988 first = 0;
989
990 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
991 i++, up++) {
992 up->port.iobase = old_serial_port[i].port;
993 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
994 up->port.uartclk = old_serial_port[i].baud_base * 16;
995 up->port.flags = old_serial_port[i].flags;
996 up->port.membase = old_serial_port[i].iomem_base;
997 up->port.iotype = old_serial_port[i].io_type;
998 up->port.regshift = old_serial_port[i].iomem_reg_shift;
999 up->port.ops = &m32r_sio_pops;
1000 }
1001}
1002
1003static void __init m32r_sio_register_ports(struct uart_driver *drv)
1004{
1005 int i;
1006
1007 m32r_sio_init_ports();
1008
1009 for (i = 0; i < UART_NR; i++) {
1010 struct uart_sio_port *up = &m32r_sio_ports[i];
1011
1012 up->port.line = i;
1013 up->port.ops = &m32r_sio_pops;
1014 init_timer(&up->timer);
1015 up->timer.function = m32r_sio_timeout;
1016
1017 /*
1018 * ALPHA_KLUDGE_MCR needs to be killed.
1019 */
1020 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
1021 up->mcr_force = ALPHA_KLUDGE_MCR;
1022
1023 uart_add_one_port(drv, &up->port);
1024 }
1025}
1026
1027#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1028
1029/*
1030 * Wait for transmitter & holding register to empty
1031 */
1032static inline void wait_for_xmitr(struct uart_sio_port *up)
1033{
1034 unsigned int status, tmout = 10000;
1035
1036 /* Wait up to 10ms for the character(s) to be sent. */
1037 do {
1038 status = sio_in(up, SIOSTS);
1039
1040 if (--tmout == 0)
1041 break;
1042 udelay(1);
1043 } while ((status & UART_EMPTY) != UART_EMPTY);
1044
1045 /* Wait up to 1s for flow control if necessary */
1046 if (up->port.flags & UPF_CONS_FLOW) {
1047 tmout = 1000000;
1048 while (--tmout)
1049 udelay(1);
1050 }
1051}
1052
1053/*
1054 * Print a string to the serial port trying not to disturb
1055 * any possible real use of the port...
1056 *
1057 * The console_lock must be held when we get here.
1058 */
1059static void m32r_sio_console_write(struct console *co, const char *s,
1060 unsigned int count)
1061{
1062 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1063 unsigned int ier;
1064 int i;
1065
1066 /*
1067 * First save the UER then disable the interrupts
1068 */
1069 ier = sio_in(up, SIOTRCR);
1070 sio_out(up, SIOTRCR, 0);
1071
1072 /*
1073 * Now, do each character
1074 */
1075 for (i = 0; i < count; i++, s++) {
1076 wait_for_xmitr(up);
1077
1078 /*
1079 * Send the character out.
1080 * If a LF, also do CR...
1081 */
1082 sio_out(up, SIOTXB, *s);
1083
1084 if (*s == 10) {
1085 wait_for_xmitr(up);
1086 sio_out(up, SIOTXB, 13);
1087 }
1088 }
1089
1090 /*
1091 * Finally, wait for transmitter to become empty
1092 * and restore the IER
1093 */
1094 wait_for_xmitr(up);
1095 sio_out(up, SIOTRCR, ier);
1096}
1097
1098static int __init m32r_sio_console_setup(struct console *co, char *options)
1099{
1100 struct uart_port *port;
1101 int baud = 9600;
1102 int bits = 8;
1103 int parity = 'n';
1104 int flow = 'n';
1105
1106 /*
1107 * Check whether an invalid uart number has been specified, and
1108 * if so, search for the first available port that does have
1109 * console support.
1110 */
1111 if (co->index >= UART_NR)
1112 co->index = 0;
1113 port = &m32r_sio_ports[co->index].port;
1114
1115 /*
1116 * Temporary fix.
1117 */
1118 spin_lock_init(&port->lock);
1119
1120 if (options)
1121 uart_parse_options(options, &baud, &parity, &bits, &flow);
1122
1123 return uart_set_options(port, co, baud, parity, bits, flow);
1124}
1125
1126extern struct uart_driver m32r_sio_reg;
1127static struct console m32r_sio_console = {
1128 .name = "ttyS",
1129 .write = m32r_sio_console_write,
1130 .device = uart_console_device,
1131 .setup = m32r_sio_console_setup,
1132 .flags = CON_PRINTBUFFER,
1133 .index = -1,
1134 .data = &m32r_sio_reg,
1135};
1136
1137static int __init m32r_sio_console_init(void)
1138{
1139 sio_reset();
1140 sio_init();
1141 m32r_sio_init_ports();
1142 register_console(&m32r_sio_console);
1143 return 0;
1144}
1145console_initcall(m32r_sio_console_init);
1146
1147#define M32R_SIO_CONSOLE &m32r_sio_console
1148#else
1149#define M32R_SIO_CONSOLE NULL
1150#endif
1151
1152static struct uart_driver m32r_sio_reg = {
1153 .owner = THIS_MODULE,
1154 .driver_name = "sio",
1155 .devfs_name = "tts/",
1156 .dev_name = "ttyS",
1157 .major = TTY_MAJOR,
1158 .minor = 64,
1159 .nr = UART_NR,
1160 .cons = M32R_SIO_CONSOLE,
1161};
1162
1163/**
1164 * m32r_sio_suspend_port - suspend one serial port
1165 * @line: serial line number
1166 *
1167 * Suspend one serial port.
1168 */
1169void m32r_sio_suspend_port(int line)
1170{
1171 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1172}
1173
1174/**
1175 * m32r_sio_resume_port - resume one serial port
1176 * @line: serial line number
1177 *
1178 * Resume one serial port.
1179 */
1180void m32r_sio_resume_port(int line)
1181{
1182 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1183}
1184
1185static int __init m32r_sio_init(void)
1186{
1187 int ret, i;
1188
1189 printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.11 $ ");
1190
1191 for (i = 0; i < NR_IRQS; i++)
1192 spin_lock_init(&irq_lists[i].lock);
1193
1194 ret = uart_register_driver(&m32r_sio_reg);
1195 if (ret >= 0)
1196 m32r_sio_register_ports(&m32r_sio_reg);
1197
1198 return ret;
1199}
1200
1201static void __exit m32r_sio_exit(void)
1202{
1203 int i;
1204
1205 for (i = 0; i < UART_NR; i++)
1206 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1207
1208 uart_unregister_driver(&m32r_sio_reg);
1209}
1210
1211module_init(m32r_sio_init);
1212module_exit(m32r_sio_exit);
1213
1214EXPORT_SYMBOL(m32r_sio_suspend_port);
1215EXPORT_SYMBOL(m32r_sio_resume_port);
1216
1217MODULE_LICENSE("GPL");
1218MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.11 $");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 19:10:10 -0500