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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/serial/jsm
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/serial/jsm')
-rw-r--r--drivers/serial/jsm/Makefile8
-rw-r--r--drivers/serial/jsm/jsm.h437
-rw-r--r--drivers/serial/jsm/jsm_driver.c404
-rw-r--r--drivers/serial/jsm/jsm_neo.c1427
-rw-r--r--drivers/serial/jsm/jsm_tty.c1038
5 files changed, 3314 insertions, 0 deletions
diff --git a/drivers/serial/jsm/Makefile b/drivers/serial/jsm/Makefile
new file mode 100644
index 000000000000..e46b6e0f8b18
--- /dev/null
+++ b/drivers/serial/jsm/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Jasmine adapter
3#
4
5obj-$(CONFIG_SERIAL_JSM) += jsm.o
6
7jsm-objs := jsm_driver.o jsm_neo.o jsm_tty.o
8
diff --git a/drivers/serial/jsm/jsm.h b/drivers/serial/jsm/jsm.h
new file mode 100644
index 000000000000..b12ee02a0f7c
--- /dev/null
+++ b/drivers/serial/jsm/jsm.h
@@ -0,0 +1,437 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ltcfwd.linux.ibm.com>
24 *
25 ***********************************************************************/
26
27#ifndef __JSM_DRIVER_H
28#define __JSM_DRIVER_H
29
30#include <linux/kernel.h>
31#include <linux/version.h>
32#include <linux/types.h> /* To pick up the varions Linux types */
33#include <linux/tty.h>
34#include <linux/serial_core.h>
35#include <linux/device.h>
36
37/*
38 * Debugging levels can be set using debug insmod variable
39 * They can also be compiled out completely.
40 */
41enum {
42 DBG_INIT = 0x01,
43 DBG_BASIC = 0x02,
44 DBG_CORE = 0x04,
45 DBG_OPEN = 0x08,
46 DBG_CLOSE = 0x10,
47 DBG_READ = 0x20,
48 DBG_WRITE = 0x40,
49 DBG_IOCTL = 0x80,
50 DBG_PROC = 0x100,
51 DBG_PARAM = 0x200,
52 DBG_PSCAN = 0x400,
53 DBG_EVENT = 0x800,
54 DBG_DRAIN = 0x1000,
55 DBG_MSIGS = 0x2000,
56 DBG_MGMT = 0x4000,
57 DBG_INTR = 0x8000,
58 DBG_CARR = 0x10000,
59};
60
61#define jsm_printk(nlevel, klevel, pdev, fmt, args...) \
62 if ((DBG_##nlevel & jsm_debug)) \
63 dev_printk(KERN_##klevel, pdev->dev, fmt, ## args)
64
65#define MAXPORTS 8
66#define MAX_STOPS_SENT 5
67
68/* Board type definitions */
69
70#define T_NEO 0000
71#define T_CLASSIC 0001
72#define T_PCIBUS 0400
73
74/* Board State Definitions */
75
76#define BD_RUNNING 0x0
77#define BD_REASON 0x7f
78#define BD_NOTFOUND 0x1
79#define BD_NOIOPORT 0x2
80#define BD_NOMEM 0x3
81#define BD_NOBIOS 0x4
82#define BD_NOFEP 0x5
83#define BD_FAILED 0x6
84#define BD_ALLOCATED 0x7
85#define BD_TRIBOOT 0x8
86#define BD_BADKME 0x80
87
88
89/* 4 extra for alignment play space */
90#define WRITEBUFLEN ((4096) + 4)
91#define MYFLIPLEN N_TTY_BUF_SIZE
92
93#define JSM_VERSION "jsm: 1.1-1-INKERNEL"
94#define JSM_PARTNUM "40002438_A-INKERNEL"
95
96/*
97 * All the possible states the driver can be while being loaded.
98 */
99enum {
100 DRIVER_INITIALIZED = 0,
101 DRIVER_READY
102};
103
104/*
105 * All the possible states the board can be while booting up.
106 */
107enum {
108 BOARD_FAILED = 0,
109 BOARD_FOUND,
110 BOARD_READY
111};
112
113struct board_id {
114 u8 *name;
115 u32 maxports;
116};
117
118struct jsm_board;
119struct jsm_channel;
120
121/************************************************************************
122 * Per board operations structure *
123 ************************************************************************/
124struct board_ops {
125 irqreturn_t (*intr) (int irq, void *voidbrd, struct pt_regs *regs);
126 void (*uart_init) (struct jsm_channel *ch);
127 void (*uart_off) (struct jsm_channel *ch);
128 void (*param) (struct jsm_channel *ch);
129 void (*assert_modem_signals) (struct jsm_channel *ch);
130 void (*flush_uart_write) (struct jsm_channel *ch);
131 void (*flush_uart_read) (struct jsm_channel *ch);
132 void (*disable_receiver) (struct jsm_channel *ch);
133 void (*enable_receiver) (struct jsm_channel *ch);
134 void (*send_break) (struct jsm_channel *ch);
135 void (*clear_break) (struct jsm_channel *ch, int);
136 void (*send_start_character) (struct jsm_channel *ch);
137 void (*send_stop_character) (struct jsm_channel *ch);
138 void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch);
139 u32 (*get_uart_bytes_left) (struct jsm_channel *ch);
140 void (*send_immediate_char) (struct jsm_channel *ch, unsigned char);
141};
142
143
144/*
145 * Per-board information
146 */
147struct jsm_board
148{
149 int boardnum; /* Board number: 0-32 */
150
151 int type; /* Type of board */
152 char *name; /* Product Name */
153 u8 rev; /* PCI revision ID */
154 struct pci_dev *pci_dev;
155 u32 maxports; /* MAX ports this board can handle */
156
157 spinlock_t bd_lock; /* Used to protect board */
158
159 spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and
160 * the interrupt routine from each other.
161 */
162
163 u32 state; /* State of card. */
164 wait_queue_head_t state_wait; /* Place to sleep on for state change */
165
166 u32 nasync; /* Number of ports on card */
167
168 u32 irq; /* Interrupt request number */
169 u64 intr_count; /* Count of interrupts */
170
171 u64 membase; /* Start of base memory of the card */
172 u64 membase_end; /* End of base memory of the card */
173
174 u8 __iomem *re_map_membase;/* Remapped memory of the card */
175
176 u64 iobase; /* Start of io base of the card */
177 u64 iobase_end; /* End of io base of the card */
178
179 u32 bd_uart_offset; /* Space between each UART */
180
181 struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
182 char *flipbuf; /* Our flip buffer, alloced if board is found */
183
184 u16 dpatype; /* The board "type", as defined by DPA */
185 u16 dpastatus; /* The board "status", as defined by DPA */
186
187 u32 bd_dividend; /* Board/UARTs specific dividend */
188
189 struct board_ops *bd_ops;
190
191 struct list_head jsm_board_entry;
192};
193
194/************************************************************************
195 * Device flag definitions for ch_flags.
196 ************************************************************************/
197#define CH_PRON 0x0001 /* Printer on string */
198#define CH_STOP 0x0002 /* Output is stopped */
199#define CH_STOPI 0x0004 /* Input is stopped */
200#define CH_CD 0x0008 /* Carrier is present */
201#define CH_FCAR 0x0010 /* Carrier forced on */
202#define CH_HANGUP 0x0020 /* Hangup received */
203
204#define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
205#define CH_OPENING 0x0080 /* Port in fragile open state */
206#define CH_CLOSING 0x0100 /* Port in fragile close state */
207#define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
208#define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
209#define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
210#define CH_BREAK_SENDING 0x1000 /* Break is being sent */
211#define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
212#define CH_FLIPBUF_IN_USE 0x4000 /* Channel's flipbuf is in use */
213#define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
214
215/* Our Read/Error/Write queue sizes */
216#define RQUEUEMASK 0x1FFF /* 8 K - 1 */
217#define EQUEUEMASK 0x1FFF /* 8 K - 1 */
218#define WQUEUEMASK 0x0FFF /* 4 K - 1 */
219#define RQUEUESIZE (RQUEUEMASK + 1)
220#define EQUEUESIZE RQUEUESIZE
221#define WQUEUESIZE (WQUEUEMASK + 1)
222
223
224/************************************************************************
225 * Channel information structure.
226 ************************************************************************/
227struct jsm_channel {
228 struct uart_port uart_port;
229 struct jsm_board *ch_bd; /* Board structure pointer */
230
231 spinlock_t ch_lock; /* provide for serialization */
232 wait_queue_head_t ch_flags_wait;
233
234 u32 ch_portnum; /* Port number, 0 offset. */
235 u32 ch_open_count; /* open count */
236 u32 ch_flags; /* Channel flags */
237
238 u64 ch_close_delay; /* How long we should drop RTS/DTR for */
239
240 u64 ch_cpstime; /* Time for CPS calculations */
241
242 tcflag_t ch_c_iflag; /* channel iflags */
243 tcflag_t ch_c_cflag; /* channel cflags */
244 tcflag_t ch_c_oflag; /* channel oflags */
245 tcflag_t ch_c_lflag; /* channel lflags */
246 u8 ch_stopc; /* Stop character */
247 u8 ch_startc; /* Start character */
248
249 u32 ch_old_baud; /* Cache of the current baud */
250 u32 ch_custom_speed;/* Custom baud, if set */
251
252 u32 ch_wopen; /* Waiting for open process cnt */
253
254 u8 ch_mostat; /* FEP output modem status */
255 u8 ch_mistat; /* FEP input modem status */
256
257 struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */
258 u8 ch_cached_lsr; /* Cached value of the LSR register */
259
260 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
261 u16 ch_r_head; /* Head location of the read queue */
262 u16 ch_r_tail; /* Tail location of the read queue */
263
264 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
265 u16 ch_e_head; /* Head location of the error queue */
266 u16 ch_e_tail; /* Tail location of the error queue */
267
268 u8 *ch_wqueue; /* Our write queue buffer - malloc'ed */
269 u16 ch_w_head; /* Head location of the write queue */
270 u16 ch_w_tail; /* Tail location of the write queue */
271
272 u64 ch_rxcount; /* total of data received so far */
273 u64 ch_txcount; /* total of data transmitted so far */
274
275 u8 ch_r_tlevel; /* Receive Trigger level */
276 u8 ch_t_tlevel; /* Transmit Trigger level */
277
278 u8 ch_r_watermark; /* Receive Watermark */
279
280
281 u32 ch_stops_sent; /* How many times I have sent a stop character
282 * to try to stop the other guy sending.
283 */
284 u64 ch_err_parity; /* Count of parity errors on channel */
285 u64 ch_err_frame; /* Count of framing errors on channel */
286 u64 ch_err_break; /* Count of breaks on channel */
287 u64 ch_err_overrun; /* Count of overruns on channel */
288
289 u64 ch_xon_sends; /* Count of xons transmitted */
290 u64 ch_xoff_sends; /* Count of xoffs transmitted */
291};
292
293
294/************************************************************************
295 * Per channel/port NEO UART structure *
296 ************************************************************************
297 * Base Structure Entries Usage Meanings to Host *
298 * *
299 * W = read write R = read only *
300 * U = Unused. *
301 ************************************************************************/
302
303struct neo_uart_struct {
304 u8 txrx; /* WR RHR/THR - Holding Reg */
305 u8 ier; /* WR IER - Interrupt Enable Reg */
306 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
307 u8 lcr; /* WR LCR - Line Control Reg */
308 u8 mcr; /* WR MCR - Modem Control Reg */
309 u8 lsr; /* WR LSR - Line Status Reg */
310 u8 msr; /* WR MSR - Modem Status Reg */
311 u8 spr; /* WR SPR - Scratch Pad Reg */
312 u8 fctr; /* WR FCTR - Feature Control Reg */
313 u8 efr; /* WR EFR - Enhanced Function Reg */
314 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
315 u8 rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */
316 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
317 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
318 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
319 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
320
321 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
322 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
323 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
324 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
325};
326
327/* Where to read the extended interrupt register (32bits instead of 8bits) */
328#define UART_17158_POLL_ADDR_OFFSET 0x80
329
330/*
331 * These are the redefinitions for the FCTR on the XR17C158, since
332 * Exar made them different than their earlier design. (XR16C854)
333 */
334
335/* These are only applicable when table D is selected */
336#define UART_17158_FCTR_RTS_NODELAY 0x00
337#define UART_17158_FCTR_RTS_4DELAY 0x01
338#define UART_17158_FCTR_RTS_6DELAY 0x02
339#define UART_17158_FCTR_RTS_8DELAY 0x03
340#define UART_17158_FCTR_RTS_12DELAY 0x12
341#define UART_17158_FCTR_RTS_16DELAY 0x05
342#define UART_17158_FCTR_RTS_20DELAY 0x13
343#define UART_17158_FCTR_RTS_24DELAY 0x06
344#define UART_17158_FCTR_RTS_28DELAY 0x14
345#define UART_17158_FCTR_RTS_32DELAY 0x07
346#define UART_17158_FCTR_RTS_36DELAY 0x16
347#define UART_17158_FCTR_RTS_40DELAY 0x08
348#define UART_17158_FCTR_RTS_44DELAY 0x09
349#define UART_17158_FCTR_RTS_48DELAY 0x10
350#define UART_17158_FCTR_RTS_52DELAY 0x11
351
352#define UART_17158_FCTR_RTS_IRDA 0x10
353#define UART_17158_FCTR_RS485 0x20
354#define UART_17158_FCTR_TRGA 0x00
355#define UART_17158_FCTR_TRGB 0x40
356#define UART_17158_FCTR_TRGC 0x80
357#define UART_17158_FCTR_TRGD 0xC0
358
359/* 17158 trigger table selects.. */
360#define UART_17158_FCTR_BIT6 0x40
361#define UART_17158_FCTR_BIT7 0x80
362
363/* 17158 TX/RX memmapped buffer offsets */
364#define UART_17158_RX_FIFOSIZE 64
365#define UART_17158_TX_FIFOSIZE 64
366
367/* 17158 Extended IIR's */
368#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
369#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
370#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
371#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
372
373/*
374 * These are the extended interrupts that get sent
375 * back to us from the UART's 32bit interrupt register
376 */
377#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
378#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
379#define UART_17158_TXRDY 0x3 /* TX Ready */
380#define UART_17158_MSR 0x4 /* Modem State Change */
381#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
382#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
383
384/*
385 * These are the EXTENDED definitions for the 17C158's Interrupt
386 * Enable Register.
387 */
388#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
389#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
390#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
391#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
392#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
393
394#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
395#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
396
397#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
398#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
399#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
400#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
401
402#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
403#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
404#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
405#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
406
407/*
408 * Our Global Variables.
409 */
410extern struct uart_driver jsm_uart_driver;
411extern struct board_ops jsm_neo_ops;
412extern int jsm_debug;
413extern int jsm_rawreadok;
414
415extern int jsm_driver_state; /* The state of the driver */
416extern char *jsm_driver_state_text[];/* Array of driver state text */
417
418extern spinlock_t jsm_board_head_lock;
419extern struct list_head jsm_board_head;
420
421/*************************************************************************
422 *
423 * Prototypes for non-static functions used in more than one module
424 *
425 *************************************************************************/
426int jsm_tty_write(struct uart_port *port);
427int jsm_tty_init(struct jsm_board *);
428int jsm_uart_port_init(struct jsm_board *);
429int jsm_remove_uart_port(struct jsm_board *);
430void jsm_input(struct jsm_channel *ch);
431void jsm_carrier(struct jsm_channel *ch);
432void jsm_check_queue_flow_control(struct jsm_channel *ch);
433
434void jsm_create_driver_sysfiles(struct device_driver *);
435void jsm_remove_driver_sysfiles(struct device_driver *);
436
437#endif
diff --git a/drivers/serial/jsm/jsm_driver.c b/drivers/serial/jsm/jsm_driver.c
new file mode 100644
index 000000000000..d4847d4f1473
--- /dev/null
+++ b/drivers/serial/jsm/jsm_driver.c
@@ -0,0 +1,404 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ltcfwd.linux.ibm.com>
24 *
25 ***********************************************************************/
26#include <linux/moduleparam.h>
27#include <linux/pci.h>
28
29#include "jsm.h"
30
31MODULE_AUTHOR("Digi International, http://www.digi.com");
32MODULE_DESCRIPTION("Driver for the Digi International Neo PCI based product line");
33MODULE_SUPPORTED_DEVICE("jsm");
34
35#define JSM_DRIVER_NAME "jsm"
36#define NR_PORTS 32
37#define JSM_MINOR_START 0
38
39struct uart_driver jsm_uart_driver = {
40 .owner = THIS_MODULE,
41 .driver_name = JSM_DRIVER_NAME,
42 .dev_name = "ttyn",
43 .major = 253,
44 .minor = JSM_MINOR_START,
45 .nr = NR_PORTS,
46 .cons = NULL,
47};
48
49int jsm_debug;
50int jsm_rawreadok;
51module_param(jsm_debug, int, 0);
52module_param(jsm_rawreadok, int, 0);
53MODULE_PARM_DESC(jsm_debug, "Driver debugging level");
54MODULE_PARM_DESC(jsm_rawreadok, "Bypass flip buffers on input");
55
56/*
57 * Globals
58 */
59int jsm_driver_state = DRIVER_INITIALIZED;
60spinlock_t jsm_board_head_lock = SPIN_LOCK_UNLOCKED;
61LIST_HEAD(jsm_board_head);
62
63static struct pci_device_id jsm_pci_tbl[] = {
64 { PCI_DEVICE (PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9), 0, 0, 0 },
65 { PCI_DEVICE (PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9PRI), 0, 0, 1 },
66 { PCI_DEVICE (PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45), 0, 0, 2 },
67 { PCI_DEVICE (PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45PRI), 0, 0, 3 },
68 { 0,} /* 0 terminated list. */
69};
70MODULE_DEVICE_TABLE(pci, jsm_pci_tbl);
71
72static struct board_id jsm_Ids[] = {
73 { PCI_DEVICE_NEO_2DB9_PCI_NAME, 2 },
74 { PCI_DEVICE_NEO_2DB9PRI_PCI_NAME, 2 },
75 { PCI_DEVICE_NEO_2RJ45_PCI_NAME, 2 },
76 { PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME, 2 },
77 { NULL, 0 }
78};
79
80char *jsm_driver_state_text[] = {
81 "Driver Initialized",
82 "Driver Ready."
83};
84
85static int jsm_finalize_board_init(struct jsm_board *brd)
86{
87 int rc = 0;
88
89 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
90
91 if (brd->irq) {
92 rc = request_irq(brd->irq, brd->bd_ops->intr, SA_INTERRUPT|SA_SHIRQ, "JSM", brd);
93
94 if (rc) {
95 printk(KERN_WARNING "Failed to hook IRQ %d\n",brd->irq);
96 brd->state = BOARD_FAILED;
97 brd->dpastatus = BD_NOFEP;
98 rc = -ENODEV;
99 } else
100 jsm_printk(INIT, INFO, &brd->pci_dev,
101 "Requested and received usage of IRQ %d\n", brd->irq);
102 }
103 return rc;
104}
105
106/*
107 * jsm_found_board()
108 *
109 * A board has been found, init it.
110 */
111static int jsm_found_board(struct pci_dev *pdev, int id)
112{
113 struct jsm_board *brd;
114 int i = 0;
115 int rc = 0;
116 struct list_head *tmp;
117 struct jsm_board *cur_board_entry;
118 unsigned long lock_flags;
119 int adapter_count = 0;
120 int retval;
121
122 brd = kmalloc(sizeof(struct jsm_board), GFP_KERNEL);
123 if (!brd) {
124 dev_err(&pdev->dev, "memory allocation for board structure failed\n");
125 return -ENOMEM;
126 }
127 memset(brd, 0, sizeof(struct jsm_board));
128
129 spin_lock_irqsave(&jsm_board_head_lock, lock_flags);
130 list_for_each(tmp, &jsm_board_head) {
131 cur_board_entry =
132 list_entry(tmp, struct jsm_board,
133 jsm_board_entry);
134 if (cur_board_entry->boardnum != adapter_count) {
135 break;
136 }
137 adapter_count++;
138 }
139
140 list_add_tail(&brd->jsm_board_entry, &jsm_board_head);
141 spin_unlock_irqrestore(&jsm_board_head_lock, lock_flags);
142
143 /* store the info for the board we've found */
144 brd->boardnum = adapter_count;
145 brd->pci_dev = pdev;
146 brd->name = jsm_Ids[id].name;
147 brd->maxports = jsm_Ids[id].maxports;
148 brd->dpastatus = BD_NOFEP;
149 init_waitqueue_head(&brd->state_wait);
150
151 spin_lock_init(&brd->bd_lock);
152 spin_lock_init(&brd->bd_intr_lock);
153
154 brd->state = BOARD_FOUND;
155
156 for (i = 0; i < brd->maxports; i++)
157 brd->channels[i] = NULL;
158
159 /* store which revision we have */
160 pci_read_config_byte(pdev, PCI_REVISION_ID, &brd->rev);
161
162 brd->irq = pdev->irq;
163
164 switch(brd->pci_dev->device) {
165
166 case PCI_DEVICE_ID_NEO_2DB9:
167 case PCI_DEVICE_ID_NEO_2DB9PRI:
168 case PCI_DEVICE_ID_NEO_2RJ45:
169 case PCI_DEVICE_ID_NEO_2RJ45PRI:
170
171 /*
172 * This chip is set up 100% when we get to it.
173 * No need to enable global interrupts or anything.
174 */
175 brd->dpatype = T_NEO | T_PCIBUS;
176
177 jsm_printk(INIT, INFO, &brd->pci_dev,
178 "jsm_found_board - NEO adapter\n");
179
180 /* get the PCI Base Address Registers */
181 brd->membase = pci_resource_start(pdev, 0);
182 brd->membase_end = pci_resource_end(pdev, 0);
183
184 if (brd->membase & 1)
185 brd->membase &= ~3;
186 else
187 brd->membase &= ~15;
188
189 /* Assign the board_ops struct */
190 brd->bd_ops = &jsm_neo_ops;
191
192 brd->bd_uart_offset = 0x200;
193 brd->bd_dividend = 921600;
194
195 brd->re_map_membase = ioremap(brd->membase, 0x1000);
196 jsm_printk(INIT, INFO, &brd->pci_dev,
197 "remapped mem: 0x%p\n", brd->re_map_membase);
198 if (!brd->re_map_membase) {
199 kfree(brd);
200 dev_err(&pdev->dev, "card has no PCI Memory resources, failing board.\n");
201 return -ENOMEM;
202 }
203 break;
204
205 default:
206 dev_err(&pdev->dev, "Did not find any compatible Neo or Classic PCI boards in system.\n");
207 kfree(brd);
208 return -ENXIO;
209 }
210
211 /*
212 * Do tty device initialization.
213 */
214 rc = jsm_finalize_board_init(brd);
215 if (rc < 0) {
216 dev_err(&pdev->dev, "Can't finalize board init (%d)\n", rc);
217 brd->state = BOARD_FAILED;
218 retval = -ENXIO;
219 goto failed0;
220 }
221
222 rc = jsm_tty_init(brd);
223 if (rc < 0) {
224 dev_err(&pdev->dev, "Can't init tty devices (%d)\n", rc);
225 brd->state = BOARD_FAILED;
226 retval = -ENXIO;
227 goto failed1;
228 }
229
230 rc = jsm_uart_port_init(brd);
231 if (rc < 0) {
232 dev_err(&pdev->dev, "Can't init uart port (%d)\n", rc);
233 brd->state = BOARD_FAILED;
234 retval = -ENXIO;
235 goto failed1;
236 }
237
238 brd->state = BOARD_READY;
239 brd->dpastatus = BD_RUNNING;
240
241 /* Log the information about the board */
242 dev_info(&pdev->dev, "board %d: %s (rev %d), irq %d\n",adapter_count, brd->name, brd->rev, brd->irq);
243
244 /*
245 * allocate flip buffer for board.
246 *
247 * Okay to malloc with GFP_KERNEL, we are not at interrupt
248 * context, and there are no locks held.
249 */
250 brd->flipbuf = kmalloc(MYFLIPLEN, GFP_KERNEL);
251 if (!brd->flipbuf) {
252 dev_err(&pdev->dev, "memory allocation for flipbuf failed\n");
253 brd->state = BOARD_FAILED;
254 retval = -ENOMEM;
255 goto failed1;
256 }
257 memset(brd->flipbuf, 0, MYFLIPLEN);
258
259 jsm_create_driver_sysfiles(pdev->dev.driver);
260
261 wake_up_interruptible(&brd->state_wait);
262 return 0;
263failed1:
264 free_irq(brd->irq, brd);
265failed0:
266 kfree(brd);
267 iounmap(brd->re_map_membase);
268 return retval;
269}
270
271/* returns count (>= 0), or negative on error */
272static int jsm_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
273{
274 int rc;
275
276 rc = pci_enable_device(pdev);
277 if (rc) {
278 dev_err(&pdev->dev, "Device enable FAILED\n");
279 return rc;
280 }
281
282 if ((rc = pci_request_regions(pdev, "jsm"))) {
283 dev_err(&pdev->dev, "pci_request_region FAILED\n");
284 pci_disable_device(pdev);
285 return rc;
286 }
287
288 if ((rc = jsm_found_board(pdev, ent->driver_data))) {
289 dev_err(&pdev->dev, "jsm_found_board FAILED\n");
290 pci_release_regions(pdev);
291 pci_disable_device(pdev);
292 return rc;
293 }
294 return rc;
295}
296
297
298/*
299 * jsm_cleanup_board()
300 *
301 * Free all the memory associated with a board
302 */
303static void jsm_cleanup_board(struct jsm_board *brd)
304{
305 int i = 0;
306
307 free_irq(brd->irq, brd);
308 iounmap(brd->re_map_membase);
309
310 /* Free all allocated channels structs */
311 for (i = 0; i < brd->maxports; i++) {
312 if (brd->channels[i]) {
313 if (brd->channels[i]->ch_rqueue)
314 kfree(brd->channels[i]->ch_rqueue);
315 if (brd->channels[i]->ch_equeue)
316 kfree(brd->channels[i]->ch_equeue);
317 if (brd->channels[i]->ch_wqueue)
318 kfree(brd->channels[i]->ch_wqueue);
319 kfree(brd->channels[i]);
320 }
321 }
322
323 pci_release_regions(brd->pci_dev);
324 pci_disable_device(brd->pci_dev);
325 kfree(brd->flipbuf);
326 kfree(brd);
327}
328
329static void jsm_remove_one(struct pci_dev *dev)
330{
331 unsigned long lock_flags;
332 struct list_head *tmp;
333 struct jsm_board *brd;
334
335 spin_lock_irqsave(&jsm_board_head_lock, lock_flags);
336 list_for_each(tmp, &jsm_board_head) {
337 brd = list_entry(tmp, struct jsm_board,
338 jsm_board_entry);
339 if ( brd != NULL && brd->pci_dev == dev) {
340 jsm_remove_uart_port(brd);
341 jsm_cleanup_board(brd);
342 list_del(&brd->jsm_board_entry);
343 break;
344 }
345 }
346 spin_unlock_irqrestore(&jsm_board_head_lock, lock_flags);
347 return;
348}
349
350struct pci_driver jsm_driver = {
351 .name = "jsm",
352 .probe = jsm_init_one,
353 .id_table = jsm_pci_tbl,
354 .remove = __devexit_p(jsm_remove_one),
355};
356
357/*
358 * jsm_init_module()
359 *
360 * Module load. This is where it all starts.
361 */
362static int __init jsm_init_module(void)
363{
364 int rc = 0;
365
366 printk(KERN_INFO "%s, Digi International Part Number %s\n",
367 JSM_VERSION, JSM_VERSION);
368
369 /*
370 * Initialize global stuff
371 */
372
373 rc = uart_register_driver(&jsm_uart_driver);
374 if (rc < 0) {
375 return rc;
376 }
377
378 rc = pci_register_driver(&jsm_driver);
379 if (rc < 0) {
380 uart_unregister_driver(&jsm_uart_driver);
381 return rc;
382 }
383 jsm_driver_state = DRIVER_READY;
384
385 return rc;
386}
387
388module_init(jsm_init_module);
389
390/*
391 * jsm_exit_module()
392 *
393 * Module unload. This is where it all ends.
394 */
395static void __exit jsm_exit_module(void)
396{
397 jsm_remove_driver_sysfiles(&jsm_driver.driver);
398
399 pci_unregister_driver(&jsm_driver);
400
401 uart_unregister_driver(&jsm_uart_driver);
402}
403module_exit(jsm_exit_module);
404MODULE_LICENSE("GPL");
diff --git a/drivers/serial/jsm/jsm_neo.c b/drivers/serial/jsm/jsm_neo.c
new file mode 100644
index 000000000000..9b79c1ff6c72
--- /dev/null
+++ b/drivers/serial/jsm/jsm_neo.c
@@ -0,0 +1,1427 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ltcfwd.linux.ibm.com>
24 *
25 ***********************************************************************/
26#include <linux/delay.h> /* For udelay */
27#include <linux/serial_reg.h> /* For the various UART offsets */
28#include <linux/tty.h>
29#include <linux/pci.h>
30#include <asm/io.h>
31
32#include "jsm.h" /* Driver main header file */
33
34static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
35
36/*
37 * This function allows calls to ensure that all outstanding
38 * PCI writes have been completed, by doing a PCI read against
39 * a non-destructive, read-only location on the Neo card.
40 *
41 * In this case, we are reading the DVID (Read-only Device Identification)
42 * value of the Neo card.
43 */
44static inline void neo_pci_posting_flush(struct jsm_board *bd)
45{
46 readb(bd->re_map_membase + 0x8D);
47}
48
49static void neo_set_cts_flow_control(struct jsm_channel *ch)
50{
51 u8 ier = readb(&ch->ch_neo_uart->ier);
52 u8 efr = readb(&ch->ch_neo_uart->efr);
53
54 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
55
56 /* Turn on auto CTS flow control */
57 ier |= (UART_17158_IER_CTSDSR);
58 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
59
60 /* Turn off auto Xon flow control */
61 efr &= ~(UART_17158_EFR_IXON);
62
63 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
64 writeb(0, &ch->ch_neo_uart->efr);
65
66 /* Turn on UART enhanced bits */
67 writeb(efr, &ch->ch_neo_uart->efr);
68
69 /* Turn on table D, with 8 char hi/low watermarks */
70 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
71
72 /* Feed the UART our trigger levels */
73 writeb(8, &ch->ch_neo_uart->tfifo);
74 ch->ch_t_tlevel = 8;
75
76 writeb(ier, &ch->ch_neo_uart->ier);
77}
78
79static void neo_set_rts_flow_control(struct jsm_channel *ch)
80{
81 u8 ier = readb(&ch->ch_neo_uart->ier);
82 u8 efr = readb(&ch->ch_neo_uart->efr);
83
84 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
85
86 /* Turn on auto RTS flow control */
87 ier |= (UART_17158_IER_RTSDTR);
88 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
89
90 /* Turn off auto Xoff flow control */
91 ier &= ~(UART_17158_IER_XOFF);
92 efr &= ~(UART_17158_EFR_IXOFF);
93
94 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
95 writeb(0, &ch->ch_neo_uart->efr);
96
97 /* Turn on UART enhanced bits */
98 writeb(efr, &ch->ch_neo_uart->efr);
99
100 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
101 ch->ch_r_watermark = 4;
102
103 writeb(56, &ch->ch_neo_uart->rfifo);
104 ch->ch_r_tlevel = 56;
105
106 writeb(ier, &ch->ch_neo_uart->ier);
107
108 /*
109 * From the Neo UART spec sheet:
110 * The auto RTS/DTR function must be started by asserting
111 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
112 * it is enabled.
113 */
114 ch->ch_mostat |= (UART_MCR_RTS);
115}
116
117
118static void neo_set_ixon_flow_control(struct jsm_channel *ch)
119{
120 u8 ier = readb(&ch->ch_neo_uart->ier);
121 u8 efr = readb(&ch->ch_neo_uart->efr);
122
123 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
124
125 /* Turn off auto CTS flow control */
126 ier &= ~(UART_17158_IER_CTSDSR);
127 efr &= ~(UART_17158_EFR_CTSDSR);
128
129 /* Turn on auto Xon flow control */
130 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
131
132 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
133 writeb(0, &ch->ch_neo_uart->efr);
134
135 /* Turn on UART enhanced bits */
136 writeb(efr, &ch->ch_neo_uart->efr);
137
138 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
139 ch->ch_r_watermark = 4;
140
141 writeb(32, &ch->ch_neo_uart->rfifo);
142 ch->ch_r_tlevel = 32;
143
144 /* Tell UART what start/stop chars it should be looking for */
145 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
146 writeb(0, &ch->ch_neo_uart->xonchar2);
147
148 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
149 writeb(0, &ch->ch_neo_uart->xoffchar2);
150
151 writeb(ier, &ch->ch_neo_uart->ier);
152}
153
154static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
155{
156 u8 ier = readb(&ch->ch_neo_uart->ier);
157 u8 efr = readb(&ch->ch_neo_uart->efr);
158
159 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
160
161 /* Turn off auto RTS flow control */
162 ier &= ~(UART_17158_IER_RTSDTR);
163 efr &= ~(UART_17158_EFR_RTSDTR);
164
165 /* Turn on auto Xoff flow control */
166 ier |= (UART_17158_IER_XOFF);
167 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
168
169 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
170 writeb(0, &ch->ch_neo_uart->efr);
171
172 /* Turn on UART enhanced bits */
173 writeb(efr, &ch->ch_neo_uart->efr);
174
175 /* Turn on table D, with 8 char hi/low watermarks */
176 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
177
178 writeb(8, &ch->ch_neo_uart->tfifo);
179 ch->ch_t_tlevel = 8;
180
181 /* Tell UART what start/stop chars it should be looking for */
182 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
183 writeb(0, &ch->ch_neo_uart->xonchar2);
184
185 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
186 writeb(0, &ch->ch_neo_uart->xoffchar2);
187
188 writeb(ier, &ch->ch_neo_uart->ier);
189}
190
191static void neo_set_no_input_flow_control(struct jsm_channel *ch)
192{
193 u8 ier = readb(&ch->ch_neo_uart->ier);
194 u8 efr = readb(&ch->ch_neo_uart->efr);
195
196 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
197
198 /* Turn off auto RTS flow control */
199 ier &= ~(UART_17158_IER_RTSDTR);
200 efr &= ~(UART_17158_EFR_RTSDTR);
201
202 /* Turn off auto Xoff flow control */
203 ier &= ~(UART_17158_IER_XOFF);
204 if (ch->ch_c_iflag & IXON)
205 efr &= ~(UART_17158_EFR_IXOFF);
206 else
207 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
208
209 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
210 writeb(0, &ch->ch_neo_uart->efr);
211
212 /* Turn on UART enhanced bits */
213 writeb(efr, &ch->ch_neo_uart->efr);
214
215 /* Turn on table D, with 8 char hi/low watermarks */
216 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
217
218 ch->ch_r_watermark = 0;
219
220 writeb(16, &ch->ch_neo_uart->tfifo);
221 ch->ch_t_tlevel = 16;
222
223 writeb(16, &ch->ch_neo_uart->rfifo);
224 ch->ch_r_tlevel = 16;
225
226 writeb(ier, &ch->ch_neo_uart->ier);
227}
228
229static void neo_set_no_output_flow_control(struct jsm_channel *ch)
230{
231 u8 ier = readb(&ch->ch_neo_uart->ier);
232 u8 efr = readb(&ch->ch_neo_uart->efr);
233
234 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
235
236 /* Turn off auto CTS flow control */
237 ier &= ~(UART_17158_IER_CTSDSR);
238 efr &= ~(UART_17158_EFR_CTSDSR);
239
240 /* Turn off auto Xon flow control */
241 if (ch->ch_c_iflag & IXOFF)
242 efr &= ~(UART_17158_EFR_IXON);
243 else
244 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
245
246 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
247 writeb(0, &ch->ch_neo_uart->efr);
248
249 /* Turn on UART enhanced bits */
250 writeb(efr, &ch->ch_neo_uart->efr);
251
252 /* Turn on table D, with 8 char hi/low watermarks */
253 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
254
255 ch->ch_r_watermark = 0;
256
257 writeb(16, &ch->ch_neo_uart->tfifo);
258 ch->ch_t_tlevel = 16;
259
260 writeb(16, &ch->ch_neo_uart->rfifo);
261 ch->ch_r_tlevel = 16;
262
263 writeb(ier, &ch->ch_neo_uart->ier);
264}
265
266static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
267{
268
269 /* if hardware flow control is set, then skip this whole thing */
270 if (ch->ch_c_cflag & CRTSCTS)
271 return;
272
273 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
274
275 /* Tell UART what start/stop chars it should be looking for */
276 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
277 writeb(0, &ch->ch_neo_uart->xonchar2);
278
279 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
280 writeb(0, &ch->ch_neo_uart->xoffchar2);
281}
282
283static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
284{
285 int qleft = 0;
286 u8 linestatus = 0;
287 u8 error_mask = 0;
288 int n = 0;
289 int total = 0;
290 u16 head;
291 u16 tail;
292
293 if (!ch)
294 return;
295
296 /* cache head and tail of queue */
297 head = ch->ch_r_head & RQUEUEMASK;
298 tail = ch->ch_r_tail & RQUEUEMASK;
299
300 /* Get our cached LSR */
301 linestatus = ch->ch_cached_lsr;
302 ch->ch_cached_lsr = 0;
303
304 /* Store how much space we have left in the queue */
305 if ((qleft = tail - head - 1) < 0)
306 qleft += RQUEUEMASK + 1;
307
308 /*
309 * If the UART is not in FIFO mode, force the FIFO copy to
310 * NOT be run, by setting total to 0.
311 *
312 * On the other hand, if the UART IS in FIFO mode, then ask
313 * the UART to give us an approximation of data it has RX'ed.
314 */
315 if (!(ch->ch_flags & CH_FIFO_ENABLED))
316 total = 0;
317 else {
318 total = readb(&ch->ch_neo_uart->rfifo);
319
320 /*
321 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
322 *
323 * This resolves a problem/bug with the Exar chip that sometimes
324 * returns a bogus value in the rfifo register.
325 * The count can be any where from 0-3 bytes "off".
326 * Bizarre, but true.
327 */
328 total -= 3;
329 }
330
331 /*
332 * Finally, bound the copy to make sure we don't overflow
333 * our own queue...
334 * The byte by byte copy loop below this loop this will
335 * deal with the queue overflow possibility.
336 */
337 total = min(total, qleft);
338
339 while (total > 0) {
340 /*
341 * Grab the linestatus register, we need to check
342 * to see if there are any errors in the FIFO.
343 */
344 linestatus = readb(&ch->ch_neo_uart->lsr);
345
346 /*
347 * Break out if there is a FIFO error somewhere.
348 * This will allow us to go byte by byte down below,
349 * finding the exact location of the error.
350 */
351 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
352 break;
353
354 /* Make sure we don't go over the end of our queue */
355 n = min(((u32) total), (RQUEUESIZE - (u32) head));
356
357 /*
358 * Cut down n even further if needed, this is to fix
359 * a problem with memcpy_fromio() with the Neo on the
360 * IBM pSeries platform.
361 * 15 bytes max appears to be the magic number.
362 */
363 n = min((u32) n, (u32) 12);
364
365 /*
366 * Since we are grabbing the linestatus register, which
367 * will reset some bits after our read, we need to ensure
368 * we don't miss our TX FIFO emptys.
369 */
370 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
371 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
372
373 linestatus = 0;
374
375 /* Copy data from uart to the queue */
376 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
377 /*
378 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
379 * that all the data currently in the FIFO is free of
380 * breaks and parity/frame/orun errors.
381 */
382 memset(ch->ch_equeue + head, 0, n);
383
384 /* Add to and flip head if needed */
385 head = (head + n) & RQUEUEMASK;
386 total -= n;
387 qleft -= n;
388 ch->ch_rxcount += n;
389 }
390
391 /*
392 * Create a mask to determine whether we should
393 * insert the character (if any) into our queue.
394 */
395 if (ch->ch_c_iflag & IGNBRK)
396 error_mask |= UART_LSR_BI;
397
398 /*
399 * Now cleanup any leftover bytes still in the UART.
400 * Also deal with any possible queue overflow here as well.
401 */
402 while (1) {
403
404 /*
405 * Its possible we have a linestatus from the loop above
406 * this, so we "OR" on any extra bits.
407 */
408 linestatus |= readb(&ch->ch_neo_uart->lsr);
409
410 /*
411 * If the chip tells us there is no more data pending to
412 * be read, we can then leave.
413 * But before we do, cache the linestatus, just in case.
414 */
415 if (!(linestatus & UART_LSR_DR)) {
416 ch->ch_cached_lsr = linestatus;
417 break;
418 }
419
420 /* No need to store this bit */
421 linestatus &= ~UART_LSR_DR;
422
423 /*
424 * Since we are grabbing the linestatus register, which
425 * will reset some bits after our read, we need to ensure
426 * we don't miss our TX FIFO emptys.
427 */
428 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
429 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
430 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
431 }
432
433 /*
434 * Discard character if we are ignoring the error mask.
435 */
436 if (linestatus & error_mask) {
437 u8 discard;
438 linestatus = 0;
439 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
440 continue;
441 }
442
443 /*
444 * If our queue is full, we have no choice but to drop some data.
445 * The assumption is that HWFLOW or SWFLOW should have stopped
446 * things way way before we got to this point.
447 *
448 * I decided that I wanted to ditch the oldest data first,
449 * I hope thats okay with everyone? Yes? Good.
450 */
451 while (qleft < 1) {
452 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
453 "Queue full, dropping DATA:%x LSR:%x\n",
454 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
455
456 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
457 ch->ch_err_overrun++;
458 qleft++;
459 }
460
461 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
462 ch->ch_equeue[head] = (u8) linestatus;
463
464 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
465 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
466
467 /* Ditch any remaining linestatus value. */
468 linestatus = 0;
469
470 /* Add to and flip head if needed */
471 head = (head + 1) & RQUEUEMASK;
472
473 qleft--;
474 ch->ch_rxcount++;
475 }
476
477 /*
478 * Write new final heads to channel structure.
479 */
480 ch->ch_r_head = head & RQUEUEMASK;
481 ch->ch_e_head = head & EQUEUEMASK;
482 jsm_input(ch);
483}
484
485static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
486{
487 u16 head;
488 u16 tail;
489 int n;
490 int s;
491 int qlen;
492 u32 len_written = 0;
493
494 if (!ch)
495 return;
496
497 /* No data to write to the UART */
498 if (ch->ch_w_tail == ch->ch_w_head)
499 return;
500
501 /* If port is "stopped", don't send any data to the UART */
502 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
503 return;
504 /*
505 * If FIFOs are disabled. Send data directly to txrx register
506 */
507 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
508 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
509
510 ch->ch_cached_lsr |= lsrbits;
511 if (ch->ch_cached_lsr & UART_LSR_THRE) {
512 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
513
514 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
515 jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
516 "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]);
517 ch->ch_w_tail++;
518 ch->ch_w_tail &= WQUEUEMASK;
519 ch->ch_txcount++;
520 }
521 return;
522 }
523
524 /*
525 * We have to do it this way, because of the EXAR TXFIFO count bug.
526 */
527 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
528 return;
529
530 len_written = 0;
531 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
532
533 /* cache head and tail of queue */
534 head = ch->ch_w_head & WQUEUEMASK;
535 tail = ch->ch_w_tail & WQUEUEMASK;
536 qlen = (head - tail) & WQUEUEMASK;
537
538 /* Find minimum of the FIFO space, versus queue length */
539 n = min(n, qlen);
540
541 while (n > 0) {
542
543 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
544 s = min(s, n);
545
546 if (s <= 0)
547 break;
548
549 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
550 /* Add and flip queue if needed */
551 tail = (tail + s) & WQUEUEMASK;
552 n -= s;
553 ch->ch_txcount += s;
554 len_written += s;
555 }
556
557 /* Update the final tail */
558 ch->ch_w_tail = tail & WQUEUEMASK;
559
560 if (len_written >= ch->ch_t_tlevel)
561 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
562
563 if (!jsm_tty_write(&ch->uart_port))
564 uart_write_wakeup(&ch->uart_port);
565}
566
567static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
568{
569 u8 msignals = signals;
570
571 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
572 "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
573
574 if (!ch)
575 return;
576
577 /* Scrub off lower bits. They signify delta's, which I don't care about */
578 msignals &= 0xf0;
579
580 if (msignals & UART_MSR_DCD)
581 ch->ch_mistat |= UART_MSR_DCD;
582 else
583 ch->ch_mistat &= ~UART_MSR_DCD;
584
585 if (msignals & UART_MSR_DSR)
586 ch->ch_mistat |= UART_MSR_DSR;
587 else
588 ch->ch_mistat &= ~UART_MSR_DSR;
589
590 if (msignals & UART_MSR_RI)
591 ch->ch_mistat |= UART_MSR_RI;
592 else
593 ch->ch_mistat &= ~UART_MSR_RI;
594
595 if (msignals & UART_MSR_CTS)
596 ch->ch_mistat |= UART_MSR_CTS;
597 else
598 ch->ch_mistat &= ~UART_MSR_CTS;
599
600 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
601 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
602 ch->ch_portnum,
603 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
604 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
605 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
606 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
607 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
608 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
609}
610
611/* Make the UART raise any of the output signals we want up */
612static void neo_assert_modem_signals(struct jsm_channel *ch)
613{
614 u8 out;
615
616 if (!ch)
617 return;
618
619 out = ch->ch_mostat;
620
621 writeb(out, &ch->ch_neo_uart->mcr);
622
623 /* flush write operation */
624 neo_pci_posting_flush(ch->ch_bd);
625}
626
627/*
628 * Flush the WRITE FIFO on the Neo.
629 *
630 * NOTE: Channel lock MUST be held before calling this function!
631 */
632static void neo_flush_uart_write(struct jsm_channel *ch)
633{
634 u8 tmp = 0;
635 int i = 0;
636
637 if (!ch)
638 return;
639
640 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
641
642 for (i = 0; i < 10; i++) {
643
644 /* Check to see if the UART feels it completely flushed the FIFO. */
645 tmp = readb(&ch->ch_neo_uart->isr_fcr);
646 if (tmp & 4) {
647 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
648 "Still flushing TX UART... i: %d\n", i);
649 udelay(10);
650 }
651 else
652 break;
653 }
654
655 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
656}
657
658
659/*
660 * Flush the READ FIFO on the Neo.
661 *
662 * NOTE: Channel lock MUST be held before calling this function!
663 */
664static void neo_flush_uart_read(struct jsm_channel *ch)
665{
666 u8 tmp = 0;
667 int i = 0;
668
669 if (!ch)
670 return;
671
672 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
673
674 for (i = 0; i < 10; i++) {
675
676 /* Check to see if the UART feels it completely flushed the FIFO. */
677 tmp = readb(&ch->ch_neo_uart->isr_fcr);
678 if (tmp & 2) {
679 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
680 "Still flushing RX UART... i: %d\n", i);
681 udelay(10);
682 }
683 else
684 break;
685 }
686}
687
688/*
689 * No locks are assumed to be held when calling this function.
690 */
691void neo_clear_break(struct jsm_channel *ch, int force)
692{
693 unsigned long lock_flags;
694
695 spin_lock_irqsave(&ch->ch_lock, lock_flags);
696
697 /* Turn break off, and unset some variables */
698 if (ch->ch_flags & CH_BREAK_SENDING) {
699 u8 temp = readb(&ch->ch_neo_uart->lcr);
700 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
701
702 ch->ch_flags &= ~(CH_BREAK_SENDING);
703 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
704 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
705
706 /* flush write operation */
707 neo_pci_posting_flush(ch->ch_bd);
708 }
709 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
710}
711
712/*
713 * Parse the ISR register.
714 */
715static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
716{
717 struct jsm_channel *ch;
718 u8 isr;
719 u8 cause;
720 unsigned long lock_flags;
721
722 if (!brd)
723 return;
724
725 if (port > brd->maxports)
726 return;
727
728 ch = brd->channels[port];
729 if (!ch)
730 return;
731
732 /* Here we try to figure out what caused the interrupt to happen */
733 while (1) {
734
735 isr = readb(&ch->ch_neo_uart->isr_fcr);
736
737 /* Bail if no pending interrupt */
738 if (isr & UART_IIR_NO_INT)
739 break;
740
741 /*
742 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
743 */
744 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
745
746 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
747 "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
748
749 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
750 /* Read data from uart -> queue */
751 neo_copy_data_from_uart_to_queue(ch);
752
753 /* Call our tty layer to enforce queue flow control if needed. */
754 spin_lock_irqsave(&ch->ch_lock, lock_flags);
755 jsm_check_queue_flow_control(ch);
756 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
757 }
758
759 if (isr & UART_IIR_THRI) {
760 /* Transfer data (if any) from Write Queue -> UART. */
761 spin_lock_irqsave(&ch->ch_lock, lock_flags);
762 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
763 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
764 neo_copy_data_from_queue_to_uart(ch);
765 }
766
767 if (isr & UART_17158_IIR_XONXOFF) {
768 cause = readb(&ch->ch_neo_uart->xoffchar1);
769
770 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
771 "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
772
773 /*
774 * Since the UART detected either an XON or
775 * XOFF match, we need to figure out which
776 * one it was, so we can suspend or resume data flow.
777 */
778 spin_lock_irqsave(&ch->ch_lock, lock_flags);
779 if (cause == UART_17158_XON_DETECT) {
780 /* Is output stopped right now, if so, resume it */
781 if (brd->channels[port]->ch_flags & CH_STOP) {
782 ch->ch_flags &= ~(CH_STOP);
783 }
784 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
785 "Port %d. XON detected in incoming data\n", port);
786 }
787 else if (cause == UART_17158_XOFF_DETECT) {
788 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
789 ch->ch_flags |= CH_STOP;
790 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
791 "Setting CH_STOP\n");
792 }
793 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
794 "Port: %d. XOFF detected in incoming data\n", port);
795 }
796 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
797 }
798
799 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
800 /*
801 * If we get here, this means the hardware is doing auto flow control.
802 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
803 */
804 cause = readb(&ch->ch_neo_uart->mcr);
805
806 /* Which pin is doing auto flow? RTS or DTR? */
807 spin_lock_irqsave(&ch->ch_lock, lock_flags);
808 if ((cause & 0x4) == 0) {
809 if (cause & UART_MCR_RTS)
810 ch->ch_mostat |= UART_MCR_RTS;
811 else
812 ch->ch_mostat &= ~(UART_MCR_RTS);
813 } else {
814 if (cause & UART_MCR_DTR)
815 ch->ch_mostat |= UART_MCR_DTR;
816 else
817 ch->ch_mostat &= ~(UART_MCR_DTR);
818 }
819 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
820 }
821
822 /* Parse any modem signal changes */
823 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
824 "MOD_STAT: sending to parse_modem_sigs\n");
825 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
826 }
827}
828
829static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
830{
831 struct jsm_channel *ch;
832 int linestatus;
833 unsigned long lock_flags;
834
835 if (!brd)
836 return;
837
838 if (port > brd->maxports)
839 return;
840
841 ch = brd->channels[port];
842 if (!ch)
843 return;
844
845 linestatus = readb(&ch->ch_neo_uart->lsr);
846
847 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
848 "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
849
850 ch->ch_cached_lsr |= linestatus;
851
852 if (ch->ch_cached_lsr & UART_LSR_DR) {
853 /* Read data from uart -> queue */
854 neo_copy_data_from_uart_to_queue(ch);
855 spin_lock_irqsave(&ch->ch_lock, lock_flags);
856 jsm_check_queue_flow_control(ch);
857 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
858 }
859
860 /*
861 * This is a special flag. It indicates that at least 1
862 * RX error (parity, framing, or break) has happened.
863 * Mark this in our struct, which will tell me that I have
864 *to do the special RX+LSR read for this FIFO load.
865 */
866 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
867 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
868 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
869 __FILE__, __LINE__, port);
870
871 /*
872 * The next 3 tests should *NOT* happen, as the above test
873 * should encapsulate all 3... At least, thats what Exar says.
874 */
875
876 if (linestatus & UART_LSR_PE) {
877 ch->ch_err_parity++;
878 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
879 "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
880 }
881
882 if (linestatus & UART_LSR_FE) {
883 ch->ch_err_frame++;
884 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
885 "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
886 }
887
888 if (linestatus & UART_LSR_BI) {
889 ch->ch_err_break++;
890 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
891 "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
892 }
893
894 if (linestatus & UART_LSR_OE) {
895 /*
896 * Rx Oruns. Exar says that an orun will NOT corrupt
897 * the FIFO. It will just replace the holding register
898 * with this new data byte. So basically just ignore this.
899 * Probably we should eventually have an orun stat in our driver...
900 */
901 ch->ch_err_overrun++;
902 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
903 "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
904 }
905
906 if (linestatus & UART_LSR_THRE) {
907 spin_lock_irqsave(&ch->ch_lock, lock_flags);
908 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
909 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
910
911 /* Transfer data (if any) from Write Queue -> UART. */
912 neo_copy_data_from_queue_to_uart(ch);
913 }
914 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
915 spin_lock_irqsave(&ch->ch_lock, lock_flags);
916 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
917 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
918
919 /* Transfer data (if any) from Write Queue -> UART. */
920 neo_copy_data_from_queue_to_uart(ch);
921 }
922}
923
924/*
925 * neo_param()
926 * Send any/all changes to the line to the UART.
927 */
928static void neo_param(struct jsm_channel *ch)
929{
930 u8 lcr = 0;
931 u8 uart_lcr = 0;
932 u8 ier = 0;
933 u32 baud = 9600;
934 int quot = 0;
935 struct jsm_board *bd;
936
937 bd = ch->ch_bd;
938 if (!bd)
939 return;
940
941 /*
942 * If baud rate is zero, flush queues, and set mval to drop DTR.
943 */
944 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
945 ch->ch_r_head = ch->ch_r_tail = 0;
946 ch->ch_e_head = ch->ch_e_tail = 0;
947 ch->ch_w_head = ch->ch_w_tail = 0;
948
949 neo_flush_uart_write(ch);
950 neo_flush_uart_read(ch);
951
952 ch->ch_flags |= (CH_BAUD0);
953 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
954 neo_assert_modem_signals(ch);
955 ch->ch_old_baud = 0;
956 return;
957
958 } else if (ch->ch_custom_speed) {
959 baud = ch->ch_custom_speed;
960 if (ch->ch_flags & CH_BAUD0)
961 ch->ch_flags &= ~(CH_BAUD0);
962 } else {
963 int iindex = 0;
964 int jindex = 0;
965
966 const u64 bauds[4][16] = {
967 {
968 0, 50, 75, 110,
969 134, 150, 200, 300,
970 600, 1200, 1800, 2400,
971 4800, 9600, 19200, 38400 },
972 {
973 0, 57600, 115200, 230400,
974 460800, 150, 200, 921600,
975 600, 1200, 1800, 2400,
976 4800, 9600, 19200, 38400 },
977 {
978 0, 57600, 76800, 115200,
979 131657, 153600, 230400, 460800,
980 921600, 1200, 1800, 2400,
981 4800, 9600, 19200, 38400 },
982 {
983 0, 57600, 115200, 230400,
984 460800, 150, 200, 921600,
985 600, 1200, 1800, 2400,
986 4800, 9600, 19200, 38400 }
987 };
988
989 baud = C_BAUD(ch->uart_port.info->tty) & 0xff;
990
991 if (ch->ch_c_cflag & CBAUDEX)
992 iindex = 1;
993
994 jindex = baud;
995
996 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
997 baud = bauds[iindex][jindex];
998 else {
999 jsm_printk(IOCTL, DEBUG, &ch->ch_bd->pci_dev,
1000 "baud indices were out of range (%d)(%d)",
1001 iindex, jindex);
1002 baud = 0;
1003 }
1004
1005 if (baud == 0)
1006 baud = 9600;
1007
1008 if (ch->ch_flags & CH_BAUD0)
1009 ch->ch_flags &= ~(CH_BAUD0);
1010 }
1011
1012 if (ch->ch_c_cflag & PARENB)
1013 lcr |= UART_LCR_PARITY;
1014
1015 if (!(ch->ch_c_cflag & PARODD))
1016 lcr |= UART_LCR_EPAR;
1017
1018 /*
1019 * Not all platforms support mark/space parity,
1020 * so this will hide behind an ifdef.
1021 */
1022#ifdef CMSPAR
1023 if (ch->ch_c_cflag & CMSPAR)
1024 lcr |= UART_LCR_SPAR;
1025#endif
1026
1027 if (ch->ch_c_cflag & CSTOPB)
1028 lcr |= UART_LCR_STOP;
1029
1030 switch (ch->ch_c_cflag & CSIZE) {
1031 case CS5:
1032 lcr |= UART_LCR_WLEN5;
1033 break;
1034 case CS6:
1035 lcr |= UART_LCR_WLEN6;
1036 break;
1037 case CS7:
1038 lcr |= UART_LCR_WLEN7;
1039 break;
1040 case CS8:
1041 default:
1042 lcr |= UART_LCR_WLEN8;
1043 break;
1044 }
1045
1046 ier = readb(&ch->ch_neo_uart->ier);
1047 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1048
1049 if (baud == 0)
1050 baud = 9600;
1051
1052 quot = ch->ch_bd->bd_dividend / baud;
1053
1054 if (quot != 0) {
1055 ch->ch_old_baud = baud;
1056 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1057 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1058 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1059 writeb(lcr, &ch->ch_neo_uart->lcr);
1060 }
1061
1062 if (uart_lcr != lcr)
1063 writeb(lcr, &ch->ch_neo_uart->lcr);
1064
1065 if (ch->ch_c_cflag & CREAD)
1066 ier |= (UART_IER_RDI | UART_IER_RLSI);
1067
1068 ier |= (UART_IER_THRI | UART_IER_MSI);
1069
1070 writeb(ier, &ch->ch_neo_uart->ier);
1071
1072 /* Set new start/stop chars */
1073 neo_set_new_start_stop_chars(ch);
1074
1075 if (ch->ch_c_cflag & CRTSCTS)
1076 neo_set_cts_flow_control(ch);
1077 else if (ch->ch_c_iflag & IXON) {
1078 /* If start/stop is set to disable, then we should disable flow control */
1079 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1080 neo_set_no_output_flow_control(ch);
1081 else
1082 neo_set_ixon_flow_control(ch);
1083 }
1084 else
1085 neo_set_no_output_flow_control(ch);
1086
1087 if (ch->ch_c_cflag & CRTSCTS)
1088 neo_set_rts_flow_control(ch);
1089 else if (ch->ch_c_iflag & IXOFF) {
1090 /* If start/stop is set to disable, then we should disable flow control */
1091 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1092 neo_set_no_input_flow_control(ch);
1093 else
1094 neo_set_ixoff_flow_control(ch);
1095 }
1096 else
1097 neo_set_no_input_flow_control(ch);
1098 /*
1099 * Adjust the RX FIFO Trigger level if baud is less than 9600.
1100 * Not exactly elegant, but this is needed because of the Exar chip's
1101 * delay on firing off the RX FIFO interrupt on slower baud rates.
1102 */
1103 if (baud < 9600) {
1104 writeb(1, &ch->ch_neo_uart->rfifo);
1105 ch->ch_r_tlevel = 1;
1106 }
1107
1108 neo_assert_modem_signals(ch);
1109
1110 /* Get current status of the modem signals now */
1111 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1112 return;
1113}
1114
1115/*
1116 * jsm_neo_intr()
1117 *
1118 * Neo specific interrupt handler.
1119 */
1120static irqreturn_t neo_intr(int irq, void *voidbrd, struct pt_regs *regs)
1121{
1122 struct jsm_board *brd = (struct jsm_board *) voidbrd;
1123 struct jsm_channel *ch;
1124 int port = 0;
1125 int type = 0;
1126 int current_port;
1127 u32 tmp;
1128 u32 uart_poll;
1129 unsigned long lock_flags;
1130 unsigned long lock_flags2;
1131 int outofloop_count = 0;
1132
1133 brd->intr_count++;
1134
1135 /* Lock out the slow poller from running on this board. */
1136 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1137
1138 /*
1139 * Read in "extended" IRQ information from the 32bit Neo register.
1140 * Bits 0-7: What port triggered the interrupt.
1141 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1142 */
1143 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1144
1145 jsm_printk(INTR, INFO, &brd->pci_dev,
1146 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1147
1148 if (!uart_poll) {
1149 jsm_printk(INTR, INFO, &brd->pci_dev,
1150 "Kernel interrupted to me, but no pending interrupts...\n");
1151 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1152 return IRQ_NONE;
1153 }
1154
1155 /* At this point, we have at least SOMETHING to service, dig further... */
1156
1157 current_port = 0;
1158
1159 /* Loop on each port */
1160 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1161
1162 tmp = uart_poll;
1163 outofloop_count++;
1164
1165 /* Check current port to see if it has interrupt pending */
1166 if ((tmp & jsm_offset_table[current_port]) != 0) {
1167 port = current_port;
1168 type = tmp >> (8 + (port * 3));
1169 type &= 0x7;
1170 } else {
1171 current_port++;
1172 continue;
1173 }
1174
1175 jsm_printk(INTR, INFO, &brd->pci_dev,
1176 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1177
1178 /* Remove this port + type from uart_poll */
1179 uart_poll &= ~(jsm_offset_table[port]);
1180
1181 if (!type) {
1182 /* If no type, just ignore it, and move onto next port */
1183 jsm_printk(INTR, ERR, &brd->pci_dev,
1184 "Interrupt with no type! port: %d\n", port);
1185 continue;
1186 }
1187
1188 /* Switch on type of interrupt we have */
1189 switch (type) {
1190
1191 case UART_17158_RXRDY_TIMEOUT:
1192 /*
1193 * RXRDY Time-out is cleared by reading data in the
1194 * RX FIFO until it falls below the trigger level.
1195 */
1196
1197 /* Verify the port is in range. */
1198 if (port > brd->nasync)
1199 continue;
1200
1201 ch = brd->channels[port];
1202 neo_copy_data_from_uart_to_queue(ch);
1203
1204 /* Call our tty layer to enforce queue flow control if needed. */
1205 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1206 jsm_check_queue_flow_control(ch);
1207 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1208
1209 continue;
1210
1211 case UART_17158_RX_LINE_STATUS:
1212 /*
1213 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1214 */
1215 neo_parse_lsr(brd, port);
1216 continue;
1217
1218 case UART_17158_TXRDY:
1219 /*
1220 * TXRDY interrupt clears after reading ISR register for the UART channel.
1221 */
1222
1223 /*
1224 * Yes, this is odd...
1225 * Why would I check EVERY possibility of type of
1226 * interrupt, when we know its TXRDY???
1227 * Becuz for some reason, even tho we got triggered for TXRDY,
1228 * it seems to be occassionally wrong. Instead of TX, which
1229 * it should be, I was getting things like RXDY too. Weird.
1230 */
1231 neo_parse_isr(brd, port);
1232 continue;
1233
1234 case UART_17158_MSR:
1235 /*
1236 * MSR or flow control was seen.
1237 */
1238 neo_parse_isr(brd, port);
1239 continue;
1240
1241 default:
1242 /*
1243 * The UART triggered us with a bogus interrupt type.
1244 * It appears the Exar chip, when REALLY bogged down, will throw
1245 * these once and awhile.
1246 * Its harmless, just ignore it and move on.
1247 */
1248 jsm_printk(INTR, ERR, &brd->pci_dev,
1249 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1250 continue;
1251 }
1252 }
1253
1254 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1255
1256 jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1257 return IRQ_HANDLED;
1258}
1259
1260/*
1261 * Neo specific way of turning off the receiver.
1262 * Used as a way to enforce queue flow control when in
1263 * hardware flow control mode.
1264 */
1265static void neo_disable_receiver(struct jsm_channel *ch)
1266{
1267 u8 tmp = readb(&ch->ch_neo_uart->ier);
1268 tmp &= ~(UART_IER_RDI);
1269 writeb(tmp, &ch->ch_neo_uart->ier);
1270
1271 /* flush write operation */
1272 neo_pci_posting_flush(ch->ch_bd);
1273}
1274
1275
1276/*
1277 * Neo specific way of turning on the receiver.
1278 * Used as a way to un-enforce queue flow control when in
1279 * hardware flow control mode.
1280 */
1281static void neo_enable_receiver(struct jsm_channel *ch)
1282{
1283 u8 tmp = readb(&ch->ch_neo_uart->ier);
1284 tmp |= (UART_IER_RDI);
1285 writeb(tmp, &ch->ch_neo_uart->ier);
1286
1287 /* flush write operation */
1288 neo_pci_posting_flush(ch->ch_bd);
1289}
1290
1291static void neo_send_start_character(struct jsm_channel *ch)
1292{
1293 if (!ch)
1294 return;
1295
1296 if (ch->ch_startc != __DISABLED_CHAR) {
1297 ch->ch_xon_sends++;
1298 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1299
1300 /* flush write operation */
1301 neo_pci_posting_flush(ch->ch_bd);
1302 }
1303}
1304
1305static void neo_send_stop_character(struct jsm_channel *ch)
1306{
1307 if (!ch)
1308 return;
1309
1310 if (ch->ch_stopc != __DISABLED_CHAR) {
1311 ch->ch_xoff_sends++;
1312 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1313
1314 /* flush write operation */
1315 neo_pci_posting_flush(ch->ch_bd);
1316 }
1317}
1318
1319/*
1320 * neo_uart_init
1321 */
1322static void neo_uart_init(struct jsm_channel *ch)
1323{
1324 writeb(0, &ch->ch_neo_uart->ier);
1325 writeb(0, &ch->ch_neo_uart->efr);
1326 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1327
1328 /* Clear out UART and FIFO */
1329 readb(&ch->ch_neo_uart->txrx);
1330 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1331 readb(&ch->ch_neo_uart->lsr);
1332 readb(&ch->ch_neo_uart->msr);
1333
1334 ch->ch_flags |= CH_FIFO_ENABLED;
1335
1336 /* Assert any signals we want up */
1337 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1338}
1339
1340/*
1341 * Make the UART completely turn off.
1342 */
1343static void neo_uart_off(struct jsm_channel *ch)
1344{
1345 /* Turn off UART enhanced bits */
1346 writeb(0, &ch->ch_neo_uart->efr);
1347
1348 /* Stop all interrupts from occurring. */
1349 writeb(0, &ch->ch_neo_uart->ier);
1350}
1351
1352static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1353{
1354 u8 left = 0;
1355 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1356
1357 /* We must cache the LSR as some of the bits get reset once read... */
1358 ch->ch_cached_lsr |= lsr;
1359
1360 /* Determine whether the Transmitter is empty or not */
1361 if (!(lsr & UART_LSR_TEMT))
1362 left = 1;
1363 else {
1364 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1365 left = 0;
1366 }
1367
1368 return left;
1369}
1370
1371/* Channel lock MUST be held by the calling function! */
1372static void neo_send_break(struct jsm_channel *ch)
1373{
1374 /*
1375 * Set the time we should stop sending the break.
1376 * If we are already sending a break, toss away the existing
1377 * time to stop, and use this new value instead.
1378 */
1379
1380 /* Tell the UART to start sending the break */
1381 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1382 u8 temp = readb(&ch->ch_neo_uart->lcr);
1383 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1384 ch->ch_flags |= (CH_BREAK_SENDING);
1385
1386 /* flush write operation */
1387 neo_pci_posting_flush(ch->ch_bd);
1388 }
1389}
1390
1391/*
1392 * neo_send_immediate_char.
1393 *
1394 * Sends a specific character as soon as possible to the UART,
1395 * jumping over any bytes that might be in the write queue.
1396 *
1397 * The channel lock MUST be held by the calling function.
1398 */
1399static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1400{
1401 if (!ch)
1402 return;
1403
1404 writeb(c, &ch->ch_neo_uart->txrx);
1405
1406 /* flush write operation */
1407 neo_pci_posting_flush(ch->ch_bd);
1408}
1409
1410struct board_ops jsm_neo_ops = {
1411 .intr = neo_intr,
1412 .uart_init = neo_uart_init,
1413 .uart_off = neo_uart_off,
1414 .param = neo_param,
1415 .assert_modem_signals = neo_assert_modem_signals,
1416 .flush_uart_write = neo_flush_uart_write,
1417 .flush_uart_read = neo_flush_uart_read,
1418 .disable_receiver = neo_disable_receiver,
1419 .enable_receiver = neo_enable_receiver,
1420 .send_break = neo_send_break,
1421 .clear_break = neo_clear_break,
1422 .send_start_character = neo_send_start_character,
1423 .send_stop_character = neo_send_stop_character,
1424 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1425 .get_uart_bytes_left = neo_get_uart_bytes_left,
1426 .send_immediate_char = neo_send_immediate_char
1427};
diff --git a/drivers/serial/jsm/jsm_tty.c b/drivers/serial/jsm/jsm_tty.c
new file mode 100644
index 000000000000..7fb7cc07074b
--- /dev/null
+++ b/drivers/serial/jsm/jsm_tty.c
@@ -0,0 +1,1038 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ltcfwd.linux.ibm.com>
24 *
25 ***********************************************************************/
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_reg.h>
29#include <linux/delay.h> /* For udelay */
30#include <linux/pci.h>
31
32#include "jsm.h"
33
34static inline int jsm_get_mstat(struct jsm_channel *ch)
35{
36 unsigned char mstat;
37 unsigned result;
38
39 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "start\n");
40
41 mstat = (ch->ch_mostat | ch->ch_mistat);
42
43 result = 0;
44
45 if (mstat & UART_MCR_DTR)
46 result |= TIOCM_DTR;
47 if (mstat & UART_MCR_RTS)
48 result |= TIOCM_RTS;
49 if (mstat & UART_MSR_CTS)
50 result |= TIOCM_CTS;
51 if (mstat & UART_MSR_DSR)
52 result |= TIOCM_DSR;
53 if (mstat & UART_MSR_RI)
54 result |= TIOCM_RI;
55 if (mstat & UART_MSR_DCD)
56 result |= TIOCM_CD;
57
58 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "finish\n");
59 return result;
60}
61
62static unsigned int jsm_tty_tx_empty(struct uart_port *port)
63{
64 return TIOCSER_TEMT;
65}
66
67/*
68 * Return modem signals to ld.
69 */
70static unsigned int jsm_tty_get_mctrl(struct uart_port *port)
71{
72 int result;
73 struct jsm_channel *channel = (struct jsm_channel *)port;
74
75 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
76
77 result = jsm_get_mstat(channel);
78
79 if (result < 0)
80 return -ENXIO;
81
82 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
83
84 return result;
85}
86
87/*
88 * jsm_set_modem_info()
89 *
90 * Set modem signals, called by ld.
91 */
92static void jsm_tty_set_mctrl(struct uart_port *port, unsigned int mctrl)
93{
94 struct jsm_channel *channel = (struct jsm_channel *)port;
95
96 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
97
98 if (mctrl & TIOCM_RTS)
99 channel->ch_mostat |= UART_MCR_RTS;
100 else
101 channel->ch_mostat &= ~UART_MCR_RTS;
102
103 if (mctrl & TIOCM_DTR)
104 channel->ch_mostat |= UART_MCR_DTR;
105 else
106 channel->ch_mostat &= ~UART_MCR_DTR;
107
108 channel->ch_bd->bd_ops->assert_modem_signals(channel);
109
110 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
111 udelay(10);
112}
113
114static void jsm_tty_start_tx(struct uart_port *port, unsigned int tty_start)
115{
116 struct jsm_channel *channel = (struct jsm_channel *)port;
117
118 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
119
120 channel->ch_flags &= ~(CH_STOP);
121 jsm_tty_write(port);
122
123 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
124}
125
126static void jsm_tty_stop_tx(struct uart_port *port, unsigned int tty_stop)
127{
128 struct jsm_channel *channel = (struct jsm_channel *)port;
129
130 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
131
132 channel->ch_flags |= (CH_STOP);
133
134 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
135}
136
137static void jsm_tty_send_xchar(struct uart_port *port, char ch)
138{
139 unsigned long lock_flags;
140 struct jsm_channel *channel = (struct jsm_channel *)port;
141
142 spin_lock_irqsave(&port->lock, lock_flags);
143 if (ch == port->info->tty->termios->c_cc[VSTART])
144 channel->ch_bd->bd_ops->send_start_character(channel);
145
146 if (ch == port->info->tty->termios->c_cc[VSTOP])
147 channel->ch_bd->bd_ops->send_stop_character(channel);
148 spin_unlock_irqrestore(&port->lock, lock_flags);
149}
150
151static void jsm_tty_stop_rx(struct uart_port *port)
152{
153 struct jsm_channel *channel = (struct jsm_channel *)port;
154
155 channel->ch_bd->bd_ops->disable_receiver(channel);
156}
157
158static void jsm_tty_break(struct uart_port *port, int break_state)
159{
160 unsigned long lock_flags;
161 struct jsm_channel *channel = (struct jsm_channel *)port;
162
163 spin_lock_irqsave(&port->lock, lock_flags);
164 if (break_state == -1)
165 channel->ch_bd->bd_ops->send_break(channel);
166 else
167 channel->ch_bd->bd_ops->clear_break(channel, 0);
168
169 spin_unlock_irqrestore(&port->lock, lock_flags);
170}
171
172static int jsm_tty_open(struct uart_port *port)
173{
174 struct jsm_board *brd;
175 int rc = 0;
176 struct jsm_channel *channel = (struct jsm_channel *)port;
177
178 /* Get board pointer from our array of majors we have allocated */
179 brd = channel->ch_bd;
180
181 /*
182 * Allocate channel buffers for read/write/error.
183 * Set flag, so we don't get trounced on.
184 */
185 channel->ch_flags |= (CH_OPENING);
186
187 /* Drop locks, as malloc with GFP_KERNEL can sleep */
188
189 if (!channel->ch_rqueue) {
190 channel->ch_rqueue = (u8 *) kmalloc(RQUEUESIZE, GFP_KERNEL);
191 if (!channel->ch_rqueue) {
192 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
193 "unable to allocate read queue buf");
194 return -ENOMEM;
195 }
196 memset(channel->ch_rqueue, 0, RQUEUESIZE);
197 }
198 if (!channel->ch_equeue) {
199 channel->ch_equeue = (u8 *) kmalloc(EQUEUESIZE, GFP_KERNEL);
200 if (!channel->ch_equeue) {
201 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
202 "unable to allocate error queue buf");
203 return -ENOMEM;
204 }
205 memset(channel->ch_equeue, 0, EQUEUESIZE);
206 }
207 if (!channel->ch_wqueue) {
208 channel->ch_wqueue = (u8 *) kmalloc(WQUEUESIZE, GFP_KERNEL);
209 if (!channel->ch_wqueue) {
210 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
211 "unable to allocate write queue buf");
212 return -ENOMEM;
213 }
214 memset(channel->ch_wqueue, 0, WQUEUESIZE);
215 }
216
217 channel->ch_flags &= ~(CH_OPENING);
218 /*
219 * Initialize if neither terminal is open.
220 */
221 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev,
222 "jsm_open: initializing channel in open...\n");
223
224 /*
225 * Flush input queues.
226 */
227 channel->ch_r_head = channel->ch_r_tail = 0;
228 channel->ch_e_head = channel->ch_e_tail = 0;
229 channel->ch_w_head = channel->ch_w_tail = 0;
230
231 brd->bd_ops->flush_uart_write(channel);
232 brd->bd_ops->flush_uart_read(channel);
233
234 channel->ch_flags = 0;
235 channel->ch_cached_lsr = 0;
236 channel->ch_stops_sent = 0;
237
238 channel->ch_c_cflag = port->info->tty->termios->c_cflag;
239 channel->ch_c_iflag = port->info->tty->termios->c_iflag;
240 channel->ch_c_oflag = port->info->tty->termios->c_oflag;
241 channel->ch_c_lflag = port->info->tty->termios->c_lflag;
242 channel->ch_startc = port->info->tty->termios->c_cc[VSTART];
243 channel->ch_stopc = port->info->tty->termios->c_cc[VSTOP];
244
245 /* Tell UART to init itself */
246 brd->bd_ops->uart_init(channel);
247
248 /*
249 * Run param in case we changed anything
250 */
251 brd->bd_ops->param(channel);
252
253 jsm_carrier(channel);
254
255 channel->ch_open_count++;
256
257 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev, "finish\n");
258 return rc;
259}
260
261static void jsm_tty_close(struct uart_port *port)
262{
263 struct jsm_board *bd;
264 struct termios *ts;
265 struct jsm_channel *channel = (struct jsm_channel *)port;
266
267 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "start\n");
268
269 bd = channel->ch_bd;
270 ts = channel->uart_port.info->tty->termios;
271
272 channel->ch_flags &= ~(CH_STOPI);
273
274 channel->ch_open_count--;
275
276 /*
277 * If we have HUPCL set, lower DTR and RTS
278 */
279 if (channel->ch_c_cflag & HUPCL) {
280 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev,
281 "Close. HUPCL set, dropping DTR/RTS\n");
282
283 /* Drop RTS/DTR */
284 channel->ch_mostat &= ~(UART_MCR_DTR | UART_MCR_RTS);
285 bd->bd_ops->assert_modem_signals(channel);
286 }
287
288 channel->ch_old_baud = 0;
289
290 /* Turn off UART interrupts for this port */
291 channel->ch_bd->bd_ops->uart_off(channel);
292
293 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "finish\n");
294}
295
296static void jsm_tty_set_termios(struct uart_port *port,
297 struct termios *termios,
298 struct termios *old_termios)
299{
300 unsigned long lock_flags;
301 struct jsm_channel *channel = (struct jsm_channel *)port;
302
303 spin_lock_irqsave(&port->lock, lock_flags);
304 channel->ch_c_cflag = termios->c_cflag;
305 channel->ch_c_iflag = termios->c_iflag;
306 channel->ch_c_oflag = termios->c_oflag;
307 channel->ch_c_lflag = termios->c_lflag;
308 channel->ch_startc = termios->c_cc[VSTART];
309 channel->ch_stopc = termios->c_cc[VSTOP];
310
311 channel->ch_bd->bd_ops->param(channel);
312 jsm_carrier(channel);
313 spin_unlock_irqrestore(&port->lock, lock_flags);
314}
315
316static const char *jsm_tty_type(struct uart_port *port)
317{
318 return "jsm";
319}
320
321static void jsm_tty_release_port(struct uart_port *port)
322{
323}
324
325static int jsm_tty_request_port(struct uart_port *port)
326{
327 return 0;
328}
329
330static void jsm_config_port(struct uart_port *port, int flags)
331{
332 port->type = PORT_JSM;
333}
334
335static struct uart_ops jsm_ops = {
336 .tx_empty = jsm_tty_tx_empty,
337 .set_mctrl = jsm_tty_set_mctrl,
338 .get_mctrl = jsm_tty_get_mctrl,
339 .stop_tx = jsm_tty_stop_tx,
340 .start_tx = jsm_tty_start_tx,
341 .send_xchar = jsm_tty_send_xchar,
342 .stop_rx = jsm_tty_stop_rx,
343 .break_ctl = jsm_tty_break,
344 .startup = jsm_tty_open,
345 .shutdown = jsm_tty_close,
346 .set_termios = jsm_tty_set_termios,
347 .type = jsm_tty_type,
348 .release_port = jsm_tty_release_port,
349 .request_port = jsm_tty_request_port,
350 .config_port = jsm_config_port,
351};
352
353/*
354 * jsm_tty_init()
355 *
356 * Init the tty subsystem. Called once per board after board has been
357 * downloaded and init'ed.
358 */
359int jsm_tty_init(struct jsm_board *brd)
360{
361 int i;
362 void __iomem *vaddr;
363 struct jsm_channel *ch;
364
365 if (!brd)
366 return -ENXIO;
367
368 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
369
370 /*
371 * Initialize board structure elements.
372 */
373
374 brd->nasync = brd->maxports;
375
376 /*
377 * Allocate channel memory that might not have been allocated
378 * when the driver was first loaded.
379 */
380 for (i = 0; i < brd->nasync; i++) {
381 if (!brd->channels[i]) {
382
383 /*
384 * Okay to malloc with GFP_KERNEL, we are not at
385 * interrupt context, and there are no locks held.
386 */
387 brd->channels[i] = kmalloc(sizeof(struct jsm_channel), GFP_KERNEL);
388 if (!brd->channels[i]) {
389 jsm_printk(CORE, ERR, &brd->pci_dev,
390 "%s:%d Unable to allocate memory for channel struct\n",
391 __FILE__, __LINE__);
392 }
393 memset(brd->channels[i], 0, sizeof(struct jsm_channel));
394 }
395 }
396
397 ch = brd->channels[0];
398 vaddr = brd->re_map_membase;
399
400 /* Set up channel variables */
401 for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
402
403 if (!brd->channels[i])
404 continue;
405
406 spin_lock_init(&ch->ch_lock);
407
408 if (brd->bd_uart_offset == 0x200)
409 ch->ch_neo_uart = vaddr + (brd->bd_uart_offset * i);
410
411 ch->ch_bd = brd;
412 ch->ch_portnum = i;
413
414 /* .25 second delay */
415 ch->ch_close_delay = 250;
416
417 init_waitqueue_head(&ch->ch_flags_wait);
418 }
419
420 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
421 return 0;
422}
423
424int jsm_uart_port_init(struct jsm_board *brd)
425{
426 int i;
427 struct jsm_channel *ch;
428
429 if (!brd)
430 return -ENXIO;
431
432 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
433
434 /*
435 * Initialize board structure elements.
436 */
437
438 brd->nasync = brd->maxports;
439
440 /* Set up channel variables */
441 for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
442
443 if (!brd->channels[i])
444 continue;
445
446 brd->channels[i]->uart_port.irq = brd->irq;
447 brd->channels[i]->uart_port.type = PORT_JSM;
448 brd->channels[i]->uart_port.iotype = UPIO_MEM;
449 brd->channels[i]->uart_port.membase = brd->re_map_membase;
450 brd->channels[i]->uart_port.fifosize = 16;
451 brd->channels[i]->uart_port.ops = &jsm_ops;
452 brd->channels[i]->uart_port.line = brd->channels[i]->ch_portnum + brd->boardnum * 2;
453 if (uart_add_one_port (&jsm_uart_driver, &brd->channels[i]->uart_port))
454 printk(KERN_INFO "Added device failed\n");
455 else
456 printk(KERN_INFO "Added device \n");
457 }
458
459 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
460 return 0;
461}
462
463int jsm_remove_uart_port(struct jsm_board *brd)
464{
465 int i;
466 struct jsm_channel *ch;
467
468 if (!brd)
469 return -ENXIO;
470
471 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
472
473 /*
474 * Initialize board structure elements.
475 */
476
477 brd->nasync = brd->maxports;
478
479 /* Set up channel variables */
480 for (i = 0; i < brd->nasync; i++) {
481
482 if (!brd->channels[i])
483 continue;
484
485 ch = brd->channels[i];
486
487 uart_remove_one_port(&jsm_uart_driver, &brd->channels[i]->uart_port);
488 }
489
490 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
491 return 0;
492}
493
494void jsm_input(struct jsm_channel *ch)
495{
496 struct jsm_board *bd;
497 struct tty_struct *tp;
498 u32 rmask;
499 u16 head;
500 u16 tail;
501 int data_len;
502 unsigned long lock_flags;
503 int flip_len;
504 int len = 0;
505 int n = 0;
506 char *buf = NULL;
507 char *buf2 = NULL;
508 int s = 0;
509 int i = 0;
510
511 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start\n");
512
513 if (!ch)
514 return;
515
516 tp = ch->uart_port.info->tty;
517
518 bd = ch->ch_bd;
519 if(!bd)
520 return;
521
522 spin_lock_irqsave(&ch->ch_lock, lock_flags);
523
524 /*
525 *Figure the number of characters in the buffer.
526 *Exit immediately if none.
527 */
528
529 rmask = RQUEUEMASK;
530
531 head = ch->ch_r_head & rmask;
532 tail = ch->ch_r_tail & rmask;
533
534 data_len = (head - tail) & rmask;
535 if (data_len == 0) {
536 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
537 return;
538 }
539
540 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start\n");
541
542 /*
543 *If the device is not open, or CREAD is off, flush
544 *input data and return immediately.
545 */
546 if (!tp ||
547 !(tp->termios->c_cflag & CREAD) ) {
548
549 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
550 "input. dropping %d bytes on port %d...\n", data_len, ch->ch_portnum);
551 ch->ch_r_head = tail;
552
553 /* Force queue flow control to be released, if needed */
554 jsm_check_queue_flow_control(ch);
555
556 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
557 return;
558 }
559
560 /*
561 * If we are throttled, simply don't read any data.
562 */
563 if (ch->ch_flags & CH_STOPI) {
564 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
565 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
566 "Port %d throttled, not reading any data. head: %x tail: %x\n",
567 ch->ch_portnum, head, tail);
568 return;
569 }
570
571 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start 2\n");
572
573 /*
574 * If the rxbuf is empty and we are not throttled, put as much
575 * as we can directly into the linux TTY flip buffer.
576 * The jsm_rawreadok case takes advantage of carnal knowledge that
577 * the char_buf and the flag_buf are next to each other and
578 * are each of (2 * TTY_FLIPBUF_SIZE) size.
579 *
580 * NOTE: if(!tty->real_raw), the call to ldisc.receive_buf
581 *actually still uses the flag buffer, so you can't
582 *use it for input data
583 */
584 if (jsm_rawreadok) {
585 if (tp->real_raw)
586 flip_len = MYFLIPLEN;
587 else
588 flip_len = 2 * TTY_FLIPBUF_SIZE;
589 } else
590 flip_len = TTY_FLIPBUF_SIZE - tp->flip.count;
591
592 len = min(data_len, flip_len);
593 len = min(len, (N_TTY_BUF_SIZE - 1) - tp->read_cnt);
594
595 if (len <= 0) {
596 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
597 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "jsm_input 1\n");
598 return;
599 }
600
601 /*
602 * If we're bypassing flip buffers on rx, we can blast it
603 * right into the beginning of the buffer.
604 */
605 if (jsm_rawreadok) {
606 if (tp->real_raw) {
607 if (ch->ch_flags & CH_FLIPBUF_IN_USE) {
608 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
609 "JSM - FLIPBUF in use. delaying input\n");
610 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
611 return;
612 }
613 ch->ch_flags |= CH_FLIPBUF_IN_USE;
614 buf = ch->ch_bd->flipbuf;
615 buf2 = NULL;
616 } else {
617 buf = tp->flip.char_buf;
618 buf2 = tp->flip.flag_buf;
619 }
620 } else {
621 buf = tp->flip.char_buf_ptr;
622 buf2 = tp->flip.flag_buf_ptr;
623 }
624
625 n = len;
626
627 /*
628 * n now contains the most amount of data we can copy,
629 * bounded either by the flip buffer size or the amount
630 * of data the card actually has pending...
631 */
632 while (n) {
633 s = ((head >= tail) ? head : RQUEUESIZE) - tail;
634 s = min(s, n);
635
636 if (s <= 0)
637 break;
638
639 memcpy(buf, ch->ch_rqueue + tail, s);
640
641 /* buf2 is only set when port isn't raw */
642 if (buf2)
643 memcpy(buf2, ch->ch_equeue + tail, s);
644
645 tail += s;
646 buf += s;
647 if (buf2)
648 buf2 += s;
649 n -= s;
650 /* Flip queue if needed */
651 tail &= rmask;
652 }
653
654 /*
655 * In high performance mode, we don't have to update
656 * flag_buf or any of the counts or pointers into flip buf.
657 */
658 if (!jsm_rawreadok) {
659 if (I_PARMRK(tp) || I_BRKINT(tp) || I_INPCK(tp)) {
660 for (i = 0; i < len; i++) {
661 /*
662 * Give the Linux ld the flags in the
663 * format it likes.
664 */
665 if (tp->flip.flag_buf_ptr[i] & UART_LSR_BI)
666 tp->flip.flag_buf_ptr[i] = TTY_BREAK;
667 else if (tp->flip.flag_buf_ptr[i] & UART_LSR_PE)
668 tp->flip.flag_buf_ptr[i] = TTY_PARITY;
669 else if (tp->flip.flag_buf_ptr[i] & UART_LSR_FE)
670 tp->flip.flag_buf_ptr[i] = TTY_FRAME;
671 else
672 tp->flip.flag_buf_ptr[i] = TTY_NORMAL;
673 }
674 } else {
675 memset(tp->flip.flag_buf_ptr, 0, len);
676 }
677
678 tp->flip.char_buf_ptr += len;
679 tp->flip.flag_buf_ptr += len;
680 tp->flip.count += len;
681 }
682 else if (!tp->real_raw) {
683 if (I_PARMRK(tp) || I_BRKINT(tp) || I_INPCK(tp)) {
684 for (i = 0; i < len; i++) {
685 /*
686 * Give the Linux ld the flags in the
687 * format it likes.
688 */
689 if (tp->flip.flag_buf_ptr[i] & UART_LSR_BI)
690 tp->flip.flag_buf_ptr[i] = TTY_BREAK;
691 else if (tp->flip.flag_buf_ptr[i] & UART_LSR_PE)
692 tp->flip.flag_buf_ptr[i] = TTY_PARITY;
693 else if (tp->flip.flag_buf_ptr[i] & UART_LSR_FE)
694 tp->flip.flag_buf_ptr[i] = TTY_FRAME;
695 else
696 tp->flip.flag_buf_ptr[i] = TTY_NORMAL;
697 }
698 } else
699 memset(tp->flip.flag_buf, 0, len);
700 }
701
702 /*
703 * If we're doing raw reads, jam it right into the
704 * line disc bypassing the flip buffers.
705 */
706 if (jsm_rawreadok) {
707 if (tp->real_raw) {
708 ch->ch_r_tail = tail & rmask;
709 ch->ch_e_tail = tail & rmask;
710
711 jsm_check_queue_flow_control(ch);
712
713 /* !!! WE *MUST* LET GO OF ALL LOCKS BEFORE CALLING RECEIVE BUF !!! */
714
715 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
716
717 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
718 "jsm_input. %d real_raw len:%d calling receive_buf for board %d\n",
719 __LINE__, len, ch->ch_bd->boardnum);
720 tp->ldisc.receive_buf(tp, ch->ch_bd->flipbuf, NULL, len);
721
722 /* Allow use of channel flip buffer again */
723 spin_lock_irqsave(&ch->ch_lock, lock_flags);
724 ch->ch_flags &= ~CH_FLIPBUF_IN_USE;
725 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
726
727 } else {
728 ch->ch_r_tail = tail & rmask;
729 ch->ch_e_tail = tail & rmask;
730
731 jsm_check_queue_flow_control(ch);
732
733 /* !!! WE *MUST* LET GO OF ALL LOCKS BEFORE CALLING RECEIVE BUF !!! */
734 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
735
736 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
737 "jsm_input. %d not real_raw len:%d calling receive_buf for board %d\n",
738 __LINE__, len, ch->ch_bd->boardnum);
739
740 tp->ldisc.receive_buf(tp, tp->flip.char_buf, tp->flip.flag_buf, len);
741 }
742 } else {
743 ch->ch_r_tail = tail & rmask;
744 ch->ch_e_tail = tail & rmask;
745
746 jsm_check_queue_flow_control(ch);
747
748 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
749
750 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
751 "jsm_input. %d not jsm_read raw okay scheduling flip\n", __LINE__);
752 tty_schedule_flip(tp);
753 }
754
755 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "finish\n");
756}
757
758void jsm_carrier(struct jsm_channel *ch)
759{
760 struct jsm_board *bd;
761
762 int virt_carrier = 0;
763 int phys_carrier = 0;
764
765 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev, "start\n");
766 if (!ch)
767 return;
768
769 bd = ch->ch_bd;
770
771 if (!bd)
772 return;
773
774 if (ch->ch_mistat & UART_MSR_DCD) {
775 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
776 "mistat: %x D_CD: %x\n", ch->ch_mistat, ch->ch_mistat & UART_MSR_DCD);
777 phys_carrier = 1;
778 }
779
780 if (ch->ch_c_cflag & CLOCAL)
781 virt_carrier = 1;
782
783 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
784 "DCD: physical: %d virt: %d\n", phys_carrier, virt_carrier);
785
786 /*
787 * Test for a VIRTUAL carrier transition to HIGH.
788 */
789 if (((ch->ch_flags & CH_FCAR) == 0) && (virt_carrier == 1)) {
790
791 /*
792 * When carrier rises, wake any threads waiting
793 * for carrier in the open routine.
794 */
795
796 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
797 "carrier: virt DCD rose\n");
798
799 if (waitqueue_active(&(ch->ch_flags_wait)))
800 wake_up_interruptible(&ch->ch_flags_wait);
801 }
802
803 /*
804 * Test for a PHYSICAL carrier transition to HIGH.
805 */
806 if (((ch->ch_flags & CH_CD) == 0) && (phys_carrier == 1)) {
807
808 /*
809 * When carrier rises, wake any threads waiting
810 * for carrier in the open routine.
811 */
812
813 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
814 "carrier: physical DCD rose\n");
815
816 if (waitqueue_active(&(ch->ch_flags_wait)))
817 wake_up_interruptible(&ch->ch_flags_wait);
818 }
819
820 /*
821 * Test for a PHYSICAL transition to low, so long as we aren't
822 * currently ignoring physical transitions (which is what "virtual
823 * carrier" indicates).
824 *
825 * The transition of the virtual carrier to low really doesn't
826 * matter... it really only means "ignore carrier state", not
827 * "make pretend that carrier is there".
828 */
829 if ((virt_carrier == 0) && ((ch->ch_flags & CH_CD) != 0)
830 && (phys_carrier == 0)) {
831 /*
832 * When carrier drops:
833 *
834 * Drop carrier on all open units.
835 *
836 * Flush queues, waking up any task waiting in the
837 * line discipline.
838 *
839 * Send a hangup to the control terminal.
840 *
841 * Enable all select calls.
842 */
843 if (waitqueue_active(&(ch->ch_flags_wait)))
844 wake_up_interruptible(&ch->ch_flags_wait);
845 }
846
847 /*
848 * Make sure that our cached values reflect the current reality.
849 */
850 if (virt_carrier == 1)
851 ch->ch_flags |= CH_FCAR;
852 else
853 ch->ch_flags &= ~CH_FCAR;
854
855 if (phys_carrier == 1)
856 ch->ch_flags |= CH_CD;
857 else
858 ch->ch_flags &= ~CH_CD;
859}
860
861
862void jsm_check_queue_flow_control(struct jsm_channel *ch)
863{
864 int qleft = 0;
865
866 /* Store how much space we have left in the queue */
867 if ((qleft = ch->ch_r_tail - ch->ch_r_head - 1) < 0)
868 qleft += RQUEUEMASK + 1;
869
870 /*
871 * Check to see if we should enforce flow control on our queue because
872 * the ld (or user) isn't reading data out of our queue fast enuf.
873 *
874 * NOTE: This is done based on what the current flow control of the
875 * port is set for.
876 *
877 * 1) HWFLOW (RTS) - Turn off the UART's Receive interrupt.
878 * This will cause the UART's FIFO to back up, and force
879 * the RTS signal to be dropped.
880 * 2) SWFLOW (IXOFF) - Keep trying to send a stop character to
881 * the other side, in hopes it will stop sending data to us.
882 * 3) NONE - Nothing we can do. We will simply drop any extra data
883 * that gets sent into us when the queue fills up.
884 */
885 if (qleft < 256) {
886 /* HWFLOW */
887 if (ch->ch_c_cflag & CRTSCTS) {
888 if(!(ch->ch_flags & CH_RECEIVER_OFF)) {
889 ch->ch_bd->bd_ops->disable_receiver(ch);
890 ch->ch_flags |= (CH_RECEIVER_OFF);
891 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
892 "Internal queue hit hilevel mark (%d)! Turning off interrupts.\n",
893 qleft);
894 }
895 }
896 /* SWFLOW */
897 else if (ch->ch_c_iflag & IXOFF) {
898 if (ch->ch_stops_sent <= MAX_STOPS_SENT) {
899 ch->ch_bd->bd_ops->send_stop_character(ch);
900 ch->ch_stops_sent++;
901 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
902 "Sending stop char! Times sent: %x\n", ch->ch_stops_sent);
903 }
904 }
905 }
906
907 /*
908 * Check to see if we should unenforce flow control because
909 * ld (or user) finally read enuf data out of our queue.
910 *
911 * NOTE: This is done based on what the current flow control of the
912 * port is set for.
913 *
914 * 1) HWFLOW (RTS) - Turn back on the UART's Receive interrupt.
915 * This will cause the UART's FIFO to raise RTS back up,
916 * which will allow the other side to start sending data again.
917 * 2) SWFLOW (IXOFF) - Send a start character to
918 * the other side, so it will start sending data to us again.
919 * 3) NONE - Do nothing. Since we didn't do anything to turn off the
920 * other side, we don't need to do anything now.
921 */
922 if (qleft > (RQUEUESIZE / 2)) {
923 /* HWFLOW */
924 if (ch->ch_c_cflag & CRTSCTS) {
925 if (ch->ch_flags & CH_RECEIVER_OFF) {
926 ch->ch_bd->bd_ops->enable_receiver(ch);
927 ch->ch_flags &= ~(CH_RECEIVER_OFF);
928 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
929 "Internal queue hit lowlevel mark (%d)! Turning on interrupts.\n",
930 qleft);
931 }
932 }
933 /* SWFLOW */
934 else if (ch->ch_c_iflag & IXOFF && ch->ch_stops_sent) {
935 ch->ch_stops_sent = 0;
936 ch->ch_bd->bd_ops->send_start_character(ch);
937 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "Sending start char!\n");
938 }
939 }
940}
941
942/*
943 * jsm_tty_write()
944 *
945 * Take data from the user or kernel and send it out to the FEP.
946 * In here exists all the Transparent Print magic as well.
947 */
948int jsm_tty_write(struct uart_port *port)
949{
950 int bufcount = 0, n = 0;
951 int data_count = 0,data_count1 =0;
952 u16 head;
953 u16 tail;
954 u16 tmask;
955 u32 remain;
956 int temp_tail = port->info->xmit.tail;
957 struct jsm_channel *channel = (struct jsm_channel *)port;
958
959 tmask = WQUEUEMASK;
960 head = (channel->ch_w_head) & tmask;
961 tail = (channel->ch_w_tail) & tmask;
962
963 if ((bufcount = tail - head - 1) < 0)
964 bufcount += WQUEUESIZE;
965
966 n = bufcount;
967
968 n = min(n, 56);
969 remain = WQUEUESIZE - head;
970
971 data_count = 0;
972 if (n >= remain) {
973 n -= remain;
974 while ((port->info->xmit.head != temp_tail) &&
975 (data_count < remain)) {
976 channel->ch_wqueue[head++] =
977 port->info->xmit.buf[temp_tail];
978
979 temp_tail++;
980 temp_tail &= (UART_XMIT_SIZE - 1);
981 data_count++;
982 }
983 if (data_count == remain) head = 0;
984 }
985
986 data_count1 = 0;
987 if (n > 0) {
988 remain = n;
989 while ((port->info->xmit.head != temp_tail) &&
990 (data_count1 < remain)) {
991 channel->ch_wqueue[head++] =
992 port->info->xmit.buf[temp_tail];
993
994 temp_tail++;
995 temp_tail &= (UART_XMIT_SIZE - 1);
996 data_count1++;
997
998 }
999 }
1000
1001 port->info->xmit.tail = temp_tail;
1002
1003 data_count += data_count1;
1004 if (data_count) {
1005 head &= tmask;
1006 channel->ch_w_head = head;
1007 }
1008
1009 if (data_count) {
1010 channel->ch_bd->bd_ops->copy_data_from_queue_to_uart(channel);
1011 }
1012
1013 return data_count;
1014}
1015
1016static ssize_t jsm_driver_version_show(struct device_driver *ddp, char *buf)
1017{
1018 return snprintf(buf, PAGE_SIZE, "%s\n", JSM_VERSION);
1019}
1020static DRIVER_ATTR(version, S_IRUSR, jsm_driver_version_show, NULL);
1021
1022static ssize_t jsm_driver_state_show(struct device_driver *ddp, char *buf)
1023{
1024 return snprintf(buf, PAGE_SIZE, "%s\n", jsm_driver_state_text[jsm_driver_state]);
1025}
1026static DRIVER_ATTR(state, S_IRUSR, jsm_driver_state_show, NULL);
1027
1028void jsm_create_driver_sysfiles(struct device_driver *driverfs)
1029{
1030 driver_create_file(driverfs, &driver_attr_version);
1031 driver_create_file(driverfs, &driver_attr_state);
1032}
1033
1034void jsm_remove_driver_sysfiles(struct device_driver *driverfs)
1035{
1036 driver_remove_file(driverfs, &driver_attr_version);
1037 driver_remove_file(driverfs, &driver_attr_state);
1038}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 07:38:43 -0400