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authorShawn Bohrer <shawn.bohrer@ni.com>2009-04-06 12:32:07 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-06 17:36:27 -0400
commit46a0fac9438764533245928b78d35fbaa5d7adf4 (patch)
tree9b0bf6bde8b581eda40a80e4405644f80ba091bb /drivers/serial/8250_pci.c
parent97ea33f9e375e4f9b3049ca861e5c91cc626c55f (diff)
8250_pci: add support for National Instruments 843x RS232 devices
This implements basic support for all 843x RS232 devices, but does not add DMA support. This means that sustained data transfers at high baud rates may not be possible on multiple ports simultaneously. Signed-off-by: Shawn Bohrer <shawn.bohrer@ni.com> Signed-off-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/serial/8250_pci.c')
-rw-r--r--drivers/serial/8250_pci.c193
1 files changed, 193 insertions, 0 deletions
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 533f82025adf..2f570c761faf 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -306,6 +306,36 @@ static void __devexit pci_plx9050_exit(struct pci_dev *dev)
306 } 306 }
307} 307}
308 308
309/* MITE registers */
310#define MITE_IOWBSR1 0xc4
311#define MITE_IOWCR1 0xf4
312#define MITE_LCIMR1 0x08
313#define MITE_LCIMR2 0x10
314
315#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
316
317static void __devexit pci_ni8430_exit(struct pci_dev *dev)
318{
319 void __iomem *p;
320 unsigned long base, len;
321 unsigned int bar = 0;
322
323 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
324 moan_device("no memory in bar", dev);
325 return;
326 }
327
328 base = pci_resource_start(dev, bar);
329 len = pci_resource_len(dev, bar);
330 p = ioremap_nocache(base, len);
331 if (p == NULL)
332 return;
333
334 /* Disable the CPU Interrupt */
335 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
336 iounmap(p);
337}
338
309/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 339/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310static int 340static int
311sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 341sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
@@ -597,6 +627,82 @@ static int pci_xircom_init(struct pci_dev *dev)
597 return 0; 627 return 0;
598} 628}
599 629
630#define MITE_IOWBSR1_WSIZE 0xa
631#define MITE_IOWBSR1_WIN_OFFSET 0x800
632#define MITE_IOWBSR1_WENAB (1 << 7)
633#define MITE_LCIMR1_IO_IE_0 (1 << 24)
634#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
635#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
636
637static int pci_ni8430_init(struct pci_dev *dev)
638{
639 void __iomem *p;
640 unsigned long base, len;
641 u32 device_window;
642 unsigned int bar = 0;
643
644 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
645 moan_device("no memory in bar", dev);
646 return 0;
647 }
648
649 base = pci_resource_start(dev, bar);
650 len = pci_resource_len(dev, bar);
651 p = ioremap_nocache(base, len);
652 if (p == NULL)
653 return -ENOMEM;
654
655 /* Set device window address and size in BAR0 */
656 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
657 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
658 writel(device_window, p + MITE_IOWBSR1);
659
660 /* Set window access to go to RAMSEL IO address space */
661 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
662 p + MITE_IOWCR1);
663
664 /* Enable IO Bus Interrupt 0 */
665 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
666
667 /* Enable CPU Interrupt */
668 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
669
670 iounmap(p);
671 return 0;
672}
673
674/* UART Port Control Register */
675#define NI8430_PORTCON 0x0f
676#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
677
678static int
679pci_ni8430_setup(struct serial_private *priv, struct pciserial_board *board,
680 struct uart_port *port, int idx)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar, offset = board->first_offset;
685
686 if (idx >= board->num_ports)
687 return 1;
688
689 bar = FL_GET_BASE(board->flags);
690 offset += idx * board->uart_offset;
691
692 base = pci_resource_start(priv->dev, bar);
693 len = pci_resource_len(priv->dev, bar);
694 p = ioremap_nocache(base, len);
695
696 /* enable the transciever */
697 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
698 p + offset + NI8430_PORTCON);
699
700 iounmap(p);
701
702 return setup_port(priv, port, bar, offset, board->reg_shift);
703}
704
705
600static int pci_netmos_init(struct pci_dev *dev) 706static int pci_netmos_init(struct pci_dev *dev)
601{ 707{
602 /* subdevice 0x00PS means <P> parallel, <S> serial */ 708 /* subdevice 0x00PS means <P> parallel, <S> serial */
@@ -913,6 +1019,18 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
913 .exit = __devexit_p(pci_ite887x_exit), 1019 .exit = __devexit_p(pci_ite887x_exit),
914 }, 1020 },
915 /* 1021 /*
1022 * National Instruments
1023 */
1024 {
1025 .vendor = PCI_VENDOR_ID_NI,
1026 .device = PCI_ANY_ID,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .init = pci_ni8430_init,
1030 .setup = pci_ni8430_setup,
1031 .exit = __devexit_p(pci_ni8430_exit),
1032 },
1033 /*
916 * Panacom 1034 * Panacom
917 */ 1035 */
918 { 1036 {
@@ -1280,6 +1398,10 @@ enum pci_board_num_t {
1280 pbn_exar_XR17C154, 1398 pbn_exar_XR17C154,
1281 pbn_exar_XR17C158, 1399 pbn_exar_XR17C158,
1282 pbn_pasemi_1682M, 1400 pbn_pasemi_1682M,
1401 pbn_ni8430_2,
1402 pbn_ni8430_4,
1403 pbn_ni8430_8,
1404 pbn_ni8430_16,
1283}; 1405};
1284 1406
1285/* 1407/*
@@ -1850,6 +1972,37 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1850 .num_ports = 1, 1972 .num_ports = 1,
1851 .base_baud = 8333333, 1973 .base_baud = 8333333,
1852 }, 1974 },
1975 /*
1976 * National Instruments 843x
1977 */
1978 [pbn_ni8430_16] = {
1979 .flags = FL_BASE0,
1980 .num_ports = 16,
1981 .base_baud = 3686400,
1982 .uart_offset = 0x10,
1983 .first_offset = 0x800,
1984 },
1985 [pbn_ni8430_8] = {
1986 .flags = FL_BASE0,
1987 .num_ports = 8,
1988 .base_baud = 3686400,
1989 .uart_offset = 0x10,
1990 .first_offset = 0x800,
1991 },
1992 [pbn_ni8430_4] = {
1993 .flags = FL_BASE0,
1994 .num_ports = 4,
1995 .base_baud = 3686400,
1996 .uart_offset = 0x10,
1997 .first_offset = 0x800,
1998 },
1999 [pbn_ni8430_2] = {
2000 .flags = FL_BASE0,
2001 .num_ports = 2,
2002 .base_baud = 3686400,
2003 .uart_offset = 0x10,
2004 .first_offset = 0x800,
2005 },
1853}; 2006};
1854 2007
1855static const struct pci_device_id softmodem_blacklist[] = { 2008static const struct pci_device_id softmodem_blacklist[] = {
@@ -3052,6 +3205,46 @@ static struct pci_device_id serial_pci_tbl[] = {
3052 pbn_pasemi_1682M }, 3205 pbn_pasemi_1682M },
3053 3206
3054 /* 3207 /*
3208 * National Instruments
3209 */
3210 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_ni8430_2 },
3213 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_ni8430_2 },
3216 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_ni8430_4 },
3219 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_ni8430_4 },
3222 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224 pbn_ni8430_8 },
3225 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_ni8430_8 },
3228 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_ni8430_16 },
3231 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_ni8430_16 },
3234 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236 pbn_ni8430_2 },
3237 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239 pbn_ni8430_2 },
3240 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242 pbn_ni8430_4 },
3243 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245 pbn_ni8430_4 },
3246
3247 /*
3055 * ADDI-DATA GmbH communication cards <info@addi-data.com> 3248 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3056 */ 3249 */
3057 { PCI_VENDOR_ID_ADDIDATA, 3250 { PCI_VENDOR_ID_ADDIDATA,