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authorJames Bottomley <James.Bottomley@HansenPartnership.com>2008-01-03 13:27:16 -0500
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2008-02-07 19:02:42 -0500
commit642978beb48331db1bafde0262eee33f658cfc39 (patch)
tree92305bcbd3aabce5d314bb0621ca602979965b42 /drivers/scsi
parentda19d2f53269210adfa9aa5a163a9fad8dc63d27 (diff)
[SCSI] remove m68k NCR53C9x based drivers
These drivers depend on the deprecated NCR53C9X core and need to be converted to the esp_scsi core. Acked-by: Boaz Harrosh <bharrosh@panasas.com> Cc: Linux/m68k <linux-m68k@vger.kernel.org> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/Kconfig60
-rw-r--r--drivers/scsi/Makefile7
-rw-r--r--drivers/scsi/blz1230.c353
-rw-r--r--drivers/scsi/blz2060.c306
-rw-r--r--drivers/scsi/cyberstorm.c377
-rw-r--r--drivers/scsi/cyberstormII.c314
-rw-r--r--drivers/scsi/fastlane.c421
-rw-r--r--drivers/scsi/mac_esp.c751
-rw-r--r--drivers/scsi/oktagon_esp.c606
-rw-r--r--drivers/scsi/oktagon_io.S194
10 files changed, 0 insertions, 3389 deletions
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 9680f82b3ecf..510bedb37575 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -1578,45 +1578,6 @@ config GVP11_SCSI
1578 To compile this driver as a module, choose M here: the 1578 To compile this driver as a module, choose M here: the
1579 module will be called gvp11. 1579 module will be called gvp11.
1580 1580
1581config CYBERSTORM_SCSI
1582 tristate "CyberStorm SCSI support"
1583 depends on ZORRO && SCSI
1584 help
1585 If you have an Amiga with an original (MkI) Phase5 Cyberstorm
1586 accelerator board and the optional Cyberstorm SCSI controller,
1587 answer Y. Otherwise, say N.
1588
1589config CYBERSTORMII_SCSI
1590 tristate "CyberStorm Mk II SCSI support"
1591 depends on ZORRO && SCSI
1592 help
1593 If you have an Amiga with a Phase5 Cyberstorm MkII accelerator board
1594 and the optional Cyberstorm SCSI controller, say Y. Otherwise,
1595 answer N.
1596
1597config BLZ2060_SCSI
1598 tristate "Blizzard 2060 SCSI support"
1599 depends on ZORRO && SCSI
1600 help
1601 If you have an Amiga with a Phase5 Blizzard 2060 accelerator board
1602 and want to use the onboard SCSI controller, say Y. Otherwise,
1603 answer N.
1604
1605config BLZ1230_SCSI
1606 tristate "Blizzard 1230IV/1260 SCSI support"
1607 depends on ZORRO && SCSI
1608 help
1609 If you have an Amiga 1200 with a Phase5 Blizzard 1230IV or Blizzard
1610 1260 accelerator, and the optional SCSI module, say Y. Otherwise,
1611 say N.
1612
1613config FASTLANE_SCSI
1614 tristate "Fastlane SCSI support"
1615 depends on ZORRO && SCSI
1616 help
1617 If you have the Phase5 Fastlane Z3 SCSI controller, or plan to use
1618 one in the near future, say Y to this question. Otherwise, say N.
1619
1620config SCSI_A4000T 1581config SCSI_A4000T
1621 tristate "A4000T NCR53c710 SCSI support (EXPERIMENTAL)" 1582 tristate "A4000T NCR53c710 SCSI support (EXPERIMENTAL)"
1622 depends on AMIGA && SCSI && EXPERIMENTAL 1583 depends on AMIGA && SCSI && EXPERIMENTAL
@@ -1644,15 +1605,6 @@ config SCSI_ZORRO7XX
1644 accelerator card for the Amiga 1200, 1605 accelerator card for the Amiga 1200,
1645 - the SCSI controller on the GVP Turbo 040/060 accelerator. 1606 - the SCSI controller on the GVP Turbo 040/060 accelerator.
1646 1607
1647config OKTAGON_SCSI
1648 tristate "BSC Oktagon SCSI support (EXPERIMENTAL)"
1649 depends on ZORRO && SCSI && EXPERIMENTAL
1650 help
1651 If you have the BSC Oktagon SCSI disk controller for the Amiga, say
1652 Y to this question. If you're in doubt about whether you have one,
1653 see the picture at
1654 <http://amiga.resource.cx/exp/search.pl?product=oktagon>.
1655
1656config ATARI_SCSI 1608config ATARI_SCSI
1657 tristate "Atari native SCSI support" 1609 tristate "Atari native SCSI support"
1658 depends on ATARI && SCSI 1610 depends on ATARI && SCSI
@@ -1705,18 +1657,6 @@ config MAC_SCSI
1705 SCSI-HOWTO, available from 1657 SCSI-HOWTO, available from
1706 <http://www.tldp.org/docs.html#howto>. 1658 <http://www.tldp.org/docs.html#howto>.
1707 1659
1708config SCSI_MAC_ESP
1709 tristate "Macintosh NCR53c9[46] SCSI"
1710 depends on MAC && SCSI
1711 help
1712 This is the NCR 53c9x SCSI controller found on most of the 68040
1713 based Macintoshes. If you have one of these say Y and read the
1714 SCSI-HOWTO, available from
1715 <http://www.tldp.org/docs.html#howto>.
1716
1717 To compile this driver as a module, choose M here: the
1718 module will be called mac_esp.
1719
1720config MVME147_SCSI 1660config MVME147_SCSI
1721 bool "WD33C93 SCSI driver for MVME147" 1661 bool "WD33C93 SCSI driver for MVME147"
1722 depends on MVME147 && SCSI=y 1662 depends on MVME147 && SCSI=y
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 576cfc68d469..118dc525e267 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -44,15 +44,8 @@ obj-$(CONFIG_A2091_SCSI) += a2091.o wd33c93.o
44obj-$(CONFIG_GVP11_SCSI) += gvp11.o wd33c93.o 44obj-$(CONFIG_GVP11_SCSI) += gvp11.o wd33c93.o
45obj-$(CONFIG_MVME147_SCSI) += mvme147.o wd33c93.o 45obj-$(CONFIG_MVME147_SCSI) += mvme147.o wd33c93.o
46obj-$(CONFIG_SGIWD93_SCSI) += sgiwd93.o wd33c93.o 46obj-$(CONFIG_SGIWD93_SCSI) += sgiwd93.o wd33c93.o
47obj-$(CONFIG_CYBERSTORM_SCSI) += NCR53C9x.o cyberstorm.o
48obj-$(CONFIG_CYBERSTORMII_SCSI) += NCR53C9x.o cyberstormII.o
49obj-$(CONFIG_BLZ2060_SCSI) += NCR53C9x.o blz2060.o
50obj-$(CONFIG_BLZ1230_SCSI) += NCR53C9x.o blz1230.o
51obj-$(CONFIG_FASTLANE_SCSI) += NCR53C9x.o fastlane.o
52obj-$(CONFIG_OKTAGON_SCSI) += NCR53C9x.o oktagon_esp_mod.o
53obj-$(CONFIG_ATARI_SCSI) += atari_scsi.o 47obj-$(CONFIG_ATARI_SCSI) += atari_scsi.o
54obj-$(CONFIG_MAC_SCSI) += mac_scsi.o 48obj-$(CONFIG_MAC_SCSI) += mac_scsi.o
55obj-$(CONFIG_SCSI_MAC_ESP) += mac_esp.o NCR53C9x.o
56obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o sun3_scsi_vme.o 49obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o sun3_scsi_vme.o
57obj-$(CONFIG_MVME16x_SCSI) += 53c700.o mvme16x_scsi.o 50obj-$(CONFIG_MVME16x_SCSI) += 53c700.o mvme16x_scsi.o
58obj-$(CONFIG_BVME6000_SCSI) += 53c700.o bvme6000_scsi.o 51obj-$(CONFIG_BVME6000_SCSI) += 53c700.o bvme6000_scsi.o
diff --git a/drivers/scsi/blz1230.c b/drivers/scsi/blz1230.c
deleted file mode 100644
index 23f7c24ab809..000000000000
--- a/drivers/scsi/blz1230.c
+++ /dev/null
@@ -1,353 +0,0 @@
1/* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller.
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * This driver is based on the CyberStorm driver, hence the occasional
6 * reference to CyberStorm.
7 */
8
9/* TODO:
10 *
11 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
12 * to the caches and the Sparc MMU mapping.
13 * 2) Make as few routines required outside the generic driver. A lot of the
14 * routines in this file used to be inline!
15 */
16
17#include <linux/module.h>
18
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/blkdev.h>
26#include <linux/proc_fs.h>
27#include <linux/stat.h>
28#include <linux/interrupt.h>
29
30#include "scsi.h"
31#include <scsi/scsi_host.h>
32#include "NCR53C9x.h"
33
34#include <linux/zorro.h>
35#include <asm/irq.h>
36#include <asm/amigaints.h>
37#include <asm/amigahw.h>
38
39#include <asm/pgtable.h>
40
41#define MKIV 1
42
43/* The controller registers can be found in the Z2 config area at these
44 * offsets:
45 */
46#define BLZ1230_ESP_ADDR 0x8000
47#define BLZ1230_DMA_ADDR 0x10000
48#define BLZ1230II_ESP_ADDR 0x10000
49#define BLZ1230II_DMA_ADDR 0x10021
50
51
52/* The Blizzard 1230 DMA interface
53 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
54 * Only two things can be programmed in the Blizzard DMA:
55 * 1) The data direction is controlled by the status of bit 31 (1 = write)
56 * 2) The source/dest address (word aligned, shifted one right) in bits 30-0
57 *
58 * Program DMA by first latching the highest byte of the address/direction
59 * (i.e. bits 31-24 of the long word constructed as described in steps 1+2
60 * above). Then write each byte of the address/direction (starting with the
61 * top byte, working down) to the DMA address register.
62 *
63 * Figure out interrupt status by reading the ESP status byte.
64 */
65struct blz1230_dma_registers {
66 volatile unsigned char dma_addr; /* DMA address [0x0000] */
67 unsigned char dmapad2[0x7fff];
68 volatile unsigned char dma_latch; /* DMA latch [0x8000] */
69};
70
71struct blz1230II_dma_registers {
72 volatile unsigned char dma_addr; /* DMA address [0x0000] */
73 unsigned char dmapad2[0xf];
74 volatile unsigned char dma_latch; /* DMA latch [0x0010] */
75};
76
77#define BLZ1230_DMA_WRITE 0x80000000
78
79static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
80static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
81static void dma_dump_state(struct NCR_ESP *esp);
82static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
83static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
84static void dma_ints_off(struct NCR_ESP *esp);
85static void dma_ints_on(struct NCR_ESP *esp);
86static int dma_irq_p(struct NCR_ESP *esp);
87static int dma_ports_p(struct NCR_ESP *esp);
88static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
89
90static volatile unsigned char cmd_buffer[16];
91 /* This is where all commands are put
92 * before they are transferred to the ESP chip
93 * via PIO.
94 */
95
96/***************************************************************** Detection */
97int __init blz1230_esp_detect(struct scsi_host_template *tpnt)
98{
99 struct NCR_ESP *esp;
100 struct zorro_dev *z = NULL;
101 unsigned long address;
102 struct ESP_regs *eregs;
103 unsigned long board;
104
105#if MKIV
106#define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260
107#define REAL_BLZ1230_ESP_ADDR BLZ1230_ESP_ADDR
108#define REAL_BLZ1230_DMA_ADDR BLZ1230_DMA_ADDR
109#else
110#define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060
111#define REAL_BLZ1230_ESP_ADDR BLZ1230II_ESP_ADDR
112#define REAL_BLZ1230_DMA_ADDR BLZ1230II_DMA_ADDR
113#endif
114
115 if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) {
116 board = z->resource.start;
117 if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR,
118 sizeof(struct ESP_regs), "NCR53C9x")) {
119 /* Do some magic to figure out if the blizzard is
120 * equipped with a SCSI controller
121 */
122 address = ZTWO_VADDR(board);
123 eregs = (struct ESP_regs *)(address + REAL_BLZ1230_ESP_ADDR);
124 esp = esp_allocate(tpnt, (void *)board + REAL_BLZ1230_ESP_ADDR,
125 0);
126
127 esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
128 udelay(5);
129 if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7))
130 goto err_out;
131
132 /* Do command transfer with programmed I/O */
133 esp->do_pio_cmds = 1;
134
135 /* Required functions */
136 esp->dma_bytes_sent = &dma_bytes_sent;
137 esp->dma_can_transfer = &dma_can_transfer;
138 esp->dma_dump_state = &dma_dump_state;
139 esp->dma_init_read = &dma_init_read;
140 esp->dma_init_write = &dma_init_write;
141 esp->dma_ints_off = &dma_ints_off;
142 esp->dma_ints_on = &dma_ints_on;
143 esp->dma_irq_p = &dma_irq_p;
144 esp->dma_ports_p = &dma_ports_p;
145 esp->dma_setup = &dma_setup;
146
147 /* Optional functions */
148 esp->dma_barrier = 0;
149 esp->dma_drain = 0;
150 esp->dma_invalidate = 0;
151 esp->dma_irq_entry = 0;
152 esp->dma_irq_exit = 0;
153 esp->dma_led_on = 0;
154 esp->dma_led_off = 0;
155 esp->dma_poll = 0;
156 esp->dma_reset = 0;
157
158 /* SCSI chip speed */
159 esp->cfreq = 40000000;
160
161 /* The DMA registers on the Blizzard are mapped
162 * relative to the device (i.e. in the same Zorro
163 * I/O block).
164 */
165 esp->dregs = (void *)(address + REAL_BLZ1230_DMA_ADDR);
166
167 /* ESP register base */
168 esp->eregs = eregs;
169
170 /* Set the command buffer */
171 esp->esp_command = cmd_buffer;
172 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
173
174 esp->irq = IRQ_AMIGA_PORTS;
175 esp->slot = board+REAL_BLZ1230_ESP_ADDR;
176 if (request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
177 "Blizzard 1230 SCSI IV", esp->ehost))
178 goto err_out;
179
180 /* Figure out our scsi ID on the bus */
181 esp->scsi_id = 7;
182
183 /* We don't have a differential SCSI-bus. */
184 esp->diff = 0;
185
186 esp_initialize(esp);
187
188 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
189 esps_running = esps_in_use;
190 return esps_in_use;
191 }
192 }
193 return 0;
194
195 err_out:
196 scsi_unregister(esp->ehost);
197 esp_deallocate(esp);
198 release_mem_region(board+REAL_BLZ1230_ESP_ADDR,
199 sizeof(struct ESP_regs));
200 return 0;
201}
202
203/************************************************************* DMA Functions */
204static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
205{
206 /* Since the Blizzard DMA is fully dedicated to the ESP chip,
207 * the number of bytes sent (to the ESP chip) equals the number
208 * of bytes in the FIFO - there is no buffering in the DMA controller.
209 * XXXX Do I read this right? It is from host to ESP, right?
210 */
211 return fifo_count;
212}
213
214static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
215{
216 /* I don't think there's any limit on the Blizzard DMA. So we use what
217 * the ESP chip can handle (24 bit).
218 */
219 unsigned long sz = sp->SCp.this_residual;
220 if(sz > 0x1000000)
221 sz = 0x1000000;
222 return sz;
223}
224
225static void dma_dump_state(struct NCR_ESP *esp)
226{
227 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
228 amiga_custom.intreqr, amiga_custom.intenar));
229}
230
231void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
232{
233#if MKIV
234 struct blz1230_dma_registers *dregs =
235 (struct blz1230_dma_registers *) (esp->dregs);
236#else
237 struct blz1230II_dma_registers *dregs =
238 (struct blz1230II_dma_registers *) (esp->dregs);
239#endif
240
241 cache_clear(addr, length);
242
243 addr >>= 1;
244 addr &= ~(BLZ1230_DMA_WRITE);
245
246 /* First set latch */
247 dregs->dma_latch = (addr >> 24) & 0xff;
248
249 /* Then pump the address to the DMA address register */
250#if MKIV
251 dregs->dma_addr = (addr >> 24) & 0xff;
252#endif
253 dregs->dma_addr = (addr >> 16) & 0xff;
254 dregs->dma_addr = (addr >> 8) & 0xff;
255 dregs->dma_addr = (addr ) & 0xff;
256}
257
258void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
259{
260#if MKIV
261 struct blz1230_dma_registers *dregs =
262 (struct blz1230_dma_registers *) (esp->dregs);
263#else
264 struct blz1230II_dma_registers *dregs =
265 (struct blz1230II_dma_registers *) (esp->dregs);
266#endif
267
268 cache_push(addr, length);
269
270 addr >>= 1;
271 addr |= BLZ1230_DMA_WRITE;
272
273 /* First set latch */
274 dregs->dma_latch = (addr >> 24) & 0xff;
275
276 /* Then pump the address to the DMA address register */
277#if MKIV
278 dregs->dma_addr = (addr >> 24) & 0xff;
279#endif
280 dregs->dma_addr = (addr >> 16) & 0xff;
281 dregs->dma_addr = (addr >> 8) & 0xff;
282 dregs->dma_addr = (addr ) & 0xff;
283}
284
285static void dma_ints_off(struct NCR_ESP *esp)
286{
287 disable_irq(esp->irq);
288}
289
290static void dma_ints_on(struct NCR_ESP *esp)
291{
292 enable_irq(esp->irq);
293}
294
295static int dma_irq_p(struct NCR_ESP *esp)
296{
297 return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
298}
299
300static int dma_ports_p(struct NCR_ESP *esp)
301{
302 return ((amiga_custom.intenar) & IF_PORTS);
303}
304
305static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
306{
307 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
308 * so when (write) is true, it actually means READ!
309 */
310 if(write){
311 dma_init_read(esp, addr, count);
312 } else {
313 dma_init_write(esp, addr, count);
314 }
315}
316
317#define HOSTS_C
318
319int blz1230_esp_release(struct Scsi_Host *instance)
320{
321#ifdef MODULE
322 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
323 esp_deallocate((struct NCR_ESP *)instance->hostdata);
324 esp_release();
325 release_mem_region(address, sizeof(struct ESP_regs));
326 free_irq(IRQ_AMIGA_PORTS, esp_intr);
327#endif
328 return 1;
329}
330
331
332static struct scsi_host_template driver_template = {
333 .proc_name = "esp-blz1230",
334 .proc_info = esp_proc_info,
335 .name = "Blizzard1230 SCSI IV",
336 .detect = blz1230_esp_detect,
337 .slave_alloc = esp_slave_alloc,
338 .slave_destroy = esp_slave_destroy,
339 .release = blz1230_esp_release,
340 .queuecommand = esp_queue,
341 .eh_abort_handler = esp_abort,
342 .eh_bus_reset_handler = esp_reset,
343 .can_queue = 7,
344 .this_id = 7,
345 .sg_tablesize = SG_ALL,
346 .cmd_per_lun = 1,
347 .use_clustering = ENABLE_CLUSTERING
348};
349
350
351#include "scsi_module.c"
352
353MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/blz2060.c b/drivers/scsi/blz2060.c
deleted file mode 100644
index b6203ec00961..000000000000
--- a/drivers/scsi/blz2060.c
+++ /dev/null
@@ -1,306 +0,0 @@
1/* blz2060.c: Driver for Blizzard 2060 SCSI Controller.
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * This driver is based on the CyberStorm driver, hence the occasional
6 * reference to CyberStorm.
7 */
8
9/* TODO:
10 *
11 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
12 * to the caches and the Sparc MMU mapping.
13 * 2) Make as few routines required outside the generic driver. A lot of the
14 * routines in this file used to be inline!
15 */
16
17#include <linux/module.h>
18
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/blkdev.h>
26#include <linux/proc_fs.h>
27#include <linux/stat.h>
28#include <linux/interrupt.h>
29
30#include "scsi.h"
31#include <scsi/scsi_host.h>
32#include "NCR53C9x.h"
33
34#include <linux/zorro.h>
35#include <asm/irq.h>
36#include <asm/amigaints.h>
37#include <asm/amigahw.h>
38
39#include <asm/pgtable.h>
40
41/* The controller registers can be found in the Z2 config area at these
42 * offsets:
43 */
44#define BLZ2060_ESP_ADDR 0x1ff00
45#define BLZ2060_DMA_ADDR 0x1ffe0
46
47
48/* The Blizzard 2060 DMA interface
49 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
50 * Only two things can be programmed in the Blizzard DMA:
51 * 1) The data direction is controlled by the status of bit 31 (1 = write)
52 * 2) The source/dest address (word aligned, shifted one right) in bits 30-0
53 *
54 * Figure out interrupt status by reading the ESP status byte.
55 */
56struct blz2060_dma_registers {
57 volatile unsigned char dma_led_ctrl; /* DMA led control [0x000] */
58 unsigned char dmapad1[0x0f];
59 volatile unsigned char dma_addr0; /* DMA address (MSB) [0x010] */
60 unsigned char dmapad2[0x03];
61 volatile unsigned char dma_addr1; /* DMA address [0x014] */
62 unsigned char dmapad3[0x03];
63 volatile unsigned char dma_addr2; /* DMA address [0x018] */
64 unsigned char dmapad4[0x03];
65 volatile unsigned char dma_addr3; /* DMA address (LSB) [0x01c] */
66};
67
68#define BLZ2060_DMA_WRITE 0x80000000
69
70/* DMA control bits */
71#define BLZ2060_DMA_LED 0x02 /* HD led control 1 = off */
72
73static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
74static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
75static void dma_dump_state(struct NCR_ESP *esp);
76static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
77static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
78static void dma_ints_off(struct NCR_ESP *esp);
79static void dma_ints_on(struct NCR_ESP *esp);
80static int dma_irq_p(struct NCR_ESP *esp);
81static void dma_led_off(struct NCR_ESP *esp);
82static void dma_led_on(struct NCR_ESP *esp);
83static int dma_ports_p(struct NCR_ESP *esp);
84static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
85
86static volatile unsigned char cmd_buffer[16];
87 /* This is where all commands are put
88 * before they are transferred to the ESP chip
89 * via PIO.
90 */
91
92/***************************************************************** Detection */
93int __init blz2060_esp_detect(struct scsi_host_template *tpnt)
94{
95 struct NCR_ESP *esp;
96 struct zorro_dev *z = NULL;
97 unsigned long address;
98
99 if ((z = zorro_find_device(ZORRO_PROD_PHASE5_BLIZZARD_2060, z))) {
100 unsigned long board = z->resource.start;
101 if (request_mem_region(board+BLZ2060_ESP_ADDR,
102 sizeof(struct ESP_regs), "NCR53C9x")) {
103 esp = esp_allocate(tpnt, (void *)board + BLZ2060_ESP_ADDR, 0);
104
105 /* Do command transfer with programmed I/O */
106 esp->do_pio_cmds = 1;
107
108 /* Required functions */
109 esp->dma_bytes_sent = &dma_bytes_sent;
110 esp->dma_can_transfer = &dma_can_transfer;
111 esp->dma_dump_state = &dma_dump_state;
112 esp->dma_init_read = &dma_init_read;
113 esp->dma_init_write = &dma_init_write;
114 esp->dma_ints_off = &dma_ints_off;
115 esp->dma_ints_on = &dma_ints_on;
116 esp->dma_irq_p = &dma_irq_p;
117 esp->dma_ports_p = &dma_ports_p;
118 esp->dma_setup = &dma_setup;
119
120 /* Optional functions */
121 esp->dma_barrier = 0;
122 esp->dma_drain = 0;
123 esp->dma_invalidate = 0;
124 esp->dma_irq_entry = 0;
125 esp->dma_irq_exit = 0;
126 esp->dma_led_on = &dma_led_on;
127 esp->dma_led_off = &dma_led_off;
128 esp->dma_poll = 0;
129 esp->dma_reset = 0;
130
131 /* SCSI chip speed */
132 esp->cfreq = 40000000;
133
134 /* The DMA registers on the Blizzard are mapped
135 * relative to the device (i.e. in the same Zorro
136 * I/O block).
137 */
138 address = (unsigned long)ZTWO_VADDR(board);
139 esp->dregs = (void *)(address + BLZ2060_DMA_ADDR);
140
141 /* ESP register base */
142 esp->eregs = (struct ESP_regs *)(address + BLZ2060_ESP_ADDR);
143
144 /* Set the command buffer */
145 esp->esp_command = cmd_buffer;
146 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
147
148 esp->irq = IRQ_AMIGA_PORTS;
149 request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
150 "Blizzard 2060 SCSI", esp->ehost);
151
152 /* Figure out our scsi ID on the bus */
153 esp->scsi_id = 7;
154
155 /* We don't have a differential SCSI-bus. */
156 esp->diff = 0;
157
158 esp_initialize(esp);
159
160 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
161 esps_running = esps_in_use;
162 return esps_in_use;
163 }
164 }
165 return 0;
166}
167
168/************************************************************* DMA Functions */
169static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
170{
171 /* Since the Blizzard DMA is fully dedicated to the ESP chip,
172 * the number of bytes sent (to the ESP chip) equals the number
173 * of bytes in the FIFO - there is no buffering in the DMA controller.
174 * XXXX Do I read this right? It is from host to ESP, right?
175 */
176 return fifo_count;
177}
178
179static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
180{
181 /* I don't think there's any limit on the Blizzard DMA. So we use what
182 * the ESP chip can handle (24 bit).
183 */
184 unsigned long sz = sp->SCp.this_residual;
185 if(sz > 0x1000000)
186 sz = 0x1000000;
187 return sz;
188}
189
190static void dma_dump_state(struct NCR_ESP *esp)
191{
192 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
193 amiga_custom.intreqr, amiga_custom.intenar));
194}
195
196static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
197{
198 struct blz2060_dma_registers *dregs =
199 (struct blz2060_dma_registers *) (esp->dregs);
200
201 cache_clear(addr, length);
202
203 addr >>= 1;
204 addr &= ~(BLZ2060_DMA_WRITE);
205 dregs->dma_addr3 = (addr ) & 0xff;
206 dregs->dma_addr2 = (addr >> 8) & 0xff;
207 dregs->dma_addr1 = (addr >> 16) & 0xff;
208 dregs->dma_addr0 = (addr >> 24) & 0xff;
209}
210
211static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
212{
213 struct blz2060_dma_registers *dregs =
214 (struct blz2060_dma_registers *) (esp->dregs);
215
216 cache_push(addr, length);
217
218 addr >>= 1;
219 addr |= BLZ2060_DMA_WRITE;
220 dregs->dma_addr3 = (addr ) & 0xff;
221 dregs->dma_addr2 = (addr >> 8) & 0xff;
222 dregs->dma_addr1 = (addr >> 16) & 0xff;
223 dregs->dma_addr0 = (addr >> 24) & 0xff;
224}
225
226static void dma_ints_off(struct NCR_ESP *esp)
227{
228 disable_irq(esp->irq);
229}
230
231static void dma_ints_on(struct NCR_ESP *esp)
232{
233 enable_irq(esp->irq);
234}
235
236static int dma_irq_p(struct NCR_ESP *esp)
237{
238 return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
239}
240
241static void dma_led_off(struct NCR_ESP *esp)
242{
243 ((struct blz2060_dma_registers *) (esp->dregs))->dma_led_ctrl =
244 BLZ2060_DMA_LED;
245}
246
247static void dma_led_on(struct NCR_ESP *esp)
248{
249 ((struct blz2060_dma_registers *) (esp->dregs))->dma_led_ctrl = 0;
250}
251
252static int dma_ports_p(struct NCR_ESP *esp)
253{
254 return ((amiga_custom.intenar) & IF_PORTS);
255}
256
257static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
258{
259 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
260 * so when (write) is true, it actually means READ!
261 */
262 if(write){
263 dma_init_read(esp, addr, count);
264 } else {
265 dma_init_write(esp, addr, count);
266 }
267}
268
269#define HOSTS_C
270
271int blz2060_esp_release(struct Scsi_Host *instance)
272{
273#ifdef MODULE
274 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
275
276 esp_deallocate((struct NCR_ESP *)instance->hostdata);
277 esp_release();
278 release_mem_region(address, sizeof(struct ESP_regs));
279 free_irq(IRQ_AMIGA_PORTS, esp_intr);
280#endif
281 return 1;
282}
283
284
285static struct scsi_host_template driver_template = {
286 .proc_name = "esp-blz2060",
287 .proc_info = esp_proc_info,
288 .name = "Blizzard2060 SCSI",
289 .detect = blz2060_esp_detect,
290 .slave_alloc = esp_slave_alloc,
291 .slave_destroy = esp_slave_destroy,
292 .release = blz2060_esp_release,
293 .queuecommand = esp_queue,
294 .eh_abort_handler = esp_abort,
295 .eh_bus_reset_handler = esp_reset,
296 .can_queue = 7,
297 .this_id = 7,
298 .sg_tablesize = SG_ALL,
299 .cmd_per_lun = 1,
300 .use_clustering = ENABLE_CLUSTERING
301};
302
303
304#include "scsi_module.c"
305
306MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/cyberstorm.c b/drivers/scsi/cyberstorm.c
deleted file mode 100644
index c6b98a42e89d..000000000000
--- a/drivers/scsi/cyberstorm.c
+++ /dev/null
@@ -1,377 +0,0 @@
1/* cyberstorm.c: Driver for CyberStorm SCSI Controller.
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * The CyberStorm SCSI driver is based on David S. Miller's ESP driver
6 * for the Sparc computers.
7 *
8 * This work was made possible by Phase5 who willingly (and most generously)
9 * supported me with hardware and all the information I needed.
10 */
11
12/* TODO:
13 *
14 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
15 * to the caches and the Sparc MMU mapping.
16 * 2) Make as few routines required outside the generic driver. A lot of the
17 * routines in this file used to be inline!
18 */
19
20#include <linux/module.h>
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/types.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/blkdev.h>
29#include <linux/proc_fs.h>
30#include <linux/stat.h>
31#include <linux/interrupt.h>
32
33#include "scsi.h"
34#include <scsi/scsi_host.h>
35#include "NCR53C9x.h"
36
37#include <linux/zorro.h>
38#include <asm/irq.h>
39#include <asm/amigaints.h>
40#include <asm/amigahw.h>
41
42#include <asm/pgtable.h>
43
44/* The controller registers can be found in the Z2 config area at these
45 * offsets:
46 */
47#define CYBER_ESP_ADDR 0xf400
48#define CYBER_DMA_ADDR 0xf800
49
50
51/* The CyberStorm DMA interface */
52struct cyber_dma_registers {
53 volatile unsigned char dma_addr0; /* DMA address (MSB) [0x000] */
54 unsigned char dmapad1[1];
55 volatile unsigned char dma_addr1; /* DMA address [0x002] */
56 unsigned char dmapad2[1];
57 volatile unsigned char dma_addr2; /* DMA address [0x004] */
58 unsigned char dmapad3[1];
59 volatile unsigned char dma_addr3; /* DMA address (LSB) [0x006] */
60 unsigned char dmapad4[0x3fb];
61 volatile unsigned char cond_reg; /* DMA cond (ro) [0x402] */
62#define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
63};
64
65/* DMA control bits */
66#define CYBER_DMA_LED 0x80 /* HD led control 1 = on */
67#define CYBER_DMA_WRITE 0x40 /* DMA direction. 1 = write */
68#define CYBER_DMA_Z3 0x20 /* 16 (Z2) or 32 (CHIP/Z3) bit DMA transfer */
69
70/* DMA status bits */
71#define CYBER_DMA_HNDL_INTR 0x80 /* DMA IRQ pending? */
72
73/* The bits below appears to be Phase5 Debug bits only; they were not
74 * described by Phase5 so using them may seem a bit stupid...
75 */
76#define CYBER_HOST_ID 0x02 /* If set, host ID should be 7, otherwise
77 * it should be 6.
78 */
79#define CYBER_SLOW_CABLE 0x08 /* If *not* set, assume SLOW_CABLE */
80
81static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
82static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
83static void dma_dump_state(struct NCR_ESP *esp);
84static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
85static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
86static void dma_ints_off(struct NCR_ESP *esp);
87static void dma_ints_on(struct NCR_ESP *esp);
88static int dma_irq_p(struct NCR_ESP *esp);
89static void dma_led_off(struct NCR_ESP *esp);
90static void dma_led_on(struct NCR_ESP *esp);
91static int dma_ports_p(struct NCR_ESP *esp);
92static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
93
94static unsigned char ctrl_data = 0; /* Keep backup of the stuff written
95 * to ctrl_reg. Always write a copy
96 * to this register when writing to
97 * the hardware register!
98 */
99
100static volatile unsigned char cmd_buffer[16];
101 /* This is where all commands are put
102 * before they are transferred to the ESP chip
103 * via PIO.
104 */
105
106/***************************************************************** Detection */
107int __init cyber_esp_detect(struct scsi_host_template *tpnt)
108{
109 struct NCR_ESP *esp;
110 struct zorro_dev *z = NULL;
111 unsigned long address;
112
113 while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
114 unsigned long board = z->resource.start;
115 if ((z->id == ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM ||
116 z->id == ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060) &&
117 request_mem_region(board+CYBER_ESP_ADDR,
118 sizeof(struct ESP_regs), "NCR53C9x")) {
119 /* Figure out if this is a CyberStorm or really a
120 * Fastlane/Blizzard Mk II by looking at the board size.
121 * CyberStorm maps 64kB
122 * (ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM does anyway)
123 */
124 if(z->resource.end-board != 0xffff) {
125 release_mem_region(board+CYBER_ESP_ADDR,
126 sizeof(struct ESP_regs));
127 return 0;
128 }
129 esp = esp_allocate(tpnt, (void *)board + CYBER_ESP_ADDR, 0);
130
131 /* Do command transfer with programmed I/O */
132 esp->do_pio_cmds = 1;
133
134 /* Required functions */
135 esp->dma_bytes_sent = &dma_bytes_sent;
136 esp->dma_can_transfer = &dma_can_transfer;
137 esp->dma_dump_state = &dma_dump_state;
138 esp->dma_init_read = &dma_init_read;
139 esp->dma_init_write = &dma_init_write;
140 esp->dma_ints_off = &dma_ints_off;
141 esp->dma_ints_on = &dma_ints_on;
142 esp->dma_irq_p = &dma_irq_p;
143 esp->dma_ports_p = &dma_ports_p;
144 esp->dma_setup = &dma_setup;
145
146 /* Optional functions */
147 esp->dma_barrier = 0;
148 esp->dma_drain = 0;
149 esp->dma_invalidate = 0;
150 esp->dma_irq_entry = 0;
151 esp->dma_irq_exit = 0;
152 esp->dma_led_on = &dma_led_on;
153 esp->dma_led_off = &dma_led_off;
154 esp->dma_poll = 0;
155 esp->dma_reset = 0;
156
157 /* SCSI chip speed */
158 esp->cfreq = 40000000;
159
160 /* The DMA registers on the CyberStorm are mapped
161 * relative to the device (i.e. in the same Zorro
162 * I/O block).
163 */
164 address = (unsigned long)ZTWO_VADDR(board);
165 esp->dregs = (void *)(address + CYBER_DMA_ADDR);
166
167 /* ESP register base */
168 esp->eregs = (struct ESP_regs *)(address + CYBER_ESP_ADDR);
169
170 /* Set the command buffer */
171 esp->esp_command = cmd_buffer;
172 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
173
174 esp->irq = IRQ_AMIGA_PORTS;
175 request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
176 "CyberStorm SCSI", esp->ehost);
177 /* Figure out our scsi ID on the bus */
178 /* The DMA cond flag contains a hardcoded jumper bit
179 * which can be used to select host number 6 or 7.
180 * However, even though it may change, we use a hardcoded
181 * value of 7.
182 */
183 esp->scsi_id = 7;
184
185 /* We don't have a differential SCSI-bus. */
186 esp->diff = 0;
187
188 esp_initialize(esp);
189
190 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
191 esps_running = esps_in_use;
192 return esps_in_use;
193 }
194 }
195 return 0;
196}
197
198/************************************************************* DMA Functions */
199static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
200{
201 /* Since the CyberStorm DMA is fully dedicated to the ESP chip,
202 * the number of bytes sent (to the ESP chip) equals the number
203 * of bytes in the FIFO - there is no buffering in the DMA controller.
204 * XXXX Do I read this right? It is from host to ESP, right?
205 */
206 return fifo_count;
207}
208
209static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
210{
211 /* I don't think there's any limit on the CyberDMA. So we use what
212 * the ESP chip can handle (24 bit).
213 */
214 unsigned long sz = sp->SCp.this_residual;
215 if(sz > 0x1000000)
216 sz = 0x1000000;
217 return sz;
218}
219
220static void dma_dump_state(struct NCR_ESP *esp)
221{
222 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
223 esp->esp_id, ((struct cyber_dma_registers *)
224 (esp->dregs))->cond_reg));
225 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
226 amiga_custom.intreqr, amiga_custom.intenar));
227}
228
229static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
230{
231 struct cyber_dma_registers *dregs =
232 (struct cyber_dma_registers *) esp->dregs;
233
234 cache_clear(addr, length);
235
236 addr &= ~(1);
237 dregs->dma_addr0 = (addr >> 24) & 0xff;
238 dregs->dma_addr1 = (addr >> 16) & 0xff;
239 dregs->dma_addr2 = (addr >> 8) & 0xff;
240 dregs->dma_addr3 = (addr ) & 0xff;
241 ctrl_data &= ~(CYBER_DMA_WRITE);
242
243 /* Check if physical address is outside Z2 space and of
244 * block length/block aligned in memory. If this is the
245 * case, enable 32 bit transfer. In all other cases, fall back
246 * to 16 bit transfer.
247 * Obviously 32 bit transfer should be enabled if the DMA address
248 * and length are 32 bit aligned. However, this leads to some
249 * strange behavior. Even 64 bit aligned addr/length fails.
250 * Until I've found a reason for this, 32 bit transfer is only
251 * used for full-block transfers (1kB).
252 * -jskov
253 */
254#if 0
255 if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
256 (addr < 0xff0000)))
257 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
258 else
259 ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
260#else
261 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
262#endif
263 dregs->ctrl_reg = ctrl_data;
264}
265
266static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
267{
268 struct cyber_dma_registers *dregs =
269 (struct cyber_dma_registers *) esp->dregs;
270
271 cache_push(addr, length);
272
273 addr |= 1;
274 dregs->dma_addr0 = (addr >> 24) & 0xff;
275 dregs->dma_addr1 = (addr >> 16) & 0xff;
276 dregs->dma_addr2 = (addr >> 8) & 0xff;
277 dregs->dma_addr3 = (addr ) & 0xff;
278 ctrl_data |= CYBER_DMA_WRITE;
279
280 /* See comment above */
281#if 0
282 if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
283 (addr < 0xff0000)))
284 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
285 else
286 ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
287#else
288 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
289#endif
290 dregs->ctrl_reg = ctrl_data;
291}
292
293static void dma_ints_off(struct NCR_ESP *esp)
294{
295 disable_irq(esp->irq);
296}
297
298static void dma_ints_on(struct NCR_ESP *esp)
299{
300 enable_irq(esp->irq);
301}
302
303static int dma_irq_p(struct NCR_ESP *esp)
304{
305 /* It's important to check the DMA IRQ bit in the correct way! */
306 return ((esp_read(esp->eregs->esp_status) & ESP_STAT_INTR) &&
307 ((((struct cyber_dma_registers *)(esp->dregs))->cond_reg) &
308 CYBER_DMA_HNDL_INTR));
309}
310
311static void dma_led_off(struct NCR_ESP *esp)
312{
313 ctrl_data &= ~CYBER_DMA_LED;
314 ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
315}
316
317static void dma_led_on(struct NCR_ESP *esp)
318{
319 ctrl_data |= CYBER_DMA_LED;
320 ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
321}
322
323static int dma_ports_p(struct NCR_ESP *esp)
324{
325 return ((amiga_custom.intenar) & IF_PORTS);
326}
327
328static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
329{
330 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
331 * so when (write) is true, it actually means READ!
332 */
333 if(write){
334 dma_init_read(esp, addr, count);
335 } else {
336 dma_init_write(esp, addr, count);
337 }
338}
339
340#define HOSTS_C
341
342int cyber_esp_release(struct Scsi_Host *instance)
343{
344#ifdef MODULE
345 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
346
347 esp_deallocate((struct NCR_ESP *)instance->hostdata);
348 esp_release();
349 release_mem_region(address, sizeof(struct ESP_regs));
350 free_irq(IRQ_AMIGA_PORTS, esp_intr);
351#endif
352 return 1;
353}
354
355
356static struct scsi_host_template driver_template = {
357 .proc_name = "esp-cyberstorm",
358 .proc_info = esp_proc_info,
359 .name = "CyberStorm SCSI",
360 .detect = cyber_esp_detect,
361 .slave_alloc = esp_slave_alloc,
362 .slave_destroy = esp_slave_destroy,
363 .release = cyber_esp_release,
364 .queuecommand = esp_queue,
365 .eh_abort_handler = esp_abort,
366 .eh_bus_reset_handler = esp_reset,
367 .can_queue = 7,
368 .this_id = 7,
369 .sg_tablesize = SG_ALL,
370 .cmd_per_lun = 1,
371 .use_clustering = ENABLE_CLUSTERING
372};
373
374
375#include "scsi_module.c"
376
377MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/cyberstormII.c b/drivers/scsi/cyberstormII.c
deleted file mode 100644
index e336e853e66f..000000000000
--- a/drivers/scsi/cyberstormII.c
+++ /dev/null
@@ -1,314 +0,0 @@
1/* cyberstormII.c: Driver for CyberStorm SCSI Mk II
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * This driver is based on cyberstorm.c
6 */
7
8/* TODO:
9 *
10 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
11 * to the caches and the Sparc MMU mapping.
12 * 2) Make as few routines required outside the generic driver. A lot of the
13 * routines in this file used to be inline!
14 */
15
16#include <linux/module.h>
17
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/types.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/blkdev.h>
25#include <linux/proc_fs.h>
26#include <linux/stat.h>
27#include <linux/interrupt.h>
28
29#include "scsi.h"
30#include <scsi/scsi_host.h>
31#include "NCR53C9x.h"
32
33#include <linux/zorro.h>
34#include <asm/irq.h>
35#include <asm/amigaints.h>
36#include <asm/amigahw.h>
37
38#include <asm/pgtable.h>
39
40/* The controller registers can be found in the Z2 config area at these
41 * offsets:
42 */
43#define CYBERII_ESP_ADDR 0x1ff03
44#define CYBERII_DMA_ADDR 0x1ff43
45
46
47/* The CyberStorm II DMA interface */
48struct cyberII_dma_registers {
49 volatile unsigned char cond_reg; /* DMA cond (ro) [0x000] */
50#define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
51 unsigned char dmapad4[0x3f];
52 volatile unsigned char dma_addr0; /* DMA address (MSB) [0x040] */
53 unsigned char dmapad1[3];
54 volatile unsigned char dma_addr1; /* DMA address [0x044] */
55 unsigned char dmapad2[3];
56 volatile unsigned char dma_addr2; /* DMA address [0x048] */
57 unsigned char dmapad3[3];
58 volatile unsigned char dma_addr3; /* DMA address (LSB) [0x04c] */
59};
60
61/* DMA control bits */
62#define CYBERII_DMA_LED 0x02 /* HD led control 1 = on */
63
64static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
65static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
66static void dma_dump_state(struct NCR_ESP *esp);
67static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
68static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
69static void dma_ints_off(struct NCR_ESP *esp);
70static void dma_ints_on(struct NCR_ESP *esp);
71static int dma_irq_p(struct NCR_ESP *esp);
72static void dma_led_off(struct NCR_ESP *esp);
73static void dma_led_on(struct NCR_ESP *esp);
74static int dma_ports_p(struct NCR_ESP *esp);
75static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
76
77static volatile unsigned char cmd_buffer[16];
78 /* This is where all commands are put
79 * before they are transferred to the ESP chip
80 * via PIO.
81 */
82
83/***************************************************************** Detection */
84int __init cyberII_esp_detect(struct scsi_host_template *tpnt)
85{
86 struct NCR_ESP *esp;
87 struct zorro_dev *z = NULL;
88 unsigned long address;
89 struct ESP_regs *eregs;
90
91 if ((z = zorro_find_device(ZORRO_PROD_PHASE5_CYBERSTORM_MK_II, z))) {
92 unsigned long board = z->resource.start;
93 if (request_mem_region(board+CYBERII_ESP_ADDR,
94 sizeof(struct ESP_regs), "NCR53C9x")) {
95 /* Do some magic to figure out if the CyberStorm Mk II
96 * is equipped with a SCSI controller
97 */
98 address = (unsigned long)ZTWO_VADDR(board);
99 eregs = (struct ESP_regs *)(address + CYBERII_ESP_ADDR);
100
101 esp = esp_allocate(tpnt, (void *)board + CYBERII_ESP_ADDR, 0);
102
103 esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
104 udelay(5);
105 if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7)) {
106 esp_deallocate(esp);
107 scsi_unregister(esp->ehost);
108 release_mem_region(board+CYBERII_ESP_ADDR,
109 sizeof(struct ESP_regs));
110 return 0; /* Bail out if address did not hold data */
111 }
112
113 /* Do command transfer with programmed I/O */
114 esp->do_pio_cmds = 1;
115
116 /* Required functions */
117 esp->dma_bytes_sent = &dma_bytes_sent;
118 esp->dma_can_transfer = &dma_can_transfer;
119 esp->dma_dump_state = &dma_dump_state;
120 esp->dma_init_read = &dma_init_read;
121 esp->dma_init_write = &dma_init_write;
122 esp->dma_ints_off = &dma_ints_off;
123 esp->dma_ints_on = &dma_ints_on;
124 esp->dma_irq_p = &dma_irq_p;
125 esp->dma_ports_p = &dma_ports_p;
126 esp->dma_setup = &dma_setup;
127
128 /* Optional functions */
129 esp->dma_barrier = 0;
130 esp->dma_drain = 0;
131 esp->dma_invalidate = 0;
132 esp->dma_irq_entry = 0;
133 esp->dma_irq_exit = 0;
134 esp->dma_led_on = &dma_led_on;
135 esp->dma_led_off = &dma_led_off;
136 esp->dma_poll = 0;
137 esp->dma_reset = 0;
138
139 /* SCSI chip speed */
140 esp->cfreq = 40000000;
141
142 /* The DMA registers on the CyberStorm are mapped
143 * relative to the device (i.e. in the same Zorro
144 * I/O block).
145 */
146 esp->dregs = (void *)(address + CYBERII_DMA_ADDR);
147
148 /* ESP register base */
149 esp->eregs = eregs;
150
151 /* Set the command buffer */
152 esp->esp_command = cmd_buffer;
153 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
154
155 esp->irq = IRQ_AMIGA_PORTS;
156 request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
157 "CyberStorm SCSI Mk II", esp->ehost);
158
159 /* Figure out our scsi ID on the bus */
160 esp->scsi_id = 7;
161
162 /* We don't have a differential SCSI-bus. */
163 esp->diff = 0;
164
165 esp_initialize(esp);
166
167 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
168 esps_running = esps_in_use;
169 return esps_in_use;
170 }
171 }
172 return 0;
173}
174
175/************************************************************* DMA Functions */
176static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
177{
178 /* Since the CyberStorm DMA is fully dedicated to the ESP chip,
179 * the number of bytes sent (to the ESP chip) equals the number
180 * of bytes in the FIFO - there is no buffering in the DMA controller.
181 * XXXX Do I read this right? It is from host to ESP, right?
182 */
183 return fifo_count;
184}
185
186static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
187{
188 /* I don't think there's any limit on the CyberDMA. So we use what
189 * the ESP chip can handle (24 bit).
190 */
191 unsigned long sz = sp->SCp.this_residual;
192 if(sz > 0x1000000)
193 sz = 0x1000000;
194 return sz;
195}
196
197static void dma_dump_state(struct NCR_ESP *esp)
198{
199 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
200 esp->esp_id, ((struct cyberII_dma_registers *)
201 (esp->dregs))->cond_reg));
202 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
203 amiga_custom.intreqr, amiga_custom.intenar));
204}
205
206static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
207{
208 struct cyberII_dma_registers *dregs =
209 (struct cyberII_dma_registers *) esp->dregs;
210
211 cache_clear(addr, length);
212
213 addr &= ~(1);
214 dregs->dma_addr0 = (addr >> 24) & 0xff;
215 dregs->dma_addr1 = (addr >> 16) & 0xff;
216 dregs->dma_addr2 = (addr >> 8) & 0xff;
217 dregs->dma_addr3 = (addr ) & 0xff;
218}
219
220static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
221{
222 struct cyberII_dma_registers *dregs =
223 (struct cyberII_dma_registers *) esp->dregs;
224
225 cache_push(addr, length);
226
227 addr |= 1;
228 dregs->dma_addr0 = (addr >> 24) & 0xff;
229 dregs->dma_addr1 = (addr >> 16) & 0xff;
230 dregs->dma_addr2 = (addr >> 8) & 0xff;
231 dregs->dma_addr3 = (addr ) & 0xff;
232}
233
234static void dma_ints_off(struct NCR_ESP *esp)
235{
236 disable_irq(esp->irq);
237}
238
239static void dma_ints_on(struct NCR_ESP *esp)
240{
241 enable_irq(esp->irq);
242}
243
244static int dma_irq_p(struct NCR_ESP *esp)
245{
246 /* It's important to check the DMA IRQ bit in the correct way! */
247 return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
248}
249
250static void dma_led_off(struct NCR_ESP *esp)
251{
252 ((struct cyberII_dma_registers *)(esp->dregs))->ctrl_reg &= ~CYBERII_DMA_LED;
253}
254
255static void dma_led_on(struct NCR_ESP *esp)
256{
257 ((struct cyberII_dma_registers *)(esp->dregs))->ctrl_reg |= CYBERII_DMA_LED;
258}
259
260static int dma_ports_p(struct NCR_ESP *esp)
261{
262 return ((amiga_custom.intenar) & IF_PORTS);
263}
264
265static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
266{
267 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
268 * so when (write) is true, it actually means READ!
269 */
270 if(write){
271 dma_init_read(esp, addr, count);
272 } else {
273 dma_init_write(esp, addr, count);
274 }
275}
276
277#define HOSTS_C
278
279int cyberII_esp_release(struct Scsi_Host *instance)
280{
281#ifdef MODULE
282 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
283
284 esp_deallocate((struct NCR_ESP *)instance->hostdata);
285 esp_release();
286 release_mem_region(address, sizeof(struct ESP_regs));
287 free_irq(IRQ_AMIGA_PORTS, esp_intr);
288#endif
289 return 1;
290}
291
292
293static struct scsi_host_template driver_template = {
294 .proc_name = "esp-cyberstormII",
295 .proc_info = esp_proc_info,
296 .name = "CyberStorm Mk II SCSI",
297 .detect = cyberII_esp_detect,
298 .slave_alloc = esp_slave_alloc,
299 .slave_destroy = esp_slave_destroy,
300 .release = cyberII_esp_release,
301 .queuecommand = esp_queue,
302 .eh_abort_handler = esp_abort,
303 .eh_bus_reset_handler = esp_reset,
304 .can_queue = 7,
305 .this_id = 7,
306 .sg_tablesize = SG_ALL,
307 .cmd_per_lun = 1,
308 .use_clustering = ENABLE_CLUSTERING
309};
310
311
312#include "scsi_module.c"
313
314MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/fastlane.c b/drivers/scsi/fastlane.c
deleted file mode 100644
index 4266a2139b5f..000000000000
--- a/drivers/scsi/fastlane.c
+++ /dev/null
@@ -1,421 +0,0 @@
1/* fastlane.c: Driver for Phase5's Fastlane SCSI Controller.
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * This driver is based on the CyberStorm driver, hence the occasional
6 * reference to CyberStorm.
7 *
8 * Betatesting & crucial adjustments by
9 * Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
10 *
11 */
12
13/* TODO:
14 *
15 * o According to the doc from laire, it is required to reset the DMA when
16 * the transfer is done. ATM we reset DMA just before every new
17 * dma_init_(read|write).
18 *
19 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
20 * to the caches and the Sparc MMU mapping.
21 * 2) Make as few routines required outside the generic driver. A lot of the
22 * routines in this file used to be inline!
23 */
24
25#include <linux/module.h>
26
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/delay.h>
30#include <linux/types.h>
31#include <linux/string.h>
32#include <linux/slab.h>
33#include <linux/blkdev.h>
34#include <linux/proc_fs.h>
35#include <linux/stat.h>
36#include <linux/interrupt.h>
37
38#include "scsi.h"
39#include <scsi/scsi_host.h>
40#include "NCR53C9x.h"
41
42#include <linux/zorro.h>
43#include <asm/irq.h>
44
45#include <asm/amigaints.h>
46#include <asm/amigahw.h>
47
48#include <asm/pgtable.h>
49
50/* Such day has just come... */
51#if 0
52/* Let this defined unless you really need to enable DMA IRQ one day */
53#define NODMAIRQ
54#endif
55
56/* The controller registers can be found in the Z2 config area at these
57 * offsets:
58 */
59#define FASTLANE_ESP_ADDR 0x1000001
60#define FASTLANE_DMA_ADDR 0x1000041
61
62
63/* The Fastlane DMA interface */
64struct fastlane_dma_registers {
65 volatile unsigned char cond_reg; /* DMA status (ro) [0x0000] */
66#define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
67 unsigned char dmapad1[0x3f];
68 volatile unsigned char clear_strobe; /* DMA clear (wo) [0x0040] */
69};
70
71
72/* DMA status bits */
73#define FASTLANE_DMA_MINT 0x80
74#define FASTLANE_DMA_IACT 0x40
75#define FASTLANE_DMA_CREQ 0x20
76
77/* DMA control bits */
78#define FASTLANE_DMA_FCODE 0xa0
79#define FASTLANE_DMA_MASK 0xf3
80#define FASTLANE_DMA_LED 0x10 /* HD led control 1 = on */
81#define FASTLANE_DMA_WRITE 0x08 /* 1 = write */
82#define FASTLANE_DMA_ENABLE 0x04 /* Enable DMA */
83#define FASTLANE_DMA_EDI 0x02 /* Enable DMA IRQ ? */
84#define FASTLANE_DMA_ESI 0x01 /* Enable SCSI IRQ */
85
86static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
87static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
88static void dma_dump_state(struct NCR_ESP *esp);
89static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
90static void dma_init_write(struct NCR_ESP *esp, __u32 vaddr, int length);
91static void dma_ints_off(struct NCR_ESP *esp);
92static void dma_ints_on(struct NCR_ESP *esp);
93static int dma_irq_p(struct NCR_ESP *esp);
94static void dma_irq_exit(struct NCR_ESP *esp);
95static void dma_led_off(struct NCR_ESP *esp);
96static void dma_led_on(struct NCR_ESP *esp);
97static int dma_ports_p(struct NCR_ESP *esp);
98static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
99
100static unsigned char ctrl_data = 0; /* Keep backup of the stuff written
101 * to ctrl_reg. Always write a copy
102 * to this register when writing to
103 * the hardware register!
104 */
105
106static volatile unsigned char cmd_buffer[16];
107 /* This is where all commands are put
108 * before they are transferred to the ESP chip
109 * via PIO.
110 */
111
112static inline void dma_clear(struct NCR_ESP *esp)
113{
114 struct fastlane_dma_registers *dregs =
115 (struct fastlane_dma_registers *) (esp->dregs);
116 unsigned long *t;
117
118 ctrl_data = (ctrl_data & FASTLANE_DMA_MASK);
119 dregs->ctrl_reg = ctrl_data;
120
121 t = (unsigned long *)(esp->edev);
122
123 dregs->clear_strobe = 0;
124 *t = 0 ;
125}
126
127/***************************************************************** Detection */
128int __init fastlane_esp_detect(struct scsi_host_template *tpnt)
129{
130 struct NCR_ESP *esp;
131 struct zorro_dev *z = NULL;
132 unsigned long address;
133
134 if ((z = zorro_find_device(ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060, z))) {
135 unsigned long board = z->resource.start;
136 if (request_mem_region(board+FASTLANE_ESP_ADDR,
137 sizeof(struct ESP_regs), "NCR53C9x")) {
138 /* Check if this is really a fastlane controller. The problem
139 * is that also the cyberstorm and blizzard controllers use
140 * this ID value. Fortunately only Fastlane maps in Z3 space
141 */
142 if (board < 0x1000000) {
143 goto err_release;
144 }
145 esp = esp_allocate(tpnt, (void *)board + FASTLANE_ESP_ADDR, 0);
146
147 /* Do command transfer with programmed I/O */
148 esp->do_pio_cmds = 1;
149
150 /* Required functions */
151 esp->dma_bytes_sent = &dma_bytes_sent;
152 esp->dma_can_transfer = &dma_can_transfer;
153 esp->dma_dump_state = &dma_dump_state;
154 esp->dma_init_read = &dma_init_read;
155 esp->dma_init_write = &dma_init_write;
156 esp->dma_ints_off = &dma_ints_off;
157 esp->dma_ints_on = &dma_ints_on;
158 esp->dma_irq_p = &dma_irq_p;
159 esp->dma_ports_p = &dma_ports_p;
160 esp->dma_setup = &dma_setup;
161
162 /* Optional functions */
163 esp->dma_barrier = 0;
164 esp->dma_drain = 0;
165 esp->dma_invalidate = 0;
166 esp->dma_irq_entry = 0;
167 esp->dma_irq_exit = &dma_irq_exit;
168 esp->dma_led_on = &dma_led_on;
169 esp->dma_led_off = &dma_led_off;
170 esp->dma_poll = 0;
171 esp->dma_reset = 0;
172
173 /* Initialize the portBits (enable IRQs) */
174 ctrl_data = (FASTLANE_DMA_FCODE |
175#ifndef NODMAIRQ
176 FASTLANE_DMA_EDI |
177#endif
178 FASTLANE_DMA_ESI);
179
180
181 /* SCSI chip clock */
182 esp->cfreq = 40000000;
183
184
185 /* Map the physical address space into virtual kernel space */
186 address = (unsigned long)
187 z_ioremap(board, z->resource.end-board+1);
188
189 if(!address){
190 printk("Could not remap Fastlane controller memory!");
191 goto err_unregister;
192 }
193
194
195 /* The DMA registers on the Fastlane are mapped
196 * relative to the device (i.e. in the same Zorro
197 * I/O block).
198 */
199 esp->dregs = (void *)(address + FASTLANE_DMA_ADDR);
200
201 /* ESP register base */
202 esp->eregs = (struct ESP_regs *)(address + FASTLANE_ESP_ADDR);
203
204 /* Board base */
205 esp->edev = (void *) address;
206
207 /* Set the command buffer */
208 esp->esp_command = cmd_buffer;
209 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
210
211 esp->irq = IRQ_AMIGA_PORTS;
212 esp->slot = board+FASTLANE_ESP_ADDR;
213 if (request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
214 "Fastlane SCSI", esp->ehost)) {
215 printk(KERN_WARNING "Fastlane: Could not get IRQ%d, aborting.\n", IRQ_AMIGA_PORTS);
216 goto err_unmap;
217 }
218
219 /* Controller ID */
220 esp->scsi_id = 7;
221
222 /* We don't have a differential SCSI-bus. */
223 esp->diff = 0;
224
225 dma_clear(esp);
226 esp_initialize(esp);
227
228 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
229 esps_running = esps_in_use;
230 return esps_in_use;
231 }
232 }
233 return 0;
234
235 err_unmap:
236 z_iounmap((void *)address);
237 err_unregister:
238 scsi_unregister (esp->ehost);
239 err_release:
240 release_mem_region(z->resource.start+FASTLANE_ESP_ADDR,
241 sizeof(struct ESP_regs));
242 return 0;
243}
244
245
246/************************************************************* DMA Functions */
247static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
248{
249 /* Since the Fastlane DMA is fully dedicated to the ESP chip,
250 * the number of bytes sent (to the ESP chip) equals the number
251 * of bytes in the FIFO - there is no buffering in the DMA controller.
252 * XXXX Do I read this right? It is from host to ESP, right?
253 */
254 return fifo_count;
255}
256
257static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
258{
259 unsigned long sz = sp->SCp.this_residual;
260 if(sz > 0xfffc)
261 sz = 0xfffc;
262 return sz;
263}
264
265static void dma_dump_state(struct NCR_ESP *esp)
266{
267 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
268 esp->esp_id, ((struct fastlane_dma_registers *)
269 (esp->dregs))->cond_reg));
270 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
271 amiga_custom.intreqr, amiga_custom.intenar));
272}
273
274static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
275{
276 struct fastlane_dma_registers *dregs =
277 (struct fastlane_dma_registers *) (esp->dregs);
278 unsigned long *t;
279
280 cache_clear(addr, length);
281
282 dma_clear(esp);
283
284 t = (unsigned long *)((addr & 0x00ffffff) + esp->edev);
285
286 dregs->clear_strobe = 0;
287 *t = addr;
288
289 ctrl_data = (ctrl_data & FASTLANE_DMA_MASK) | FASTLANE_DMA_ENABLE;
290 dregs->ctrl_reg = ctrl_data;
291}
292
293static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
294{
295 struct fastlane_dma_registers *dregs =
296 (struct fastlane_dma_registers *) (esp->dregs);
297 unsigned long *t;
298
299 cache_push(addr, length);
300
301 dma_clear(esp);
302
303 t = (unsigned long *)((addr & 0x00ffffff) + (esp->edev));
304
305 dregs->clear_strobe = 0;
306 *t = addr;
307
308 ctrl_data = ((ctrl_data & FASTLANE_DMA_MASK) |
309 FASTLANE_DMA_ENABLE |
310 FASTLANE_DMA_WRITE);
311 dregs->ctrl_reg = ctrl_data;
312}
313
314
315static void dma_ints_off(struct NCR_ESP *esp)
316{
317 disable_irq(esp->irq);
318}
319
320static void dma_ints_on(struct NCR_ESP *esp)
321{
322 enable_irq(esp->irq);
323}
324
325static void dma_irq_exit(struct NCR_ESP *esp)
326{
327 struct fastlane_dma_registers *dregs =
328 (struct fastlane_dma_registers *) (esp->dregs);
329
330 dregs->ctrl_reg = ctrl_data & ~(FASTLANE_DMA_EDI|FASTLANE_DMA_ESI);
331#ifdef __mc68000__
332 nop();
333#endif
334 dregs->ctrl_reg = ctrl_data;
335}
336
337static int dma_irq_p(struct NCR_ESP *esp)
338{
339 struct fastlane_dma_registers *dregs =
340 (struct fastlane_dma_registers *) (esp->dregs);
341 unsigned char dma_status;
342
343 dma_status = dregs->cond_reg;
344
345 if(dma_status & FASTLANE_DMA_IACT)
346 return 0; /* not our IRQ */
347
348 /* Return non-zero if ESP requested IRQ */
349 return (
350#ifndef NODMAIRQ
351 (dma_status & FASTLANE_DMA_CREQ) &&
352#endif
353 (!(dma_status & FASTLANE_DMA_MINT)) &&
354 (esp_read(((struct ESP_regs *) (esp->eregs))->esp_status) & ESP_STAT_INTR));
355}
356
357static void dma_led_off(struct NCR_ESP *esp)
358{
359 ctrl_data &= ~FASTLANE_DMA_LED;
360 ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
361}
362
363static void dma_led_on(struct NCR_ESP *esp)
364{
365 ctrl_data |= FASTLANE_DMA_LED;
366 ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
367}
368
369static int dma_ports_p(struct NCR_ESP *esp)
370{
371 return ((amiga_custom.intenar) & IF_PORTS);
372}
373
374static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
375{
376 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
377 * so when (write) is true, it actually means READ!
378 */
379 if(write){
380 dma_init_read(esp, addr, count);
381 } else {
382 dma_init_write(esp, addr, count);
383 }
384}
385
386#define HOSTS_C
387
388int fastlane_esp_release(struct Scsi_Host *instance)
389{
390#ifdef MODULE
391 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
392 esp_deallocate((struct NCR_ESP *)instance->hostdata);
393 esp_release();
394 release_mem_region(address, sizeof(struct ESP_regs));
395 free_irq(IRQ_AMIGA_PORTS, esp_intr);
396#endif
397 return 1;
398}
399
400
401static struct scsi_host_template driver_template = {
402 .proc_name = "esp-fastlane",
403 .proc_info = esp_proc_info,
404 .name = "Fastlane SCSI",
405 .detect = fastlane_esp_detect,
406 .slave_alloc = esp_slave_alloc,
407 .slave_destroy = esp_slave_destroy,
408 .release = fastlane_esp_release,
409 .queuecommand = esp_queue,
410 .eh_abort_handler = esp_abort,
411 .eh_bus_reset_handler = esp_reset,
412 .can_queue = 7,
413 .this_id = 7,
414 .sg_tablesize = SG_ALL,
415 .cmd_per_lun = 1,
416 .use_clustering = ENABLE_CLUSTERING
417};
418
419#include "scsi_module.c"
420
421MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/mac_esp.c b/drivers/scsi/mac_esp.c
deleted file mode 100644
index bcb49021b7e2..000000000000
--- a/drivers/scsi/mac_esp.c
+++ /dev/null
@@ -1,751 +0,0 @@
1/*
2 * 68k mac 53c9[46] scsi driver
3 *
4 * copyright (c) 1998, David Weis weisd3458@uni.edu
5 *
6 * debugging on Quadra 800 and 660AV Michael Schmitz, Dave Kilzer 7/98
7 *
8 * based loosely on cyber_esp.c
9 */
10
11/* these are unused for now */
12#define myreadl(addr) (*(volatile unsigned int *) (addr))
13#define mywritel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))
14
15
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/types.h>
19#include <linux/ctype.h>
20#include <linux/string.h>
21#include <linux/slab.h>
22#include <linux/blkdev.h>
23#include <linux/proc_fs.h>
24#include <linux/stat.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27
28#include "scsi.h"
29#include <scsi/scsi_host.h>
30#include "NCR53C9x.h"
31
32#include <asm/io.h>
33
34#include <asm/setup.h>
35#include <asm/irq.h>
36#include <asm/macints.h>
37#include <asm/machw.h>
38#include <asm/mac_via.h>
39
40#include <asm/pgtable.h>
41
42#include <asm/macintosh.h>
43
44/* #define DEBUG_MAC_ESP */
45
46extern void esp_handle(struct NCR_ESP *esp);
47extern void mac_esp_intr(int irq, void *dev_id);
48
49static int dma_bytes_sent(struct NCR_ESP * esp, int fifo_count);
50static int dma_can_transfer(struct NCR_ESP * esp, Scsi_Cmnd *sp);
51static void dma_dump_state(struct NCR_ESP * esp);
52static void dma_init_read(struct NCR_ESP * esp, char * vaddress, int length);
53static void dma_init_write(struct NCR_ESP * esp, char * vaddress, int length);
54static void dma_ints_off(struct NCR_ESP * esp);
55static void dma_ints_on(struct NCR_ESP * esp);
56static int dma_irq_p(struct NCR_ESP * esp);
57static int dma_irq_p_quick(struct NCR_ESP * esp);
58static void dma_led_off(struct NCR_ESP * esp);
59static void dma_led_on(struct NCR_ESP *esp);
60static int dma_ports_p(struct NCR_ESP *esp);
61static void dma_setup(struct NCR_ESP * esp, __u32 addr, int count, int write);
62static void dma_setup_quick(struct NCR_ESP * esp, __u32 addr, int count, int write);
63
64static int esp_dafb_dma_irq_p(struct NCR_ESP * espdev);
65static int esp_iosb_dma_irq_p(struct NCR_ESP * espdev);
66
67static volatile unsigned char cmd_buffer[16];
68 /* This is where all commands are put
69 * before they are transferred to the ESP chip
70 * via PIO.
71 */
72
73static int esp_initialized = 0;
74
75static int setup_num_esps = -1;
76static int setup_disconnect = -1;
77static int setup_nosync = -1;
78static int setup_can_queue = -1;
79static int setup_cmd_per_lun = -1;
80static int setup_sg_tablesize = -1;
81#ifdef SUPPORT_TAGS
82static int setup_use_tagged_queuing = -1;
83#endif
84static int setup_hostid = -1;
85
86/*
87 * Experimental ESP inthandler; check macints.c to make sure dev_id is
88 * set up properly!
89 */
90
91void mac_esp_intr(int irq, void *dev_id)
92{
93 struct NCR_ESP *esp = (struct NCR_ESP *) dev_id;
94 int irq_p = 0;
95
96 /* Handle the one ESP interrupt showing at this IRQ level. */
97 if(((esp)->irq & 0xff) == irq) {
98 /*
99 * Debug ..
100 */
101 irq_p = esp->dma_irq_p(esp);
102 printk("mac_esp: irq_p %x current %p disconnected %p\n",
103 irq_p, esp->current_SC, esp->disconnected_SC);
104
105 /*
106 * Mac: if we're here, it's an ESP interrupt for sure!
107 */
108 if((esp->current_SC || esp->disconnected_SC)) {
109 esp->dma_ints_off(esp);
110
111 ESPIRQ(("I%d(", esp->esp_id));
112 esp_handle(esp);
113 ESPIRQ((")"));
114
115 esp->dma_ints_on(esp);
116 }
117 }
118}
119
120/*
121 * Debug hooks; use for playing with the interrupt flag testing and interrupt
122 * acknowledge on the various machines
123 */
124
125void scsi_esp_polled(int irq, void *dev_id)
126{
127 if (esp_initialized == 0)
128 return;
129
130 mac_esp_intr(irq, dev_id);
131}
132
133void fake_intr(int irq, void *dev_id)
134{
135#ifdef DEBUG_MAC_ESP
136 printk("mac_esp: got irq\n");
137#endif
138
139 mac_esp_intr(irq, dev_id);
140}
141
142irqreturn_t fake_drq(int irq, void *dev_id)
143{
144 printk("mac_esp: got drq\n");
145 return IRQ_HANDLED;
146}
147
148#define DRIVER_SETUP
149
150/*
151 * Function : mac_esp_setup(char *str)
152 *
153 * Purpose : booter command line initialization of the overrides array,
154 *
155 * Inputs : str - parameters, separated by commas.
156 *
157 * Currently unused in the new driver; need to add settable parameters to the
158 * detect function.
159 *
160 */
161
162static int __init mac_esp_setup(char *str) {
163#ifdef DRIVER_SETUP
164 /* Format of mac53c9x parameter is:
165 * mac53c9x=<num_esps>,<disconnect>,<nosync>,<can_queue>,<cmd_per_lun>,<sg_tablesize>,<hostid>,<use_tags>
166 * Negative values mean don't change.
167 */
168
169 char *this_opt;
170 long opt;
171
172 this_opt = strsep (&str, ",");
173 if(this_opt) {
174 opt = simple_strtol( this_opt, NULL, 0 );
175
176 if (opt >= 0 && opt <= 2)
177 setup_num_esps = opt;
178 else if (opt > 2)
179 printk( "mac_esp_setup: invalid number of hosts %ld !\n", opt );
180
181 this_opt = strsep (&str, ",");
182 }
183 if(this_opt) {
184 opt = simple_strtol( this_opt, NULL, 0 );
185
186 if (opt > 0)
187 setup_disconnect = opt;
188
189 this_opt = strsep (&str, ",");
190 }
191 if(this_opt) {
192 opt = simple_strtol( this_opt, NULL, 0 );
193
194 if (opt >= 0)
195 setup_nosync = opt;
196
197 this_opt = strsep (&str, ",");
198 }
199 if(this_opt) {
200 opt = simple_strtol( this_opt, NULL, 0 );
201
202 if (opt > 0)
203 setup_can_queue = opt;
204
205 this_opt = strsep (&str, ",");
206 }
207 if(this_opt) {
208 opt = simple_strtol( this_opt, NULL, 0 );
209
210 if (opt > 0)
211 setup_cmd_per_lun = opt;
212
213 this_opt = strsep (&str, ",");
214 }
215 if(this_opt) {
216 opt = simple_strtol( this_opt, NULL, 0 );
217
218 if (opt >= 0) {
219 setup_sg_tablesize = opt;
220 /* Must be <= SG_ALL (255) */
221 if (setup_sg_tablesize > SG_ALL)
222 setup_sg_tablesize = SG_ALL;
223 }
224
225 this_opt = strsep (&str, ",");
226 }
227 if(this_opt) {
228 opt = simple_strtol( this_opt, NULL, 0 );
229
230 /* Must be between 0 and 7 */
231 if (opt >= 0 && opt <= 7)
232 setup_hostid = opt;
233 else if (opt > 7)
234 printk( "mac_esp_setup: invalid host ID %ld !\n", opt);
235
236 this_opt = strsep (&str, ",");
237 }
238#ifdef SUPPORT_TAGS
239 if(this_opt) {
240 opt = simple_strtol( this_opt, NULL, 0 );
241 if (opt >= 0)
242 setup_use_tagged_queuing = !!opt;
243 }
244#endif
245#endif
246 return 1;
247}
248
249__setup("mac53c9x=", mac_esp_setup);
250
251
252/*
253 * ESP address 'detection'
254 */
255
256unsigned long get_base(int chip_num)
257{
258 /*
259 * using the chip_num and mac model, figure out where the
260 * chips are mapped
261 */
262
263 unsigned long io_base = 0x50f00000;
264 unsigned int second_offset = 0x402;
265 unsigned long scsi_loc = 0;
266
267 switch (macintosh_config->scsi_type) {
268
269 /* 950, 900, 700 */
270 case MAC_SCSI_QUADRA2:
271 scsi_loc = io_base + 0xf000 + ((chip_num == 0) ? 0 : second_offset);
272 break;
273
274 /* av's */
275 case MAC_SCSI_QUADRA3:
276 scsi_loc = io_base + 0x18000 + ((chip_num == 0) ? 0 : second_offset);
277 break;
278
279 /* most quadra/centris models are like this */
280 case MAC_SCSI_QUADRA:
281 scsi_loc = io_base + 0x10000;
282 break;
283
284 default:
285 printk("mac_esp: get_base: hit default!\n");
286 scsi_loc = io_base + 0x10000;
287 break;
288
289 } /* switch */
290
291 printk("mac_esp: io base at 0x%lx\n", scsi_loc);
292
293 return scsi_loc;
294}
295
296/*
297 * Model dependent ESP setup
298 */
299
300int mac_esp_detect(struct scsi_host_template * tpnt)
301{
302 int quick = 0;
303 int chipnum, chipspresent = 0;
304#if 0
305 unsigned long timeout;
306#endif
307
308 if (esp_initialized > 0)
309 return -ENODEV;
310
311 /* what do we have in this machine... */
312 if (MACHW_PRESENT(MAC_SCSI_96)) {
313 chipspresent ++;
314 }
315
316 if (MACHW_PRESENT(MAC_SCSI_96_2)) {
317 chipspresent ++;
318 }
319
320 /* number of ESPs present ? */
321 if (setup_num_esps >= 0) {
322 if (chipspresent >= setup_num_esps)
323 chipspresent = setup_num_esps;
324 else
325 printk("mac_esp_detect: num_hosts detected %d setup %d \n",
326 chipspresent, setup_num_esps);
327 }
328
329 /* TODO: add disconnect / nosync flags */
330
331 /* setup variables */
332 tpnt->can_queue =
333 (setup_can_queue > 0) ? setup_can_queue : 7;
334 tpnt->cmd_per_lun =
335 (setup_cmd_per_lun > 0) ? setup_cmd_per_lun : 1;
336 tpnt->sg_tablesize =
337 (setup_sg_tablesize >= 0) ? setup_sg_tablesize : SG_ALL;
338
339 if (setup_hostid >= 0)
340 tpnt->this_id = setup_hostid;
341 else {
342 /* use 7 as default */
343 tpnt->this_id = 7;
344 }
345
346#ifdef SUPPORT_TAGS
347 if (setup_use_tagged_queuing < 0)
348 setup_use_tagged_queuing = DEFAULT_USE_TAGGED_QUEUING;
349#endif
350
351 for (chipnum = 0; chipnum < chipspresent; chipnum ++) {
352 struct NCR_ESP * esp;
353
354 esp = esp_allocate(tpnt, NULL, 0);
355 esp->eregs = (struct ESP_regs *) get_base(chipnum);
356
357 esp->dma_irq_p = &esp_dafb_dma_irq_p;
358 if (chipnum == 0) {
359
360 if (macintosh_config->scsi_type == MAC_SCSI_QUADRA) {
361 /* most machines except those below :-) */
362 quick = 1;
363 esp->dma_irq_p = &esp_iosb_dma_irq_p;
364 } else if (macintosh_config->scsi_type == MAC_SCSI_QUADRA3) {
365 /* mostly av's */
366 quick = 0;
367 } else {
368 /* q950, 900, 700 */
369 quick = 1;
370 out_be32(0xf9800024, 0x1d1);
371 esp->dregs = (void *) 0xf9800024;
372 }
373
374 } else { /* chipnum */
375
376 quick = 1;
377 out_be32(0xf9800028, 0x1d1);
378 esp->dregs = (void *) 0xf9800028;
379
380 } /* chipnum == 0 */
381
382 /* use pio for command bytes; pio for message/data: TBI */
383 esp->do_pio_cmds = 1;
384
385 /* Set the command buffer */
386 esp->esp_command = (volatile unsigned char*) cmd_buffer;
387 esp->esp_command_dvma = (__u32) cmd_buffer;
388
389 /* various functions */
390 esp->dma_bytes_sent = &dma_bytes_sent;
391 esp->dma_can_transfer = &dma_can_transfer;
392 esp->dma_dump_state = &dma_dump_state;
393 esp->dma_init_read = NULL;
394 esp->dma_init_write = NULL;
395 esp->dma_ints_off = &dma_ints_off;
396 esp->dma_ints_on = &dma_ints_on;
397
398 esp->dma_ports_p = &dma_ports_p;
399
400
401 /* Optional functions */
402 esp->dma_barrier = NULL;
403 esp->dma_drain = NULL;
404 esp->dma_invalidate = NULL;
405 esp->dma_irq_entry = NULL;
406 esp->dma_irq_exit = NULL;
407 esp->dma_led_on = NULL;
408 esp->dma_led_off = NULL;
409 esp->dma_poll = NULL;
410 esp->dma_reset = NULL;
411
412 /* SCSI chip speed */
413 /* below esp->cfreq = 40000000; */
414
415
416 if (quick) {
417 /* 'quick' means there's handshake glue logic like in the 5380 case */
418 esp->dma_setup = &dma_setup_quick;
419 } else {
420 esp->dma_setup = &dma_setup;
421 }
422
423 if (chipnum == 0) {
424
425 esp->irq = IRQ_MAC_SCSI;
426
427 request_irq(IRQ_MAC_SCSI, esp_intr, 0, "Mac ESP SCSI", esp->ehost);
428#if 0 /* conflicts with IOP ADB */
429 request_irq(IRQ_MAC_SCSIDRQ, fake_drq, 0, "Mac ESP DRQ", esp->ehost);
430#endif
431
432 if (macintosh_config->scsi_type == MAC_SCSI_QUADRA) {
433 esp->cfreq = 16500000;
434 } else {
435 esp->cfreq = 25000000;
436 }
437
438
439 } else { /* chipnum == 1 */
440
441 esp->irq = IRQ_MAC_SCSIDRQ;
442#if 0 /* conflicts with IOP ADB */
443 request_irq(IRQ_MAC_SCSIDRQ, esp_intr, 0, "Mac ESP SCSI 2", esp->ehost);
444#endif
445
446 esp->cfreq = 25000000;
447
448 }
449
450 if (quick) {
451 printk("esp: using quick version\n");
452 }
453
454 printk("esp: addr at 0x%p\n", esp->eregs);
455
456 esp->scsi_id = 7;
457 esp->diff = 0;
458
459 esp_initialize(esp);
460
461 } /* for chipnum */
462
463 if (chipspresent)
464 printk("\nmac_esp: %d esp controllers found\n", chipspresent);
465
466 esp_initialized = chipspresent;
467
468 return chipspresent;
469}
470
471static int mac_esp_release(struct Scsi_Host *shost)
472{
473 if (shost->irq)
474 free_irq(shost->irq, NULL);
475 if (shost->io_port && shost->n_io_port)
476 release_region(shost->io_port, shost->n_io_port);
477 scsi_unregister(shost);
478 return 0;
479}
480
481/*
482 * I've been wondering what this is supposed to do, for some time. Talking
483 * to Allen Briggs: These machines have an extra register someplace where the
484 * DRQ pin of the ESP can be monitored. That isn't useful for determining
485 * anything else (such as reselect interrupt or other magic) though.
486 * Maybe make the semantics should be changed like
487 * if (esp->current_SC)
488 * ... check DRQ flag ...
489 * else
490 * ... disconnected, check pending VIA interrupt ...
491 *
492 * There's a problem with using the dabf flag or mac_irq_pending() here: both
493 * seem to return 1 even though no interrupt is currently pending, resulting
494 * in esp_exec_cmd() holding off the next command, and possibly infinite loops
495 * in esp_intr().
496 * Short term fix: just use esp_status & ESP_STAT_INTR here, as long as we
497 * use simple PIO. The DRQ status will be important when implementing pseudo
498 * DMA mode (set up ESP transfer count, return, do a batch of bytes in PIO or
499 * 'hardware handshake' mode upon DRQ).
500 * If you plan on changing this (i.e. to save the esp_status register access in
501 * favor of a VIA register access or a shadow register for the IFR), make sure
502 * to try a debug version of this first to monitor what registers would be a good
503 * indicator of the ESP interrupt.
504 */
505
506static int esp_dafb_dma_irq_p(struct NCR_ESP * esp)
507{
508 unsigned int ret;
509 int sreg = esp_read(esp->eregs->esp_status);
510
511#ifdef DEBUG_MAC_ESP
512 printk("mac_esp: esp_dafb_dma_irq_p dafb %d irq %d\n",
513 readl(esp->dregs), mac_irq_pending(IRQ_MAC_SCSI));
514#endif
515
516 sreg &= ESP_STAT_INTR;
517
518 /*
519 * maybe working; this is essentially what's used for iosb_dma_irq_p
520 */
521 if (sreg)
522 return 1;
523 else
524 return 0;
525
526 /*
527 * didn't work ...
528 */
529#if 0
530 if (esp->current_SC)
531 ret = readl(esp->dregs) & 0x200;
532 else if (esp->disconnected_SC)
533 ret = 1; /* sreg ?? */
534 else
535 ret = mac_irq_pending(IRQ_MAC_SCSI);
536
537 return(ret);
538#endif
539
540}
541
542/*
543 * See above: testing mac_irq_pending always returned 8 (SCSI IRQ) regardless
544 * of the actual ESP status.
545 */
546
547static int esp_iosb_dma_irq_p(struct NCR_ESP * esp)
548{
549 int ret = mac_irq_pending(IRQ_MAC_SCSI) || mac_irq_pending(IRQ_MAC_SCSIDRQ);
550 int sreg = esp_read(esp->eregs->esp_status);
551
552#ifdef DEBUG_MAC_ESP
553 printk("mac_esp: dma_irq_p drq %d irq %d sreg %x curr %p disc %p\n",
554 mac_irq_pending(IRQ_MAC_SCSIDRQ), mac_irq_pending(IRQ_MAC_SCSI),
555 sreg, esp->current_SC, esp->disconnected_SC);
556#endif
557
558 sreg &= ESP_STAT_INTR;
559
560 if (sreg)
561 return (sreg);
562 else
563 return 0;
564}
565
566/*
567 * This seems to be OK for PIO at least ... usually 0 after PIO.
568 */
569
570static int dma_bytes_sent(struct NCR_ESP * esp, int fifo_count)
571{
572
573#ifdef DEBUG_MAC_ESP
574 printk("mac_esp: dma bytes sent = %x\n", fifo_count);
575#endif
576
577 return fifo_count;
578}
579
580/*
581 * dma_can_transfer is used to switch between DMA and PIO, if DMA (pseudo)
582 * is ever implemented. Returning 0 here will use PIO.
583 */
584
585static int dma_can_transfer(struct NCR_ESP * esp, Scsi_Cmnd * sp)
586{
587 unsigned long sz = sp->SCp.this_residual;
588#if 0 /* no DMA yet; make conditional */
589 if (sz > 0x10000000) {
590 sz = 0x10000000;
591 }
592 printk("mac_esp: dma can transfer = 0lx%x\n", sz);
593#else
594
595#ifdef DEBUG_MAC_ESP
596 printk("mac_esp: pio to transfer = %ld\n", sz);
597#endif
598
599 sz = 0;
600#endif
601 return sz;
602}
603
604/*
605 * Not yet ...
606 */
607
608static void dma_dump_state(struct NCR_ESP * esp)
609{
610#ifdef DEBUG_MAC_ESP
611 printk("mac_esp: dma_dump_state: called\n");
612#endif
613#if 0
614 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
615 esp->esp_id, ((struct mac_dma_registers *)
616 (esp->dregs))->cond_reg));
617#endif
618}
619
620/*
621 * DMA setup: should be used to set up the ESP transfer count for pseudo
622 * DMA transfers; need a DRQ transfer function to do the actual transfer
623 */
624
625static void dma_init_read(struct NCR_ESP * esp, char * vaddress, int length)
626{
627 printk("mac_esp: dma_init_read\n");
628}
629
630
631static void dma_init_write(struct NCR_ESP * esp, char * vaddress, int length)
632{
633 printk("mac_esp: dma_init_write\n");
634}
635
636
637static void dma_ints_off(struct NCR_ESP * esp)
638{
639 disable_irq(esp->irq);
640}
641
642
643static void dma_ints_on(struct NCR_ESP * esp)
644{
645 enable_irq(esp->irq);
646}
647
648/*
649 * generic dma_irq_p(), unused
650 */
651
652static int dma_irq_p(struct NCR_ESP * esp)
653{
654 int i = esp_read(esp->eregs->esp_status);
655
656#ifdef DEBUG_MAC_ESP
657 printk("mac_esp: dma_irq_p status %d\n", i);
658#endif
659
660 return (i & ESP_STAT_INTR);
661}
662
663static int dma_irq_p_quick(struct NCR_ESP * esp)
664{
665 /*
666 * Copied from iosb_dma_irq_p()
667 */
668 int ret = mac_irq_pending(IRQ_MAC_SCSI) || mac_irq_pending(IRQ_MAC_SCSIDRQ);
669 int sreg = esp_read(esp->eregs->esp_status);
670
671#ifdef DEBUG_MAC_ESP
672 printk("mac_esp: dma_irq_p drq %d irq %d sreg %x curr %p disc %p\n",
673 mac_irq_pending(IRQ_MAC_SCSIDRQ), mac_irq_pending(IRQ_MAC_SCSI),
674 sreg, esp->current_SC, esp->disconnected_SC);
675#endif
676
677 sreg &= ESP_STAT_INTR;
678
679 if (sreg)
680 return (sreg);
681 else
682 return 0;
683
684}
685
686static void dma_led_off(struct NCR_ESP * esp)
687{
688#ifdef DEBUG_MAC_ESP
689 printk("mac_esp: dma_led_off: called\n");
690#endif
691}
692
693
694static void dma_led_on(struct NCR_ESP * esp)
695{
696#ifdef DEBUG_MAC_ESP
697 printk("mac_esp: dma_led_on: called\n");
698#endif
699}
700
701
702static int dma_ports_p(struct NCR_ESP * esp)
703{
704 return 0;
705}
706
707
708static void dma_setup(struct NCR_ESP * esp, __u32 addr, int count, int write)
709{
710
711#ifdef DEBUG_MAC_ESP
712 printk("mac_esp: dma_setup\n");
713#endif
714
715 if (write) {
716 dma_init_read(esp, (char *) addr, count);
717 } else {
718 dma_init_write(esp, (char *) addr, count);
719 }
720}
721
722
723static void dma_setup_quick(struct NCR_ESP * esp, __u32 addr, int count, int write)
724{
725#ifdef DEBUG_MAC_ESP
726 printk("mac_esp: dma_setup_quick\n");
727#endif
728}
729
730static struct scsi_host_template driver_template = {
731 .proc_name = "mac_esp",
732 .name = "Mac 53C9x SCSI",
733 .detect = mac_esp_detect,
734 .slave_alloc = esp_slave_alloc,
735 .slave_destroy = esp_slave_destroy,
736 .release = mac_esp_release,
737 .info = esp_info,
738 .queuecommand = esp_queue,
739 .eh_abort_handler = esp_abort,
740 .eh_bus_reset_handler = esp_reset,
741 .can_queue = 7,
742 .this_id = 7,
743 .sg_tablesize = SG_ALL,
744 .cmd_per_lun = 1,
745 .use_clustering = DISABLE_CLUSTERING
746};
747
748
749#include "scsi_module.c"
750
751MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/oktagon_esp.c b/drivers/scsi/oktagon_esp.c
deleted file mode 100644
index 8e5eadbd5c51..000000000000
--- a/drivers/scsi/oktagon_esp.c
+++ /dev/null
@@ -1,606 +0,0 @@
1/*
2 * Oktagon_esp.c -- Driver for bsc Oktagon
3 *
4 * Written by Carsten Pluntke 1998
5 *
6 * Based on cyber_esp.c
7 */
8
9
10#if defined(CONFIG_AMIGA) || defined(CONFIG_APUS)
11#define USE_BOTTOM_HALF
12#endif
13
14#include <linux/module.h>
15
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/types.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/blkdev.h>
22#include <linux/proc_fs.h>
23#include <linux/stat.h>
24#include <linux/reboot.h>
25#include <asm/system.h>
26#include <asm/ptrace.h>
27#include <asm/pgtable.h>
28
29
30#include "scsi.h"
31#include <scsi/scsi_host.h>
32#include "NCR53C9x.h"
33
34#include <linux/zorro.h>
35#include <asm/irq.h>
36#include <asm/amigaints.h>
37#include <asm/amigahw.h>
38
39#ifdef USE_BOTTOM_HALF
40#include <linux/workqueue.h>
41#include <linux/interrupt.h>
42#endif
43
44/* The controller registers can be found in the Z2 config area at these
45 * offsets:
46 */
47#define OKTAGON_ESP_ADDR 0x03000
48#define OKTAGON_DMA_ADDR 0x01000
49
50
51static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
52static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
53static void dma_dump_state(struct NCR_ESP *esp);
54static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length);
55static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length);
56static void dma_ints_off(struct NCR_ESP *esp);
57static void dma_ints_on(struct NCR_ESP *esp);
58static int dma_irq_p(struct NCR_ESP *esp);
59static void dma_led_off(struct NCR_ESP *esp);
60static void dma_led_on(struct NCR_ESP *esp);
61static int dma_ports_p(struct NCR_ESP *esp);
62static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
63
64static void dma_irq_exit(struct NCR_ESP *esp);
65static void dma_invalidate(struct NCR_ESP *esp);
66
67static void dma_mmu_get_scsi_one(struct NCR_ESP *,Scsi_Cmnd *);
68static void dma_mmu_get_scsi_sgl(struct NCR_ESP *,Scsi_Cmnd *);
69static void dma_mmu_release_scsi_one(struct NCR_ESP *,Scsi_Cmnd *);
70static void dma_mmu_release_scsi_sgl(struct NCR_ESP *,Scsi_Cmnd *);
71static void dma_advance_sg(Scsi_Cmnd *);
72static int oktagon_notify_reboot(struct notifier_block *this, unsigned long code, void *x);
73
74#ifdef USE_BOTTOM_HALF
75static void dma_commit(struct work_struct *unused);
76
77long oktag_to_io(long *paddr, long *addr, long len);
78long oktag_from_io(long *addr, long *paddr, long len);
79
80static DECLARE_WORK(tq_fake_dma, dma_commit);
81
82#define DMA_MAXTRANSFER 0x8000
83
84#else
85
86/*
87 * No bottom half. Use transfer directly from IRQ. Find a narrow path
88 * between too much IRQ overhead and clogging the IRQ for too long.
89 */
90
91#define DMA_MAXTRANSFER 0x1000
92
93#endif
94
95static struct notifier_block oktagon_notifier = {
96 oktagon_notify_reboot,
97 NULL,
98 0
99};
100
101static long *paddress;
102static long *address;
103static long len;
104static long dma_on;
105static int direction;
106static struct NCR_ESP *current_esp;
107
108
109static volatile unsigned char cmd_buffer[16];
110 /* This is where all commands are put
111 * before they are trasfered to the ESP chip
112 * via PIO.
113 */
114
115/***************************************************************** Detection */
116int oktagon_esp_detect(struct scsi_host_template *tpnt)
117{
118 struct NCR_ESP *esp;
119 struct zorro_dev *z = NULL;
120 unsigned long address;
121 struct ESP_regs *eregs;
122
123 while ((z = zorro_find_device(ZORRO_PROD_BSC_OKTAGON_2008, z))) {
124 unsigned long board = z->resource.start;
125 if (request_mem_region(board+OKTAGON_ESP_ADDR,
126 sizeof(struct ESP_regs), "NCR53C9x")) {
127 /*
128 * It is a SCSI controller.
129 * Hardwire Host adapter to SCSI ID 7
130 */
131
132 address = (unsigned long)ZTWO_VADDR(board);
133 eregs = (struct ESP_regs *)(address + OKTAGON_ESP_ADDR);
134
135 /* This line was 5 lines lower */
136 esp = esp_allocate(tpnt, (void *)board + OKTAGON_ESP_ADDR, 0);
137
138 /* we have to shift the registers only one bit for oktagon */
139 esp->shift = 1;
140
141 esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
142 udelay(5);
143 if (esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7))
144 return 0; /* Bail out if address did not hold data */
145
146 /* Do command transfer with programmed I/O */
147 esp->do_pio_cmds = 1;
148
149 /* Required functions */
150 esp->dma_bytes_sent = &dma_bytes_sent;
151 esp->dma_can_transfer = &dma_can_transfer;
152 esp->dma_dump_state = &dma_dump_state;
153 esp->dma_init_read = &dma_init_read;
154 esp->dma_init_write = &dma_init_write;
155 esp->dma_ints_off = &dma_ints_off;
156 esp->dma_ints_on = &dma_ints_on;
157 esp->dma_irq_p = &dma_irq_p;
158 esp->dma_ports_p = &dma_ports_p;
159 esp->dma_setup = &dma_setup;
160
161 /* Optional functions */
162 esp->dma_barrier = 0;
163 esp->dma_drain = 0;
164 esp->dma_invalidate = &dma_invalidate;
165 esp->dma_irq_entry = 0;
166 esp->dma_irq_exit = &dma_irq_exit;
167 esp->dma_led_on = &dma_led_on;
168 esp->dma_led_off = &dma_led_off;
169 esp->dma_poll = 0;
170 esp->dma_reset = 0;
171
172 esp->dma_mmu_get_scsi_one = &dma_mmu_get_scsi_one;
173 esp->dma_mmu_get_scsi_sgl = &dma_mmu_get_scsi_sgl;
174 esp->dma_mmu_release_scsi_one = &dma_mmu_release_scsi_one;
175 esp->dma_mmu_release_scsi_sgl = &dma_mmu_release_scsi_sgl;
176 esp->dma_advance_sg = &dma_advance_sg;
177
178 /* SCSI chip speed */
179 /* Looking at the quartz of the SCSI board... */
180 esp->cfreq = 25000000;
181
182 /* The DMA registers on the CyberStorm are mapped
183 * relative to the device (i.e. in the same Zorro
184 * I/O block).
185 */
186 esp->dregs = (void *)(address + OKTAGON_DMA_ADDR);
187
188 paddress = (long *) esp->dregs;
189
190 /* ESP register base */
191 esp->eregs = eregs;
192
193 /* Set the command buffer */
194 esp->esp_command = (volatile unsigned char*) cmd_buffer;
195
196 /* Yes, the virtual address. See below. */
197 esp->esp_command_dvma = (__u32) cmd_buffer;
198
199 esp->irq = IRQ_AMIGA_PORTS;
200 request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
201 "BSC Oktagon SCSI", esp->ehost);
202
203 /* Figure out our scsi ID on the bus */
204 esp->scsi_id = 7;
205
206 /* We don't have a differential SCSI-bus. */
207 esp->diff = 0;
208
209 esp_initialize(esp);
210
211 printk("ESP_Oktagon Driver 1.1"
212#ifdef USE_BOTTOM_HALF
213 " [BOTTOM_HALF]"
214#else
215 " [IRQ]"
216#endif
217 " registered.\n");
218 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps,esps_in_use);
219 esps_running = esps_in_use;
220 current_esp = esp;
221 register_reboot_notifier(&oktagon_notifier);
222 return esps_in_use;
223 }
224 }
225 return 0;
226}
227
228
229/*
230 * On certain configurations the SCSI equipment gets confused on reboot,
231 * so we have to reset it then.
232 */
233
234static int
235oktagon_notify_reboot(struct notifier_block *this, unsigned long code, void *x)
236{
237 struct NCR_ESP *esp;
238
239 if((code == SYS_DOWN || code == SYS_HALT) && (esp = current_esp))
240 {
241 esp_bootup_reset(esp,esp->eregs);
242 udelay(500); /* Settle time. Maybe unnecessary. */
243 }
244 return NOTIFY_DONE;
245}
246
247
248
249#ifdef USE_BOTTOM_HALF
250
251
252/*
253 * The bsc Oktagon controller has no real DMA, so we have to do the 'DMA
254 * transfer' in the interrupt (Yikes!) or use a bottom half to not to clutter
255 * IRQ's for longer-than-good.
256 *
257 * FIXME
258 * BIG PROBLEM: 'len' is usually the buffer length, not the expected length
259 * of the data. So DMA may finish prematurely, further reads lead to
260 * 'machine check' on APUS systems (don't know about m68k systems, AmigaOS
261 * deliberately ignores the bus faults) and a normal copy-loop can't
262 * be exited prematurely just at the right moment by the dma_invalidate IRQ.
263 * So do it the hard way, write an own copier in assembler and
264 * catch the exception.
265 * -- Carsten
266 */
267
268
269static void dma_commit(struct work_struct *unused)
270{
271 long wait,len2,pos;
272 struct NCR_ESP *esp;
273
274 ESPDATA(("Transfer: %ld bytes, Address 0x%08lX, Direction: %d\n",
275 len,(long) address,direction));
276 dma_ints_off(current_esp);
277
278 pos = 0;
279 wait = 1;
280 if(direction) /* write? (memory to device) */
281 {
282 while(len > 0)
283 {
284 len2 = oktag_to_io(paddress, address+pos, len);
285 if(!len2)
286 {
287 if(wait > 1000)
288 {
289 printk("Expedited DMA exit (writing) %ld\n",len);
290 break;
291 }
292 mdelay(wait);
293 wait *= 2;
294 }
295 pos += len2;
296 len -= len2*sizeof(long);
297 }
298 } else {
299 while(len > 0)
300 {
301 len2 = oktag_from_io(address+pos, paddress, len);
302 if(!len2)
303 {
304 if(wait > 1000)
305 {
306 printk("Expedited DMA exit (reading) %ld\n",len);
307 break;
308 }
309 mdelay(wait);
310 wait *= 2;
311 }
312 pos += len2;
313 len -= len2*sizeof(long);
314 }
315 }
316
317 /* to make esp->shift work */
318 esp=current_esp;
319
320#if 0
321 len2 = (esp_read(current_esp->eregs->esp_tclow) & 0xff) |
322 ((esp_read(current_esp->eregs->esp_tcmed) & 0xff) << 8);
323
324 /*
325 * Uh uh. If you see this, len and transfer count registers were out of
326 * sync. That means really serious trouble.
327 */
328
329 if(len2)
330 printk("Eeeek!! Transfer count still %ld!\n",len2);
331#endif
332
333 /*
334 * Normally we just need to exit and wait for the interrupt to come.
335 * But at least one device (my Microtek ScanMaker 630) regularly mis-
336 * calculates the bytes it should send which is really ugly because
337 * it locks up the SCSI bus if not accounted for.
338 */
339
340 if(!(esp_read(current_esp->eregs->esp_status) & ESP_STAT_INTR))
341 {
342 long len = 100;
343 long trash[10];
344
345 /*
346 * Interrupt bit was not set. Either the device is just plain lazy
347 * so we give it a 10 ms chance or...
348 */
349 while(len-- && (!(esp_read(current_esp->eregs->esp_status) & ESP_STAT_INTR)))
350 udelay(100);
351
352
353 if(!(esp_read(current_esp->eregs->esp_status) & ESP_STAT_INTR))
354 {
355 /*
356 * So we think that the transfer count is out of sync. Since we
357 * have all we want we are happy and can ditch the trash.
358 */
359
360 len = DMA_MAXTRANSFER;
361
362 while(len-- && (!(esp_read(current_esp->eregs->esp_status) & ESP_STAT_INTR)))
363 oktag_from_io(trash,paddress,2);
364
365 if(!(esp_read(current_esp->eregs->esp_status) & ESP_STAT_INTR))
366 {
367 /*
368 * Things really have gone wrong. If we leave the system in that
369 * state, the SCSI bus is locked forever. I hope that this will
370 * turn the system in a more or less running state.
371 */
372 printk("Device is bolixed, trying bus reset...\n");
373 esp_bootup_reset(current_esp,current_esp->eregs);
374 }
375 }
376 }
377
378 ESPDATA(("Transfer_finale: do_data_finale should come\n"));
379
380 len = 0;
381 dma_on = 0;
382 dma_ints_on(current_esp);
383}
384
385#endif
386
387/************************************************************* DMA Functions */
388static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
389{
390 /* Since the CyberStorm DMA is fully dedicated to the ESP chip,
391 * the number of bytes sent (to the ESP chip) equals the number
392 * of bytes in the FIFO - there is no buffering in the DMA controller.
393 * XXXX Do I read this right? It is from host to ESP, right?
394 */
395 return fifo_count;
396}
397
398static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
399{
400 unsigned long sz = sp->SCp.this_residual;
401 if(sz > DMA_MAXTRANSFER)
402 sz = DMA_MAXTRANSFER;
403 return sz;
404}
405
406static void dma_dump_state(struct NCR_ESP *esp)
407{
408}
409
410/*
411 * What the f$@& is this?
412 *
413 * Some SCSI devices (like my Microtek ScanMaker 630 scanner) want to transfer
414 * more data than requested. How much? Dunno. So ditch the bogus data into
415 * the sink, hoping the device will advance to the next phase sooner or later.
416 *
417 * -- Carsten
418 */
419
420static long oktag_eva_buffer[16]; /* The data sink */
421
422static void oktag_check_dma(void)
423{
424 struct NCR_ESP *esp;
425
426 esp=current_esp;
427 if(!len)
428 {
429 address = oktag_eva_buffer;
430 len = 2;
431 /* esp_do_data sets them to zero like len */
432 esp_write(current_esp->eregs->esp_tclow,2);
433 esp_write(current_esp->eregs->esp_tcmed,0);
434 }
435}
436
437static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length)
438{
439 /* Zorro is noncached, everything else done using processor. */
440 /* cache_clear(addr, length); */
441
442 if(dma_on)
443 panic("dma_init_read while dma process is initialized/running!\n");
444 direction = 0;
445 address = (long *) vaddress;
446 current_esp = esp;
447 len = length;
448 oktag_check_dma();
449 dma_on = 1;
450}
451
452static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length)
453{
454 /* cache_push(addr, length); */
455
456 if(dma_on)
457 panic("dma_init_write while dma process is initialized/running!\n");
458 direction = 1;
459 address = (long *) vaddress;
460 current_esp = esp;
461 len = length;
462 oktag_check_dma();
463 dma_on = 1;
464}
465
466static void dma_ints_off(struct NCR_ESP *esp)
467{
468 disable_irq(esp->irq);
469}
470
471static void dma_ints_on(struct NCR_ESP *esp)
472{
473 enable_irq(esp->irq);
474}
475
476static int dma_irq_p(struct NCR_ESP *esp)
477{
478 /* It's important to check the DMA IRQ bit in the correct way! */
479 return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
480}
481
482static void dma_led_off(struct NCR_ESP *esp)
483{
484}
485
486static void dma_led_on(struct NCR_ESP *esp)
487{
488}
489
490static int dma_ports_p(struct NCR_ESP *esp)
491{
492 return ((amiga_custom.intenar) & IF_PORTS);
493}
494
495static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
496{
497 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
498 * so when (write) is true, it actually means READ!
499 */
500 if(write){
501 dma_init_read(esp, addr, count);
502 } else {
503 dma_init_write(esp, addr, count);
504 }
505}
506
507/*
508 * IRQ entry when DMA transfer is ready to be started
509 */
510
511static void dma_irq_exit(struct NCR_ESP *esp)
512{
513#ifdef USE_BOTTOM_HALF
514 if(dma_on)
515 {
516 schedule_work(&tq_fake_dma);
517 }
518#else
519 while(len && !dma_irq_p(esp))
520 {
521 if(direction)
522 *paddress = *address++;
523 else
524 *address++ = *paddress;
525 len -= (sizeof(long));
526 }
527 len = 0;
528 dma_on = 0;
529#endif
530}
531
532/*
533 * IRQ entry when DMA has just finished
534 */
535
536static void dma_invalidate(struct NCR_ESP *esp)
537{
538}
539
540/*
541 * Since the processor does the data transfer we have to use the custom
542 * mmu interface to pass the virtual address, not the physical.
543 */
544
545void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd *sp)
546{
547 sp->SCp.ptr =
548 sp->request_buffer;
549}
550
551void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd *sp)
552{
553 sp->SCp.ptr = sg_virt(sp->SCp.buffer);
554}
555
556void dma_mmu_release_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd *sp)
557{
558}
559
560void dma_mmu_release_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd *sp)
561{
562}
563
564void dma_advance_sg(Scsi_Cmnd *sp)
565{
566 sp->SCp.ptr = sg_virt(sp->SCp.buffer);
567}
568
569
570#define HOSTS_C
571
572int oktagon_esp_release(struct Scsi_Host *instance)
573{
574#ifdef MODULE
575 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
576 esp_release();
577 release_mem_region(address, sizeof(struct ESP_regs));
578 free_irq(IRQ_AMIGA_PORTS, esp_intr);
579 unregister_reboot_notifier(&oktagon_notifier);
580#endif
581 return 1;
582}
583
584
585static struct scsi_host_template driver_template = {
586 .proc_name = "esp-oktagon",
587 .proc_info = &esp_proc_info,
588 .name = "BSC Oktagon SCSI",
589 .detect = oktagon_esp_detect,
590 .slave_alloc = esp_slave_alloc,
591 .slave_destroy = esp_slave_destroy,
592 .release = oktagon_esp_release,
593 .queuecommand = esp_queue,
594 .eh_abort_handler = esp_abort,
595 .eh_bus_reset_handler = esp_reset,
596 .can_queue = 7,
597 .this_id = 7,
598 .sg_tablesize = SG_ALL,
599 .cmd_per_lun = 1,
600 .use_clustering = ENABLE_CLUSTERING
601};
602
603
604#include "scsi_module.c"
605
606MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/oktagon_io.S b/drivers/scsi/oktagon_io.S
deleted file mode 100644
index 8a7340b02707..000000000000
--- a/drivers/scsi/oktagon_io.S
+++ /dev/null
@@ -1,194 +0,0 @@
1/* -*- mode: asm -*-
2 * Due to problems while transferring data I've put these routines as assembly
3 * code.
4 * Since I'm no PPC assembler guru, the code is just the assembler version of
5
6int oktag_to_io(long *paddr,long *addr,long len)
7{
8 long *addr2 = addr;
9 for(len=(len+sizeof(long)-1)/sizeof(long);len--;)
10 *paddr = *addr2++;
11 return addr2 - addr;
12}
13
14int oktag_from_io(long *addr,long *paddr,long len)
15{
16 long *addr2 = addr;
17 for(len=(len+sizeof(long)-1)/sizeof(long);len--;)
18 *addr2++ = *paddr;
19 return addr2 - addr;
20}
21
22 * assembled using gcc -O2 -S, with two exception catch points where data
23 * is moved to/from the IO register.
24 */
25
26
27#ifdef CONFIG_APUS
28
29 .file "oktagon_io.c"
30
31gcc2_compiled.:
32/*
33 .section ".text"
34*/
35 .align 2
36 .globl oktag_to_io
37 .type oktag_to_io,@function
38oktag_to_io:
39 addi 5,5,3
40 srwi 5,5,2
41 cmpwi 1,5,0
42 mr 9,3
43 mr 3,4
44 addi 5,5,-1
45 bc 12,6,.L3
46.L5:
47 cmpwi 1,5,0
48 lwz 0,0(3)
49 addi 3,3,4
50 addi 5,5,-1
51exp1: stw 0,0(9)
52 bc 4,6,.L5
53.L3:
54ret1: subf 3,4,3
55 srawi 3,3,2
56 blr
57.Lfe1:
58 .size oktag_to_io,.Lfe1-oktag_to_io
59 .align 2
60 .globl oktag_from_io
61 .type oktag_from_io,@function
62oktag_from_io:
63 addi 5,5,3
64 srwi 5,5,2
65 cmpwi 1,5,0
66 mr 9,3
67 addi 5,5,-1
68 bc 12,6,.L9
69.L11:
70 cmpwi 1,5,0
71exp2: lwz 0,0(4)
72 addi 5,5,-1
73 stw 0,0(3)
74 addi 3,3,4
75 bc 4,6,.L11
76.L9:
77ret2: subf 3,9,3
78 srawi 3,3,2
79 blr
80.Lfe2:
81 .size oktag_from_io,.Lfe2-oktag_from_io
82 .ident "GCC: (GNU) egcs-2.90.29 980515 (egcs-1.0.3 release)"
83
84/*
85 * Exception table.
86 * Second longword shows where to jump when an exception at the addr the first
87 * longword is pointing to is caught.
88 */
89
90.section __ex_table,"a"
91 .align 2
92oktagon_except:
93 .long exp1,ret1
94 .long exp2,ret2
95
96#else
97
98/*
99The code which follows is for 680x0 based assembler and is meant for
100Linux/m68k. It was created by cross compiling the code using the
101instructions given above. I then added the four labels used in the
102exception handler table at the bottom of this file.
103- Kevin <kcozens@interlog.com>
104*/
105
106#ifdef CONFIG_AMIGA
107
108 .file "oktagon_io.c"
109 .version "01.01"
110gcc2_compiled.:
111.text
112 .align 2
113.globl oktag_to_io
114 .type oktag_to_io,@function
115oktag_to_io:
116 link.w %a6,#0
117 move.l %d2,-(%sp)
118 move.l 8(%a6),%a1
119 move.l 12(%a6),%d1
120 move.l %d1,%a0
121 move.l 16(%a6),%d0
122 addq.l #3,%d0
123 lsr.l #2,%d0
124 subq.l #1,%d0
125 moveq.l #-1,%d2
126 cmp.l %d0,%d2
127 jbeq .L3
128.L5:
129exp1:
130 move.l (%a0)+,(%a1)
131 dbra %d0,.L5
132 clr.w %d0
133 subq.l #1,%d0
134 jbcc .L5
135.L3:
136ret1:
137 move.l %a0,%d0
138 sub.l %d1,%d0
139 asr.l #2,%d0
140 move.l -4(%a6),%d2
141 unlk %a6
142 rts
143
144.Lfe1:
145 .size oktag_to_io,.Lfe1-oktag_to_io
146 .align 2
147.globl oktag_from_io
148 .type oktag_from_io,@function
149oktag_from_io:
150 link.w %a6,#0
151 move.l %d2,-(%sp)
152 move.l 8(%a6),%d1
153 move.l 12(%a6),%a1
154 move.l %d1,%a0
155 move.l 16(%a6),%d0
156 addq.l #3,%d0
157 lsr.l #2,%d0
158 subq.l #1,%d0
159 moveq.l #-1,%d2
160 cmp.l %d0,%d2
161 jbeq .L9
162.L11:
163exp2:
164 move.l (%a1),(%a0)+
165 dbra %d0,.L11
166 clr.w %d0
167 subq.l #1,%d0
168 jbcc .L11
169.L9:
170ret2:
171 move.l %a0,%d0
172 sub.l %d1,%d0
173 asr.l #2,%d0
174 move.l -4(%a6),%d2
175 unlk %a6
176 rts
177.Lfe2:
178 .size oktag_from_io,.Lfe2-oktag_from_io
179 .ident "GCC: (GNU) 2.7.2.1"
180
181/*
182 * Exception table.
183 * Second longword shows where to jump when an exception at the addr the first
184 * longword is pointing to is caught.
185 */
186
187.section __ex_table,"a"
188 .align 2
189oktagon_except:
190 .long exp1,ret1
191 .long exp2,ret2
192
193#endif
194#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 06:43:45 -0500