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authorPaul Mackerras <paulus@samba.org>2007-04-29 22:38:01 -0400
committerPaul Mackerras <paulus@samba.org>2007-04-29 22:38:01 -0400
commit49e1900d4cc2e7bcecb681fe60f0990bec2dcce8 (patch)
tree253801ebf57e0a23856a2c7be129c2c178f62fdf /drivers/scsi
parent34f6d749c0a328817d5e36274e53121c1db734dc (diff)
parentb9099ff63c75216d6ca10bce5a1abcd9293c27e6 (diff)
Merge branch 'linux-2.6' into for-2.6.22
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/3w-xxxx.c11
-rw-r--r--drivers/scsi/Kconfig6
-rw-r--r--drivers/scsi/Makefile3
-rw-r--r--drivers/scsi/esp.c4394
-rw-r--r--drivers/scsi/esp.h406
-rw-r--r--drivers/scsi/esp_scsi.c2711
-rw-r--r--drivers/scsi/esp_scsi.h560
-rw-r--r--drivers/scsi/hosts.c4
-rw-r--r--drivers/scsi/qlogicpti.c4
-rw-r--r--drivers/scsi/scsi_netlink.c5
-rw-r--r--drivers/scsi/scsi_transport_iscsi.c4
-rw-r--r--drivers/scsi/sun_esp.c634
12 files changed, 3931 insertions, 4811 deletions
diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c
index bf5d63e1beee..656bdb1352d8 100644
--- a/drivers/scsi/3w-xxxx.c
+++ b/drivers/scsi/3w-xxxx.c
@@ -1864,10 +1864,17 @@ static int tw_scsiop_read_write(TW_Device_Extension *tw_dev, int request_id)
1864/* This function will handle the request sense scsi command */ 1864/* This function will handle the request sense scsi command */
1865static int tw_scsiop_request_sense(TW_Device_Extension *tw_dev, int request_id) 1865static int tw_scsiop_request_sense(TW_Device_Extension *tw_dev, int request_id)
1866{ 1866{
1867 char request_buffer[18];
1868
1867 dprintk(KERN_NOTICE "3w-xxxx: tw_scsiop_request_sense()\n"); 1869 dprintk(KERN_NOTICE "3w-xxxx: tw_scsiop_request_sense()\n");
1868 1870
1869 /* For now we just zero the request buffer */ 1871 memset(request_buffer, 0, sizeof(request_buffer));
1870 memset(tw_dev->srb[request_id]->request_buffer, 0, tw_dev->srb[request_id]->request_bufflen); 1872 request_buffer[0] = 0x70; /* Immediate fixed format */
1873 request_buffer[7] = 10; /* minimum size per SPC: 18 bytes */
1874 /* leave all other fields zero, giving effectively NO_SENSE return */
1875 tw_transfer_internal(tw_dev, request_id, request_buffer,
1876 sizeof(request_buffer));
1877
1871 tw_dev->state[request_id] = TW_S_COMPLETED; 1878 tw_dev->state[request_id] = TW_S_COMPLETED;
1872 tw_state_request_finish(tw_dev, request_id); 1879 tw_state_request_finish(tw_dev, request_id);
1873 1880
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 4cd280e86966..fcc4cb6c7f46 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -1763,9 +1763,15 @@ config SUN3X_ESP
1763 The ESP was an on-board SCSI controller used on Sun 3/80 1763 The ESP was an on-board SCSI controller used on Sun 3/80
1764 machines. Say Y here to compile in support for it. 1764 machines. Say Y here to compile in support for it.
1765 1765
1766config SCSI_ESP_CORE
1767 tristate "ESP Scsi Driver Core"
1768 depends on SCSI
1769 select SCSI_SPI_ATTRS
1770
1766config SCSI_SUNESP 1771config SCSI_SUNESP
1767 tristate "Sparc ESP Scsi Driver" 1772 tristate "Sparc ESP Scsi Driver"
1768 depends on SBUS && SCSI 1773 depends on SBUS && SCSI
1774 select SCSI_ESP_CORE
1769 help 1775 help
1770 This is the driver for the Sun ESP SCSI host adapter. The ESP 1776 This is the driver for the Sun ESP SCSI host adapter. The ESP
1771 chipset is present in most SPARC SBUS-based computers. 1777 chipset is present in most SPARC SBUS-based computers.
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 79ecf4ebe6eb..70cff4c599d7 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -106,7 +106,8 @@ obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o
106obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/ 106obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/
107obj-$(CONFIG_MEGARAID_SAS) += megaraid/ 107obj-$(CONFIG_MEGARAID_SAS) += megaraid/
108obj-$(CONFIG_SCSI_ACARD) += atp870u.o 108obj-$(CONFIG_SCSI_ACARD) += atp870u.o
109obj-$(CONFIG_SCSI_SUNESP) += esp.o 109obj-$(CONFIG_SCSI_ESP_CORE) += esp_scsi.o
110obj-$(CONFIG_SCSI_SUNESP) += sun_esp.o
110obj-$(CONFIG_SCSI_GDTH) += gdth.o 111obj-$(CONFIG_SCSI_GDTH) += gdth.o
111obj-$(CONFIG_SCSI_INITIO) += initio.o 112obj-$(CONFIG_SCSI_INITIO) += initio.o
112obj-$(CONFIG_SCSI_INIA100) += a100u2w.o 113obj-$(CONFIG_SCSI_INIA100) += a100u2w.o
diff --git a/drivers/scsi/esp.c b/drivers/scsi/esp.c
deleted file mode 100644
index 2c2fe80bc42a..000000000000
--- a/drivers/scsi/esp.c
+++ /dev/null
@@ -1,4394 +0,0 @@
1/* esp.c: ESP Sun SCSI driver.
2 *
3 * Copyright (C) 1995, 1998, 2006 David S. Miller (davem@davemloft.net)
4 */
5
6/* TODO:
7 *
8 * 1) Maybe disable parity checking in config register one for SCSI1
9 * targets. (Gilmore says parity error on the SBus can lock up
10 * old sun4c's)
11 * 2) Add support for DMA2 pipelining.
12 * 3) Add tagged queueing.
13 */
14
15#include <linux/kernel.h>
16#include <linux/delay.h>
17#include <linux/types.h>
18#include <linux/string.h>
19#include <linux/slab.h>
20#include <linux/blkdev.h>
21#include <linux/proc_fs.h>
22#include <linux/stat.h>
23#include <linux/init.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h>
26#include <linux/module.h>
27
28#include "esp.h"
29
30#include <asm/sbus.h>
31#include <asm/dma.h>
32#include <asm/system.h>
33#include <asm/ptrace.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#ifndef __sparc_v9__
39#include <asm/machines.h>
40#include <asm/idprom.h>
41#endif
42
43#include <scsi/scsi.h>
44#include <scsi/scsi_cmnd.h>
45#include <scsi/scsi_device.h>
46#include <scsi/scsi_eh.h>
47#include <scsi/scsi_host.h>
48#include <scsi/scsi_tcq.h>
49
50#define DRV_VERSION "1.101"
51
52#define DEBUG_ESP
53/* #define DEBUG_ESP_HME */
54/* #define DEBUG_ESP_DATA */
55/* #define DEBUG_ESP_QUEUE */
56/* #define DEBUG_ESP_DISCONNECT */
57/* #define DEBUG_ESP_STATUS */
58/* #define DEBUG_ESP_PHASES */
59/* #define DEBUG_ESP_WORKBUS */
60/* #define DEBUG_STATE_MACHINE */
61/* #define DEBUG_ESP_CMDS */
62/* #define DEBUG_ESP_IRQS */
63/* #define DEBUG_SDTR */
64/* #define DEBUG_ESP_SG */
65
66/* Use the following to sprinkle debugging messages in a way which
67 * suits you if combinations of the above become too verbose when
68 * trying to track down a specific problem.
69 */
70/* #define DEBUG_ESP_MISC */
71
72#if defined(DEBUG_ESP)
73#define ESPLOG(foo) printk foo
74#else
75#define ESPLOG(foo)
76#endif /* (DEBUG_ESP) */
77
78#if defined(DEBUG_ESP_HME)
79#define ESPHME(foo) printk foo
80#else
81#define ESPHME(foo)
82#endif
83
84#if defined(DEBUG_ESP_DATA)
85#define ESPDATA(foo) printk foo
86#else
87#define ESPDATA(foo)
88#endif
89
90#if defined(DEBUG_ESP_QUEUE)
91#define ESPQUEUE(foo) printk foo
92#else
93#define ESPQUEUE(foo)
94#endif
95
96#if defined(DEBUG_ESP_DISCONNECT)
97#define ESPDISC(foo) printk foo
98#else
99#define ESPDISC(foo)
100#endif
101
102#if defined(DEBUG_ESP_STATUS)
103#define ESPSTAT(foo) printk foo
104#else
105#define ESPSTAT(foo)
106#endif
107
108#if defined(DEBUG_ESP_PHASES)
109#define ESPPHASE(foo) printk foo
110#else
111#define ESPPHASE(foo)
112#endif
113
114#if defined(DEBUG_ESP_WORKBUS)
115#define ESPBUS(foo) printk foo
116#else
117#define ESPBUS(foo)
118#endif
119
120#if defined(DEBUG_ESP_IRQS)
121#define ESPIRQ(foo) printk foo
122#else
123#define ESPIRQ(foo)
124#endif
125
126#if defined(DEBUG_SDTR)
127#define ESPSDTR(foo) printk foo
128#else
129#define ESPSDTR(foo)
130#endif
131
132#if defined(DEBUG_ESP_MISC)
133#define ESPMISC(foo) printk foo
134#else
135#define ESPMISC(foo)
136#endif
137
138/* Command phase enumeration. */
139enum {
140 not_issued = 0x00, /* Still in the issue_SC queue. */
141
142 /* Various forms of selecting a target. */
143#define in_slct_mask 0x10
144 in_slct_norm = 0x10, /* ESP is arbitrating, normal selection */
145 in_slct_stop = 0x11, /* ESP will select, then stop with IRQ */
146 in_slct_msg = 0x12, /* select, then send a message */
147 in_slct_tag = 0x13, /* select and send tagged queue msg */
148 in_slct_sneg = 0x14, /* select and acquire sync capabilities */
149
150 /* Any post selection activity. */
151#define in_phases_mask 0x20
152 in_datain = 0x20, /* Data is transferring from the bus */
153 in_dataout = 0x21, /* Data is transferring to the bus */
154 in_data_done = 0x22, /* Last DMA data operation done (maybe) */
155 in_msgin = 0x23, /* Eating message from target */
156 in_msgincont = 0x24, /* Eating more msg bytes from target */
157 in_msgindone = 0x25, /* Decide what to do with what we got */
158 in_msgout = 0x26, /* Sending message to target */
159 in_msgoutdone = 0x27, /* Done sending msg out */
160 in_cmdbegin = 0x28, /* Sending cmd after abnormal selection */
161 in_cmdend = 0x29, /* Done sending slow cmd */
162 in_status = 0x2a, /* Was in status phase, finishing cmd */
163 in_freeing = 0x2b, /* freeing the bus for cmd cmplt or disc */
164 in_the_dark = 0x2c, /* Don't know what bus phase we are in */
165
166 /* Special states, ie. not normal bus transitions... */
167#define in_spec_mask 0x80
168 in_abortone = 0x80, /* Aborting one command currently */
169 in_abortall = 0x81, /* Blowing away all commands we have */
170 in_resetdev = 0x82, /* SCSI target reset in progress */
171 in_resetbus = 0x83, /* SCSI bus reset in progress */
172 in_tgterror = 0x84, /* Target did something stupid */
173};
174
175enum {
176 /* Zero has special meaning, see skipahead[12]. */
177/*0*/ do_never,
178
179/*1*/ do_phase_determine,
180/*2*/ do_reset_bus,
181/*3*/ do_reset_complete,
182/*4*/ do_work_bus,
183/*5*/ do_intr_end
184};
185
186/* Forward declarations. */
187static irqreturn_t esp_intr(int irq, void *dev_id);
188
189/* Debugging routines */
190struct esp_cmdstrings {
191 u8 cmdchar;
192 char *text;
193} esp_cmd_strings[] = {
194 /* Miscellaneous */
195 { ESP_CMD_NULL, "ESP_NOP", },
196 { ESP_CMD_FLUSH, "FIFO_FLUSH", },
197 { ESP_CMD_RC, "RSTESP", },
198 { ESP_CMD_RS, "RSTSCSI", },
199 /* Disconnected State Group */
200 { ESP_CMD_RSEL, "RESLCTSEQ", },
201 { ESP_CMD_SEL, "SLCTNATN", },
202 { ESP_CMD_SELA, "SLCTATN", },
203 { ESP_CMD_SELAS, "SLCTATNSTOP", },
204 { ESP_CMD_ESEL, "ENSLCTRESEL", },
205 { ESP_CMD_DSEL, "DISSELRESEL", },
206 { ESP_CMD_SA3, "SLCTATN3", },
207 { ESP_CMD_RSEL3, "RESLCTSEQ", },
208 /* Target State Group */
209 { ESP_CMD_SMSG, "SNDMSG", },
210 { ESP_CMD_SSTAT, "SNDSTATUS", },
211 { ESP_CMD_SDATA, "SNDDATA", },
212 { ESP_CMD_DSEQ, "DISCSEQ", },
213 { ESP_CMD_TSEQ, "TERMSEQ", },
214 { ESP_CMD_TCCSEQ, "TRGTCMDCOMPSEQ", },
215 { ESP_CMD_DCNCT, "DISC", },
216 { ESP_CMD_RMSG, "RCVMSG", },
217 { ESP_CMD_RCMD, "RCVCMD", },
218 { ESP_CMD_RDATA, "RCVDATA", },
219 { ESP_CMD_RCSEQ, "RCVCMDSEQ", },
220 /* Initiator State Group */
221 { ESP_CMD_TI, "TRANSINFO", },
222 { ESP_CMD_ICCSEQ, "INICMDSEQCOMP", },
223 { ESP_CMD_MOK, "MSGACCEPTED", },
224 { ESP_CMD_TPAD, "TPAD", },
225 { ESP_CMD_SATN, "SATN", },
226 { ESP_CMD_RATN, "RATN", },
227};
228#define NUM_ESP_COMMANDS ((sizeof(esp_cmd_strings)) / (sizeof(struct esp_cmdstrings)))
229
230/* Print textual representation of an ESP command */
231static inline void esp_print_cmd(u8 espcmd)
232{
233 u8 dma_bit = espcmd & ESP_CMD_DMA;
234 int i;
235
236 espcmd &= ~dma_bit;
237 for (i = 0; i < NUM_ESP_COMMANDS; i++)
238 if (esp_cmd_strings[i].cmdchar == espcmd)
239 break;
240 if (i == NUM_ESP_COMMANDS)
241 printk("ESP_Unknown");
242 else
243 printk("%s%s", esp_cmd_strings[i].text,
244 ((dma_bit) ? "+DMA" : ""));
245}
246
247/* Print the status register's value */
248static inline void esp_print_statreg(u8 statreg)
249{
250 u8 phase;
251
252 printk("STATUS<");
253 phase = statreg & ESP_STAT_PMASK;
254 printk("%s,", (phase == ESP_DOP ? "DATA-OUT" :
255 (phase == ESP_DIP ? "DATA-IN" :
256 (phase == ESP_CMDP ? "COMMAND" :
257 (phase == ESP_STATP ? "STATUS" :
258 (phase == ESP_MOP ? "MSG-OUT" :
259 (phase == ESP_MIP ? "MSG_IN" :
260 "unknown")))))));
261 if (statreg & ESP_STAT_TDONE)
262 printk("TRANS_DONE,");
263 if (statreg & ESP_STAT_TCNT)
264 printk("TCOUNT_ZERO,");
265 if (statreg & ESP_STAT_PERR)
266 printk("P_ERROR,");
267 if (statreg & ESP_STAT_SPAM)
268 printk("SPAM,");
269 if (statreg & ESP_STAT_INTR)
270 printk("IRQ,");
271 printk(">");
272}
273
274/* Print the interrupt register's value */
275static inline void esp_print_ireg(u8 intreg)
276{
277 printk("INTREG< ");
278 if (intreg & ESP_INTR_S)
279 printk("SLCT_NATN ");
280 if (intreg & ESP_INTR_SATN)
281 printk("SLCT_ATN ");
282 if (intreg & ESP_INTR_RSEL)
283 printk("RSLCT ");
284 if (intreg & ESP_INTR_FDONE)
285 printk("FDONE ");
286 if (intreg & ESP_INTR_BSERV)
287 printk("BSERV ");
288 if (intreg & ESP_INTR_DC)
289 printk("DISCNCT ");
290 if (intreg & ESP_INTR_IC)
291 printk("ILL_CMD ");
292 if (intreg & ESP_INTR_SR)
293 printk("SCSI_BUS_RESET ");
294 printk(">");
295}
296
297/* Print the sequence step registers contents */
298static inline void esp_print_seqreg(u8 stepreg)
299{
300 stepreg &= ESP_STEP_VBITS;
301 printk("STEP<%s>",
302 (stepreg == ESP_STEP_ASEL ? "SLCT_ARB_CMPLT" :
303 (stepreg == ESP_STEP_SID ? "1BYTE_MSG_SENT" :
304 (stepreg == ESP_STEP_NCMD ? "NOT_IN_CMD_PHASE" :
305 (stepreg == ESP_STEP_PPC ? "CMD_BYTES_LOST" :
306 (stepreg == ESP_STEP_FINI4 ? "CMD_SENT_OK" :
307 "UNKNOWN"))))));
308}
309
310static char *phase_string(int phase)
311{
312 switch (phase) {
313 case not_issued:
314 return "UNISSUED";
315 case in_slct_norm:
316 return "SLCTNORM";
317 case in_slct_stop:
318 return "SLCTSTOP";
319 case in_slct_msg:
320 return "SLCTMSG";
321 case in_slct_tag:
322 return "SLCTTAG";
323 case in_slct_sneg:
324 return "SLCTSNEG";
325 case in_datain:
326 return "DATAIN";
327 case in_dataout:
328 return "DATAOUT";
329 case in_data_done:
330 return "DATADONE";
331 case in_msgin:
332 return "MSGIN";
333 case in_msgincont:
334 return "MSGINCONT";
335 case in_msgindone:
336 return "MSGINDONE";
337 case in_msgout:
338 return "MSGOUT";
339 case in_msgoutdone:
340 return "MSGOUTDONE";
341 case in_cmdbegin:
342 return "CMDBEGIN";
343 case in_cmdend:
344 return "CMDEND";
345 case in_status:
346 return "STATUS";
347 case in_freeing:
348 return "FREEING";
349 case in_the_dark:
350 return "CLUELESS";
351 case in_abortone:
352 return "ABORTONE";
353 case in_abortall:
354 return "ABORTALL";
355 case in_resetdev:
356 return "RESETDEV";
357 case in_resetbus:
358 return "RESETBUS";
359 case in_tgterror:
360 return "TGTERROR";
361 default:
362 return "UNKNOWN";
363 };
364}
365
366#ifdef DEBUG_STATE_MACHINE
367static inline void esp_advance_phase(struct scsi_cmnd *s, int newphase)
368{
369 ESPLOG(("<%s>", phase_string(newphase)));
370 s->SCp.sent_command = s->SCp.phase;
371 s->SCp.phase = newphase;
372}
373#else
374#define esp_advance_phase(__s, __newphase) \
375 (__s)->SCp.sent_command = (__s)->SCp.phase; \
376 (__s)->SCp.phase = (__newphase);
377#endif
378
379#ifdef DEBUG_ESP_CMDS
380static inline void esp_cmd(struct esp *esp, u8 cmd)
381{
382 esp->espcmdlog[esp->espcmdent] = cmd;
383 esp->espcmdent = (esp->espcmdent + 1) & 31;
384 sbus_writeb(cmd, esp->eregs + ESP_CMD);
385}
386#else
387#define esp_cmd(__esp, __cmd) \
388 sbus_writeb((__cmd), ((__esp)->eregs) + ESP_CMD)
389#endif
390
391#define ESP_INTSOFF(__dregs) \
392 sbus_writel(sbus_readl((__dregs)+DMA_CSR)&~(DMA_INT_ENAB), (__dregs)+DMA_CSR)
393#define ESP_INTSON(__dregs) \
394 sbus_writel(sbus_readl((__dregs)+DMA_CSR)|DMA_INT_ENAB, (__dregs)+DMA_CSR)
395#define ESP_IRQ_P(__dregs) \
396 (sbus_readl((__dregs)+DMA_CSR) & (DMA_HNDL_INTR|DMA_HNDL_ERROR))
397
398/* How we use the various Linux SCSI data structures for operation.
399 *
400 * struct scsi_cmnd:
401 *
402 * We keep track of the synchronous capabilities of a target
403 * in the device member, using sync_min_period and
404 * sync_max_offset. These are the values we directly write
405 * into the ESP registers while running a command. If offset
406 * is zero the ESP will use asynchronous transfers.
407 * If the borken flag is set we assume we shouldn't even bother
408 * trying to negotiate for synchronous transfer as this target
409 * is really stupid. If we notice the target is dropping the
410 * bus, and we have been allowing it to disconnect, we clear
411 * the disconnect flag.
412 */
413
414
415/* Manipulation of the ESP command queues. Thanks to the aha152x driver
416 * and its author, Juergen E. Fischer, for the methods used here.
417 * Note that these are per-ESP queues, not global queues like
418 * the aha152x driver uses.
419 */
420static inline void append_SC(struct scsi_cmnd **SC, struct scsi_cmnd *new_SC)
421{
422 struct scsi_cmnd *end;
423
424 new_SC->host_scribble = (unsigned char *) NULL;
425 if (!*SC)
426 *SC = new_SC;
427 else {
428 for (end=*SC;end->host_scribble;end=(struct scsi_cmnd *)end->host_scribble)
429 ;
430 end->host_scribble = (unsigned char *) new_SC;
431 }
432}
433
434static inline void prepend_SC(struct scsi_cmnd **SC, struct scsi_cmnd *new_SC)
435{
436 new_SC->host_scribble = (unsigned char *) *SC;
437 *SC = new_SC;
438}
439
440static inline struct scsi_cmnd *remove_first_SC(struct scsi_cmnd **SC)
441{
442 struct scsi_cmnd *ptr;
443 ptr = *SC;
444 if (ptr)
445 *SC = (struct scsi_cmnd *) (*SC)->host_scribble;
446 return ptr;
447}
448
449static inline struct scsi_cmnd *remove_SC(struct scsi_cmnd **SC, int target, int lun)
450{
451 struct scsi_cmnd *ptr, *prev;
452
453 for (ptr = *SC, prev = NULL;
454 ptr && ((ptr->device->id != target) || (ptr->device->lun != lun));
455 prev = ptr, ptr = (struct scsi_cmnd *) ptr->host_scribble)
456 ;
457 if (ptr) {
458 if (prev)
459 prev->host_scribble=ptr->host_scribble;
460 else
461 *SC=(struct scsi_cmnd *)ptr->host_scribble;
462 }
463 return ptr;
464}
465
466/* Resetting various pieces of the ESP scsi driver chipset/buses. */
467static void esp_reset_dma(struct esp *esp)
468{
469 int can_do_burst16, can_do_burst32, can_do_burst64;
470 int can_do_sbus64;
471 u32 tmp;
472
473 can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
474 can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
475 can_do_burst64 = 0;
476 can_do_sbus64 = 0;
477 if (sbus_can_dma_64bit(esp->sdev))
478 can_do_sbus64 = 1;
479 if (sbus_can_burst64(esp->sdev))
480 can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
481
482 /* Punt the DVMA into a known state. */
483 if (esp->dma->revision != dvmahme) {
484 tmp = sbus_readl(esp->dregs + DMA_CSR);
485 sbus_writel(tmp | DMA_RST_SCSI, esp->dregs + DMA_CSR);
486 sbus_writel(tmp & ~DMA_RST_SCSI, esp->dregs + DMA_CSR);
487 }
488 switch (esp->dma->revision) {
489 case dvmahme:
490 /* This is the HME DVMA gate array. */
491
492 sbus_writel(DMA_RESET_FAS366, esp->dregs + DMA_CSR);
493 sbus_writel(DMA_RST_SCSI, esp->dregs + DMA_CSR);
494
495 esp->prev_hme_dmacsr = (DMA_PARITY_OFF|DMA_2CLKS|DMA_SCSI_DISAB|DMA_INT_ENAB);
496 esp->prev_hme_dmacsr &= ~(DMA_ENABLE|DMA_ST_WRITE|DMA_BRST_SZ);
497
498 if (can_do_burst64)
499 esp->prev_hme_dmacsr |= DMA_BRST64;
500 else if (can_do_burst32)
501 esp->prev_hme_dmacsr |= DMA_BRST32;
502
503 if (can_do_sbus64) {
504 esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
505 sbus_set_sbus64(esp->sdev, esp->bursts);
506 }
507
508 /* This chip is horrible. */
509 while (sbus_readl(esp->dregs + DMA_CSR) & DMA_PEND_READ)
510 udelay(1);
511
512 sbus_writel(0, esp->dregs + DMA_CSR);
513 sbus_writel(esp->prev_hme_dmacsr, esp->dregs + DMA_CSR);
514
515 /* This is necessary to avoid having the SCSI channel
516 * engine lock up on us.
517 */
518 sbus_writel(0, esp->dregs + DMA_ADDR);
519
520 break;
521 case dvmarev2:
522 /* This is the gate array found in the sun4m
523 * NCR SBUS I/O subsystem.
524 */
525 if (esp->erev != esp100) {
526 tmp = sbus_readl(esp->dregs + DMA_CSR);
527 sbus_writel(tmp | DMA_3CLKS, esp->dregs + DMA_CSR);
528 }
529 break;
530 case dvmarev3:
531 tmp = sbus_readl(esp->dregs + DMA_CSR);
532 tmp &= ~DMA_3CLKS;
533 tmp |= DMA_2CLKS;
534 if (can_do_burst32) {
535 tmp &= ~DMA_BRST_SZ;
536 tmp |= DMA_BRST32;
537 }
538 sbus_writel(tmp, esp->dregs + DMA_CSR);
539 break;
540 case dvmaesc1:
541 /* This is the DMA unit found on SCSI/Ether cards. */
542 tmp = sbus_readl(esp->dregs + DMA_CSR);
543 tmp |= DMA_ADD_ENABLE;
544 tmp &= ~DMA_BCNT_ENAB;
545 if (!can_do_burst32 && can_do_burst16) {
546 tmp |= DMA_ESC_BURST;
547 } else {
548 tmp &= ~(DMA_ESC_BURST);
549 }
550 sbus_writel(tmp, esp->dregs + DMA_CSR);
551 break;
552 default:
553 break;
554 };
555 ESP_INTSON(esp->dregs);
556}
557
558/* Reset the ESP chip, _not_ the SCSI bus. */
559static void __init esp_reset_esp(struct esp *esp)
560{
561 u8 family_code, version;
562 int i;
563
564 /* Now reset the ESP chip */
565 esp_cmd(esp, ESP_CMD_RC);
566 esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
567 esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
568
569 /* Reload the configuration registers */
570 sbus_writeb(esp->cfact, esp->eregs + ESP_CFACT);
571 esp->prev_stp = 0;
572 sbus_writeb(esp->prev_stp, esp->eregs + ESP_STP);
573 esp->prev_soff = 0;
574 sbus_writeb(esp->prev_soff, esp->eregs + ESP_SOFF);
575 sbus_writeb(esp->neg_defp, esp->eregs + ESP_TIMEO);
576
577 /* This is the only point at which it is reliable to read
578 * the ID-code for a fast ESP chip variants.
579 */
580 esp->max_period = ((35 * esp->ccycle) / 1000);
581 if (esp->erev == fast) {
582 version = sbus_readb(esp->eregs + ESP_UID);
583 family_code = (version & 0xf8) >> 3;
584 if (family_code == 0x02)
585 esp->erev = fas236;
586 else if (family_code == 0x0a)
587 esp->erev = fashme; /* Version is usually '5'. */
588 else
589 esp->erev = fas100a;
590 ESPMISC(("esp%d: FAST chip is %s (family=%d, version=%d)\n",
591 esp->esp_id,
592 (esp->erev == fas236) ? "fas236" :
593 ((esp->erev == fas100a) ? "fas100a" :
594 "fasHME"), family_code, (version & 7)));
595
596 esp->min_period = ((4 * esp->ccycle) / 1000);
597 } else {
598 esp->min_period = ((5 * esp->ccycle) / 1000);
599 }
600 esp->max_period = (esp->max_period + 3)>>2;
601 esp->min_period = (esp->min_period + 3)>>2;
602
603 sbus_writeb(esp->config1, esp->eregs + ESP_CFG1);
604 switch (esp->erev) {
605 case esp100:
606 /* nothing to do */
607 break;
608 case esp100a:
609 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
610 break;
611 case esp236:
612 /* Slow 236 */
613 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
614 esp->prev_cfg3 = esp->config3[0];
615 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
616 break;
617 case fashme:
618 esp->config2 |= (ESP_CONFIG2_HME32 | ESP_CONFIG2_HMEFENAB);
619 /* fallthrough... */
620 case fas236:
621 /* Fast 236 or HME */
622 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
623 for (i = 0; i < 16; i++) {
624 if (esp->erev == fashme) {
625 u8 cfg3;
626
627 cfg3 = ESP_CONFIG3_FCLOCK | ESP_CONFIG3_OBPUSH;
628 if (esp->scsi_id >= 8)
629 cfg3 |= ESP_CONFIG3_IDBIT3;
630 esp->config3[i] |= cfg3;
631 } else {
632 esp->config3[i] |= ESP_CONFIG3_FCLK;
633 }
634 }
635 esp->prev_cfg3 = esp->config3[0];
636 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
637 if (esp->erev == fashme) {
638 esp->radelay = 80;
639 } else {
640 if (esp->diff)
641 esp->radelay = 0;
642 else
643 esp->radelay = 96;
644 }
645 break;
646 case fas100a:
647 /* Fast 100a */
648 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
649 for (i = 0; i < 16; i++)
650 esp->config3[i] |= ESP_CONFIG3_FCLOCK;
651 esp->prev_cfg3 = esp->config3[0];
652 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
653 esp->radelay = 32;
654 break;
655 default:
656 panic("esp: what could it be... I wonder...");
657 break;
658 };
659
660 /* Eat any bitrot in the chip */
661 sbus_readb(esp->eregs + ESP_INTRPT);
662 udelay(100);
663}
664
665/* This places the ESP into a known state at boot time. */
666static void __init esp_bootup_reset(struct esp *esp)
667{
668 u8 tmp;
669
670 /* Reset the DMA */
671 esp_reset_dma(esp);
672
673 /* Reset the ESP */
674 esp_reset_esp(esp);
675
676 /* Reset the SCSI bus, but tell ESP not to generate an irq */
677 tmp = sbus_readb(esp->eregs + ESP_CFG1);
678 tmp |= ESP_CONFIG1_SRRDISAB;
679 sbus_writeb(tmp, esp->eregs + ESP_CFG1);
680
681 esp_cmd(esp, ESP_CMD_RS);
682 udelay(400);
683
684 sbus_writeb(esp->config1, esp->eregs + ESP_CFG1);
685
686 /* Eat any bitrot in the chip and we are done... */
687 sbus_readb(esp->eregs + ESP_INTRPT);
688}
689
690static int __init esp_find_dvma(struct esp *esp, struct sbus_dev *dma_sdev)
691{
692 struct sbus_dev *sdev = esp->sdev;
693 struct sbus_dma *dma;
694
695 if (dma_sdev != NULL) {
696 for_each_dvma(dma) {
697 if (dma->sdev == dma_sdev)
698 break;
699 }
700 } else {
701 for_each_dvma(dma) {
702 /* If allocated already, can't use it. */
703 if (dma->allocated)
704 continue;
705
706 if (dma->sdev == NULL)
707 break;
708
709 /* If bus + slot are the same and it has the
710 * correct OBP name, it's ours.
711 */
712 if (sdev->bus == dma->sdev->bus &&
713 sdev->slot == dma->sdev->slot &&
714 (!strcmp(dma->sdev->prom_name, "dma") ||
715 !strcmp(dma->sdev->prom_name, "espdma")))
716 break;
717 }
718 }
719
720 /* If we don't know how to handle the dvma,
721 * do not use this device.
722 */
723 if (dma == NULL) {
724 printk("Cannot find dvma for ESP%d's SCSI\n", esp->esp_id);
725 return -1;
726 }
727 if (dma->allocated) {
728 printk("esp%d: can't use my espdma\n", esp->esp_id);
729 return -1;
730 }
731 dma->allocated = 1;
732 esp->dma = dma;
733 esp->dregs = dma->regs;
734
735 return 0;
736}
737
738static int __init esp_map_regs(struct esp *esp, int hme)
739{
740 struct sbus_dev *sdev = esp->sdev;
741 struct resource *res;
742
743 /* On HME, two reg sets exist, first is DVMA,
744 * second is ESP registers.
745 */
746 if (hme)
747 res = &sdev->resource[1];
748 else
749 res = &sdev->resource[0];
750
751 esp->eregs = sbus_ioremap(res, 0, ESP_REG_SIZE, "ESP Registers");
752
753 if (esp->eregs == 0)
754 return -1;
755 return 0;
756}
757
758static int __init esp_map_cmdarea(struct esp *esp)
759{
760 struct sbus_dev *sdev = esp->sdev;
761
762 esp->esp_command = sbus_alloc_consistent(sdev, 16,
763 &esp->esp_command_dvma);
764 if (esp->esp_command == NULL ||
765 esp->esp_command_dvma == 0)
766 return -1;
767 return 0;
768}
769
770static int __init esp_register_irq(struct esp *esp)
771{
772 esp->ehost->irq = esp->irq = esp->sdev->irqs[0];
773
774 /* We used to try various overly-clever things to
775 * reduce the interrupt processing overhead on
776 * sun4c/sun4m when multiple ESP's shared the
777 * same IRQ. It was too complex and messy to
778 * sanely maintain.
779 */
780 if (request_irq(esp->ehost->irq, esp_intr,
781 IRQF_SHARED, "ESP SCSI", esp)) {
782 printk("esp%d: Cannot acquire irq line\n",
783 esp->esp_id);
784 return -1;
785 }
786
787 printk("esp%d: IRQ %d ", esp->esp_id,
788 esp->ehost->irq);
789
790 return 0;
791}
792
793static void __init esp_get_scsi_id(struct esp *esp)
794{
795 struct sbus_dev *sdev = esp->sdev;
796 struct device_node *dp = sdev->ofdev.node;
797
798 esp->scsi_id = of_getintprop_default(dp,
799 "initiator-id",
800 -1);
801 if (esp->scsi_id == -1)
802 esp->scsi_id = of_getintprop_default(dp,
803 "scsi-initiator-id",
804 -1);
805 if (esp->scsi_id == -1)
806 esp->scsi_id = (sdev->bus == NULL) ? 7 :
807 of_getintprop_default(sdev->bus->ofdev.node,
808 "scsi-initiator-id",
809 7);
810 esp->ehost->this_id = esp->scsi_id;
811 esp->scsi_id_mask = (1 << esp->scsi_id);
812
813}
814
815static void __init esp_get_clock_params(struct esp *esp)
816{
817 struct sbus_dev *sdev = esp->sdev;
818 int prom_node = esp->prom_node;
819 int sbus_prom_node;
820 unsigned int fmhz;
821 u8 ccf;
822
823 if (sdev != NULL && sdev->bus != NULL)
824 sbus_prom_node = sdev->bus->prom_node;
825 else
826 sbus_prom_node = 0;
827
828 /* This is getting messy but it has to be done
829 * correctly or else you get weird behavior all
830 * over the place. We are trying to basically
831 * figure out three pieces of information.
832 *
833 * a) Clock Conversion Factor
834 *
835 * This is a representation of the input
836 * crystal clock frequency going into the
837 * ESP on this machine. Any operation whose
838 * timing is longer than 400ns depends on this
839 * value being correct. For example, you'll
840 * get blips for arbitration/selection during
841 * high load or with multiple targets if this
842 * is not set correctly.
843 *
844 * b) Selection Time-Out
845 *
846 * The ESP isn't very bright and will arbitrate
847 * for the bus and try to select a target
848 * forever if you let it. This value tells
849 * the ESP when it has taken too long to
850 * negotiate and that it should interrupt
851 * the CPU so we can see what happened.
852 * The value is computed as follows (from
853 * NCR/Symbios chip docs).
854 *
855 * (Time Out Period) * (Input Clock)
856 * STO = ----------------------------------
857 * (8192) * (Clock Conversion Factor)
858 *
859 * You usually want the time out period to be
860 * around 250ms, I think we'll set it a little
861 * bit higher to account for fully loaded SCSI
862 * bus's and slow devices that don't respond so
863 * quickly to selection attempts. (yeah, I know
864 * this is out of spec. but there is a lot of
865 * buggy pieces of firmware out there so bite me)
866 *
867 * c) Imperical constants for synchronous offset
868 * and transfer period register values
869 *
870 * This entails the smallest and largest sync
871 * period we could ever handle on this ESP.
872 */
873
874 fmhz = prom_getintdefault(prom_node, "clock-frequency", -1);
875 if (fmhz == -1)
876 fmhz = (!sbus_prom_node) ? 0 :
877 prom_getintdefault(sbus_prom_node, "clock-frequency", -1);
878
879 if (fmhz <= (5000000))
880 ccf = 0;
881 else
882 ccf = (((5000000 - 1) + (fmhz))/(5000000));
883
884 if (!ccf || ccf > 8) {
885 /* If we can't find anything reasonable,
886 * just assume 20MHZ. This is the clock
887 * frequency of the older sun4c's where I've
888 * been unable to find the clock-frequency
889 * PROM property. All other machines provide
890 * useful values it seems.
891 */
892 ccf = ESP_CCF_F4;
893 fmhz = (20000000);
894 }
895
896 if (ccf == (ESP_CCF_F7 + 1))
897 esp->cfact = ESP_CCF_F0;
898 else if (ccf == ESP_CCF_NEVER)
899 esp->cfact = ESP_CCF_F2;
900 else
901 esp->cfact = ccf;
902 esp->raw_cfact = ccf;
903
904 esp->cfreq = fmhz;
905 esp->ccycle = ESP_MHZ_TO_CYCLE(fmhz);
906 esp->ctick = ESP_TICK(ccf, esp->ccycle);
907 esp->neg_defp = ESP_NEG_DEFP(fmhz, ccf);
908 esp->sync_defp = SYNC_DEFP_SLOW;
909
910 printk("SCSI ID %d Clk %dMHz CCYC=%d CCF=%d TOut %d ",
911 esp->scsi_id, (fmhz / 1000000),
912 (int)esp->ccycle, (int)ccf, (int) esp->neg_defp);
913}
914
915static void __init esp_get_bursts(struct esp *esp, struct sbus_dev *dma)
916{
917 struct sbus_dev *sdev = esp->sdev;
918 u8 bursts;
919
920 bursts = prom_getintdefault(esp->prom_node, "burst-sizes", 0xff);
921
922 if (dma) {
923 u8 tmp = prom_getintdefault(dma->prom_node,
924 "burst-sizes", 0xff);
925 if (tmp != 0xff)
926 bursts &= tmp;
927 }
928
929 if (sdev->bus) {
930 u8 tmp = prom_getintdefault(sdev->bus->prom_node,
931 "burst-sizes", 0xff);
932 if (tmp != 0xff)
933 bursts &= tmp;
934 }
935
936 if (bursts == 0xff ||
937 (bursts & DMA_BURST16) == 0 ||
938 (bursts & DMA_BURST32) == 0)
939 bursts = (DMA_BURST32 - 1);
940
941 esp->bursts = bursts;
942}
943
944static void __init esp_get_revision(struct esp *esp)
945{
946 u8 tmp;
947
948 esp->config1 = (ESP_CONFIG1_PENABLE | (esp->scsi_id & 7));
949 esp->config2 = (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY);
950 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
951
952 tmp = sbus_readb(esp->eregs + ESP_CFG2);
953 tmp &= ~ESP_CONFIG2_MAGIC;
954 if (tmp != (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY)) {
955 /* If what we write to cfg2 does not come back, cfg2
956 * is not implemented, therefore this must be a plain
957 * esp100.
958 */
959 esp->erev = esp100;
960 printk("NCR53C90(esp100)\n");
961 } else {
962 esp->config2 = 0;
963 esp->prev_cfg3 = esp->config3[0] = 5;
964 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
965 sbus_writeb(0, esp->eregs + ESP_CFG3);
966 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
967
968 tmp = sbus_readb(esp->eregs + ESP_CFG3);
969 if (tmp != 5) {
970 /* The cfg2 register is implemented, however
971 * cfg3 is not, must be esp100a.
972 */
973 esp->erev = esp100a;
974 printk("NCR53C90A(esp100a)\n");
975 } else {
976 int target;
977
978 for (target = 0; target < 16; target++)
979 esp->config3[target] = 0;
980 esp->prev_cfg3 = 0;
981 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
982
983 /* All of cfg{1,2,3} implemented, must be one of
984 * the fas variants, figure out which one.
985 */
986 if (esp->raw_cfact > ESP_CCF_F5) {
987 esp->erev = fast;
988 esp->sync_defp = SYNC_DEFP_FAST;
989 printk("NCR53C9XF(espfast)\n");
990 } else {
991 esp->erev = esp236;
992 printk("NCR53C9x(esp236)\n");
993 }
994 esp->config2 = 0;
995 sbus_writeb(esp->config2, esp->eregs + ESP_CFG2);
996 }
997 }
998}
999
1000static void __init esp_init_swstate(struct esp *esp)
1001{
1002 int i;
1003
1004 /* Command queues... */
1005 esp->current_SC = NULL;
1006 esp->disconnected_SC = NULL;
1007 esp->issue_SC = NULL;
1008
1009 /* Target and current command state... */
1010 esp->targets_present = 0;
1011 esp->resetting_bus = 0;
1012 esp->snip = 0;
1013
1014 init_waitqueue_head(&esp->reset_queue);
1015
1016 /* Debugging... */
1017 for(i = 0; i < 32; i++)
1018 esp->espcmdlog[i] = 0;
1019 esp->espcmdent = 0;
1020
1021 /* MSG phase state... */
1022 for(i = 0; i < 16; i++) {
1023 esp->cur_msgout[i] = 0;
1024 esp->cur_msgin[i] = 0;
1025 }
1026 esp->prevmsgout = esp->prevmsgin = 0;
1027 esp->msgout_len = esp->msgin_len = 0;
1028
1029 /* Clear the one behind caches to hold unmatchable values. */
1030 esp->prev_soff = esp->prev_stp = esp->prev_cfg3 = 0xff;
1031 esp->prev_hme_dmacsr = 0xffffffff;
1032}
1033
1034static int __init detect_one_esp(struct scsi_host_template *tpnt,
1035 struct device *dev,
1036 struct sbus_dev *esp_dev,
1037 struct sbus_dev *espdma,
1038 struct sbus_bus *sbus,
1039 int hme)
1040{
1041 static int instance;
1042 struct Scsi_Host *esp_host = scsi_host_alloc(tpnt, sizeof(struct esp));
1043 struct esp *esp;
1044
1045 if (!esp_host)
1046 return -ENOMEM;
1047
1048 if (hme)
1049 esp_host->max_id = 16;
1050 esp = (struct esp *) esp_host->hostdata;
1051 esp->ehost = esp_host;
1052 esp->sdev = esp_dev;
1053 esp->esp_id = instance;
1054 esp->prom_node = esp_dev->prom_node;
1055 prom_getstring(esp->prom_node, "name", esp->prom_name,
1056 sizeof(esp->prom_name));
1057
1058 if (esp_find_dvma(esp, espdma) < 0)
1059 goto fail_unlink;
1060 if (esp_map_regs(esp, hme) < 0) {
1061 printk("ESP registers unmappable");
1062 goto fail_dvma_release;
1063 }
1064 if (esp_map_cmdarea(esp) < 0) {
1065 printk("ESP DVMA transport area unmappable");
1066 goto fail_unmap_regs;
1067 }
1068 if (esp_register_irq(esp) < 0)
1069 goto fail_unmap_cmdarea;
1070
1071 esp_get_scsi_id(esp);
1072
1073 esp->diff = prom_getbool(esp->prom_node, "differential");
1074 if (esp->diff)
1075 printk("Differential ");
1076
1077 esp_get_clock_params(esp);
1078 esp_get_bursts(esp, espdma);
1079 esp_get_revision(esp);
1080 esp_init_swstate(esp);
1081
1082 esp_bootup_reset(esp);
1083
1084 if (scsi_add_host(esp_host, dev))
1085 goto fail_free_irq;
1086
1087 dev_set_drvdata(&esp_dev->ofdev.dev, esp);
1088
1089 scsi_scan_host(esp_host);
1090 instance++;
1091
1092 return 0;
1093
1094fail_free_irq:
1095 free_irq(esp->ehost->irq, esp);
1096
1097fail_unmap_cmdarea:
1098 sbus_free_consistent(esp->sdev, 16,
1099 (void *) esp->esp_command,
1100 esp->esp_command_dvma);
1101
1102fail_unmap_regs:
1103 sbus_iounmap(esp->eregs, ESP_REG_SIZE);
1104
1105fail_dvma_release:
1106 esp->dma->allocated = 0;
1107
1108fail_unlink:
1109 scsi_host_put(esp_host);
1110 return -1;
1111}
1112
1113/* Detecting ESP chips on the machine. This is the simple and easy
1114 * version.
1115 */
1116static int __devexit esp_remove_common(struct esp *esp)
1117{
1118 unsigned int irq = esp->ehost->irq;
1119
1120 scsi_remove_host(esp->ehost);
1121
1122 ESP_INTSOFF(esp->dregs);
1123#if 0
1124 esp_reset_dma(esp);
1125 esp_reset_esp(esp);
1126#endif
1127
1128 free_irq(irq, esp);
1129 sbus_free_consistent(esp->sdev, 16,
1130 (void *) esp->esp_command, esp->esp_command_dvma);
1131 sbus_iounmap(esp->eregs, ESP_REG_SIZE);
1132 esp->dma->allocated = 0;
1133
1134 scsi_host_put(esp->ehost);
1135
1136 return 0;
1137}
1138
1139
1140#ifdef CONFIG_SUN4
1141
1142#include <asm/sun4paddr.h>
1143
1144static struct sbus_dev sun4_esp_dev;
1145
1146static int __init esp_sun4_probe(struct scsi_host_template *tpnt)
1147{
1148 if (sun4_esp_physaddr) {
1149 memset(&sun4_esp_dev, 0, sizeof(sun4_esp_dev));
1150 sun4_esp_dev.reg_addrs[0].phys_addr = sun4_esp_physaddr;
1151 sun4_esp_dev.irqs[0] = 4;
1152 sun4_esp_dev.resource[0].start = sun4_esp_physaddr;
1153 sun4_esp_dev.resource[0].end =
1154 sun4_esp_physaddr + ESP_REG_SIZE - 1;
1155 sun4_esp_dev.resource[0].flags = IORESOURCE_IO;
1156
1157 return detect_one_esp(tpnt, NULL,
1158 &sun4_esp_dev, NULL, NULL, 0);
1159 }
1160 return 0;
1161}
1162
1163static int __devexit esp_sun4_remove(void)
1164{
1165 struct of_device *dev = &sun4_esp_dev.ofdev;
1166 struct esp *esp = dev_get_drvdata(&dev->dev);
1167
1168 return esp_remove_common(esp);
1169}
1170
1171#else /* !CONFIG_SUN4 */
1172
1173static int __devinit esp_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1174{
1175 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
1176 struct device_node *dp = dev->node;
1177 struct sbus_dev *dma_sdev = NULL;
1178 int hme = 0;
1179
1180 if (dp->parent &&
1181 (!strcmp(dp->parent->name, "espdma") ||
1182 !strcmp(dp->parent->name, "dma")))
1183 dma_sdev = sdev->parent;
1184 else if (!strcmp(dp->name, "SUNW,fas")) {
1185 dma_sdev = sdev;
1186 hme = 1;
1187 }
1188
1189 return detect_one_esp(match->data, &dev->dev,
1190 sdev, dma_sdev, sdev->bus, hme);
1191}
1192
1193static int __devexit esp_sbus_remove(struct of_device *dev)
1194{
1195 struct esp *esp = dev_get_drvdata(&dev->dev);
1196
1197 return esp_remove_common(esp);
1198}
1199
1200#endif /* !CONFIG_SUN4 */
1201
1202/* The info function will return whatever useful
1203 * information the developer sees fit. If not provided, then
1204 * the name field will be used instead.
1205 */
1206static const char *esp_info(struct Scsi_Host *host)
1207{
1208 struct esp *esp;
1209
1210 esp = (struct esp *) host->hostdata;
1211 switch (esp->erev) {
1212 case esp100:
1213 return "Sparc ESP100 (NCR53C90)";
1214 case esp100a:
1215 return "Sparc ESP100A (NCR53C90A)";
1216 case esp236:
1217 return "Sparc ESP236";
1218 case fas236:
1219 return "Sparc ESP236-FAST";
1220 case fashme:
1221 return "Sparc ESP366-HME";
1222 case fas100a:
1223 return "Sparc ESP100A-FAST";
1224 default:
1225 return "Bogon ESP revision";
1226 };
1227}
1228
1229/* From Wolfgang Stanglmeier's NCR scsi driver. */
1230struct info_str
1231{
1232 char *buffer;
1233 int length;
1234 int offset;
1235 int pos;
1236};
1237
1238static void copy_mem_info(struct info_str *info, char *data, int len)
1239{
1240 if (info->pos + len > info->length)
1241 len = info->length - info->pos;
1242
1243 if (info->pos + len < info->offset) {
1244 info->pos += len;
1245 return;
1246 }
1247 if (info->pos < info->offset) {
1248 data += (info->offset - info->pos);
1249 len -= (info->offset - info->pos);
1250 }
1251
1252 if (len > 0) {
1253 memcpy(info->buffer + info->pos, data, len);
1254 info->pos += len;
1255 }
1256}
1257
1258static int copy_info(struct info_str *info, char *fmt, ...)
1259{
1260 va_list args;
1261 char buf[81];
1262 int len;
1263
1264 va_start(args, fmt);
1265 len = vsprintf(buf, fmt, args);
1266 va_end(args);
1267
1268 copy_mem_info(info, buf, len);
1269 return len;
1270}
1271
1272static int esp_host_info(struct esp *esp, char *ptr, off_t offset, int len)
1273{
1274 struct scsi_device *sdev;
1275 struct info_str info;
1276 int i;
1277
1278 info.buffer = ptr;
1279 info.length = len;
1280 info.offset = offset;
1281 info.pos = 0;
1282
1283 copy_info(&info, "Sparc ESP Host Adapter:\n");
1284 copy_info(&info, "\tPROM node\t\t%08x\n", (unsigned int) esp->prom_node);
1285 copy_info(&info, "\tPROM name\t\t%s\n", esp->prom_name);
1286 copy_info(&info, "\tESP Model\t\t");
1287 switch (esp->erev) {
1288 case esp100:
1289 copy_info(&info, "ESP100\n");
1290 break;
1291 case esp100a:
1292 copy_info(&info, "ESP100A\n");
1293 break;
1294 case esp236:
1295 copy_info(&info, "ESP236\n");
1296 break;
1297 case fas236:
1298 copy_info(&info, "FAS236\n");
1299 break;
1300 case fas100a:
1301 copy_info(&info, "FAS100A\n");
1302 break;
1303 case fast:
1304 copy_info(&info, "FAST\n");
1305 break;
1306 case fashme:
1307 copy_info(&info, "Happy Meal FAS\n");
1308 break;
1309 case espunknown:
1310 default:
1311 copy_info(&info, "Unknown!\n");
1312 break;
1313 };
1314 copy_info(&info, "\tDMA Revision\t\t");
1315 switch (esp->dma->revision) {
1316 case dvmarev0:
1317 copy_info(&info, "Rev 0\n");
1318 break;
1319 case dvmaesc1:
1320 copy_info(&info, "ESC Rev 1\n");
1321 break;
1322 case dvmarev1:
1323 copy_info(&info, "Rev 1\n");
1324 break;
1325 case dvmarev2:
1326 copy_info(&info, "Rev 2\n");
1327 break;
1328 case dvmarev3:
1329 copy_info(&info, "Rev 3\n");
1330 break;
1331 case dvmarevplus:
1332 copy_info(&info, "Rev 1+\n");
1333 break;
1334 case dvmahme:
1335 copy_info(&info, "Rev HME/FAS\n");
1336 break;
1337 default:
1338 copy_info(&info, "Unknown!\n");
1339 break;
1340 };
1341 copy_info(&info, "\tLive Targets\t\t[ ");
1342 for (i = 0; i < 15; i++) {
1343 if (esp->targets_present & (1 << i))
1344 copy_info(&info, "%d ", i);
1345 }
1346 copy_info(&info, "]\n\n");
1347
1348 /* Now describe the state of each existing target. */
1349 copy_info(&info, "Target #\tconfig3\t\tSync Capabilities\tDisconnect\tWide\n");
1350
1351 shost_for_each_device(sdev, esp->ehost) {
1352 struct esp_device *esp_dev = sdev->hostdata;
1353 uint id = sdev->id;
1354
1355 if (!(esp->targets_present & (1 << id)))
1356 continue;
1357
1358 copy_info(&info, "%d\t\t", id);
1359 copy_info(&info, "%08lx\t", esp->config3[id]);
1360 copy_info(&info, "[%02lx,%02lx]\t\t\t",
1361 esp_dev->sync_max_offset,
1362 esp_dev->sync_min_period);
1363 copy_info(&info, "%s\t\t",
1364 esp_dev->disconnect ? "yes" : "no");
1365 copy_info(&info, "%s\n",
1366 (esp->config3[id] & ESP_CONFIG3_EWIDE) ? "yes" : "no");
1367 }
1368 return info.pos > info.offset? info.pos - info.offset : 0;
1369}
1370
1371/* ESP proc filesystem code. */
1372static int esp_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1373 int length, int inout)
1374{
1375 struct esp *esp = (struct esp *) host->hostdata;
1376
1377 if (inout)
1378 return -EINVAL; /* not yet */
1379
1380 if (start)
1381 *start = buffer;
1382
1383 return esp_host_info(esp, buffer, offset, length);
1384}
1385
1386static void esp_get_dmabufs(struct esp *esp, struct scsi_cmnd *sp)
1387{
1388 if (sp->use_sg == 0) {
1389 sp->SCp.this_residual = sp->request_bufflen;
1390 sp->SCp.buffer = (struct scatterlist *) sp->request_buffer;
1391 sp->SCp.buffers_residual = 0;
1392 if (sp->request_bufflen) {
1393 sp->SCp.have_data_in = sbus_map_single(esp->sdev, sp->SCp.buffer,
1394 sp->SCp.this_residual,
1395 sp->sc_data_direction);
1396 sp->SCp.ptr = (char *) ((unsigned long)sp->SCp.have_data_in);
1397 } else {
1398 sp->SCp.ptr = NULL;
1399 }
1400 } else {
1401 sp->SCp.buffer = (struct scatterlist *) sp->request_buffer;
1402 sp->SCp.buffers_residual = sbus_map_sg(esp->sdev,
1403 sp->SCp.buffer,
1404 sp->use_sg,
1405 sp->sc_data_direction);
1406 sp->SCp.this_residual = sg_dma_len(sp->SCp.buffer);
1407 sp->SCp.ptr = (char *) ((unsigned long)sg_dma_address(sp->SCp.buffer));
1408 }
1409}
1410
1411static void esp_release_dmabufs(struct esp *esp, struct scsi_cmnd *sp)
1412{
1413 if (sp->use_sg) {
1414 sbus_unmap_sg(esp->sdev, sp->request_buffer, sp->use_sg,
1415 sp->sc_data_direction);
1416 } else if (sp->request_bufflen) {
1417 sbus_unmap_single(esp->sdev,
1418 sp->SCp.have_data_in,
1419 sp->request_bufflen,
1420 sp->sc_data_direction);
1421 }
1422}
1423
1424static void esp_restore_pointers(struct esp *esp, struct scsi_cmnd *sp)
1425{
1426 struct esp_pointers *ep = &esp->data_pointers[sp->device->id];
1427
1428 sp->SCp.ptr = ep->saved_ptr;
1429 sp->SCp.buffer = ep->saved_buffer;
1430 sp->SCp.this_residual = ep->saved_this_residual;
1431 sp->SCp.buffers_residual = ep->saved_buffers_residual;
1432}
1433
1434static void esp_save_pointers(struct esp *esp, struct scsi_cmnd *sp)
1435{
1436 struct esp_pointers *ep = &esp->data_pointers[sp->device->id];
1437
1438 ep->saved_ptr = sp->SCp.ptr;
1439 ep->saved_buffer = sp->SCp.buffer;
1440 ep->saved_this_residual = sp->SCp.this_residual;
1441 ep->saved_buffers_residual = sp->SCp.buffers_residual;
1442}
1443
1444/* Some rules:
1445 *
1446 * 1) Never ever panic while something is live on the bus.
1447 * If there is to be any chance of syncing the disks this
1448 * rule is to be obeyed.
1449 *
1450 * 2) Any target that causes a foul condition will no longer
1451 * have synchronous transfers done to it, no questions
1452 * asked.
1453 *
1454 * 3) Keep register accesses to a minimum. Think about some
1455 * day when we have Xbus machines this is running on and
1456 * the ESP chip is on the other end of the machine on a
1457 * different board from the cpu where this is running.
1458 */
1459
1460/* Fire off a command. We assume the bus is free and that the only
1461 * case where we could see an interrupt is where we have disconnected
1462 * commands active and they are trying to reselect us.
1463 */
1464static inline void esp_check_cmd(struct esp *esp, struct scsi_cmnd *sp)
1465{
1466 switch (sp->cmd_len) {
1467 case 6:
1468 case 10:
1469 case 12:
1470 esp->esp_slowcmd = 0;
1471 break;
1472
1473 default:
1474 esp->esp_slowcmd = 1;
1475 esp->esp_scmdleft = sp->cmd_len;
1476 esp->esp_scmdp = &sp->cmnd[0];
1477 break;
1478 };
1479}
1480
1481static inline void build_sync_nego_msg(struct esp *esp, int period, int offset)
1482{
1483 esp->cur_msgout[0] = EXTENDED_MESSAGE;
1484 esp->cur_msgout[1] = 3;
1485 esp->cur_msgout[2] = EXTENDED_SDTR;
1486 esp->cur_msgout[3] = period;
1487 esp->cur_msgout[4] = offset;
1488 esp->msgout_len = 5;
1489}
1490
1491/* SIZE is in bits, currently HME only supports 16 bit wide transfers. */
1492static inline void build_wide_nego_msg(struct esp *esp, int size)
1493{
1494 esp->cur_msgout[0] = EXTENDED_MESSAGE;
1495 esp->cur_msgout[1] = 2;
1496 esp->cur_msgout[2] = EXTENDED_WDTR;
1497 switch (size) {
1498 case 32:
1499 esp->cur_msgout[3] = 2;
1500 break;
1501 case 16:
1502 esp->cur_msgout[3] = 1;
1503 break;
1504 case 8:
1505 default:
1506 esp->cur_msgout[3] = 0;
1507 break;
1508 };
1509
1510 esp->msgout_len = 4;
1511}
1512
1513static void esp_exec_cmd(struct esp *esp)
1514{
1515 struct scsi_cmnd *SCptr;
1516 struct scsi_device *SDptr;
1517 struct esp_device *esp_dev;
1518 volatile u8 *cmdp = esp->esp_command;
1519 u8 the_esp_command;
1520 int lun, target;
1521 int i;
1522
1523 /* Hold off if we have disconnected commands and
1524 * an IRQ is showing...
1525 */
1526 if (esp->disconnected_SC && ESP_IRQ_P(esp->dregs))
1527 return;
1528
1529 /* Grab first member of the issue queue. */
1530 SCptr = esp->current_SC = remove_first_SC(&esp->issue_SC);
1531
1532 /* Safe to panic here because current_SC is null. */
1533 if (!SCptr)
1534 panic("esp: esp_exec_cmd and issue queue is NULL");
1535
1536 SDptr = SCptr->device;
1537 esp_dev = SDptr->hostdata;
1538 lun = SCptr->device->lun;
1539 target = SCptr->device->id;
1540
1541 esp->snip = 0;
1542 esp->msgout_len = 0;
1543
1544 /* Send it out whole, or piece by piece? The ESP
1545 * only knows how to automatically send out 6, 10,
1546 * and 12 byte commands. I used to think that the
1547 * Linux SCSI code would never throw anything other
1548 * than that to us, but then again there is the
1549 * SCSI generic driver which can send us anything.
1550 */
1551 esp_check_cmd(esp, SCptr);
1552
1553 /* If arbitration/selection is successful, the ESP will leave
1554 * ATN asserted, causing the target to go into message out
1555 * phase. The ESP will feed the target the identify and then
1556 * the target can only legally go to one of command,
1557 * datain/out, status, or message in phase, or stay in message
1558 * out phase (should we be trying to send a sync negotiation
1559 * message after the identify). It is not allowed to drop
1560 * BSY, but some buggy targets do and we check for this
1561 * condition in the selection complete code. Most of the time
1562 * we'll make the command bytes available to the ESP and it
1563 * will not interrupt us until it finishes command phase, we
1564 * cannot do this for command sizes the ESP does not
1565 * understand and in this case we'll get interrupted right
1566 * when the target goes into command phase.
1567 *
1568 * It is absolutely _illegal_ in the presence of SCSI-2 devices
1569 * to use the ESP select w/o ATN command. When SCSI-2 devices are
1570 * present on the bus we _must_ always go straight to message out
1571 * phase with an identify message for the target. Being that
1572 * selection attempts in SCSI-1 w/o ATN was an option, doing SCSI-2
1573 * selections should not confuse SCSI-1 we hope.
1574 */
1575
1576 if (esp_dev->sync) {
1577 /* this targets sync is known */
1578#ifndef __sparc_v9__
1579do_sync_known:
1580#endif
1581 if (esp_dev->disconnect)
1582 *cmdp++ = IDENTIFY(1, lun);
1583 else
1584 *cmdp++ = IDENTIFY(0, lun);
1585
1586 if (esp->esp_slowcmd) {
1587 the_esp_command = (ESP_CMD_SELAS | ESP_CMD_DMA);
1588 esp_advance_phase(SCptr, in_slct_stop);
1589 } else {
1590 the_esp_command = (ESP_CMD_SELA | ESP_CMD_DMA);
1591 esp_advance_phase(SCptr, in_slct_norm);
1592 }
1593 } else if (!(esp->targets_present & (1<<target)) || !(esp_dev->disconnect)) {
1594 /* After the bootup SCSI code sends both the
1595 * TEST_UNIT_READY and INQUIRY commands we want
1596 * to at least attempt allowing the device to
1597 * disconnect.
1598 */
1599 ESPMISC(("esp: Selecting device for first time. target=%d "
1600 "lun=%d\n", target, SCptr->device->lun));
1601 if (!SDptr->borken && !esp_dev->disconnect)
1602 esp_dev->disconnect = 1;
1603
1604 *cmdp++ = IDENTIFY(0, lun);
1605 esp->prevmsgout = NOP;
1606 esp_advance_phase(SCptr, in_slct_norm);
1607 the_esp_command = (ESP_CMD_SELA | ESP_CMD_DMA);
1608
1609 /* Take no chances... */
1610 esp_dev->sync_max_offset = 0;
1611 esp_dev->sync_min_period = 0;
1612 } else {
1613 /* Sorry, I have had way too many problems with
1614 * various CDROM devices on ESP. -DaveM
1615 */
1616 int cdrom_hwbug_wkaround = 0;
1617
1618#ifndef __sparc_v9__
1619 /* Never allow disconnects or synchronous transfers on
1620 * SparcStation1 and SparcStation1+. Allowing those
1621 * to be enabled seems to lockup the machine completely.
1622 */
1623 if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) ||
1624 (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) {
1625 /* But we are nice and allow tapes and removable
1626 * disks (but not CDROMs) to disconnect.
1627 */
1628 if(SDptr->type == TYPE_TAPE ||
1629 (SDptr->type != TYPE_ROM && SDptr->removable))
1630 esp_dev->disconnect = 1;
1631 else
1632 esp_dev->disconnect = 0;
1633 esp_dev->sync_max_offset = 0;
1634 esp_dev->sync_min_period = 0;
1635 esp_dev->sync = 1;
1636 esp->snip = 0;
1637 goto do_sync_known;
1638 }
1639#endif /* !(__sparc_v9__) */
1640
1641 /* We've talked to this guy before,
1642 * but never negotiated. Let's try,
1643 * need to attempt WIDE first, before
1644 * sync nego, as per SCSI 2 standard.
1645 */
1646 if (esp->erev == fashme && !esp_dev->wide) {
1647 if (!SDptr->borken &&
1648 SDptr->type != TYPE_ROM &&
1649 SDptr->removable == 0) {
1650 build_wide_nego_msg(esp, 16);
1651 esp_dev->wide = 1;
1652 esp->wnip = 1;
1653 goto after_nego_msg_built;
1654 } else {
1655 esp_dev->wide = 1;
1656 /* Fall through and try sync. */
1657 }
1658 }
1659
1660 if (!SDptr->borken) {
1661 if ((SDptr->type == TYPE_ROM)) {
1662 /* Nice try sucker... */
1663 ESPMISC(("esp%d: Disabling sync for buggy "
1664 "CDROM.\n", esp->esp_id));
1665 cdrom_hwbug_wkaround = 1;
1666 build_sync_nego_msg(esp, 0, 0);
1667 } else if (SDptr->removable != 0) {
1668 ESPMISC(("esp%d: Not negotiating sync/wide but "
1669 "allowing disconnect for removable media.\n",
1670 esp->esp_id));
1671 build_sync_nego_msg(esp, 0, 0);
1672 } else {
1673 build_sync_nego_msg(esp, esp->sync_defp, 15);
1674 }
1675 } else {
1676 build_sync_nego_msg(esp, 0, 0);
1677 }
1678 esp_dev->sync = 1;
1679 esp->snip = 1;
1680
1681after_nego_msg_built:
1682 /* A fix for broken SCSI1 targets, when they disconnect
1683 * they lock up the bus and confuse ESP. So disallow
1684 * disconnects for SCSI1 targets for now until we
1685 * find a better fix.
1686 *
1687 * Addendum: This is funny, I figured out what was going
1688 * on. The blotzed SCSI1 target would disconnect,
1689 * one of the other SCSI2 targets or both would be
1690 * disconnected as well. The SCSI1 target would
1691 * stay disconnected long enough that we start
1692 * up a command on one of the SCSI2 targets. As
1693 * the ESP is arbitrating for the bus the SCSI1
1694 * target begins to arbitrate as well to reselect
1695 * the ESP. The SCSI1 target refuses to drop it's
1696 * ID bit on the data bus even though the ESP is
1697 * at ID 7 and is the obvious winner for any
1698 * arbitration. The ESP is a poor sport and refuses
1699 * to lose arbitration, it will continue indefinitely
1700 * trying to arbitrate for the bus and can only be
1701 * stopped via a chip reset or SCSI bus reset.
1702 * Therefore _no_ disconnects for SCSI1 targets
1703 * thank you very much. ;-)
1704 */
1705 if(((SDptr->scsi_level < 3) &&
1706 (SDptr->type != TYPE_TAPE) &&
1707 SDptr->removable == 0) ||
1708 cdrom_hwbug_wkaround || SDptr->borken) {
1709 ESPMISC((KERN_INFO "esp%d: Disabling DISCONNECT for target %d "
1710 "lun %d\n", esp->esp_id, SCptr->device->id, SCptr->device->lun));
1711 esp_dev->disconnect = 0;
1712 *cmdp++ = IDENTIFY(0, lun);
1713 } else {
1714 *cmdp++ = IDENTIFY(1, lun);
1715 }
1716
1717 /* ESP fifo is only so big...
1718 * Make this look like a slow command.
1719 */
1720 esp->esp_slowcmd = 1;
1721 esp->esp_scmdleft = SCptr->cmd_len;
1722 esp->esp_scmdp = &SCptr->cmnd[0];
1723
1724 the_esp_command = (ESP_CMD_SELAS | ESP_CMD_DMA);
1725 esp_advance_phase(SCptr, in_slct_msg);
1726 }
1727
1728 if (!esp->esp_slowcmd)
1729 for (i = 0; i < SCptr->cmd_len; i++)
1730 *cmdp++ = SCptr->cmnd[i];
1731
1732 /* HME sucks... */
1733 if (esp->erev == fashme)
1734 sbus_writeb((target & 0xf) | (ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT),
1735 esp->eregs + ESP_BUSID);
1736 else
1737 sbus_writeb(target & 7, esp->eregs + ESP_BUSID);
1738 if (esp->prev_soff != esp_dev->sync_max_offset ||
1739 esp->prev_stp != esp_dev->sync_min_period ||
1740 (esp->erev > esp100a &&
1741 esp->prev_cfg3 != esp->config3[target])) {
1742 esp->prev_soff = esp_dev->sync_max_offset;
1743 esp->prev_stp = esp_dev->sync_min_period;
1744 sbus_writeb(esp->prev_soff, esp->eregs + ESP_SOFF);
1745 sbus_writeb(esp->prev_stp, esp->eregs + ESP_STP);
1746 if (esp->erev > esp100a) {
1747 esp->prev_cfg3 = esp->config3[target];
1748 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
1749 }
1750 }
1751 i = (cmdp - esp->esp_command);
1752
1753 if (esp->erev == fashme) {
1754 esp_cmd(esp, ESP_CMD_FLUSH); /* Grrr! */
1755
1756 /* Set up the DMA and HME counters */
1757 sbus_writeb(i, esp->eregs + ESP_TCLOW);
1758 sbus_writeb(0, esp->eregs + ESP_TCMED);
1759 sbus_writeb(0, esp->eregs + FAS_RLO);
1760 sbus_writeb(0, esp->eregs + FAS_RHI);
1761 esp_cmd(esp, the_esp_command);
1762
1763 /* Talk about touchy hardware... */
1764 esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
1765 (DMA_SCSI_DISAB | DMA_ENABLE)) &
1766 ~(DMA_ST_WRITE));
1767 sbus_writel(16, esp->dregs + DMA_COUNT);
1768 sbus_writel(esp->esp_command_dvma, esp->dregs + DMA_ADDR);
1769 sbus_writel(esp->prev_hme_dmacsr, esp->dregs + DMA_CSR);
1770 } else {
1771 u32 tmp;
1772
1773 /* Set up the DMA and ESP counters */
1774 sbus_writeb(i, esp->eregs + ESP_TCLOW);
1775 sbus_writeb(0, esp->eregs + ESP_TCMED);
1776 tmp = sbus_readl(esp->dregs + DMA_CSR);
1777 tmp &= ~DMA_ST_WRITE;
1778 tmp |= DMA_ENABLE;
1779 sbus_writel(tmp, esp->dregs + DMA_CSR);
1780 if (esp->dma->revision == dvmaesc1) {
1781 if (i) /* Workaround ESC gate array SBUS rerun bug. */
1782 sbus_writel(PAGE_SIZE, esp->dregs + DMA_COUNT);
1783 }
1784 sbus_writel(esp->esp_command_dvma, esp->dregs + DMA_ADDR);
1785
1786 /* Tell ESP to "go". */
1787 esp_cmd(esp, the_esp_command);
1788 }
1789}
1790
1791/* Queue a SCSI command delivered from the mid-level Linux SCSI code. */
1792static int esp_queue(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
1793{
1794 struct esp *esp;
1795
1796 /* Set up func ptr and initial driver cmd-phase. */
1797 SCpnt->scsi_done = done;
1798 SCpnt->SCp.phase = not_issued;
1799
1800 /* We use the scratch area. */
1801 ESPQUEUE(("esp_queue: target=%d lun=%d ", SCpnt->device->id, SCpnt->device->lun));
1802 ESPDISC(("N<%02x,%02x>", SCpnt->device->id, SCpnt->device->lun));
1803
1804 esp = (struct esp *) SCpnt->device->host->hostdata;
1805 esp_get_dmabufs(esp, SCpnt);
1806 esp_save_pointers(esp, SCpnt); /* FIXME for tag queueing */
1807
1808 SCpnt->SCp.Status = CHECK_CONDITION;
1809 SCpnt->SCp.Message = 0xff;
1810 SCpnt->SCp.sent_command = 0;
1811
1812 /* Place into our queue. */
1813 if (SCpnt->cmnd[0] == REQUEST_SENSE) {
1814 ESPQUEUE(("RQSENSE\n"));
1815 prepend_SC(&esp->issue_SC, SCpnt);
1816 } else {
1817 ESPQUEUE(("\n"));
1818 append_SC(&esp->issue_SC, SCpnt);
1819 }
1820
1821 /* Run it now if we can. */
1822 if (!esp->current_SC && !esp->resetting_bus)
1823 esp_exec_cmd(esp);
1824
1825 return 0;
1826}
1827
1828/* Dump driver state. */
1829static void esp_dump_cmd(struct scsi_cmnd *SCptr)
1830{
1831 ESPLOG(("[tgt<%02x> lun<%02x> "
1832 "pphase<%s> cphase<%s>]",
1833 SCptr->device->id, SCptr->device->lun,
1834 phase_string(SCptr->SCp.sent_command),
1835 phase_string(SCptr->SCp.phase)));
1836}
1837
1838static void esp_dump_state(struct esp *esp)
1839{
1840 struct scsi_cmnd *SCptr = esp->current_SC;
1841#ifdef DEBUG_ESP_CMDS
1842 int i;
1843#endif
1844
1845 ESPLOG(("esp%d: dumping state\n", esp->esp_id));
1846 ESPLOG(("esp%d: dma -- cond_reg<%08x> addr<%08x>\n",
1847 esp->esp_id,
1848 sbus_readl(esp->dregs + DMA_CSR),
1849 sbus_readl(esp->dregs + DMA_ADDR)));
1850 ESPLOG(("esp%d: SW [sreg<%02x> sstep<%02x> ireg<%02x>]\n",
1851 esp->esp_id, esp->sreg, esp->seqreg, esp->ireg));
1852 ESPLOG(("esp%d: HW reread [sreg<%02x> sstep<%02x> ireg<%02x>]\n",
1853 esp->esp_id,
1854 sbus_readb(esp->eregs + ESP_STATUS),
1855 sbus_readb(esp->eregs + ESP_SSTEP),
1856 sbus_readb(esp->eregs + ESP_INTRPT)));
1857#ifdef DEBUG_ESP_CMDS
1858 printk("esp%d: last ESP cmds [", esp->esp_id);
1859 i = (esp->espcmdent - 1) & 31;
1860 printk("<"); esp_print_cmd(esp->espcmdlog[i]); printk(">");
1861 i = (i - 1) & 31;
1862 printk("<"); esp_print_cmd(esp->espcmdlog[i]); printk(">");
1863 i = (i - 1) & 31;
1864 printk("<"); esp_print_cmd(esp->espcmdlog[i]); printk(">");
1865 i = (i - 1) & 31;
1866 printk("<"); esp_print_cmd(esp->espcmdlog[i]); printk(">");
1867 printk("]\n");
1868#endif /* (DEBUG_ESP_CMDS) */
1869
1870 if (SCptr) {
1871 ESPLOG(("esp%d: current command ", esp->esp_id));
1872 esp_dump_cmd(SCptr);
1873 }
1874 ESPLOG(("\n"));
1875 SCptr = esp->disconnected_SC;
1876 ESPLOG(("esp%d: disconnected ", esp->esp_id));
1877 while (SCptr) {
1878 esp_dump_cmd(SCptr);
1879 SCptr = (struct scsi_cmnd *) SCptr->host_scribble;
1880 }
1881 ESPLOG(("\n"));
1882}
1883
1884/* Abort a command. The host_lock is acquired by caller. */
1885static int esp_abort(struct scsi_cmnd *SCptr)
1886{
1887 struct esp *esp = (struct esp *) SCptr->device->host->hostdata;
1888 int don;
1889
1890 ESPLOG(("esp%d: Aborting command\n", esp->esp_id));
1891 esp_dump_state(esp);
1892
1893 /* Wheee, if this is the current command on the bus, the
1894 * best we can do is assert ATN and wait for msgout phase.
1895 * This should even fix a hung SCSI bus when we lose state
1896 * in the driver and timeout because the eventual phase change
1897 * will cause the ESP to (eventually) give an interrupt.
1898 */
1899 if (esp->current_SC == SCptr) {
1900 esp->cur_msgout[0] = ABORT;
1901 esp->msgout_len = 1;
1902 esp->msgout_ctr = 0;
1903 esp_cmd(esp, ESP_CMD_SATN);
1904 return SUCCESS;
1905 }
1906
1907 /* If it is still in the issue queue then we can safely
1908 * call the completion routine and report abort success.
1909 */
1910 don = (sbus_readl(esp->dregs + DMA_CSR) & DMA_INT_ENAB);
1911 if (don) {
1912 ESP_INTSOFF(esp->dregs);
1913 }
1914 if (esp->issue_SC) {
1915 struct scsi_cmnd **prev, *this;
1916 for (prev = (&esp->issue_SC), this = esp->issue_SC;
1917 this != NULL;
1918 prev = (struct scsi_cmnd **) &(this->host_scribble),
1919 this = (struct scsi_cmnd *) this->host_scribble) {
1920
1921 if (this == SCptr) {
1922 *prev = (struct scsi_cmnd *) this->host_scribble;
1923 this->host_scribble = NULL;
1924
1925 esp_release_dmabufs(esp, this);
1926 this->result = DID_ABORT << 16;
1927 this->scsi_done(this);
1928
1929 if (don)
1930 ESP_INTSON(esp->dregs);
1931
1932 return SUCCESS;
1933 }
1934 }
1935 }
1936
1937 /* Yuck, the command to abort is disconnected, it is not
1938 * worth trying to abort it now if something else is live
1939 * on the bus at this time. So, we let the SCSI code wait
1940 * a little bit and try again later.
1941 */
1942 if (esp->current_SC) {
1943 if (don)
1944 ESP_INTSON(esp->dregs);
1945 return FAILED;
1946 }
1947
1948 /* It's disconnected, we have to reconnect to re-establish
1949 * the nexus and tell the device to abort. However, we really
1950 * cannot 'reconnect' per se. Don't try to be fancy, just
1951 * indicate failure, which causes our caller to reset the whole
1952 * bus.
1953 */
1954
1955 if (don)
1956 ESP_INTSON(esp->dregs);
1957
1958 return FAILED;
1959}
1960
1961/* We've sent ESP_CMD_RS to the ESP, the interrupt had just
1962 * arrived indicating the end of the SCSI bus reset. Our job
1963 * is to clean out the command queues and begin re-execution
1964 * of SCSI commands once more.
1965 */
1966static int esp_finish_reset(struct esp *esp)
1967{
1968 struct scsi_cmnd *sp = esp->current_SC;
1969
1970 /* Clean up currently executing command, if any. */
1971 if (sp != NULL) {
1972 esp->current_SC = NULL;
1973
1974 esp_release_dmabufs(esp, sp);
1975 sp->result = (DID_RESET << 16);
1976
1977 sp->scsi_done(sp);
1978 }
1979
1980 /* Clean up disconnected queue, they have been invalidated
1981 * by the bus reset.
1982 */
1983 if (esp->disconnected_SC) {
1984 while ((sp = remove_first_SC(&esp->disconnected_SC)) != NULL) {
1985 esp_release_dmabufs(esp, sp);
1986 sp->result = (DID_RESET << 16);
1987
1988 sp->scsi_done(sp);
1989 }
1990 }
1991
1992 /* SCSI bus reset is complete. */
1993 esp->resetting_bus = 0;
1994 wake_up(&esp->reset_queue);
1995
1996 /* Ok, now it is safe to get commands going once more. */
1997 if (esp->issue_SC)
1998 esp_exec_cmd(esp);
1999
2000 return do_intr_end;
2001}
2002
2003static int esp_do_resetbus(struct esp *esp)
2004{
2005 ESPLOG(("esp%d: Resetting scsi bus\n", esp->esp_id));
2006 esp->resetting_bus = 1;
2007 esp_cmd(esp, ESP_CMD_RS);
2008
2009 return do_intr_end;
2010}
2011
2012/* Reset ESP chip, reset hanging bus, then kill active and
2013 * disconnected commands for targets without soft reset.
2014 *
2015 * The host_lock is acquired by caller.
2016 */
2017static int esp_reset(struct scsi_cmnd *SCptr)
2018{
2019 struct esp *esp = (struct esp *) SCptr->device->host->hostdata;
2020
2021 spin_lock_irq(esp->ehost->host_lock);
2022 (void) esp_do_resetbus(esp);
2023 spin_unlock_irq(esp->ehost->host_lock);
2024
2025 wait_event(esp->reset_queue, (esp->resetting_bus == 0));
2026
2027 return SUCCESS;
2028}
2029
2030/* Internal ESP done function. */
2031static void esp_done(struct esp *esp, int error)
2032{
2033 struct scsi_cmnd *done_SC = esp->current_SC;
2034
2035 esp->current_SC = NULL;
2036
2037 esp_release_dmabufs(esp, done_SC);
2038 done_SC->result = error;
2039
2040 done_SC->scsi_done(done_SC);
2041
2042 /* Bus is free, issue any commands in the queue. */
2043 if (esp->issue_SC && !esp->current_SC)
2044 esp_exec_cmd(esp);
2045
2046}
2047
2048/* Wheee, ESP interrupt engine. */
2049
2050/* Forward declarations. */
2051static int esp_do_phase_determine(struct esp *esp);
2052static int esp_do_data_finale(struct esp *esp);
2053static int esp_select_complete(struct esp *esp);
2054static int esp_do_status(struct esp *esp);
2055static int esp_do_msgin(struct esp *esp);
2056static int esp_do_msgindone(struct esp *esp);
2057static int esp_do_msgout(struct esp *esp);
2058static int esp_do_cmdbegin(struct esp *esp);
2059
2060#define sreg_datainp(__sreg) (((__sreg) & ESP_STAT_PMASK) == ESP_DIP)
2061#define sreg_dataoutp(__sreg) (((__sreg) & ESP_STAT_PMASK) == ESP_DOP)
2062
2063/* Read any bytes found in the FAS366 fifo, storing them into
2064 * the ESP driver software state structure.
2065 */
2066static void hme_fifo_read(struct esp *esp)
2067{
2068 u8 count = 0;
2069 u8 status = esp->sreg;
2070
2071 /* Cannot safely frob the fifo for these following cases, but
2072 * we must always read the fifo when the reselect interrupt
2073 * is pending.
2074 */
2075 if (((esp->ireg & ESP_INTR_RSEL) == 0) &&
2076 (sreg_datainp(status) ||
2077 sreg_dataoutp(status) ||
2078 (esp->current_SC &&
2079 esp->current_SC->SCp.phase == in_data_done))) {
2080 ESPHME(("<wkaround_skipped>"));
2081 } else {
2082 unsigned long fcnt = sbus_readb(esp->eregs + ESP_FFLAGS) & ESP_FF_FBYTES;
2083
2084 /* The HME stores bytes in multiples of 2 in the fifo. */
2085 ESPHME(("hme_fifo[fcnt=%d", (int)fcnt));
2086 while (fcnt) {
2087 esp->hme_fifo_workaround_buffer[count++] =
2088 sbus_readb(esp->eregs + ESP_FDATA);
2089 esp->hme_fifo_workaround_buffer[count++] =
2090 sbus_readb(esp->eregs + ESP_FDATA);
2091 ESPHME(("<%02x,%02x>", esp->hme_fifo_workaround_buffer[count-2], esp->hme_fifo_workaround_buffer[count-1]));
2092 fcnt--;
2093 }
2094 if (sbus_readb(esp->eregs + ESP_STATUS2) & ESP_STAT2_F1BYTE) {
2095 ESPHME(("<poke_byte>"));
2096 sbus_writeb(0, esp->eregs + ESP_FDATA);
2097 esp->hme_fifo_workaround_buffer[count++] =
2098 sbus_readb(esp->eregs + ESP_FDATA);
2099 ESPHME(("<%02x,0x00>", esp->hme_fifo_workaround_buffer[count-1]));
2100 ESPHME(("CMD_FLUSH"));
2101 esp_cmd(esp, ESP_CMD_FLUSH);
2102 } else {
2103 ESPHME(("no_xtra_byte"));
2104 }
2105 }
2106 ESPHME(("wkarnd_cnt=%d]", (int)count));
2107 esp->hme_fifo_workaround_count = count;
2108}
2109
2110static inline void hme_fifo_push(struct esp *esp, u8 *bytes, u8 count)
2111{
2112 esp_cmd(esp, ESP_CMD_FLUSH);
2113 while (count) {
2114 u8 tmp = *bytes++;
2115 sbus_writeb(tmp, esp->eregs + ESP_FDATA);
2116 sbus_writeb(0, esp->eregs + ESP_FDATA);
2117 count--;
2118 }
2119}
2120
2121/* We try to avoid some interrupts by jumping ahead and see if the ESP
2122 * has gotten far enough yet. Hence the following.
2123 */
2124static inline int skipahead1(struct esp *esp, struct scsi_cmnd *scp,
2125 int prev_phase, int new_phase)
2126{
2127 if (scp->SCp.sent_command != prev_phase)
2128 return 0;
2129 if (ESP_IRQ_P(esp->dregs)) {
2130 /* Yes, we are able to save an interrupt. */
2131 if (esp->erev == fashme)
2132 esp->sreg2 = sbus_readb(esp->eregs + ESP_STATUS2);
2133 esp->sreg = (sbus_readb(esp->eregs + ESP_STATUS) & ~(ESP_STAT_INTR));
2134 esp->ireg = sbus_readb(esp->eregs + ESP_INTRPT);
2135 if (esp->erev == fashme) {
2136 /* This chip is really losing. */
2137 ESPHME(("HME["));
2138 /* Must latch fifo before reading the interrupt
2139 * register else garbage ends up in the FIFO
2140 * which confuses the driver utterly.
2141 * Happy Meal indeed....
2142 */
2143 ESPHME(("fifo_workaround]"));
2144 if (!(esp->sreg2 & ESP_STAT2_FEMPTY) ||
2145 (esp->sreg2 & ESP_STAT2_F1BYTE))
2146 hme_fifo_read(esp);
2147 }
2148 if (!(esp->ireg & ESP_INTR_SR))
2149 return 0;
2150 else
2151 return do_reset_complete;
2152 }
2153 /* Ho hum, target is taking forever... */
2154 scp->SCp.sent_command = new_phase; /* so we don't recurse... */
2155 return do_intr_end;
2156}
2157
2158static inline int skipahead2(struct esp *esp, struct scsi_cmnd *scp,
2159 int prev_phase1, int prev_phase2, int new_phase)
2160{
2161 if (scp->SCp.sent_command != prev_phase1 &&
2162 scp->SCp.sent_command != prev_phase2)
2163 return 0;
2164 if (ESP_IRQ_P(esp->dregs)) {
2165 /* Yes, we are able to save an interrupt. */
2166 if (esp->erev == fashme)
2167 esp->sreg2 = sbus_readb(esp->eregs + ESP_STATUS2);
2168 esp->sreg = (sbus_readb(esp->eregs + ESP_STATUS) & ~(ESP_STAT_INTR));
2169 esp->ireg = sbus_readb(esp->eregs + ESP_INTRPT);
2170 if (esp->erev == fashme) {
2171 /* This chip is really losing. */
2172 ESPHME(("HME["));
2173
2174 /* Must latch fifo before reading the interrupt
2175 * register else garbage ends up in the FIFO
2176 * which confuses the driver utterly.
2177 * Happy Meal indeed....
2178 */
2179 ESPHME(("fifo_workaround]"));
2180 if (!(esp->sreg2 & ESP_STAT2_FEMPTY) ||
2181 (esp->sreg2 & ESP_STAT2_F1BYTE))
2182 hme_fifo_read(esp);
2183 }
2184 if (!(esp->ireg & ESP_INTR_SR))
2185 return 0;
2186 else
2187 return do_reset_complete;
2188 }
2189 /* Ho hum, target is taking forever... */
2190 scp->SCp.sent_command = new_phase; /* so we don't recurse... */
2191 return do_intr_end;
2192}
2193
2194/* Now some dma helpers. */
2195static void dma_setup(struct esp *esp, __u32 addr, int count, int write)
2196{
2197 u32 nreg = sbus_readl(esp->dregs + DMA_CSR);
2198
2199 if (write)
2200 nreg |= DMA_ST_WRITE;
2201 else
2202 nreg &= ~(DMA_ST_WRITE);
2203 nreg |= DMA_ENABLE;
2204 sbus_writel(nreg, esp->dregs + DMA_CSR);
2205 if (esp->dma->revision == dvmaesc1) {
2206 /* This ESC gate array sucks! */
2207 __u32 src = addr;
2208 __u32 dest = src + count;
2209
2210 if (dest & (PAGE_SIZE - 1))
2211 count = PAGE_ALIGN(count);
2212 sbus_writel(count, esp->dregs + DMA_COUNT);
2213 }
2214 sbus_writel(addr, esp->dregs + DMA_ADDR);
2215}
2216
2217static void dma_drain(struct esp *esp)
2218{
2219 u32 tmp;
2220
2221 if (esp->dma->revision == dvmahme)
2222 return;
2223 if ((tmp = sbus_readl(esp->dregs + DMA_CSR)) & DMA_FIFO_ISDRAIN) {
2224 switch (esp->dma->revision) {
2225 default:
2226 tmp |= DMA_FIFO_STDRAIN;
2227 sbus_writel(tmp, esp->dregs + DMA_CSR);
2228
2229 case dvmarev3:
2230 case dvmaesc1:
2231 while (sbus_readl(esp->dregs + DMA_CSR) & DMA_FIFO_ISDRAIN)
2232 udelay(1);
2233 };
2234 }
2235}
2236
2237static void dma_invalidate(struct esp *esp)
2238{
2239 u32 tmp;
2240
2241 if (esp->dma->revision == dvmahme) {
2242 sbus_writel(DMA_RST_SCSI, esp->dregs + DMA_CSR);
2243
2244 esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
2245 (DMA_PARITY_OFF | DMA_2CLKS |
2246 DMA_SCSI_DISAB | DMA_INT_ENAB)) &
2247 ~(DMA_ST_WRITE | DMA_ENABLE));
2248
2249 sbus_writel(0, esp->dregs + DMA_CSR);
2250 sbus_writel(esp->prev_hme_dmacsr, esp->dregs + DMA_CSR);
2251
2252 /* This is necessary to avoid having the SCSI channel
2253 * engine lock up on us.
2254 */
2255 sbus_writel(0, esp->dregs + DMA_ADDR);
2256 } else {
2257 while ((tmp = sbus_readl(esp->dregs + DMA_CSR)) & DMA_PEND_READ)
2258 udelay(1);
2259
2260 tmp &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
2261 tmp |= DMA_FIFO_INV;
2262 sbus_writel(tmp, esp->dregs + DMA_CSR);
2263 tmp &= ~DMA_FIFO_INV;
2264 sbus_writel(tmp, esp->dregs + DMA_CSR);
2265 }
2266}
2267
2268static inline void dma_flashclear(struct esp *esp)
2269{
2270 dma_drain(esp);
2271 dma_invalidate(esp);
2272}
2273
2274static int dma_can_transfer(struct esp *esp, struct scsi_cmnd *sp)
2275{
2276 __u32 base, end, sz;
2277
2278 if (esp->dma->revision == dvmarev3) {
2279 sz = sp->SCp.this_residual;
2280 if (sz > 0x1000000)
2281 sz = 0x1000000;
2282 } else {
2283 base = ((__u32)((unsigned long)sp->SCp.ptr));
2284 base &= (0x1000000 - 1);
2285 end = (base + sp->SCp.this_residual);
2286 if (end > 0x1000000)
2287 end = 0x1000000;
2288 sz = (end - base);
2289 }
2290 return sz;
2291}
2292
2293/* Misc. esp helper macros. */
2294#define esp_setcount(__eregs, __cnt, __hme) \
2295 sbus_writeb(((__cnt)&0xff), (__eregs) + ESP_TCLOW); \
2296 sbus_writeb((((__cnt)>>8)&0xff), (__eregs) + ESP_TCMED); \
2297 if (__hme) { \
2298 sbus_writeb((((__cnt)>>16)&0xff), (__eregs) + FAS_RLO); \
2299 sbus_writeb(0, (__eregs) + FAS_RHI); \
2300 }
2301
2302#define esp_getcount(__eregs, __hme) \
2303 ((sbus_readb((__eregs) + ESP_TCLOW)&0xff) | \
2304 ((sbus_readb((__eregs) + ESP_TCMED)&0xff) << 8) | \
2305 ((__hme) ? sbus_readb((__eregs) + FAS_RLO) << 16 : 0))
2306
2307#define fcount(__esp) \
2308 (((__esp)->erev == fashme) ? \
2309 (__esp)->hme_fifo_workaround_count : \
2310 sbus_readb(((__esp)->eregs) + ESP_FFLAGS) & ESP_FF_FBYTES)
2311
2312#define fnzero(__esp) \
2313 (((__esp)->erev == fashme) ? 0 : \
2314 sbus_readb(((__esp)->eregs) + ESP_FFLAGS) & ESP_FF_ONOTZERO)
2315
2316/* XXX speculative nops unnecessary when continuing amidst a data phase
2317 * XXX even on esp100!!! another case of flooding the bus with I/O reg
2318 * XXX writes...
2319 */
2320#define esp_maybe_nop(__esp) \
2321 if ((__esp)->erev == esp100) \
2322 esp_cmd((__esp), ESP_CMD_NULL)
2323
2324#define sreg_to_dataphase(__sreg) \
2325 ((((__sreg) & ESP_STAT_PMASK) == ESP_DOP) ? in_dataout : in_datain)
2326
2327/* The ESP100 when in synchronous data phase, can mistake a long final
2328 * REQ pulse from the target as an extra byte, it places whatever is on
2329 * the data lines into the fifo. For now, we will assume when this
2330 * happens that the target is a bit quirky and we don't want to
2331 * be talking synchronously to it anyways. Regardless, we need to
2332 * tell the ESP to eat the extraneous byte so that we can proceed
2333 * to the next phase.
2334 */
2335static int esp100_sync_hwbug(struct esp *esp, struct scsi_cmnd *sp, int fifocnt)
2336{
2337 /* Do not touch this piece of code. */
2338 if ((!(esp->erev == esp100)) ||
2339 (!(sreg_datainp((esp->sreg = sbus_readb(esp->eregs + ESP_STATUS))) &&
2340 !fifocnt) &&
2341 !(sreg_dataoutp(esp->sreg) && !fnzero(esp)))) {
2342 if (sp->SCp.phase == in_dataout)
2343 esp_cmd(esp, ESP_CMD_FLUSH);
2344 return 0;
2345 } else {
2346 /* Async mode for this guy. */
2347 build_sync_nego_msg(esp, 0, 0);
2348
2349 /* Ack the bogus byte, but set ATN first. */
2350 esp_cmd(esp, ESP_CMD_SATN);
2351 esp_cmd(esp, ESP_CMD_MOK);
2352 return 1;
2353 }
2354}
2355
2356/* This closes the window during a selection with a reselect pending, because
2357 * we use DMA for the selection process the FIFO should hold the correct
2358 * contents if we get reselected during this process. So we just need to
2359 * ack the possible illegal cmd interrupt pending on the esp100.
2360 */
2361static inline int esp100_reconnect_hwbug(struct esp *esp)
2362{
2363 u8 tmp;
2364
2365 if (esp->erev != esp100)
2366 return 0;
2367 tmp = sbus_readb(esp->eregs + ESP_INTRPT);
2368 if (tmp & ESP_INTR_SR)
2369 return 1;
2370 return 0;
2371}
2372
2373/* This verifies the BUSID bits during a reselection so that we know which
2374 * target is talking to us.
2375 */
2376static inline int reconnect_target(struct esp *esp)
2377{
2378 int it, me = esp->scsi_id_mask, targ = 0;
2379
2380 if (2 != fcount(esp))
2381 return -1;
2382 if (esp->erev == fashme) {
2383 /* HME does not latch it's own BUS ID bits during
2384 * a reselection. Also the target number is given
2385 * as an unsigned char, not as a sole bit number
2386 * like the other ESP's do.
2387 * Happy Meal indeed....
2388 */
2389 targ = esp->hme_fifo_workaround_buffer[0];
2390 } else {
2391 it = sbus_readb(esp->eregs + ESP_FDATA);
2392 if (!(it & me))
2393 return -1;
2394 it &= ~me;
2395 if (it & (it - 1))
2396 return -1;
2397 while (!(it & 1))
2398 targ++, it >>= 1;
2399 }
2400 return targ;
2401}
2402
2403/* This verifies the identify from the target so that we know which lun is
2404 * being reconnected.
2405 */
2406static inline int reconnect_lun(struct esp *esp)
2407{
2408 int lun;
2409
2410 if ((esp->sreg & ESP_STAT_PMASK) != ESP_MIP)
2411 return -1;
2412 if (esp->erev == fashme)
2413 lun = esp->hme_fifo_workaround_buffer[1];
2414 else
2415 lun = sbus_readb(esp->eregs + ESP_FDATA);
2416
2417 /* Yes, you read this correctly. We report lun of zero
2418 * if we see parity error. ESP reports parity error for
2419 * the lun byte, and this is the only way to hope to recover
2420 * because the target is connected.
2421 */
2422 if (esp->sreg & ESP_STAT_PERR)
2423 return 0;
2424
2425 /* Check for illegal bits being set in the lun. */
2426 if ((lun & 0x40) || !(lun & 0x80))
2427 return -1;
2428
2429 return lun & 7;
2430}
2431
2432/* This puts the driver in a state where it can revitalize a command that
2433 * is being continued due to reselection.
2434 */
2435static inline void esp_connect(struct esp *esp, struct scsi_cmnd *sp)
2436{
2437 struct esp_device *esp_dev = sp->device->hostdata;
2438
2439 if (esp->prev_soff != esp_dev->sync_max_offset ||
2440 esp->prev_stp != esp_dev->sync_min_period ||
2441 (esp->erev > esp100a &&
2442 esp->prev_cfg3 != esp->config3[sp->device->id])) {
2443 esp->prev_soff = esp_dev->sync_max_offset;
2444 esp->prev_stp = esp_dev->sync_min_period;
2445 sbus_writeb(esp->prev_soff, esp->eregs + ESP_SOFF);
2446 sbus_writeb(esp->prev_stp, esp->eregs + ESP_STP);
2447 if (esp->erev > esp100a) {
2448 esp->prev_cfg3 = esp->config3[sp->device->id];
2449 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
2450 }
2451 }
2452 esp->current_SC = sp;
2453}
2454
2455/* This will place the current working command back into the issue queue
2456 * if we are to receive a reselection amidst a selection attempt.
2457 */
2458static inline void esp_reconnect(struct esp *esp, struct scsi_cmnd *sp)
2459{
2460 if (!esp->disconnected_SC)
2461 ESPLOG(("esp%d: Weird, being reselected but disconnected "
2462 "command queue is empty.\n", esp->esp_id));
2463 esp->snip = 0;
2464 esp->current_SC = NULL;
2465 sp->SCp.phase = not_issued;
2466 append_SC(&esp->issue_SC, sp);
2467}
2468
2469/* Begin message in phase. */
2470static int esp_do_msgin(struct esp *esp)
2471{
2472 /* Must be very careful with the fifo on the HME */
2473 if ((esp->erev != fashme) ||
2474 !(sbus_readb(esp->eregs + ESP_STATUS2) & ESP_STAT2_FEMPTY))
2475 esp_cmd(esp, ESP_CMD_FLUSH);
2476 esp_maybe_nop(esp);
2477 esp_cmd(esp, ESP_CMD_TI);
2478 esp->msgin_len = 1;
2479 esp->msgin_ctr = 0;
2480 esp_advance_phase(esp->current_SC, in_msgindone);
2481 return do_work_bus;
2482}
2483
2484/* This uses various DMA csr fields and the fifo flags count value to
2485 * determine how many bytes were successfully sent/received by the ESP.
2486 */
2487static inline int esp_bytes_sent(struct esp *esp, int fifo_count)
2488{
2489 int rval = sbus_readl(esp->dregs + DMA_ADDR) - esp->esp_command_dvma;
2490
2491 if (esp->dma->revision == dvmarev1)
2492 rval -= (4 - ((sbus_readl(esp->dregs + DMA_CSR) & DMA_READ_AHEAD)>>11));
2493 return rval - fifo_count;
2494}
2495
2496static inline void advance_sg(struct scsi_cmnd *sp)
2497{
2498 ++sp->SCp.buffer;
2499 --sp->SCp.buffers_residual;
2500 sp->SCp.this_residual = sg_dma_len(sp->SCp.buffer);
2501 sp->SCp.ptr = (char *)((unsigned long)sg_dma_address(sp->SCp.buffer));
2502}
2503
2504/* Please note that the way I've coded these routines is that I _always_
2505 * check for a disconnect during any and all information transfer
2506 * phases. The SCSI standard states that the target _can_ cause a BUS
2507 * FREE condition by dropping all MSG/CD/IO/BSY signals. Also note
2508 * that during information transfer phases the target controls every
2509 * change in phase, the only thing the initiator can do is "ask" for
2510 * a message out phase by driving ATN true. The target can, and sometimes
2511 * will, completely ignore this request so we cannot assume anything when
2512 * we try to force a message out phase to abort/reset a target. Most of
2513 * the time the target will eventually be nice and go to message out, so
2514 * we may have to hold on to our state about what we want to tell the target
2515 * for some period of time.
2516 */
2517
2518/* I think I have things working here correctly. Even partial transfers
2519 * within a buffer or sub-buffer should not upset us at all no matter
2520 * how bad the target and/or ESP fucks things up.
2521 */
2522static int esp_do_data(struct esp *esp)
2523{
2524 struct scsi_cmnd *SCptr = esp->current_SC;
2525 int thisphase, hmuch;
2526
2527 ESPDATA(("esp_do_data: "));
2528 esp_maybe_nop(esp);
2529 thisphase = sreg_to_dataphase(esp->sreg);
2530 esp_advance_phase(SCptr, thisphase);
2531 ESPDATA(("newphase<%s> ", (thisphase == in_datain) ? "DATAIN" : "DATAOUT"));
2532 hmuch = dma_can_transfer(esp, SCptr);
2533 if (hmuch > (64 * 1024) && (esp->erev != fashme))
2534 hmuch = (64 * 1024);
2535 ESPDATA(("hmuch<%d> ", hmuch));
2536 esp->current_transfer_size = hmuch;
2537
2538 if (esp->erev == fashme) {
2539 u32 tmp = esp->prev_hme_dmacsr;
2540
2541 /* Always set the ESP count registers first. */
2542 esp_setcount(esp->eregs, hmuch, 1);
2543
2544 /* Get the DMA csr computed. */
2545 tmp |= (DMA_SCSI_DISAB | DMA_ENABLE);
2546 if (thisphase == in_datain)
2547 tmp |= DMA_ST_WRITE;
2548 else
2549 tmp &= ~(DMA_ST_WRITE);
2550 esp->prev_hme_dmacsr = tmp;
2551
2552 ESPDATA(("DMA|TI --> do_intr_end\n"));
2553 if (thisphase == in_datain) {
2554 sbus_writel(hmuch, esp->dregs + DMA_COUNT);
2555 esp_cmd(esp, ESP_CMD_DMA | ESP_CMD_TI);
2556 } else {
2557 esp_cmd(esp, ESP_CMD_DMA | ESP_CMD_TI);
2558 sbus_writel(hmuch, esp->dregs + DMA_COUNT);
2559 }
2560 sbus_writel((__u32)((unsigned long)SCptr->SCp.ptr), esp->dregs+DMA_ADDR);
2561 sbus_writel(esp->prev_hme_dmacsr, esp->dregs + DMA_CSR);
2562 } else {
2563 esp_setcount(esp->eregs, hmuch, 0);
2564 dma_setup(esp, ((__u32)((unsigned long)SCptr->SCp.ptr)),
2565 hmuch, (thisphase == in_datain));
2566 ESPDATA(("DMA|TI --> do_intr_end\n"));
2567 esp_cmd(esp, ESP_CMD_DMA | ESP_CMD_TI);
2568 }
2569 return do_intr_end;
2570}
2571
2572/* See how successful the data transfer was. */
2573static int esp_do_data_finale(struct esp *esp)
2574{
2575 struct scsi_cmnd *SCptr = esp->current_SC;
2576 struct esp_device *esp_dev = SCptr->device->hostdata;
2577 int bogus_data = 0, bytes_sent = 0, fifocnt, ecount = 0;
2578
2579 ESPDATA(("esp_do_data_finale: "));
2580
2581 if (SCptr->SCp.phase == in_datain) {
2582 if (esp->sreg & ESP_STAT_PERR) {
2583 /* Yuck, parity error. The ESP asserts ATN
2584 * so that we can go to message out phase
2585 * immediately and inform the target that
2586 * something bad happened.
2587 */
2588 ESPLOG(("esp%d: data bad parity detected.\n",
2589 esp->esp_id));
2590 esp->cur_msgout[0] = INITIATOR_ERROR;
2591 esp->msgout_len = 1;
2592 }
2593 dma_drain(esp);
2594 }
2595 dma_invalidate(esp);
2596
2597 /* This could happen for the above parity error case. */
2598 if (esp->ireg != ESP_INTR_BSERV) {
2599 /* Please go to msgout phase, please please please... */
2600 ESPLOG(("esp%d: !BSERV after data, probably to msgout\n",
2601 esp->esp_id));
2602 return esp_do_phase_determine(esp);
2603 }
2604
2605 /* Check for partial transfers and other horrible events.
2606 * Note, here we read the real fifo flags register even
2607 * on HME broken adapters because we skip the HME fifo
2608 * workaround code in esp_handle() if we are doing data
2609 * phase things. We don't want to fuck directly with
2610 * the fifo like that, especially if doing synchronous
2611 * transfers! Also, will need to double the count on
2612 * HME if we are doing wide transfers, as the HME fifo
2613 * will move and count 16-bit quantities during wide data.
2614 * SMCC _and_ Qlogic can both bite me.
2615 */
2616 fifocnt = (sbus_readb(esp->eregs + ESP_FFLAGS) & ESP_FF_FBYTES);
2617 if (esp->erev != fashme)
2618 ecount = esp_getcount(esp->eregs, 0);
2619 bytes_sent = esp->current_transfer_size;
2620
2621 ESPDATA(("trans_sz(%d), ", bytes_sent));
2622 if (esp->erev == fashme) {
2623 if (!(esp->sreg & ESP_STAT_TCNT)) {
2624 ecount = esp_getcount(esp->eregs, 1);
2625 bytes_sent -= ecount;
2626 }
2627
2628 /* Always subtract any cruft remaining in the FIFO. */
2629 if (esp->prev_cfg3 & ESP_CONFIG3_EWIDE)
2630 fifocnt <<= 1;
2631 if (SCptr->SCp.phase == in_dataout)
2632 bytes_sent -= fifocnt;
2633
2634 /* I have an IBM disk which exhibits the following
2635 * behavior during writes to it. It disconnects in
2636 * the middle of a partial transfer, the current sglist
2637 * buffer is 1024 bytes, the disk stops data transfer
2638 * at 512 bytes.
2639 *
2640 * However the FAS366 reports that 32 more bytes were
2641 * transferred than really were. This is precisely
2642 * the size of a fully loaded FIFO in wide scsi mode.
2643 * The FIFO state recorded indicates that it is empty.
2644 *
2645 * I have no idea if this is a bug in the FAS366 chip
2646 * or a bug in the firmware on this IBM disk. In any
2647 * event the following seems to be a good workaround. -DaveM
2648 */
2649 if (bytes_sent != esp->current_transfer_size &&
2650 SCptr->SCp.phase == in_dataout) {
2651 int mask = (64 - 1);
2652
2653 if ((esp->prev_cfg3 & ESP_CONFIG3_EWIDE) == 0)
2654 mask >>= 1;
2655
2656 if (bytes_sent & mask)
2657 bytes_sent -= (bytes_sent & mask);
2658 }
2659 } else {
2660 if (!(esp->sreg & ESP_STAT_TCNT))
2661 bytes_sent -= ecount;
2662 if (SCptr->SCp.phase == in_dataout)
2663 bytes_sent -= fifocnt;
2664 }
2665
2666 ESPDATA(("bytes_sent(%d), ", bytes_sent));
2667
2668 /* If we were in synchronous mode, check for peculiarities. */
2669 if (esp->erev == fashme) {
2670 if (esp_dev->sync_max_offset) {
2671 if (SCptr->SCp.phase == in_dataout)
2672 esp_cmd(esp, ESP_CMD_FLUSH);
2673 } else {
2674 esp_cmd(esp, ESP_CMD_FLUSH);
2675 }
2676 } else {
2677 if (esp_dev->sync_max_offset)
2678 bogus_data = esp100_sync_hwbug(esp, SCptr, fifocnt);
2679 else
2680 esp_cmd(esp, ESP_CMD_FLUSH);
2681 }
2682
2683 /* Until we are sure of what has happened, we are certainly
2684 * in the dark.
2685 */
2686 esp_advance_phase(SCptr, in_the_dark);
2687
2688 if (bytes_sent < 0) {
2689 /* I've seen this happen due to lost state in this
2690 * driver. No idea why it happened, but allowing
2691 * this value to be negative caused things to
2692 * lock up. This allows greater chance of recovery.
2693 * In fact every time I've seen this, it has been
2694 * a driver bug without question.
2695 */
2696 ESPLOG(("esp%d: yieee, bytes_sent < 0!\n", esp->esp_id));
2697 ESPLOG(("esp%d: csz=%d fifocount=%d ecount=%d\n",
2698 esp->esp_id,
2699 esp->current_transfer_size, fifocnt, ecount));
2700 ESPLOG(("esp%d: use_sg=%d ptr=%p this_residual=%d\n",
2701 esp->esp_id,
2702 SCptr->use_sg, SCptr->SCp.ptr, SCptr->SCp.this_residual));
2703 ESPLOG(("esp%d: Forcing async for target %d\n", esp->esp_id,
2704 SCptr->device->id));
2705 SCptr->device->borken = 1;
2706 esp_dev->sync = 0;
2707 bytes_sent = 0;
2708 }
2709
2710 /* Update the state of our transfer. */
2711 SCptr->SCp.ptr += bytes_sent;
2712 SCptr->SCp.this_residual -= bytes_sent;
2713 if (SCptr->SCp.this_residual < 0) {
2714 /* shit */
2715 ESPLOG(("esp%d: Data transfer overrun.\n", esp->esp_id));
2716 SCptr->SCp.this_residual = 0;
2717 }
2718
2719 /* Maybe continue. */
2720 if (!bogus_data) {
2721 ESPDATA(("!bogus_data, "));
2722
2723 /* NO MATTER WHAT, we advance the scatterlist,
2724 * if the target should decide to disconnect
2725 * in between scatter chunks (which is common)
2726 * we could die horribly! I used to have the sg
2727 * advance occur only if we are going back into
2728 * (or are staying in) a data phase, you can
2729 * imagine the hell I went through trying to
2730 * figure this out.
2731 */
2732 if (SCptr->use_sg && !SCptr->SCp.this_residual)
2733 advance_sg(SCptr);
2734 if (sreg_datainp(esp->sreg) || sreg_dataoutp(esp->sreg)) {
2735 ESPDATA(("to more data\n"));
2736 return esp_do_data(esp);
2737 }
2738 ESPDATA(("to new phase\n"));
2739 return esp_do_phase_determine(esp);
2740 }
2741 /* Bogus data, just wait for next interrupt. */
2742 ESPLOG(("esp%d: bogus_data during end of data phase\n",
2743 esp->esp_id));
2744 return do_intr_end;
2745}
2746
2747/* We received a non-good status return at the end of
2748 * running a SCSI command. This is used to decide if
2749 * we should clear our synchronous transfer state for
2750 * such a device when that happens.
2751 *
2752 * The idea is that when spinning up a disk or rewinding
2753 * a tape, we don't want to go into a loop re-negotiating
2754 * synchronous capabilities over and over.
2755 */
2756static int esp_should_clear_sync(struct scsi_cmnd *sp)
2757{
2758 u8 cmd = sp->cmnd[0];
2759
2760 /* These cases are for spinning up a disk and
2761 * waiting for that spinup to complete.
2762 */
2763 if (cmd == START_STOP)
2764 return 0;
2765
2766 if (cmd == TEST_UNIT_READY)
2767 return 0;
2768
2769 /* One more special case for SCSI tape drives,
2770 * this is what is used to probe the device for
2771 * completion of a rewind or tape load operation.
2772 */
2773 if (sp->device->type == TYPE_TAPE) {
2774 if (cmd == MODE_SENSE)
2775 return 0;
2776 }
2777
2778 return 1;
2779}
2780
2781/* Either a command is completing or a target is dropping off the bus
2782 * to continue the command in the background so we can do other work.
2783 */
2784static int esp_do_freebus(struct esp *esp)
2785{
2786 struct scsi_cmnd *SCptr = esp->current_SC;
2787 struct esp_device *esp_dev = SCptr->device->hostdata;
2788 int rval;
2789
2790 rval = skipahead2(esp, SCptr, in_status, in_msgindone, in_freeing);
2791 if (rval)
2792 return rval;
2793 if (esp->ireg != ESP_INTR_DC) {
2794 ESPLOG(("esp%d: Target will not disconnect\n", esp->esp_id));
2795 return do_reset_bus; /* target will not drop BSY... */
2796 }
2797 esp->msgout_len = 0;
2798 esp->prevmsgout = NOP;
2799 if (esp->prevmsgin == COMMAND_COMPLETE) {
2800 /* Normal end of nexus. */
2801 if (esp->disconnected_SC || (esp->erev == fashme))
2802 esp_cmd(esp, ESP_CMD_ESEL);
2803
2804 if (SCptr->SCp.Status != GOOD &&
2805 SCptr->SCp.Status != CONDITION_GOOD &&
2806 ((1<<SCptr->device->id) & esp->targets_present) &&
2807 esp_dev->sync &&
2808 esp_dev->sync_max_offset) {
2809 /* SCSI standard says that the synchronous capabilities
2810 * should be renegotiated at this point. Most likely
2811 * we are about to request sense from this target
2812 * in which case we want to avoid using sync
2813 * transfers until we are sure of the current target
2814 * state.
2815 */
2816 ESPMISC(("esp: Status <%d> for target %d lun %d\n",
2817 SCptr->SCp.Status, SCptr->device->id, SCptr->device->lun));
2818
2819 /* But don't do this when spinning up a disk at
2820 * boot time while we poll for completion as it
2821 * fills up the console with messages. Also, tapes
2822 * can report not ready many times right after
2823 * loading up a tape.
2824 */
2825 if (esp_should_clear_sync(SCptr) != 0)
2826 esp_dev->sync = 0;
2827 }
2828 ESPDISC(("F<%02x,%02x>", SCptr->device->id, SCptr->device->lun));
2829 esp_done(esp, ((SCptr->SCp.Status & 0xff) |
2830 ((SCptr->SCp.Message & 0xff)<<8) |
2831 (DID_OK << 16)));
2832 } else if (esp->prevmsgin == DISCONNECT) {
2833 /* Normal disconnect. */
2834 esp_cmd(esp, ESP_CMD_ESEL);
2835 ESPDISC(("D<%02x,%02x>", SCptr->device->id, SCptr->device->lun));
2836 append_SC(&esp->disconnected_SC, SCptr);
2837 esp->current_SC = NULL;
2838 if (esp->issue_SC)
2839 esp_exec_cmd(esp);
2840 } else {
2841 /* Driver bug, we do not expect a disconnect here
2842 * and should not have advanced the state engine
2843 * to in_freeing.
2844 */
2845 ESPLOG(("esp%d: last msg not disc and not cmd cmplt.\n",
2846 esp->esp_id));
2847 return do_reset_bus;
2848 }
2849 return do_intr_end;
2850}
2851
2852/* When a reselect occurs, and we cannot find the command to
2853 * reconnect to in our queues, we do this.
2854 */
2855static int esp_bad_reconnect(struct esp *esp)
2856{
2857 struct scsi_cmnd *sp;
2858
2859 ESPLOG(("esp%d: Eieeee, reconnecting unknown command!\n",
2860 esp->esp_id));
2861 ESPLOG(("QUEUE DUMP\n"));
2862 sp = esp->issue_SC;
2863 ESPLOG(("esp%d: issue_SC[", esp->esp_id));
2864 while (sp) {
2865 ESPLOG(("<%02x,%02x>", sp->device->id, sp->device->lun));
2866 sp = (struct scsi_cmnd *) sp->host_scribble;
2867 }
2868 ESPLOG(("]\n"));
2869 sp = esp->current_SC;
2870 ESPLOG(("esp%d: current_SC[", esp->esp_id));
2871 if (sp)
2872 ESPLOG(("<%02x,%02x>", sp->device->id, sp->device->lun));
2873 else
2874 ESPLOG(("<NULL>"));
2875 ESPLOG(("]\n"));
2876 sp = esp->disconnected_SC;
2877 ESPLOG(("esp%d: disconnected_SC[", esp->esp_id));
2878 while (sp) {
2879 ESPLOG(("<%02x,%02x>", sp->device->id, sp->device->lun));
2880 sp = (struct scsi_cmnd *) sp->host_scribble;
2881 }
2882 ESPLOG(("]\n"));
2883 return do_reset_bus;
2884}
2885
2886/* Do the needy when a target tries to reconnect to us. */
2887static int esp_do_reconnect(struct esp *esp)
2888{
2889 int lun, target;
2890 struct scsi_cmnd *SCptr;
2891
2892 /* Check for all bogus conditions first. */
2893 target = reconnect_target(esp);
2894 if (target < 0) {
2895 ESPDISC(("bad bus bits\n"));
2896 return do_reset_bus;
2897 }
2898 lun = reconnect_lun(esp);
2899 if (lun < 0) {
2900 ESPDISC(("target=%2x, bad identify msg\n", target));
2901 return do_reset_bus;
2902 }
2903
2904 /* Things look ok... */
2905 ESPDISC(("R<%02x,%02x>", target, lun));
2906
2907 /* Must not flush FIFO or DVMA on HME. */
2908 if (esp->erev != fashme) {
2909 esp_cmd(esp, ESP_CMD_FLUSH);
2910 if (esp100_reconnect_hwbug(esp))
2911 return do_reset_bus;
2912 esp_cmd(esp, ESP_CMD_NULL);
2913 }
2914
2915 SCptr = remove_SC(&esp->disconnected_SC, (u8) target, (u8) lun);
2916 if (!SCptr)
2917 return esp_bad_reconnect(esp);
2918
2919 esp_connect(esp, SCptr);
2920 esp_cmd(esp, ESP_CMD_MOK);
2921
2922 if (esp->erev == fashme)
2923 sbus_writeb(((SCptr->device->id & 0xf) |
2924 (ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT)),
2925 esp->eregs + ESP_BUSID);
2926
2927 /* Reconnect implies a restore pointers operation. */
2928 esp_restore_pointers(esp, SCptr);
2929
2930 esp->snip = 0;
2931 esp_advance_phase(SCptr, in_the_dark);
2932 return do_intr_end;
2933}
2934
2935/* End of NEXUS (hopefully), pick up status + message byte then leave if
2936 * all goes well.
2937 */
2938static int esp_do_status(struct esp *esp)
2939{
2940 struct scsi_cmnd *SCptr = esp->current_SC;
2941 int intr, rval;
2942
2943 rval = skipahead1(esp, SCptr, in_the_dark, in_status);
2944 if (rval)
2945 return rval;
2946 intr = esp->ireg;
2947 ESPSTAT(("esp_do_status: "));
2948 if (intr != ESP_INTR_DC) {
2949 int message_out = 0; /* for parity problems */
2950
2951 /* Ack the message. */
2952 ESPSTAT(("ack msg, "));
2953 esp_cmd(esp, ESP_CMD_MOK);
2954
2955 if (esp->erev != fashme) {
2956 dma_flashclear(esp);
2957
2958 /* Wait till the first bits settle. */
2959 while (esp->esp_command[0] == 0xff)
2960 udelay(1);
2961 } else {
2962 esp->esp_command[0] = esp->hme_fifo_workaround_buffer[0];
2963 esp->esp_command[1] = esp->hme_fifo_workaround_buffer[1];
2964 }
2965
2966 ESPSTAT(("got something, "));
2967 /* ESP chimes in with one of
2968 *
2969 * 1) function done interrupt:
2970 * both status and message in bytes
2971 * are available
2972 *
2973 * 2) bus service interrupt:
2974 * only status byte was acquired
2975 *
2976 * 3) Anything else:
2977 * can't happen, but we test for it
2978 * anyways
2979 *
2980 * ALSO: If bad parity was detected on either
2981 * the status _or_ the message byte then
2982 * the ESP has asserted ATN on the bus
2983 * and we must therefore wait for the
2984 * next phase change.
2985 */
2986 if (intr & ESP_INTR_FDONE) {
2987 /* We got it all, hallejulia. */
2988 ESPSTAT(("got both, "));
2989 SCptr->SCp.Status = esp->esp_command[0];
2990 SCptr->SCp.Message = esp->esp_command[1];
2991 esp->prevmsgin = SCptr->SCp.Message;
2992 esp->cur_msgin[0] = SCptr->SCp.Message;
2993 if (esp->sreg & ESP_STAT_PERR) {
2994 /* There was bad parity for the
2995 * message byte, the status byte
2996 * was ok.
2997 */
2998 message_out = MSG_PARITY_ERROR;
2999 }
3000 } else if (intr == ESP_INTR_BSERV) {
3001 /* Only got status byte. */
3002 ESPLOG(("esp%d: got status only, ", esp->esp_id));
3003 if (!(esp->sreg & ESP_STAT_PERR)) {
3004 SCptr->SCp.Status = esp->esp_command[0];
3005 SCptr->SCp.Message = 0xff;
3006 } else {
3007 /* The status byte had bad parity.
3008 * we leave the scsi_pointer Status
3009 * field alone as we set it to a default
3010 * of CHECK_CONDITION in esp_queue.
3011 */
3012 message_out = INITIATOR_ERROR;
3013 }
3014 } else {
3015 /* This shouldn't happen ever. */
3016 ESPSTAT(("got bolixed\n"));
3017 esp_advance_phase(SCptr, in_the_dark);
3018 return esp_do_phase_determine(esp);
3019 }
3020
3021 if (!message_out) {
3022 ESPSTAT(("status=%2x msg=%2x, ", SCptr->SCp.Status,
3023 SCptr->SCp.Message));
3024 if (SCptr->SCp.Message == COMMAND_COMPLETE) {
3025 ESPSTAT(("and was COMMAND_COMPLETE\n"));
3026 esp_advance_phase(SCptr, in_freeing);
3027 return esp_do_freebus(esp);
3028 } else {
3029 ESPLOG(("esp%d: and _not_ COMMAND_COMPLETE\n",
3030 esp->esp_id));
3031 esp->msgin_len = esp->msgin_ctr = 1;
3032 esp_advance_phase(SCptr, in_msgindone);
3033 return esp_do_msgindone(esp);
3034 }
3035 } else {
3036 /* With luck we'll be able to let the target
3037 * know that bad parity happened, it will know
3038 * which byte caused the problems and send it
3039 * again. For the case where the status byte
3040 * receives bad parity, I do not believe most
3041 * targets recover very well. We'll see.
3042 */
3043 ESPLOG(("esp%d: bad parity somewhere mout=%2x\n",
3044 esp->esp_id, message_out));
3045 esp->cur_msgout[0] = message_out;
3046 esp->msgout_len = esp->msgout_ctr = 1;
3047 esp_advance_phase(SCptr, in_the_dark);
3048 return esp_do_phase_determine(esp);
3049 }
3050 } else {
3051 /* If we disconnect now, all hell breaks loose. */
3052 ESPLOG(("esp%d: whoops, disconnect\n", esp->esp_id));
3053 esp_advance_phase(SCptr, in_the_dark);
3054 return esp_do_phase_determine(esp);
3055 }
3056}
3057
3058static int esp_enter_status(struct esp *esp)
3059{
3060 u8 thecmd = ESP_CMD_ICCSEQ;
3061
3062 esp_cmd(esp, ESP_CMD_FLUSH);
3063 if (esp->erev != fashme) {
3064 u32 tmp;
3065
3066 esp->esp_command[0] = esp->esp_command[1] = 0xff;
3067 sbus_writeb(2, esp->eregs + ESP_TCLOW);
3068 sbus_writeb(0, esp->eregs + ESP_TCMED);
3069 tmp = sbus_readl(esp->dregs + DMA_CSR);
3070 tmp |= (DMA_ST_WRITE | DMA_ENABLE);
3071 sbus_writel(tmp, esp->dregs + DMA_CSR);
3072 if (esp->dma->revision == dvmaesc1)
3073 sbus_writel(0x100, esp->dregs + DMA_COUNT);
3074 sbus_writel(esp->esp_command_dvma, esp->dregs + DMA_ADDR);
3075 thecmd |= ESP_CMD_DMA;
3076 }
3077 esp_cmd(esp, thecmd);
3078 esp_advance_phase(esp->current_SC, in_status);
3079
3080 return esp_do_status(esp);
3081}
3082
3083static int esp_disconnect_amidst_phases(struct esp *esp)
3084{
3085 struct scsi_cmnd *sp = esp->current_SC;
3086 struct esp_device *esp_dev = sp->device->hostdata;
3087
3088 /* This means real problems if we see this
3089 * here. Unless we were actually trying
3090 * to force the device to abort/reset.
3091 */
3092 ESPLOG(("esp%d Disconnect amidst phases, ", esp->esp_id));
3093 ESPLOG(("pphase<%s> cphase<%s>, ",
3094 phase_string(sp->SCp.phase),
3095 phase_string(sp->SCp.sent_command)));
3096
3097 if (esp->disconnected_SC != NULL || (esp->erev == fashme))
3098 esp_cmd(esp, ESP_CMD_ESEL);
3099
3100 switch (esp->cur_msgout[0]) {
3101 default:
3102 /* We didn't expect this to happen at all. */
3103 ESPLOG(("device is bolixed\n"));
3104 esp_advance_phase(sp, in_tgterror);
3105 esp_done(esp, (DID_ERROR << 16));
3106 break;
3107
3108 case BUS_DEVICE_RESET:
3109 ESPLOG(("device reset successful\n"));
3110 esp_dev->sync_max_offset = 0;
3111 esp_dev->sync_min_period = 0;
3112 esp_dev->sync = 0;
3113 esp_advance_phase(sp, in_resetdev);
3114 esp_done(esp, (DID_RESET << 16));
3115 break;
3116
3117 case ABORT:
3118 ESPLOG(("device abort successful\n"));
3119 esp_advance_phase(sp, in_abortone);
3120 esp_done(esp, (DID_ABORT << 16));
3121 break;
3122
3123 };
3124 return do_intr_end;
3125}
3126
3127static int esp_enter_msgout(struct esp *esp)
3128{
3129 esp_advance_phase(esp->current_SC, in_msgout);
3130 return esp_do_msgout(esp);
3131}
3132
3133static int esp_enter_msgin(struct esp *esp)
3134{
3135 esp_advance_phase(esp->current_SC, in_msgin);
3136 return esp_do_msgin(esp);
3137}
3138
3139static int esp_enter_cmd(struct esp *esp)
3140{
3141 esp_advance_phase(esp->current_SC, in_cmdbegin);
3142 return esp_do_cmdbegin(esp);
3143}
3144
3145static int esp_enter_badphase(struct esp *esp)
3146{
3147 ESPLOG(("esp%d: Bizarre bus phase %2x.\n", esp->esp_id,
3148 esp->sreg & ESP_STAT_PMASK));
3149 return do_reset_bus;
3150}
3151
3152typedef int (*espfunc_t)(struct esp *);
3153
3154static espfunc_t phase_vector[] = {
3155 esp_do_data, /* ESP_DOP */
3156 esp_do_data, /* ESP_DIP */
3157 esp_enter_cmd, /* ESP_CMDP */
3158 esp_enter_status, /* ESP_STATP */
3159 esp_enter_badphase, /* ESP_STAT_PMSG */
3160 esp_enter_badphase, /* ESP_STAT_PMSG | ESP_STAT_PIO */
3161 esp_enter_msgout, /* ESP_MOP */
3162 esp_enter_msgin, /* ESP_MIP */
3163};
3164
3165/* The target has control of the bus and we have to see where it has
3166 * taken us.
3167 */
3168static int esp_do_phase_determine(struct esp *esp)
3169{
3170 if ((esp->ireg & ESP_INTR_DC) != 0)
3171 return esp_disconnect_amidst_phases(esp);
3172 return phase_vector[esp->sreg & ESP_STAT_PMASK](esp);
3173}
3174
3175/* First interrupt after exec'ing a cmd comes here. */
3176static int esp_select_complete(struct esp *esp)
3177{
3178 struct scsi_cmnd *SCptr = esp->current_SC;
3179 struct esp_device *esp_dev = SCptr->device->hostdata;
3180 int cmd_bytes_sent, fcnt;
3181
3182 if (esp->erev != fashme)
3183 esp->seqreg = (sbus_readb(esp->eregs + ESP_SSTEP) & ESP_STEP_VBITS);
3184
3185 if (esp->erev == fashme)
3186 fcnt = esp->hme_fifo_workaround_count;
3187 else
3188 fcnt = (sbus_readb(esp->eregs + ESP_FFLAGS) & ESP_FF_FBYTES);
3189
3190 cmd_bytes_sent = esp_bytes_sent(esp, fcnt);
3191 dma_invalidate(esp);
3192
3193 /* Let's check to see if a reselect happened
3194 * while we we're trying to select. This must
3195 * be checked first.
3196 */
3197 if (esp->ireg == (ESP_INTR_RSEL | ESP_INTR_FDONE)) {
3198 esp_reconnect(esp, SCptr);
3199 return esp_do_reconnect(esp);
3200 }
3201
3202 /* Looks like things worked, we should see a bus service &
3203 * a function complete interrupt at this point. Note we
3204 * are doing a direct comparison because we don't want to
3205 * be fooled into thinking selection was successful if
3206 * ESP_INTR_DC is set, see below.
3207 */
3208 if (esp->ireg == (ESP_INTR_FDONE | ESP_INTR_BSERV)) {
3209 /* target speaks... */
3210 esp->targets_present |= (1<<SCptr->device->id);
3211
3212 /* What if the target ignores the sdtr? */
3213 if (esp->snip)
3214 esp_dev->sync = 1;
3215
3216 /* See how far, if at all, we got in getting
3217 * the information out to the target.
3218 */
3219 switch (esp->seqreg) {
3220 default:
3221
3222 case ESP_STEP_ASEL:
3223 /* Arbitration won, target selected, but
3224 * we are in some phase which is not command
3225 * phase nor is it message out phase.
3226 *
3227 * XXX We've confused the target, obviously.
3228 * XXX So clear it's state, but we also end
3229 * XXX up clearing everyone elses. That isn't
3230 * XXX so nice. I'd like to just reset this
3231 * XXX target, but if I cannot even get it's
3232 * XXX attention and finish selection to talk
3233 * XXX to it, there is not much more I can do.
3234 * XXX If we have a loaded bus we're going to
3235 * XXX spend the next second or so renegotiating
3236 * XXX for synchronous transfers.
3237 */
3238 ESPLOG(("esp%d: STEP_ASEL for tgt %d\n",
3239 esp->esp_id, SCptr->device->id));
3240
3241 case ESP_STEP_SID:
3242 /* Arbitration won, target selected, went
3243 * to message out phase, sent one message
3244 * byte, then we stopped. ATN is asserted
3245 * on the SCSI bus and the target is still
3246 * there hanging on. This is a legal
3247 * sequence step if we gave the ESP a select
3248 * and stop command.
3249 *
3250 * XXX See above, I could set the borken flag
3251 * XXX in the device struct and retry the
3252 * XXX command. But would that help for
3253 * XXX tagged capable targets?
3254 */
3255
3256 case ESP_STEP_NCMD:
3257 /* Arbitration won, target selected, maybe
3258 * sent the one message byte in message out
3259 * phase, but we did not go to command phase
3260 * in the end. Actually, we could have sent
3261 * only some of the message bytes if we tried
3262 * to send out the entire identify and tag
3263 * message using ESP_CMD_SA3.
3264 */
3265 cmd_bytes_sent = 0;
3266 break;
3267
3268 case ESP_STEP_PPC:
3269 /* No, not the powerPC pinhead. Arbitration
3270 * won, all message bytes sent if we went to
3271 * message out phase, went to command phase
3272 * but only part of the command was sent.
3273 *
3274 * XXX I've seen this, but usually in conjunction
3275 * XXX with a gross error which appears to have
3276 * XXX occurred between the time I told the
3277 * XXX ESP to arbitrate and when I got the
3278 * XXX interrupt. Could I have misloaded the
3279 * XXX command bytes into the fifo? Actually,
3280 * XXX I most likely missed a phase, and therefore
3281 * XXX went into never never land and didn't even
3282 * XXX know it. That was the old driver though.
3283 * XXX What is even more peculiar is that the ESP
3284 * XXX showed the proper function complete and
3285 * XXX bus service bits in the interrupt register.
3286 */
3287
3288 case ESP_STEP_FINI4:
3289 case ESP_STEP_FINI5:
3290 case ESP_STEP_FINI6:
3291 case ESP_STEP_FINI7:
3292 /* Account for the identify message */
3293 if (SCptr->SCp.phase == in_slct_norm)
3294 cmd_bytes_sent -= 1;
3295 };
3296
3297 if (esp->erev != fashme)
3298 esp_cmd(esp, ESP_CMD_NULL);
3299
3300 /* Be careful, we could really get fucked during synchronous
3301 * data transfers if we try to flush the fifo now.
3302 */
3303 if ((esp->erev != fashme) && /* not a Happy Meal and... */
3304 !fcnt && /* Fifo is empty and... */
3305 /* either we are not doing synchronous transfers or... */
3306 (!esp_dev->sync_max_offset ||
3307 /* We are not going into data in phase. */
3308 ((esp->sreg & ESP_STAT_PMASK) != ESP_DIP)))
3309 esp_cmd(esp, ESP_CMD_FLUSH); /* flush is safe */
3310
3311 /* See how far we got if this is not a slow command. */
3312 if (!esp->esp_slowcmd) {
3313 if (cmd_bytes_sent < 0)
3314 cmd_bytes_sent = 0;
3315 if (cmd_bytes_sent != SCptr->cmd_len) {
3316 /* Crapola, mark it as a slowcmd
3317 * so that we have some chance of
3318 * keeping the command alive with
3319 * good luck.
3320 *
3321 * XXX Actually, if we didn't send it all
3322 * XXX this means either we didn't set things
3323 * XXX up properly (driver bug) or the target
3324 * XXX or the ESP detected parity on one of
3325 * XXX the command bytes. This makes much
3326 * XXX more sense, and therefore this code
3327 * XXX should be changed to send out a
3328 * XXX parity error message or if the status
3329 * XXX register shows no parity error then
3330 * XXX just expect the target to bring the
3331 * XXX bus into message in phase so that it
3332 * XXX can send us the parity error message.
3333 * XXX SCSI sucks...
3334 */
3335 esp->esp_slowcmd = 1;
3336 esp->esp_scmdp = &(SCptr->cmnd[cmd_bytes_sent]);
3337 esp->esp_scmdleft = (SCptr->cmd_len - cmd_bytes_sent);
3338 }
3339 }
3340
3341 /* Now figure out where we went. */
3342 esp_advance_phase(SCptr, in_the_dark);
3343 return esp_do_phase_determine(esp);
3344 }
3345
3346 /* Did the target even make it? */
3347 if (esp->ireg == ESP_INTR_DC) {
3348 /* wheee... nobody there or they didn't like
3349 * what we told it to do, clean up.
3350 */
3351
3352 /* If anyone is off the bus, but working on
3353 * a command in the background for us, tell
3354 * the ESP to listen for them.
3355 */
3356 if (esp->disconnected_SC)
3357 esp_cmd(esp, ESP_CMD_ESEL);
3358
3359 if (((1<<SCptr->device->id) & esp->targets_present) &&
3360 esp->seqreg != 0 &&
3361 (esp->cur_msgout[0] == EXTENDED_MESSAGE) &&
3362 (SCptr->SCp.phase == in_slct_msg ||
3363 SCptr->SCp.phase == in_slct_stop)) {
3364 /* shit */
3365 esp->snip = 0;
3366 ESPLOG(("esp%d: Failed synchronous negotiation for target %d "
3367 "lun %d\n", esp->esp_id, SCptr->device->id, SCptr->device->lun));
3368 esp_dev->sync_max_offset = 0;
3369 esp_dev->sync_min_period = 0;
3370 esp_dev->sync = 1; /* so we don't negotiate again */
3371
3372 /* Run the command again, this time though we
3373 * won't try to negotiate for synchronous transfers.
3374 *
3375 * XXX I'd like to do something like send an
3376 * XXX INITIATOR_ERROR or ABORT message to the
3377 * XXX target to tell it, "Sorry I confused you,
3378 * XXX please come back and I will be nicer next
3379 * XXX time". But that requires having the target
3380 * XXX on the bus, and it has dropped BSY on us.
3381 */
3382 esp->current_SC = NULL;
3383 esp_advance_phase(SCptr, not_issued);
3384 prepend_SC(&esp->issue_SC, SCptr);
3385 esp_exec_cmd(esp);
3386 return do_intr_end;
3387 }
3388
3389 /* Ok, this is normal, this is what we see during boot
3390 * or whenever when we are scanning the bus for targets.
3391 * But first make sure that is really what is happening.
3392 */
3393 if (((1<<SCptr->device->id) & esp->targets_present)) {
3394 ESPLOG(("esp%d: Warning, live target %d not responding to "
3395 "selection.\n", esp->esp_id, SCptr->device->id));
3396
3397 /* This _CAN_ happen. The SCSI standard states that
3398 * the target is to _not_ respond to selection if
3399 * _it_ detects bad parity on the bus for any reason.
3400 * Therefore, we assume that if we've talked successfully
3401 * to this target before, bad parity is the problem.
3402 */
3403 esp_done(esp, (DID_PARITY << 16));
3404 } else {
3405 /* Else, there really isn't anyone there. */
3406 ESPMISC(("esp: selection failure, maybe nobody there?\n"));
3407 ESPMISC(("esp: target %d lun %d\n",
3408 SCptr->device->id, SCptr->device->lun));
3409 esp_done(esp, (DID_BAD_TARGET << 16));
3410 }
3411 return do_intr_end;
3412 }
3413
3414 ESPLOG(("esp%d: Selection failure.\n", esp->esp_id));
3415 printk("esp%d: Currently -- ", esp->esp_id);
3416 esp_print_ireg(esp->ireg); printk(" ");
3417 esp_print_statreg(esp->sreg); printk(" ");
3418 esp_print_seqreg(esp->seqreg); printk("\n");
3419 printk("esp%d: New -- ", esp->esp_id);
3420 esp->sreg = sbus_readb(esp->eregs + ESP_STATUS);
3421 esp->seqreg = sbus_readb(esp->eregs + ESP_SSTEP);
3422 esp->ireg = sbus_readb(esp->eregs + ESP_INTRPT);
3423 esp_print_ireg(esp->ireg); printk(" ");
3424 esp_print_statreg(esp->sreg); printk(" ");
3425 esp_print_seqreg(esp->seqreg); printk("\n");
3426 ESPLOG(("esp%d: resetting bus\n", esp->esp_id));
3427 return do_reset_bus; /* ugh... */
3428}
3429
3430/* Continue reading bytes for msgin phase. */
3431static int esp_do_msgincont(struct esp *esp)
3432{
3433 if (esp->ireg & ESP_INTR_BSERV) {
3434 /* in the right phase too? */
3435 if ((esp->sreg & ESP_STAT_PMASK) == ESP_MIP) {
3436 /* phew... */
3437 esp_cmd(esp, ESP_CMD_TI);
3438 esp_advance_phase(esp->current_SC, in_msgindone);
3439 return do_intr_end;
3440 }
3441
3442 /* We changed phase but ESP shows bus service,
3443 * in this case it is most likely that we, the
3444 * hacker who has been up for 20hrs straight
3445 * staring at the screen, drowned in coffee
3446 * smelling like retched cigarette ashes
3447 * have miscoded something..... so, try to
3448 * recover as best we can.
3449 */
3450 ESPLOG(("esp%d: message in mis-carriage.\n", esp->esp_id));
3451 }
3452 esp_advance_phase(esp->current_SC, in_the_dark);
3453 return do_phase_determine;
3454}
3455
3456static int check_singlebyte_msg(struct esp *esp)
3457{
3458 esp->prevmsgin = esp->cur_msgin[0];
3459 if (esp->cur_msgin[0] & 0x80) {
3460 /* wheee... */
3461 ESPLOG(("esp%d: target sends identify amidst phases\n",
3462 esp->esp_id));
3463 esp_advance_phase(esp->current_SC, in_the_dark);
3464 return 0;
3465 } else if (((esp->cur_msgin[0] & 0xf0) == 0x20) ||
3466 (esp->cur_msgin[0] == EXTENDED_MESSAGE)) {
3467 esp->msgin_len = 2;
3468 esp_advance_phase(esp->current_SC, in_msgincont);
3469 return 0;
3470 }
3471 esp_advance_phase(esp->current_SC, in_the_dark);
3472 switch (esp->cur_msgin[0]) {
3473 default:
3474 /* We don't want to hear about it. */
3475 ESPLOG(("esp%d: msg %02x which we don't know about\n", esp->esp_id,
3476 esp->cur_msgin[0]));
3477 return MESSAGE_REJECT;
3478
3479 case NOP:
3480 ESPLOG(("esp%d: target %d sends a nop\n", esp->esp_id,
3481 esp->current_SC->device->id));
3482 return 0;
3483
3484 case RESTORE_POINTERS:
3485 /* In this case we might also have to backup the
3486 * "slow command" pointer. It is rare to get such
3487 * a save/restore pointer sequence so early in the
3488 * bus transition sequences, but cover it.
3489 */
3490 if (esp->esp_slowcmd) {
3491 esp->esp_scmdleft = esp->current_SC->cmd_len;
3492 esp->esp_scmdp = &esp->current_SC->cmnd[0];
3493 }
3494 esp_restore_pointers(esp, esp->current_SC);
3495 return 0;
3496
3497 case SAVE_POINTERS:
3498 esp_save_pointers(esp, esp->current_SC);
3499 return 0;
3500
3501 case COMMAND_COMPLETE:
3502 case DISCONNECT:
3503 /* Freeing the bus, let it go. */
3504 esp->current_SC->SCp.phase = in_freeing;
3505 return 0;
3506
3507 case MESSAGE_REJECT:
3508 ESPMISC(("msg reject, "));
3509 if (esp->prevmsgout == EXTENDED_MESSAGE) {
3510 struct esp_device *esp_dev = esp->current_SC->device->hostdata;
3511
3512 /* Doesn't look like this target can
3513 * do synchronous or WIDE transfers.
3514 */
3515 ESPSDTR(("got reject, was trying nego, clearing sync/WIDE\n"));
3516 esp_dev->sync = 1;
3517 esp_dev->wide = 1;
3518 esp_dev->sync_min_period = 0;
3519 esp_dev->sync_max_offset = 0;
3520 return 0;
3521 } else {
3522 ESPMISC(("not sync nego, sending ABORT\n"));
3523 return ABORT;
3524 }
3525 };
3526}
3527
3528/* Target negotiates for synchronous transfers before we do, this
3529 * is legal although very strange. What is even funnier is that
3530 * the SCSI2 standard specifically recommends against targets doing
3531 * this because so many initiators cannot cope with this occurring.
3532 */
3533static int target_with_ants_in_pants(struct esp *esp,
3534 struct scsi_cmnd *SCptr,
3535 struct esp_device *esp_dev)
3536{
3537 if (esp_dev->sync || SCptr->device->borken) {
3538 /* sorry, no can do */
3539 ESPSDTR(("forcing to async, "));
3540 build_sync_nego_msg(esp, 0, 0);
3541 esp_dev->sync = 1;
3542 esp->snip = 1;
3543 ESPLOG(("esp%d: hoping for msgout\n", esp->esp_id));
3544 esp_advance_phase(SCptr, in_the_dark);
3545 return EXTENDED_MESSAGE;
3546 }
3547
3548 /* Ok, we'll check them out... */
3549 return 0;
3550}
3551
3552static void sync_report(struct esp *esp)
3553{
3554 int msg3, msg4;
3555 char *type;
3556
3557 msg3 = esp->cur_msgin[3];
3558 msg4 = esp->cur_msgin[4];
3559 if (msg4) {
3560 int hz = 1000000000 / (msg3 * 4);
3561 int integer = hz / 1000000;
3562 int fraction = (hz - (integer * 1000000)) / 10000;
3563 if ((esp->erev == fashme) &&
3564 (esp->config3[esp->current_SC->device->id] & ESP_CONFIG3_EWIDE)) {
3565 type = "FAST-WIDE";
3566 integer <<= 1;
3567 fraction <<= 1;
3568 } else if ((msg3 * 4) < 200) {
3569 type = "FAST";
3570 } else {
3571 type = "synchronous";
3572 }
3573
3574 /* Do not transform this back into one big printk
3575 * again, it triggers a bug in our sparc64-gcc272
3576 * sibling call optimization. -DaveM
3577 */
3578 ESPLOG((KERN_INFO "esp%d: target %d ",
3579 esp->esp_id, esp->current_SC->device->id));
3580 ESPLOG(("[period %dns offset %d %d.%02dMHz ",
3581 (int) msg3 * 4, (int) msg4,
3582 integer, fraction));
3583 ESPLOG(("%s SCSI%s]\n", type,
3584 (((msg3 * 4) < 200) ? "-II" : "")));
3585 } else {
3586 ESPLOG((KERN_INFO "esp%d: target %d asynchronous\n",
3587 esp->esp_id, esp->current_SC->device->id));
3588 }
3589}
3590
3591static int check_multibyte_msg(struct esp *esp)
3592{
3593 struct scsi_cmnd *SCptr = esp->current_SC;
3594 struct esp_device *esp_dev = SCptr->device->hostdata;
3595 u8 regval = 0;
3596 int message_out = 0;
3597
3598 ESPSDTR(("chk multibyte msg: "));
3599 if (esp->cur_msgin[2] == EXTENDED_SDTR) {
3600 int period = esp->cur_msgin[3];
3601 int offset = esp->cur_msgin[4];
3602
3603 ESPSDTR(("is sync nego response, "));
3604 if (!esp->snip) {
3605 int rval;
3606
3607 /* Target negotiates first! */
3608 ESPSDTR(("target jumps the gun, "));
3609 message_out = EXTENDED_MESSAGE; /* we must respond */
3610 rval = target_with_ants_in_pants(esp, SCptr, esp_dev);
3611 if (rval)
3612 return rval;
3613 }
3614
3615 ESPSDTR(("examining sdtr, "));
3616
3617 /* Offset cannot be larger than ESP fifo size. */
3618 if (offset > 15) {
3619 ESPSDTR(("offset too big %2x, ", offset));
3620 offset = 15;
3621 ESPSDTR(("sending back new offset\n"));
3622 build_sync_nego_msg(esp, period, offset);
3623 return EXTENDED_MESSAGE;
3624 }
3625
3626 if (offset && period > esp->max_period) {
3627 /* Yeee, async for this slow device. */
3628 ESPSDTR(("period too long %2x, ", period));
3629 build_sync_nego_msg(esp, 0, 0);
3630 ESPSDTR(("hoping for msgout\n"));
3631 esp_advance_phase(esp->current_SC, in_the_dark);
3632 return EXTENDED_MESSAGE;
3633 } else if (offset && period < esp->min_period) {
3634 ESPSDTR(("period too short %2x, ", period));
3635 period = esp->min_period;
3636 if (esp->erev > esp236)
3637 regval = 4;
3638 else
3639 regval = 5;
3640 } else if (offset) {
3641 int tmp;
3642
3643 ESPSDTR(("period is ok, "));
3644 tmp = esp->ccycle / 1000;
3645 regval = (((period << 2) + tmp - 1) / tmp);
3646 if (regval && ((esp->erev == fas100a ||
3647 esp->erev == fas236 ||
3648 esp->erev == fashme))) {
3649 if (period >= 50)
3650 regval--;
3651 }
3652 }
3653
3654 if (offset) {
3655 u8 bit;
3656
3657 esp_dev->sync_min_period = (regval & 0x1f);
3658 esp_dev->sync_max_offset = (offset | esp->radelay);
3659 if (esp->erev == fas100a || esp->erev == fas236 || esp->erev == fashme) {
3660 if ((esp->erev == fas100a) || (esp->erev == fashme))
3661 bit = ESP_CONFIG3_FAST;
3662 else
3663 bit = ESP_CONFIG3_FSCSI;
3664 if (period < 50) {
3665 /* On FAS366, if using fast-20 synchronous transfers
3666 * we need to make sure the REQ/ACK assert/deassert
3667 * control bits are clear.
3668 */
3669 if (esp->erev == fashme)
3670 esp_dev->sync_max_offset &= ~esp->radelay;
3671 esp->config3[SCptr->device->id] |= bit;
3672 } else {
3673 esp->config3[SCptr->device->id] &= ~bit;
3674 }
3675 esp->prev_cfg3 = esp->config3[SCptr->device->id];
3676 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
3677 }
3678 esp->prev_soff = esp_dev->sync_max_offset;
3679 esp->prev_stp = esp_dev->sync_min_period;
3680 sbus_writeb(esp->prev_soff, esp->eregs + ESP_SOFF);
3681 sbus_writeb(esp->prev_stp, esp->eregs + ESP_STP);
3682 ESPSDTR(("soff=%2x stp=%2x cfg3=%2x\n",
3683 esp_dev->sync_max_offset,
3684 esp_dev->sync_min_period,
3685 esp->config3[SCptr->device->id]));
3686
3687 esp->snip = 0;
3688 } else if (esp_dev->sync_max_offset) {
3689 u8 bit;
3690
3691 /* back to async mode */
3692 ESPSDTR(("unaccaptable sync nego, forcing async\n"));
3693 esp_dev->sync_max_offset = 0;
3694 esp_dev->sync_min_period = 0;
3695 esp->prev_soff = 0;
3696 esp->prev_stp = 0;
3697 sbus_writeb(esp->prev_soff, esp->eregs + ESP_SOFF);
3698 sbus_writeb(esp->prev_stp, esp->eregs + ESP_STP);
3699 if (esp->erev == fas100a || esp->erev == fas236 || esp->erev == fashme) {
3700 if ((esp->erev == fas100a) || (esp->erev == fashme))
3701 bit = ESP_CONFIG3_FAST;
3702 else
3703 bit = ESP_CONFIG3_FSCSI;
3704 esp->config3[SCptr->device->id] &= ~bit;
3705 esp->prev_cfg3 = esp->config3[SCptr->device->id];
3706 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
3707 }
3708 }
3709
3710 sync_report(esp);
3711
3712 ESPSDTR(("chk multibyte msg: sync is known, "));
3713 esp_dev->sync = 1;
3714
3715 if (message_out) {
3716 ESPLOG(("esp%d: sending sdtr back, hoping for msgout\n",
3717 esp->esp_id));
3718 build_sync_nego_msg(esp, period, offset);
3719 esp_advance_phase(SCptr, in_the_dark);
3720 return EXTENDED_MESSAGE;
3721 }
3722
3723 ESPSDTR(("returning zero\n"));
3724 esp_advance_phase(SCptr, in_the_dark); /* ...or else! */
3725 return 0;
3726 } else if (esp->cur_msgin[2] == EXTENDED_WDTR) {
3727 int size = 8 << esp->cur_msgin[3];
3728
3729 esp->wnip = 0;
3730 if (esp->erev != fashme) {
3731 ESPLOG(("esp%d: AIEEE wide msg received and not HME.\n",
3732 esp->esp_id));
3733 message_out = MESSAGE_REJECT;
3734 } else if (size > 16) {
3735 ESPLOG(("esp%d: AIEEE wide transfer for %d size "
3736 "not supported.\n", esp->esp_id, size));
3737 message_out = MESSAGE_REJECT;
3738 } else {
3739 /* Things look good; let's see what we got. */
3740 if (size == 16) {
3741 /* Set config 3 register for this target. */
3742 esp->config3[SCptr->device->id] |= ESP_CONFIG3_EWIDE;
3743 } else {
3744 /* Just make sure it was one byte sized. */
3745 if (size != 8) {
3746 ESPLOG(("esp%d: Aieee, wide nego of %d size.\n",
3747 esp->esp_id, size));
3748 message_out = MESSAGE_REJECT;
3749 goto finish;
3750 }
3751 /* Pure paranoia. */
3752 esp->config3[SCptr->device->id] &= ~(ESP_CONFIG3_EWIDE);
3753 }
3754 esp->prev_cfg3 = esp->config3[SCptr->device->id];
3755 sbus_writeb(esp->prev_cfg3, esp->eregs + ESP_CFG3);
3756
3757 /* Regardless, next try for sync transfers. */
3758 build_sync_nego_msg(esp, esp->sync_defp, 15);
3759 esp_dev->sync = 1;
3760 esp->snip = 1;
3761 message_out = EXTENDED_MESSAGE;
3762 }
3763 } else if (esp->cur_msgin[2] == EXTENDED_MODIFY_DATA_POINTER) {
3764 ESPLOG(("esp%d: rejecting modify data ptr msg\n", esp->esp_id));
3765 message_out = MESSAGE_REJECT;
3766 }
3767finish:
3768 esp_advance_phase(SCptr, in_the_dark);
3769 return message_out;
3770}
3771
3772static int esp_do_msgindone(struct esp *esp)
3773{
3774 struct scsi_cmnd *SCptr = esp->current_SC;
3775 int message_out = 0, it = 0, rval;
3776
3777 rval = skipahead1(esp, SCptr, in_msgin, in_msgindone);
3778 if (rval)
3779 return rval;
3780 if (SCptr->SCp.sent_command != in_status) {
3781 if (!(esp->ireg & ESP_INTR_DC)) {
3782 if (esp->msgin_len && (esp->sreg & ESP_STAT_PERR)) {
3783 message_out = MSG_PARITY_ERROR;
3784 esp_cmd(esp, ESP_CMD_FLUSH);
3785 } else if (esp->erev != fashme &&
3786 (it = (sbus_readb(esp->eregs + ESP_FFLAGS) & ESP_FF_FBYTES)) != 1) {
3787 /* We certainly dropped the ball somewhere. */
3788 message_out = INITIATOR_ERROR;
3789 esp_cmd(esp, ESP_CMD_FLUSH);
3790 } else if (!esp->msgin_len) {
3791 if (esp->erev == fashme)
3792 it = esp->hme_fifo_workaround_buffer[0];
3793 else
3794 it = sbus_readb(esp->eregs + ESP_FDATA);
3795 esp_advance_phase(SCptr, in_msgincont);
3796 } else {
3797 /* it is ok and we want it */
3798 if (esp->erev == fashme)
3799 it = esp->cur_msgin[esp->msgin_ctr] =
3800 esp->hme_fifo_workaround_buffer[0];
3801 else
3802 it = esp->cur_msgin[esp->msgin_ctr] =
3803 sbus_readb(esp->eregs + ESP_FDATA);
3804 esp->msgin_ctr++;
3805 }
3806 } else {
3807 esp_advance_phase(SCptr, in_the_dark);
3808 return do_work_bus;
3809 }
3810 } else {
3811 it = esp->cur_msgin[0];
3812 }
3813 if (!message_out && esp->msgin_len) {
3814 if (esp->msgin_ctr < esp->msgin_len) {
3815 esp_advance_phase(SCptr, in_msgincont);
3816 } else if (esp->msgin_len == 1) {
3817 message_out = check_singlebyte_msg(esp);
3818 } else if (esp->msgin_len == 2) {
3819 if (esp->cur_msgin[0] == EXTENDED_MESSAGE) {
3820 if ((it + 2) >= 15) {
3821 message_out = MESSAGE_REJECT;
3822 } else {
3823 esp->msgin_len = (it + 2);
3824 esp_advance_phase(SCptr, in_msgincont);
3825 }
3826 } else {
3827 message_out = MESSAGE_REJECT; /* foo on you */
3828 }
3829 } else {
3830 message_out = check_multibyte_msg(esp);
3831 }
3832 }
3833 if (message_out < 0) {
3834 return -message_out;
3835 } else if (message_out) {
3836 if (((message_out != 1) &&
3837 ((message_out < 0x20) || (message_out & 0x80))))
3838 esp->msgout_len = 1;
3839 esp->cur_msgout[0] = message_out;
3840 esp_cmd(esp, ESP_CMD_SATN);
3841 esp_advance_phase(SCptr, in_the_dark);
3842 esp->msgin_len = 0;
3843 }
3844 esp->sreg = sbus_readb(esp->eregs + ESP_STATUS);
3845 esp->sreg &= ~(ESP_STAT_INTR);
3846 if ((esp->sreg & (ESP_STAT_PMSG|ESP_STAT_PCD)) == (ESP_STAT_PMSG|ESP_STAT_PCD))
3847 esp_cmd(esp, ESP_CMD_MOK);
3848 if ((SCptr->SCp.sent_command == in_msgindone) &&
3849 (SCptr->SCp.phase == in_freeing))
3850 return esp_do_freebus(esp);
3851 return do_intr_end;
3852}
3853
3854static int esp_do_cmdbegin(struct esp *esp)
3855{
3856 struct scsi_cmnd *SCptr = esp->current_SC;
3857
3858 esp_advance_phase(SCptr, in_cmdend);
3859 if (esp->erev == fashme) {
3860 u32 tmp = sbus_readl(esp->dregs + DMA_CSR);
3861 int i;
3862
3863 for (i = 0; i < esp->esp_scmdleft; i++)
3864 esp->esp_command[i] = *esp->esp_scmdp++;
3865 esp->esp_scmdleft = 0;
3866 esp_cmd(esp, ESP_CMD_FLUSH);
3867 esp_setcount(esp->eregs, i, 1);
3868 esp_cmd(esp, (ESP_CMD_DMA | ESP_CMD_TI));
3869 tmp |= (DMA_SCSI_DISAB | DMA_ENABLE);
3870 tmp &= ~(DMA_ST_WRITE);
3871 sbus_writel(i, esp->dregs + DMA_COUNT);
3872 sbus_writel(esp->esp_command_dvma, esp->dregs + DMA_ADDR);
3873 sbus_writel(tmp, esp->dregs + DMA_CSR);
3874 } else {
3875 u8 tmp;
3876
3877 esp_cmd(esp, ESP_CMD_FLUSH);
3878 tmp = *esp->esp_scmdp++;
3879 esp->esp_scmdleft--;
3880 sbus_writeb(tmp, esp->eregs + ESP_FDATA);
3881 esp_cmd(esp, ESP_CMD_TI);
3882 }
3883 return do_intr_end;
3884}
3885
3886static int esp_do_cmddone(struct esp *esp)
3887{
3888 if (esp->erev == fashme)
3889 dma_invalidate(esp);
3890 else
3891 esp_cmd(esp, ESP_CMD_NULL);
3892
3893 if (esp->ireg & ESP_INTR_BSERV) {
3894 esp_advance_phase(esp->current_SC, in_the_dark);
3895 return esp_do_phase_determine(esp);
3896 }
3897
3898 ESPLOG(("esp%d: in do_cmddone() but didn't get BSERV interrupt.\n",
3899 esp->esp_id));
3900 return do_reset_bus;
3901}
3902
3903static int esp_do_msgout(struct esp *esp)
3904{
3905 esp_cmd(esp, ESP_CMD_FLUSH);
3906 switch (esp->msgout_len) {
3907 case 1:
3908 if (esp->erev == fashme)
3909 hme_fifo_push(esp, &esp->cur_msgout[0], 1);
3910 else
3911 sbus_writeb(esp->cur_msgout[0], esp->eregs + ESP_FDATA);
3912
3913 esp_cmd(esp, ESP_CMD_TI);
3914 break;
3915
3916 case 2:
3917 esp->esp_command[0] = esp->cur_msgout[0];
3918 esp->esp_command[1] = esp->cur_msgout[1];
3919
3920 if (esp->erev == fashme) {
3921 hme_fifo_push(esp, &esp->cur_msgout[0], 2);
3922 esp_cmd(esp, ESP_CMD_TI);
3923 } else {
3924 dma_setup(esp, esp->esp_command_dvma, 2, 0);
3925 esp_setcount(esp->eregs, 2, 0);
3926 esp_cmd(esp, ESP_CMD_DMA | ESP_CMD_TI);
3927 }
3928 break;
3929
3930 case 4:
3931 esp->esp_command[0] = esp->cur_msgout[0];
3932 esp->esp_command[1] = esp->cur_msgout[1];
3933 esp->esp_command[2] = esp->cur_msgout[2];
3934 esp->esp_command[3] = esp->cur_msgout[3];
3935 esp->snip = 1;
3936
3937 if (esp->erev == fashme) {
3938 hme_fifo_push(esp, &esp->cur_msgout[0], 4);
3939 esp_cmd(esp, ESP_CMD_TI);
3940 } else {
3941 dma_setup(esp, esp->esp_command_dvma, 4, 0);
3942 esp_setcount(esp->eregs, 4, 0);
3943 esp_cmd(esp, ESP_CMD_DMA | ESP_CMD_TI);
3944 }
3945 break;
3946
3947 case 5:
3948 esp->esp_command[0] = esp->cur_msgout[0];
3949 esp->esp_command[1] = esp->cur_msgout[1];
3950 esp->esp_command[2] = esp->cur_msgout[2];
3951 esp->esp_command[3] = esp->cur_msgout[3];
3952 esp->esp_command[4] = esp->cur_msgout[4];
3953 esp->snip = 1;
3954
3955 if (esp->erev == fashme) {
3956 hme_fifo_push(esp, &esp->cur_msgout[0], 5);
3957 esp_cmd(esp, ESP_CMD_TI);
3958 } else {
3959 dma_setup(esp, esp->esp_command_dvma, 5, 0);
3960 esp_setcount(esp->eregs, 5, 0);
3961 esp_cmd(esp, ESP_CMD_DMA | ESP_CMD_TI);
3962 }
3963 break;
3964
3965 default:
3966 /* whoops */
3967 ESPMISC(("bogus msgout sending NOP\n"));
3968 esp->cur_msgout[0] = NOP;
3969
3970 if (esp->erev == fashme) {
3971 hme_fifo_push(esp, &esp->cur_msgout[0], 1);
3972 } else {
3973 sbus_writeb(esp->cur_msgout[0], esp->eregs + ESP_FDATA);
3974 }
3975
3976 esp->msgout_len = 1;
3977 esp_cmd(esp, ESP_CMD_TI);
3978 break;
3979 };
3980
3981 esp_advance_phase(esp->current_SC, in_msgoutdone);
3982 return do_intr_end;
3983}
3984
3985static int esp_do_msgoutdone(struct esp *esp)
3986{
3987 if (esp->msgout_len > 1) {
3988 /* XXX HME/FAS ATN deassert workaround required,
3989 * XXX no DMA flushing, only possible ESP_CMD_FLUSH
3990 * XXX to kill the fifo.
3991 */
3992 if (esp->erev != fashme) {
3993 u32 tmp;
3994
3995 while ((tmp = sbus_readl(esp->dregs + DMA_CSR)) & DMA_PEND_READ)
3996 udelay(1);
3997 tmp &= ~DMA_ENABLE;
3998 sbus_writel(tmp, esp->dregs + DMA_CSR);
3999 dma_invalidate(esp);
4000 } else {
4001 esp_cmd(esp, ESP_CMD_FLUSH);
4002 }
4003 }
4004 if (!(esp->ireg & ESP_INTR_DC)) {
4005 if (esp->erev != fashme)
4006 esp_cmd(esp, ESP_CMD_NULL);
4007 switch (esp->sreg & ESP_STAT_PMASK) {
4008 case ESP_MOP:
4009 /* whoops, parity error */
4010 ESPLOG(("esp%d: still in msgout, parity error assumed\n",
4011 esp->esp_id));
4012 if (esp->msgout_len > 1)
4013 esp_cmd(esp, ESP_CMD_SATN);
4014 esp_advance_phase(esp->current_SC, in_msgout);
4015 return do_work_bus;
4016
4017 case ESP_DIP:
4018 break;
4019
4020 default:
4021 /* Happy Meal fifo is touchy... */
4022 if ((esp->erev != fashme) &&
4023 !fcount(esp) &&
4024 !(((struct esp_device *)esp->current_SC->device->hostdata)->sync_max_offset))
4025 esp_cmd(esp, ESP_CMD_FLUSH);
4026 break;
4027
4028 };
4029 } else {
4030 ESPLOG(("esp%d: disconnect, resetting bus\n", esp->esp_id));
4031 return do_reset_bus;
4032 }
4033
4034 /* If we sent out a synchronous negotiation message, update
4035 * our state.
4036 */
4037 if (esp->cur_msgout[2] == EXTENDED_MESSAGE &&
4038 esp->cur_msgout[4] == EXTENDED_SDTR) {
4039 esp->snip = 1; /* anal retentiveness... */
4040 }
4041
4042 esp->prevmsgout = esp->cur_msgout[0];
4043 esp->msgout_len = 0;
4044 esp_advance_phase(esp->current_SC, in_the_dark);
4045 return esp_do_phase_determine(esp);
4046}
4047
4048static int esp_bus_unexpected(struct esp *esp)
4049{
4050 ESPLOG(("esp%d: command in weird state %2x\n",
4051 esp->esp_id, esp->current_SC->SCp.phase));
4052 return do_reset_bus;
4053}
4054
4055static espfunc_t bus_vector[] = {
4056 esp_do_data_finale,
4057 esp_do_data_finale,
4058 esp_bus_unexpected,
4059 esp_do_msgin,
4060 esp_do_msgincont,
4061 esp_do_msgindone,
4062 esp_do_msgout,
4063 esp_do_msgoutdone,
4064 esp_do_cmdbegin,
4065 esp_do_cmddone,
4066 esp_do_status,
4067 esp_do_freebus,
4068 esp_do_phase_determine,
4069 esp_bus_unexpected,
4070 esp_bus_unexpected,
4071 esp_bus_unexpected,
4072};
4073
4074/* This is the second tier in our dual-level SCSI state machine. */
4075static int esp_work_bus(struct esp *esp)
4076{
4077 struct scsi_cmnd *SCptr = esp->current_SC;
4078 unsigned int phase;
4079
4080 ESPBUS(("esp_work_bus: "));
4081 if (!SCptr) {
4082 ESPBUS(("reconnect\n"));
4083 return esp_do_reconnect(esp);
4084 }
4085 phase = SCptr->SCp.phase;
4086 if ((phase & 0xf0) == in_phases_mask)
4087 return bus_vector[(phase & 0x0f)](esp);
4088 else if ((phase & 0xf0) == in_slct_mask)
4089 return esp_select_complete(esp);
4090 else
4091 return esp_bus_unexpected(esp);
4092}
4093
4094static espfunc_t isvc_vector[] = {
4095 NULL,
4096 esp_do_phase_determine,
4097 esp_do_resetbus,
4098 esp_finish_reset,
4099 esp_work_bus
4100};
4101
4102/* Main interrupt handler for an esp adapter. */
4103static void esp_handle(struct esp *esp)
4104{
4105 struct scsi_cmnd *SCptr;
4106 int what_next = do_intr_end;
4107
4108 SCptr = esp->current_SC;
4109
4110 /* Check for errors. */
4111 esp->sreg = sbus_readb(esp->eregs + ESP_STATUS);
4112 esp->sreg &= (~ESP_STAT_INTR);
4113 if (esp->erev == fashme) {
4114 esp->sreg2 = sbus_readb(esp->eregs + ESP_STATUS2);
4115 esp->seqreg = (sbus_readb(esp->eregs + ESP_SSTEP) & ESP_STEP_VBITS);
4116 }
4117
4118 if (esp->sreg & (ESP_STAT_SPAM)) {
4119 /* Gross error, could be due to one of:
4120 *
4121 * - top of fifo overwritten, could be because
4122 * we tried to do a synchronous transfer with
4123 * an offset greater than ESP fifo size
4124 *
4125 * - top of command register overwritten
4126 *
4127 * - DMA setup to go in one direction, SCSI
4128 * bus points in the other, whoops
4129 *
4130 * - weird phase change during asynchronous
4131 * data phase while we are initiator
4132 */
4133 ESPLOG(("esp%d: Gross error sreg=%2x\n", esp->esp_id, esp->sreg));
4134
4135 /* If a command is live on the bus we cannot safely
4136 * reset the bus, so we'll just let the pieces fall
4137 * where they may. Here we are hoping that the
4138 * target will be able to cleanly go away soon
4139 * so we can safely reset things.
4140 */
4141 if (!SCptr) {
4142 ESPLOG(("esp%d: No current cmd during gross error, "
4143 "resetting bus\n", esp->esp_id));
4144 what_next = do_reset_bus;
4145 goto state_machine;
4146 }
4147 }
4148
4149 if (sbus_readl(esp->dregs + DMA_CSR) & DMA_HNDL_ERROR) {
4150 /* A DMA gate array error. Here we must
4151 * be seeing one of two things. Either the
4152 * virtual to physical address translation
4153 * on the SBUS could not occur, else the
4154 * translation it did get pointed to a bogus
4155 * page. Ho hum...
4156 */
4157 ESPLOG(("esp%d: DMA error %08x\n", esp->esp_id,
4158 sbus_readl(esp->dregs + DMA_CSR)));
4159
4160 /* DMA gate array itself must be reset to clear the
4161 * error condition.
4162 */
4163 esp_reset_dma(esp);
4164
4165 what_next = do_reset_bus;
4166 goto state_machine;
4167 }
4168
4169 esp->ireg = sbus_readb(esp->eregs + ESP_INTRPT); /* Unlatch intr reg */
4170
4171 if (esp->erev == fashme) {
4172 /* This chip is really losing. */
4173 ESPHME(("HME["));
4174
4175 ESPHME(("sreg2=%02x,", esp->sreg2));
4176 /* Must latch fifo before reading the interrupt
4177 * register else garbage ends up in the FIFO
4178 * which confuses the driver utterly.
4179 */
4180 if (!(esp->sreg2 & ESP_STAT2_FEMPTY) ||
4181 (esp->sreg2 & ESP_STAT2_F1BYTE)) {
4182 ESPHME(("fifo_workaround]"));
4183 hme_fifo_read(esp);
4184 } else {
4185 ESPHME(("no_fifo_workaround]"));
4186 }
4187 }
4188
4189 /* No current cmd is only valid at this point when there are
4190 * commands off the bus or we are trying a reset.
4191 */
4192 if (!SCptr && !esp->disconnected_SC && !(esp->ireg & ESP_INTR_SR)) {
4193 /* Panic is safe, since current_SC is null. */
4194 ESPLOG(("esp%d: no command in esp_handle()\n", esp->esp_id));
4195 panic("esp_handle: current_SC == penguin within interrupt!");
4196 }
4197
4198 if (esp->ireg & (ESP_INTR_IC)) {
4199 /* Illegal command fed to ESP. Outside of obvious
4200 * software bugs that could cause this, there is
4201 * a condition with esp100 where we can confuse the
4202 * ESP into an erroneous illegal command interrupt
4203 * because it does not scrape the FIFO properly
4204 * for reselection. See esp100_reconnect_hwbug()
4205 * to see how we try very hard to avoid this.
4206 */
4207 ESPLOG(("esp%d: invalid command\n", esp->esp_id));
4208
4209 esp_dump_state(esp);
4210
4211 if (SCptr != NULL) {
4212 /* Devices with very buggy firmware can drop BSY
4213 * during a scatter list interrupt when using sync
4214 * mode transfers. We continue the transfer as
4215 * expected, the target drops the bus, the ESP
4216 * gets confused, and we get a illegal command
4217 * interrupt because the bus is in the disconnected
4218 * state now and ESP_CMD_TI is only allowed when
4219 * a nexus is alive on the bus.
4220 */
4221 ESPLOG(("esp%d: Forcing async and disabling disconnect for "
4222 "target %d\n", esp->esp_id, SCptr->device->id));
4223 SCptr->device->borken = 1; /* foo on you */
4224 }
4225
4226 what_next = do_reset_bus;
4227 } else if (!(esp->ireg & ~(ESP_INTR_FDONE | ESP_INTR_BSERV | ESP_INTR_DC))) {
4228 if (SCptr) {
4229 unsigned int phase = SCptr->SCp.phase;
4230
4231 if (phase & in_phases_mask) {
4232 what_next = esp_work_bus(esp);
4233 } else if (phase & in_slct_mask) {
4234 what_next = esp_select_complete(esp);
4235 } else {
4236 ESPLOG(("esp%d: interrupt for no good reason...\n",
4237 esp->esp_id));
4238 what_next = do_intr_end;
4239 }
4240 } else {
4241 ESPLOG(("esp%d: BSERV or FDONE or DC while SCptr==NULL\n",
4242 esp->esp_id));
4243 what_next = do_reset_bus;
4244 }
4245 } else if (esp->ireg & ESP_INTR_SR) {
4246 ESPLOG(("esp%d: SCSI bus reset interrupt\n", esp->esp_id));
4247 what_next = do_reset_complete;
4248 } else if (esp->ireg & (ESP_INTR_S | ESP_INTR_SATN)) {
4249 ESPLOG(("esp%d: AIEEE we have been selected by another initiator!\n",
4250 esp->esp_id));
4251 what_next = do_reset_bus;
4252 } else if (esp->ireg & ESP_INTR_RSEL) {
4253 if (SCptr == NULL) {
4254 /* This is ok. */
4255 what_next = esp_do_reconnect(esp);
4256 } else if (SCptr->SCp.phase & in_slct_mask) {
4257 /* Only selection code knows how to clean
4258 * up properly.
4259 */
4260 ESPDISC(("Reselected during selection attempt\n"));
4261 what_next = esp_select_complete(esp);
4262 } else {
4263 ESPLOG(("esp%d: Reselected while bus is busy\n",
4264 esp->esp_id));
4265 what_next = do_reset_bus;
4266 }
4267 }
4268
4269 /* This is tier-one in our dual level SCSI state machine. */
4270state_machine:
4271 while (what_next != do_intr_end) {
4272 if (what_next >= do_phase_determine &&
4273 what_next < do_intr_end) {
4274 what_next = isvc_vector[what_next](esp);
4275 } else {
4276 /* state is completely lost ;-( */
4277 ESPLOG(("esp%d: interrupt engine loses state, resetting bus\n",
4278 esp->esp_id));
4279 what_next = do_reset_bus;
4280 }
4281 }
4282}
4283
4284/* Service only the ESP described by dev_id. */
4285static irqreturn_t esp_intr(int irq, void *dev_id)
4286{
4287 struct esp *esp = dev_id;
4288 unsigned long flags;
4289
4290 spin_lock_irqsave(esp->ehost->host_lock, flags);
4291 if (ESP_IRQ_P(esp->dregs)) {
4292 ESP_INTSOFF(esp->dregs);
4293
4294 ESPIRQ(("I[%d:%d](", smp_processor_id(), esp->esp_id));
4295 esp_handle(esp);
4296 ESPIRQ((")"));
4297
4298 ESP_INTSON(esp->dregs);
4299 }
4300 spin_unlock_irqrestore(esp->ehost->host_lock, flags);
4301
4302 return IRQ_HANDLED;
4303}
4304
4305static int esp_slave_alloc(struct scsi_device *SDptr)
4306{
4307 struct esp_device *esp_dev =
4308 kmalloc(sizeof(struct esp_device), GFP_ATOMIC);
4309
4310 if (!esp_dev)
4311 return -ENOMEM;
4312 memset(esp_dev, 0, sizeof(struct esp_device));
4313 SDptr->hostdata = esp_dev;
4314 return 0;
4315}
4316
4317static void esp_slave_destroy(struct scsi_device *SDptr)
4318{
4319 struct esp *esp = (struct esp *) SDptr->host->hostdata;
4320
4321 esp->targets_present &= ~(1 << SDptr->id);
4322 kfree(SDptr->hostdata);
4323 SDptr->hostdata = NULL;
4324}
4325
4326static struct scsi_host_template esp_template = {
4327 .module = THIS_MODULE,
4328 .name = "esp",
4329 .info = esp_info,
4330 .slave_alloc = esp_slave_alloc,
4331 .slave_destroy = esp_slave_destroy,
4332 .queuecommand = esp_queue,
4333 .eh_abort_handler = esp_abort,
4334 .eh_bus_reset_handler = esp_reset,
4335 .can_queue = 7,
4336 .this_id = 7,
4337 .sg_tablesize = SG_ALL,
4338 .cmd_per_lun = 1,
4339 .use_clustering = ENABLE_CLUSTERING,
4340 .proc_name = "esp",
4341 .proc_info = esp_proc_info,
4342};
4343
4344#ifndef CONFIG_SUN4
4345static struct of_device_id esp_match[] = {
4346 {
4347 .name = "SUNW,esp",
4348 .data = &esp_template,
4349 },
4350 {
4351 .name = "SUNW,fas",
4352 .data = &esp_template,
4353 },
4354 {
4355 .name = "esp",
4356 .data = &esp_template,
4357 },
4358 {},
4359};
4360MODULE_DEVICE_TABLE(of, esp_match);
4361
4362static struct of_platform_driver esp_sbus_driver = {
4363 .name = "esp",
4364 .match_table = esp_match,
4365 .probe = esp_sbus_probe,
4366 .remove = __devexit_p(esp_sbus_remove),
4367};
4368#endif
4369
4370static int __init esp_init(void)
4371{
4372#ifdef CONFIG_SUN4
4373 return esp_sun4_probe(&esp_template);
4374#else
4375 return of_register_driver(&esp_sbus_driver, &sbus_bus_type);
4376#endif
4377}
4378
4379static void __exit esp_exit(void)
4380{
4381#ifdef CONFIG_SUN4
4382 esp_sun4_remove();
4383#else
4384 of_unregister_driver(&esp_sbus_driver);
4385#endif
4386}
4387
4388MODULE_DESCRIPTION("ESP Sun SCSI driver");
4389MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
4390MODULE_LICENSE("GPL");
4391MODULE_VERSION(DRV_VERSION);
4392
4393module_init(esp_init);
4394module_exit(esp_exit);
diff --git a/drivers/scsi/esp.h b/drivers/scsi/esp.h
deleted file mode 100644
index a98cda9121fc..000000000000
--- a/drivers/scsi/esp.h
+++ /dev/null
@@ -1,406 +0,0 @@
1/* $Id: esp.h,v 1.29 2001/12/11 04:55:47 davem Exp $
2 * esp.h: Defines and structures for the Sparc ESP (Enhanced SCSI
3 * Processor) driver under Linux.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef _SPARC_ESP_H
9#define _SPARC_ESP_H
10
11/* For dvma controller register definitions. */
12#include <asm/dma.h>
13
14/* The ESP SCSI controllers have their register sets in three
15 * "classes":
16 *
17 * 1) Registers which are both read and write.
18 * 2) Registers which are read only.
19 * 3) Registers which are write only.
20 *
21 * Yet, they all live within the same IO space.
22 */
23
24/* All the ESP registers are one byte each and are accessed longwords
25 * apart with a big-endian ordering to the bytes.
26 */
27 /* Access Description Offset */
28#define ESP_TCLOW 0x00UL /* rw Low bits of the transfer count 0x00 */
29#define ESP_TCMED 0x04UL /* rw Mid bits of the transfer count 0x04 */
30#define ESP_FDATA 0x08UL /* rw FIFO data bits 0x08 */
31#define ESP_CMD 0x0cUL /* rw SCSI command bits 0x0c */
32#define ESP_STATUS 0x10UL /* ro ESP status register 0x10 */
33#define ESP_BUSID ESP_STATUS /* wo Bus ID for select/reselect 0x10 */
34#define ESP_INTRPT 0x14UL /* ro Kind of interrupt 0x14 */
35#define ESP_TIMEO ESP_INTRPT /* wo Timeout value for select/resel 0x14 */
36#define ESP_SSTEP 0x18UL /* ro Sequence step register 0x18 */
37#define ESP_STP ESP_SSTEP /* wo Transfer period per sync 0x18 */
38#define ESP_FFLAGS 0x1cUL /* ro Bits of current FIFO info 0x1c */
39#define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
40#define ESP_CFG1 0x20UL /* rw First configuration register 0x20 */
41#define ESP_CFACT 0x24UL /* wo Clock conversion factor 0x24 */
42#define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
43#define ESP_CTEST 0x28UL /* wo Chip test register 0x28 */
44#define ESP_CFG2 0x2cUL /* rw Second configuration register 0x2c */
45#define ESP_CFG3 0x30UL /* rw Third configuration register 0x30 */
46#define ESP_TCHI 0x38UL /* rw High bits of transfer count 0x38 */
47#define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
48#define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
49#define ESP_FGRND 0x3cUL /* rw Data base for fifo 0x3c */
50#define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
51#define ESP_REG_SIZE 0x40UL
52
53/* Various revisions of the ESP board. */
54enum esp_rev {
55 esp100 = 0x00, /* NCR53C90 - very broken */
56 esp100a = 0x01, /* NCR53C90A */
57 esp236 = 0x02,
58 fas236 = 0x03,
59 fas100a = 0x04,
60 fast = 0x05,
61 fashme = 0x06,
62 espunknown = 0x07
63};
64
65/* We allocate one of these for each scsi device and attach it to
66 * SDptr->hostdata for use in the driver
67 */
68struct esp_device {
69 unsigned char sync_min_period;
70 unsigned char sync_max_offset;
71 unsigned sync:1;
72 unsigned wide:1;
73 unsigned disconnect:1;
74};
75
76struct scsi_cmnd;
77
78/* We get one of these for each ESP probed. */
79struct esp {
80 void __iomem *eregs; /* ESP controller registers */
81 void __iomem *dregs; /* DMA controller registers */
82 struct sbus_dma *dma; /* DMA controller sw state */
83 struct Scsi_Host *ehost; /* Backpointer to SCSI Host */
84 struct sbus_dev *sdev; /* Pointer to SBus entry */
85
86 /* ESP Configuration Registers */
87 u8 config1; /* Copy of the 1st config register */
88 u8 config2; /* Copy of the 2nd config register */
89 u8 config3[16]; /* Copy of the 3rd config register */
90
91 /* The current command we are sending to the ESP chip. This esp_command
92 * ptr needs to be mapped in DVMA area so we can send commands and read
93 * from the ESP fifo without burning precious CPU cycles. Programmed I/O
94 * sucks when we have the DVMA to do it for us. The ESP is stupid and will
95 * only send out 6, 10, and 12 byte SCSI commands, others we need to send
96 * one byte at a time. esp_slowcmd being set says that we are doing one
97 * of the command types ESP doesn't understand, esp_scmdp keeps track of
98 * which byte we are sending, esp_scmdleft says how many bytes to go.
99 */
100 volatile u8 *esp_command; /* Location of command (CPU view) */
101 __u32 esp_command_dvma;/* Location of command (DVMA view) */
102 unsigned char esp_clen; /* Length of this command */
103 unsigned char esp_slowcmd;
104 unsigned char *esp_scmdp;
105 unsigned char esp_scmdleft;
106
107 /* The following are used to determine the cause of an IRQ. Upon every
108 * IRQ entry we synchronize these with the hardware registers.
109 */
110 u8 ireg; /* Copy of ESP interrupt register */
111 u8 sreg; /* Copy of ESP status register */
112 u8 seqreg; /* Copy of ESP sequence step register */
113 u8 sreg2; /* Copy of HME status2 register */
114
115 /* To save register writes to the ESP, which can be expensive, we
116 * keep track of the previous value that various registers had for
117 * the last target we connected to. If they are the same for the
118 * current target, we skip the register writes as they are not needed.
119 */
120 u8 prev_soff, prev_stp;
121 u8 prev_cfg3, __cache_pad;
122
123 /* We also keep a cache of the previous FAS/HME DMA CSR register value. */
124 u32 prev_hme_dmacsr;
125
126 /* The HME is the biggest piece of shit I have ever seen. */
127 u8 hme_fifo_workaround_buffer[16 * 2];
128 u8 hme_fifo_workaround_count;
129
130 /* For each target we keep track of save/restore data
131 * pointer information. This needs to be updated majorly
132 * when we add support for tagged queueing. -DaveM
133 */
134 struct esp_pointers {
135 char *saved_ptr;
136 struct scatterlist *saved_buffer;
137 int saved_this_residual;
138 int saved_buffers_residual;
139 } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;
140
141 /* Clock periods, frequencies, synchronization, etc. */
142 unsigned int cfreq; /* Clock frequency in HZ */
143 unsigned int cfact; /* Clock conversion factor */
144 unsigned int raw_cfact; /* Raw copy from probing */
145 unsigned int ccycle; /* One ESP clock cycle */
146 unsigned int ctick; /* One ESP clock time */
147 unsigned int radelay; /* FAST chip req/ack delay */
148 unsigned int neg_defp; /* Default negotiation period */
149 unsigned int sync_defp; /* Default sync transfer period */
150 unsigned int max_period; /* longest our period can be */
151 unsigned int min_period; /* shortest period we can withstand */
152
153 struct esp *next; /* Next ESP we probed or NULL */
154 char prom_name[64]; /* Name of ESP device from prom */
155 int prom_node; /* Prom node where ESP found */
156 int esp_id; /* Unique per-ESP ID number */
157
158 /* For slow to medium speed input clock rates we shoot for 5mb/s,
159 * but for high input clock rates we try to do 10mb/s although I
160 * don't think a transfer can even run that fast with an ESP even
161 * with DMA2 scatter gather pipelining.
162 */
163#define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
164#define SYNC_DEFP_FAST 0x19 /* 10mb/s */
165
166 unsigned int snip; /* Sync. negotiation in progress */
167 unsigned int wnip; /* WIDE negotiation in progress */
168 unsigned int targets_present;/* targets spoken to before */
169
170 int current_transfer_size; /* Set at beginning of data dma */
171
172 u8 espcmdlog[32]; /* Log of current esp cmds sent. */
173 u8 espcmdent; /* Current entry in esp cmd log. */
174
175 /* Misc. info about this ESP */
176 enum esp_rev erev; /* ESP revision */
177 int irq; /* SBus IRQ for this ESP */
178 int scsi_id; /* Who am I as initiator? */
179 int scsi_id_mask; /* Bitmask of 'me'. */
180 int diff; /* Differential SCSI bus? */
181 int bursts; /* Burst sizes our DVMA supports */
182
183 /* Our command queues, only one cmd lives in the current_SC queue. */
184 struct scsi_cmnd *issue_SC; /* Commands to be issued */
185 struct scsi_cmnd *current_SC; /* Who is currently working the bus */
186 struct scsi_cmnd *disconnected_SC;/* Commands disconnected from the bus */
187
188 /* Message goo */
189 u8 cur_msgout[16];
190 u8 cur_msgin[16];
191 u8 prevmsgout, prevmsgin;
192 u8 msgout_len, msgin_len;
193 u8 msgout_ctr, msgin_ctr;
194
195 /* States that we cannot keep in the per cmd structure because they
196 * cannot be assosciated with any specific command.
197 */
198 u8 resetting_bus;
199 wait_queue_head_t reset_queue;
200};
201
202/* Bitfield meanings for the above registers. */
203
204/* ESP config reg 1, read-write, found on all ESP chips */
205#define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
206#define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
207#define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
208#define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
209#define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
210#define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
211
212/* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
213#define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
214#define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
215#define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
216#define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tmode only) */
217#define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
218#define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
219#define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
220#define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
221#define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216) */
222#define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */
223#define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
224#define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
225#define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
226
227/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
228#define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
229#define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
230#define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
231#define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
232#define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
233#define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
234#define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
235#define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
236#define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
237#define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
238#define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
239#define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
240#define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
241#define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
242#define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
243#define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
244
245/* ESP command register read-write */
246/* Group 1 commands: These may be sent at any point in time to the ESP
247 * chip. None of them can generate interrupts 'cept
248 * the "SCSI bus reset" command if you have not disabled
249 * SCSI reset interrupts in the config1 ESP register.
250 */
251#define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
252#define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
253#define ESP_CMD_RC 0x02 /* Chip reset */
254#define ESP_CMD_RS 0x03 /* SCSI bus reset */
255
256/* Group 2 commands: ESP must be an initiator and connected to a target
257 * for these commands to work.
258 */
259#define ESP_CMD_TI 0x10 /* Transfer Information */
260#define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
261#define ESP_CMD_MOK 0x12 /* Message okie-dokie */
262#define ESP_CMD_TPAD 0x18 /* Transfer Pad */
263#define ESP_CMD_SATN 0x1a /* Set ATN */
264#define ESP_CMD_RATN 0x1b /* De-assert ATN */
265
266/* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
267 * to a target as the initiator for these commands to work.
268 */
269#define ESP_CMD_SMSG 0x20 /* Send message */
270#define ESP_CMD_SSTAT 0x21 /* Send status */
271#define ESP_CMD_SDATA 0x22 /* Send data */
272#define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
273#define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
274#define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
275#define ESP_CMD_DCNCT 0x27 /* Disconnect */
276#define ESP_CMD_RMSG 0x28 /* Receive Message */
277#define ESP_CMD_RCMD 0x29 /* Receive Command */
278#define ESP_CMD_RDATA 0x2a /* Receive Data */
279#define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
280
281/* Group 4 commands: The ESP must be in the disconnected state and must
282 * not be connected to any targets as initiator for
283 * these commands to work.
284 */
285#define ESP_CMD_RSEL 0x40 /* Reselect */
286#define ESP_CMD_SEL 0x41 /* Select w/o ATN */
287#define ESP_CMD_SELA 0x42 /* Select w/ATN */
288#define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
289#define ESP_CMD_ESEL 0x44 /* Enable selection */
290#define ESP_CMD_DSEL 0x45 /* Disable selections */
291#define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
292#define ESP_CMD_RSEL3 0x47 /* Reselect3 */
293
294/* This bit enables the ESP's DMA on the SBus */
295#define ESP_CMD_DMA 0x80 /* Do DMA? */
296
297
298/* ESP status register read-only */
299#define ESP_STAT_PIO 0x01 /* IO phase bit */
300#define ESP_STAT_PCD 0x02 /* CD phase bit */
301#define ESP_STAT_PMSG 0x04 /* MSG phase bit */
302#define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
303#define ESP_STAT_TDONE 0x08 /* Transfer Completed */
304#define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
305#define ESP_STAT_PERR 0x20 /* Parity error */
306#define ESP_STAT_SPAM 0x40 /* Real bad error */
307/* This indicates the 'interrupt pending' condition on esp236, it is a reserved
308 * bit on other revs of the ESP.
309 */
310#define ESP_STAT_INTR 0x80 /* Interrupt */
311
312/* HME only: status 2 register */
313#define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
314#define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
315#define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
316#define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
317#define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
318#define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
319#define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
320#define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
321
322/* The status register can be masked with ESP_STAT_PMASK and compared
323 * with the following values to determine the current phase the ESP
324 * (at least thinks it) is in. For our purposes we also add our own
325 * software 'done' bit for our phase management engine.
326 */
327#define ESP_DOP (0) /* Data Out */
328#define ESP_DIP (ESP_STAT_PIO) /* Data In */
329#define ESP_CMDP (ESP_STAT_PCD) /* Command */
330#define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
331#define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
332#define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
333
334/* ESP interrupt register read-only */
335#define ESP_INTR_S 0x01 /* Select w/o ATN */
336#define ESP_INTR_SATN 0x02 /* Select w/ATN */
337#define ESP_INTR_RSEL 0x04 /* Reselected */
338#define ESP_INTR_FDONE 0x08 /* Function done */
339#define ESP_INTR_BSERV 0x10 /* Bus service */
340#define ESP_INTR_DC 0x20 /* Disconnect */
341#define ESP_INTR_IC 0x40 /* Illegal command given */
342#define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
343
344/* Interrupt status macros */
345#define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR))
346#define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC))
347#define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN))
348#define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S))
349#define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \
350 (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
351#define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL))
352
353/* ESP sequence step register read-only */
354#define ESP_STEP_VBITS 0x07 /* Valid bits */
355#define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
356#define ESP_STEP_SID 0x01 /* One msg byte sent */
357#define ESP_STEP_NCMD 0x02 /* Was not in command phase */
358#define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
359 * bytes to be lost
360 */
361#define ESP_STEP_FINI4 0x04 /* Command was sent ok */
362
363/* Ho hum, some ESP's set the step register to this as well... */
364#define ESP_STEP_FINI5 0x05
365#define ESP_STEP_FINI6 0x06
366#define ESP_STEP_FINI7 0x07
367
368/* ESP chip-test register read-write */
369#define ESP_TEST_TARG 0x01 /* Target test mode */
370#define ESP_TEST_INI 0x02 /* Initiator test mode */
371#define ESP_TEST_TS 0x04 /* Tristate test mode */
372
373/* ESP unique ID register read-only, found on fas236+fas100a only */
374#define ESP_UID_F100A 0x00 /* ESP FAS100A */
375#define ESP_UID_F236 0x02 /* ESP FAS236 */
376#define ESP_UID_REV 0x07 /* ESP revision */
377#define ESP_UID_FAM 0xf8 /* ESP family */
378
379/* ESP fifo flags register read-only */
380/* Note that the following implies a 16 byte FIFO on the ESP. */
381#define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
382#define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
383#define ESP_FF_SSTEP 0xe0 /* Sequence step */
384
385/* ESP clock conversion factor register write-only */
386#define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
387#define ESP_CCF_NEVER 0x01 /* Set it to this and die */
388#define ESP_CCF_F2 0x02 /* 10MHz */
389#define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
390#define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
391#define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
392#define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
393#define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
394
395/* HME only... */
396#define ESP_BUSID_RESELID 0x10
397#define ESP_BUSID_CTR32BIT 0x40
398
399#define ESP_BUS_TIMEOUT 275 /* In milli-seconds */
400#define ESP_TIMEO_CONST 8192
401#define ESP_NEG_DEFP(mhz, cfact) \
402 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
403#define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
404#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
405
406#endif /* !(_SPARC_ESP_H) */
diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
new file mode 100644
index 000000000000..99ce03331b64
--- /dev/null
+++ b/drivers/scsi/esp_scsi.c
@@ -0,0 +1,2711 @@
1/* esp_scsi.c: ESP SCSI driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/slab.h>
9#include <linux/delay.h>
10#include <linux/list.h>
11#include <linux/completion.h>
12#include <linux/kallsyms.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/irqreturn.h>
17
18#include <asm/irq.h>
19#include <asm/io.h>
20#include <asm/dma.h>
21
22#include <scsi/scsi.h>
23#include <scsi/scsi_host.h>
24#include <scsi/scsi_cmnd.h>
25#include <scsi/scsi_device.h>
26#include <scsi/scsi_tcq.h>
27#include <scsi/scsi_dbg.h>
28#include <scsi/scsi_transport_spi.h>
29
30#include "esp_scsi.h"
31
32#define DRV_MODULE_NAME "esp"
33#define PFX DRV_MODULE_NAME ": "
34#define DRV_VERSION "2.000"
35#define DRV_MODULE_RELDATE "April 19, 2007"
36
37/* SCSI bus reset settle time in seconds. */
38static int esp_bus_reset_settle = 3;
39
40static u32 esp_debug;
41#define ESP_DEBUG_INTR 0x00000001
42#define ESP_DEBUG_SCSICMD 0x00000002
43#define ESP_DEBUG_RESET 0x00000004
44#define ESP_DEBUG_MSGIN 0x00000008
45#define ESP_DEBUG_MSGOUT 0x00000010
46#define ESP_DEBUG_CMDDONE 0x00000020
47#define ESP_DEBUG_DISCONNECT 0x00000040
48#define ESP_DEBUG_DATASTART 0x00000080
49#define ESP_DEBUG_DATADONE 0x00000100
50#define ESP_DEBUG_RECONNECT 0x00000200
51#define ESP_DEBUG_AUTOSENSE 0x00000400
52
53#define esp_log_intr(f, a...) \
54do { if (esp_debug & ESP_DEBUG_INTR) \
55 printk(f, ## a); \
56} while (0)
57
58#define esp_log_reset(f, a...) \
59do { if (esp_debug & ESP_DEBUG_RESET) \
60 printk(f, ## a); \
61} while (0)
62
63#define esp_log_msgin(f, a...) \
64do { if (esp_debug & ESP_DEBUG_MSGIN) \
65 printk(f, ## a); \
66} while (0)
67
68#define esp_log_msgout(f, a...) \
69do { if (esp_debug & ESP_DEBUG_MSGOUT) \
70 printk(f, ## a); \
71} while (0)
72
73#define esp_log_cmddone(f, a...) \
74do { if (esp_debug & ESP_DEBUG_CMDDONE) \
75 printk(f, ## a); \
76} while (0)
77
78#define esp_log_disconnect(f, a...) \
79do { if (esp_debug & ESP_DEBUG_DISCONNECT) \
80 printk(f, ## a); \
81} while (0)
82
83#define esp_log_datastart(f, a...) \
84do { if (esp_debug & ESP_DEBUG_DATASTART) \
85 printk(f, ## a); \
86} while (0)
87
88#define esp_log_datadone(f, a...) \
89do { if (esp_debug & ESP_DEBUG_DATADONE) \
90 printk(f, ## a); \
91} while (0)
92
93#define esp_log_reconnect(f, a...) \
94do { if (esp_debug & ESP_DEBUG_RECONNECT) \
95 printk(f, ## a); \
96} while (0)
97
98#define esp_log_autosense(f, a...) \
99do { if (esp_debug & ESP_DEBUG_AUTOSENSE) \
100 printk(f, ## a); \
101} while (0)
102
103#define esp_read8(REG) esp->ops->esp_read8(esp, REG)
104#define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
105
106static void esp_log_fill_regs(struct esp *esp,
107 struct esp_event_ent *p)
108{
109 p->sreg = esp->sreg;
110 p->seqreg = esp->seqreg;
111 p->sreg2 = esp->sreg2;
112 p->ireg = esp->ireg;
113 p->select_state = esp->select_state;
114 p->event = esp->event;
115}
116
117void scsi_esp_cmd(struct esp *esp, u8 val)
118{
119 struct esp_event_ent *p;
120 int idx = esp->esp_event_cur;
121
122 p = &esp->esp_event_log[idx];
123 p->type = ESP_EVENT_TYPE_CMD;
124 p->val = val;
125 esp_log_fill_regs(esp, p);
126
127 esp->esp_event_cur = (idx + 1) & (ESP_EVENT_LOG_SZ - 1);
128
129 esp_write8(val, ESP_CMD);
130}
131EXPORT_SYMBOL(scsi_esp_cmd);
132
133static void esp_event(struct esp *esp, u8 val)
134{
135 struct esp_event_ent *p;
136 int idx = esp->esp_event_cur;
137
138 p = &esp->esp_event_log[idx];
139 p->type = ESP_EVENT_TYPE_EVENT;
140 p->val = val;
141 esp_log_fill_regs(esp, p);
142
143 esp->esp_event_cur = (idx + 1) & (ESP_EVENT_LOG_SZ - 1);
144
145 esp->event = val;
146}
147
148static void esp_dump_cmd_log(struct esp *esp)
149{
150 int idx = esp->esp_event_cur;
151 int stop = idx;
152
153 printk(KERN_INFO PFX "esp%d: Dumping command log\n",
154 esp->host->unique_id);
155 do {
156 struct esp_event_ent *p = &esp->esp_event_log[idx];
157
158 printk(KERN_INFO PFX "esp%d: ent[%d] %s ",
159 esp->host->unique_id, idx,
160 p->type == ESP_EVENT_TYPE_CMD ? "CMD" : "EVENT");
161
162 printk("val[%02x] sreg[%02x] seqreg[%02x] "
163 "sreg2[%02x] ireg[%02x] ss[%02x] event[%02x]\n",
164 p->val, p->sreg, p->seqreg,
165 p->sreg2, p->ireg, p->select_state, p->event);
166
167 idx = (idx + 1) & (ESP_EVENT_LOG_SZ - 1);
168 } while (idx != stop);
169}
170
171static void esp_flush_fifo(struct esp *esp)
172{
173 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
174 if (esp->rev == ESP236) {
175 int lim = 1000;
176
177 while (esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES) {
178 if (--lim == 0) {
179 printk(KERN_ALERT PFX "esp%d: ESP_FF_BYTES "
180 "will not clear!\n",
181 esp->host->unique_id);
182 break;
183 }
184 udelay(1);
185 }
186 }
187}
188
189static void hme_read_fifo(struct esp *esp)
190{
191 int fcnt = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
192 int idx = 0;
193
194 while (fcnt--) {
195 esp->fifo[idx++] = esp_read8(ESP_FDATA);
196 esp->fifo[idx++] = esp_read8(ESP_FDATA);
197 }
198 if (esp->sreg2 & ESP_STAT2_F1BYTE) {
199 esp_write8(0, ESP_FDATA);
200 esp->fifo[idx++] = esp_read8(ESP_FDATA);
201 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
202 }
203 esp->fifo_cnt = idx;
204}
205
206static void esp_set_all_config3(struct esp *esp, u8 val)
207{
208 int i;
209
210 for (i = 0; i < ESP_MAX_TARGET; i++)
211 esp->target[i].esp_config3 = val;
212}
213
214/* Reset the ESP chip, _not_ the SCSI bus. */
215static void esp_reset_esp(struct esp *esp)
216{
217 u8 family_code, version;
218
219 /* Now reset the ESP chip */
220 scsi_esp_cmd(esp, ESP_CMD_RC);
221 scsi_esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
222 scsi_esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
223
224 /* Reload the configuration registers */
225 esp_write8(esp->cfact, ESP_CFACT);
226
227 esp->prev_stp = 0;
228 esp_write8(esp->prev_stp, ESP_STP);
229
230 esp->prev_soff = 0;
231 esp_write8(esp->prev_soff, ESP_SOFF);
232
233 esp_write8(esp->neg_defp, ESP_TIMEO);
234
235 /* This is the only point at which it is reliable to read
236 * the ID-code for a fast ESP chip variants.
237 */
238 esp->max_period = ((35 * esp->ccycle) / 1000);
239 if (esp->rev == FAST) {
240 version = esp_read8(ESP_UID);
241 family_code = (version & 0xf8) >> 3;
242 if (family_code == 0x02)
243 esp->rev = FAS236;
244 else if (family_code == 0x0a)
245 esp->rev = FASHME; /* Version is usually '5'. */
246 else
247 esp->rev = FAS100A;
248 esp->min_period = ((4 * esp->ccycle) / 1000);
249 } else {
250 esp->min_period = ((5 * esp->ccycle) / 1000);
251 }
252 esp->max_period = (esp->max_period + 3)>>2;
253 esp->min_period = (esp->min_period + 3)>>2;
254
255 esp_write8(esp->config1, ESP_CFG1);
256 switch (esp->rev) {
257 case ESP100:
258 /* nothing to do */
259 break;
260
261 case ESP100A:
262 esp_write8(esp->config2, ESP_CFG2);
263 break;
264
265 case ESP236:
266 /* Slow 236 */
267 esp_write8(esp->config2, ESP_CFG2);
268 esp->prev_cfg3 = esp->target[0].esp_config3;
269 esp_write8(esp->prev_cfg3, ESP_CFG3);
270 break;
271
272 case FASHME:
273 esp->config2 |= (ESP_CONFIG2_HME32 | ESP_CONFIG2_HMEFENAB);
274 /* fallthrough... */
275
276 case FAS236:
277 /* Fast 236 or HME */
278 esp_write8(esp->config2, ESP_CFG2);
279 if (esp->rev == FASHME) {
280 u8 cfg3 = esp->target[0].esp_config3;
281
282 cfg3 |= ESP_CONFIG3_FCLOCK | ESP_CONFIG3_OBPUSH;
283 if (esp->scsi_id >= 8)
284 cfg3 |= ESP_CONFIG3_IDBIT3;
285 esp_set_all_config3(esp, cfg3);
286 } else {
287 u32 cfg3 = esp->target[0].esp_config3;
288
289 cfg3 |= ESP_CONFIG3_FCLK;
290 esp_set_all_config3(esp, cfg3);
291 }
292 esp->prev_cfg3 = esp->target[0].esp_config3;
293 esp_write8(esp->prev_cfg3, ESP_CFG3);
294 if (esp->rev == FASHME) {
295 esp->radelay = 80;
296 } else {
297 if (esp->flags & ESP_FLAG_DIFFERENTIAL)
298 esp->radelay = 0;
299 else
300 esp->radelay = 96;
301 }
302 break;
303
304 case FAS100A:
305 /* Fast 100a */
306 esp_write8(esp->config2, ESP_CFG2);
307 esp_set_all_config3(esp,
308 (esp->target[0].esp_config3 |
309 ESP_CONFIG3_FCLOCK));
310 esp->prev_cfg3 = esp->target[0].esp_config3;
311 esp_write8(esp->prev_cfg3, ESP_CFG3);
312 esp->radelay = 32;
313 break;
314
315 default:
316 break;
317 }
318
319 /* Eat any bitrot in the chip */
320 esp_read8(ESP_INTRPT);
321 udelay(100);
322}
323
324static void esp_map_dma(struct esp *esp, struct scsi_cmnd *cmd)
325{
326 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
327 struct scatterlist *sg = cmd->request_buffer;
328 int dir = cmd->sc_data_direction;
329 int total, i;
330
331 if (dir == DMA_NONE)
332 return;
333
334 BUG_ON(cmd->use_sg == 0);
335
336 spriv->u.num_sg = esp->ops->map_sg(esp, sg,
337 cmd->use_sg, dir);
338 spriv->cur_residue = sg_dma_len(sg);
339 spriv->cur_sg = sg;
340
341 total = 0;
342 for (i = 0; i < spriv->u.num_sg; i++)
343 total += sg_dma_len(&sg[i]);
344 spriv->tot_residue = total;
345}
346
347static dma_addr_t esp_cur_dma_addr(struct esp_cmd_entry *ent,
348 struct scsi_cmnd *cmd)
349{
350 struct esp_cmd_priv *p = ESP_CMD_PRIV(cmd);
351
352 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
353 return ent->sense_dma +
354 (ent->sense_ptr - cmd->sense_buffer);
355 }
356
357 return sg_dma_address(p->cur_sg) +
358 (sg_dma_len(p->cur_sg) -
359 p->cur_residue);
360}
361
362static unsigned int esp_cur_dma_len(struct esp_cmd_entry *ent,
363 struct scsi_cmnd *cmd)
364{
365 struct esp_cmd_priv *p = ESP_CMD_PRIV(cmd);
366
367 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
368 return SCSI_SENSE_BUFFERSIZE -
369 (ent->sense_ptr - cmd->sense_buffer);
370 }
371 return p->cur_residue;
372}
373
374static void esp_advance_dma(struct esp *esp, struct esp_cmd_entry *ent,
375 struct scsi_cmnd *cmd, unsigned int len)
376{
377 struct esp_cmd_priv *p = ESP_CMD_PRIV(cmd);
378
379 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
380 ent->sense_ptr += len;
381 return;
382 }
383
384 p->cur_residue -= len;
385 p->tot_residue -= len;
386 if (p->cur_residue < 0 || p->tot_residue < 0) {
387 printk(KERN_ERR PFX "esp%d: Data transfer overflow.\n",
388 esp->host->unique_id);
389 printk(KERN_ERR PFX "esp%d: cur_residue[%d] tot_residue[%d] "
390 "len[%u]\n",
391 esp->host->unique_id,
392 p->cur_residue, p->tot_residue, len);
393 p->cur_residue = 0;
394 p->tot_residue = 0;
395 }
396 if (!p->cur_residue && p->tot_residue) {
397 p->cur_sg++;
398 p->cur_residue = sg_dma_len(p->cur_sg);
399 }
400}
401
402static void esp_unmap_dma(struct esp *esp, struct scsi_cmnd *cmd)
403{
404 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
405 int dir = cmd->sc_data_direction;
406
407 if (dir == DMA_NONE)
408 return;
409
410 esp->ops->unmap_sg(esp, cmd->request_buffer,
411 spriv->u.num_sg, dir);
412}
413
414static void esp_save_pointers(struct esp *esp, struct esp_cmd_entry *ent)
415{
416 struct scsi_cmnd *cmd = ent->cmd;
417 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
418
419 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
420 ent->saved_sense_ptr = ent->sense_ptr;
421 return;
422 }
423 ent->saved_cur_residue = spriv->cur_residue;
424 ent->saved_cur_sg = spriv->cur_sg;
425 ent->saved_tot_residue = spriv->tot_residue;
426}
427
428static void esp_restore_pointers(struct esp *esp, struct esp_cmd_entry *ent)
429{
430 struct scsi_cmnd *cmd = ent->cmd;
431 struct esp_cmd_priv *spriv = ESP_CMD_PRIV(cmd);
432
433 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
434 ent->sense_ptr = ent->saved_sense_ptr;
435 return;
436 }
437 spriv->cur_residue = ent->saved_cur_residue;
438 spriv->cur_sg = ent->saved_cur_sg;
439 spriv->tot_residue = ent->saved_tot_residue;
440}
441
442static void esp_check_command_len(struct esp *esp, struct scsi_cmnd *cmd)
443{
444 if (cmd->cmd_len == 6 ||
445 cmd->cmd_len == 10 ||
446 cmd->cmd_len == 12) {
447 esp->flags &= ~ESP_FLAG_DOING_SLOWCMD;
448 } else {
449 esp->flags |= ESP_FLAG_DOING_SLOWCMD;
450 }
451}
452
453static void esp_write_tgt_config3(struct esp *esp, int tgt)
454{
455 if (esp->rev > ESP100A) {
456 u8 val = esp->target[tgt].esp_config3;
457
458 if (val != esp->prev_cfg3) {
459 esp->prev_cfg3 = val;
460 esp_write8(val, ESP_CFG3);
461 }
462 }
463}
464
465static void esp_write_tgt_sync(struct esp *esp, int tgt)
466{
467 u8 off = esp->target[tgt].esp_offset;
468 u8 per = esp->target[tgt].esp_period;
469
470 if (off != esp->prev_soff) {
471 esp->prev_soff = off;
472 esp_write8(off, ESP_SOFF);
473 }
474 if (per != esp->prev_stp) {
475 esp->prev_stp = per;
476 esp_write8(per, ESP_STP);
477 }
478}
479
480static u32 esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len)
481{
482 if (esp->rev == FASHME) {
483 /* Arbitrary segment boundaries, 24-bit counts. */
484 if (dma_len > (1U << 24))
485 dma_len = (1U << 24);
486 } else {
487 u32 base, end;
488
489 /* ESP chip limits other variants by 16-bits of transfer
490 * count. Actually on FAS100A and FAS236 we could get
491 * 24-bits of transfer count by enabling ESP_CONFIG2_FENAB
492 * in the ESP_CFG2 register but that causes other unwanted
493 * changes so we don't use it currently.
494 */
495 if (dma_len > (1U << 16))
496 dma_len = (1U << 16);
497
498 /* All of the DMA variants hooked up to these chips
499 * cannot handle crossing a 24-bit address boundary.
500 */
501 base = dma_addr & ((1U << 24) - 1U);
502 end = base + dma_len;
503 if (end > (1U << 24))
504 end = (1U <<24);
505 dma_len = end - base;
506 }
507 return dma_len;
508}
509
510static int esp_need_to_nego_wide(struct esp_target_data *tp)
511{
512 struct scsi_target *target = tp->starget;
513
514 return spi_width(target) != tp->nego_goal_width;
515}
516
517static int esp_need_to_nego_sync(struct esp_target_data *tp)
518{
519 struct scsi_target *target = tp->starget;
520
521 /* When offset is zero, period is "don't care". */
522 if (!spi_offset(target) && !tp->nego_goal_offset)
523 return 0;
524
525 if (spi_offset(target) == tp->nego_goal_offset &&
526 spi_period(target) == tp->nego_goal_period)
527 return 0;
528
529 return 1;
530}
531
532static int esp_alloc_lun_tag(struct esp_cmd_entry *ent,
533 struct esp_lun_data *lp)
534{
535 if (!ent->tag[0]) {
536 /* Non-tagged, slot already taken? */
537 if (lp->non_tagged_cmd)
538 return -EBUSY;
539
540 if (lp->hold) {
541 /* We are being held by active tagged
542 * commands.
543 */
544 if (lp->num_tagged)
545 return -EBUSY;
546
547 /* Tagged commands completed, we can unplug
548 * the queue and run this untagged command.
549 */
550 lp->hold = 0;
551 } else if (lp->num_tagged) {
552 /* Plug the queue until num_tagged decreases
553 * to zero in esp_free_lun_tag.
554 */
555 lp->hold = 1;
556 return -EBUSY;
557 }
558
559 lp->non_tagged_cmd = ent;
560 return 0;
561 } else {
562 /* Tagged command, see if blocked by a
563 * non-tagged one.
564 */
565 if (lp->non_tagged_cmd || lp->hold)
566 return -EBUSY;
567 }
568
569 BUG_ON(lp->tagged_cmds[ent->tag[1]]);
570
571 lp->tagged_cmds[ent->tag[1]] = ent;
572 lp->num_tagged++;
573
574 return 0;
575}
576
577static void esp_free_lun_tag(struct esp_cmd_entry *ent,
578 struct esp_lun_data *lp)
579{
580 if (ent->tag[0]) {
581 BUG_ON(lp->tagged_cmds[ent->tag[1]] != ent);
582 lp->tagged_cmds[ent->tag[1]] = NULL;
583 lp->num_tagged--;
584 } else {
585 BUG_ON(lp->non_tagged_cmd != ent);
586 lp->non_tagged_cmd = NULL;
587 }
588}
589
590/* When a contingent allegiance conditon is created, we force feed a
591 * REQUEST_SENSE command to the device to fetch the sense data. I
592 * tried many other schemes, relying on the scsi error handling layer
593 * to send out the REQUEST_SENSE automatically, but this was difficult
594 * to get right especially in the presence of applications like smartd
595 * which use SG_IO to send out their own REQUEST_SENSE commands.
596 */
597static void esp_autosense(struct esp *esp, struct esp_cmd_entry *ent)
598{
599 struct scsi_cmnd *cmd = ent->cmd;
600 struct scsi_device *dev = cmd->device;
601 int tgt, lun;
602 u8 *p, val;
603
604 tgt = dev->id;
605 lun = dev->lun;
606
607
608 if (!ent->sense_ptr) {
609 esp_log_autosense("esp%d: Doing auto-sense for "
610 "tgt[%d] lun[%d]\n",
611 esp->host->unique_id, tgt, lun);
612
613 ent->sense_ptr = cmd->sense_buffer;
614 ent->sense_dma = esp->ops->map_single(esp,
615 ent->sense_ptr,
616 SCSI_SENSE_BUFFERSIZE,
617 DMA_FROM_DEVICE);
618 }
619 ent->saved_sense_ptr = ent->sense_ptr;
620
621 esp->active_cmd = ent;
622
623 p = esp->command_block;
624 esp->msg_out_len = 0;
625
626 *p++ = IDENTIFY(0, lun);
627 *p++ = REQUEST_SENSE;
628 *p++ = ((dev->scsi_level <= SCSI_2) ?
629 (lun << 5) : 0);
630 *p++ = 0;
631 *p++ = 0;
632 *p++ = SCSI_SENSE_BUFFERSIZE;
633 *p++ = 0;
634
635 esp->select_state = ESP_SELECT_BASIC;
636
637 val = tgt;
638 if (esp->rev == FASHME)
639 val |= ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT;
640 esp_write8(val, ESP_BUSID);
641
642 esp_write_tgt_sync(esp, tgt);
643 esp_write_tgt_config3(esp, tgt);
644
645 val = (p - esp->command_block);
646
647 if (esp->rev == FASHME)
648 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
649 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
650 val, 16, 0, ESP_CMD_DMA | ESP_CMD_SELA);
651}
652
653static struct esp_cmd_entry *find_and_prep_issuable_command(struct esp *esp)
654{
655 struct esp_cmd_entry *ent;
656
657 list_for_each_entry(ent, &esp->queued_cmds, list) {
658 struct scsi_cmnd *cmd = ent->cmd;
659 struct scsi_device *dev = cmd->device;
660 struct esp_lun_data *lp = dev->hostdata;
661
662 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
663 ent->tag[0] = 0;
664 ent->tag[1] = 0;
665 return ent;
666 }
667
668 if (!scsi_populate_tag_msg(cmd, &ent->tag[0])) {
669 ent->tag[0] = 0;
670 ent->tag[1] = 0;
671 }
672
673 if (esp_alloc_lun_tag(ent, lp) < 0)
674 continue;
675
676 return ent;
677 }
678
679 return NULL;
680}
681
682static void esp_maybe_execute_command(struct esp *esp)
683{
684 struct esp_target_data *tp;
685 struct esp_lun_data *lp;
686 struct scsi_device *dev;
687 struct scsi_cmnd *cmd;
688 struct esp_cmd_entry *ent;
689 int tgt, lun, i;
690 u32 val, start_cmd;
691 u8 *p;
692
693 if (esp->active_cmd ||
694 (esp->flags & ESP_FLAG_RESETTING))
695 return;
696
697 ent = find_and_prep_issuable_command(esp);
698 if (!ent)
699 return;
700
701 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
702 esp_autosense(esp, ent);
703 return;
704 }
705
706 cmd = ent->cmd;
707 dev = cmd->device;
708 tgt = dev->id;
709 lun = dev->lun;
710 tp = &esp->target[tgt];
711 lp = dev->hostdata;
712
713 list_del(&ent->list);
714 list_add(&ent->list, &esp->active_cmds);
715
716 esp->active_cmd = ent;
717
718 esp_map_dma(esp, cmd);
719 esp_save_pointers(esp, ent);
720
721 esp_check_command_len(esp, cmd);
722
723 p = esp->command_block;
724
725 esp->msg_out_len = 0;
726 if (tp->flags & ESP_TGT_CHECK_NEGO) {
727 /* Need to negotiate. If the target is broken
728 * go for synchronous transfers and non-wide.
729 */
730 if (tp->flags & ESP_TGT_BROKEN) {
731 tp->flags &= ~ESP_TGT_DISCONNECT;
732 tp->nego_goal_period = 0;
733 tp->nego_goal_offset = 0;
734 tp->nego_goal_width = 0;
735 tp->nego_goal_tags = 0;
736 }
737
738 /* If the settings are not changing, skip this. */
739 if (spi_width(tp->starget) == tp->nego_goal_width &&
740 spi_period(tp->starget) == tp->nego_goal_period &&
741 spi_offset(tp->starget) == tp->nego_goal_offset) {
742 tp->flags &= ~ESP_TGT_CHECK_NEGO;
743 goto build_identify;
744 }
745
746 if (esp->rev == FASHME && esp_need_to_nego_wide(tp)) {
747 esp->msg_out_len =
748 spi_populate_width_msg(&esp->msg_out[0],
749 (tp->nego_goal_width ?
750 1 : 0));
751 tp->flags |= ESP_TGT_NEGO_WIDE;
752 } else if (esp_need_to_nego_sync(tp)) {
753 esp->msg_out_len =
754 spi_populate_sync_msg(&esp->msg_out[0],
755 tp->nego_goal_period,
756 tp->nego_goal_offset);
757 tp->flags |= ESP_TGT_NEGO_SYNC;
758 } else {
759 tp->flags &= ~ESP_TGT_CHECK_NEGO;
760 }
761
762 /* Process it like a slow command. */
763 if (tp->flags & (ESP_TGT_NEGO_WIDE | ESP_TGT_NEGO_SYNC))
764 esp->flags |= ESP_FLAG_DOING_SLOWCMD;
765 }
766
767build_identify:
768 /* If we don't have a lun-data struct yet, we're probing
769 * so do not disconnect. Also, do not disconnect unless
770 * we have a tag on this command.
771 */
772 if (lp && (tp->flags & ESP_TGT_DISCONNECT) && ent->tag[0])
773 *p++ = IDENTIFY(1, lun);
774 else
775 *p++ = IDENTIFY(0, lun);
776
777 if (ent->tag[0] && esp->rev == ESP100) {
778 /* ESP100 lacks select w/atn3 command, use select
779 * and stop instead.
780 */
781 esp->flags |= ESP_FLAG_DOING_SLOWCMD;
782 }
783
784 if (!(esp->flags & ESP_FLAG_DOING_SLOWCMD)) {
785 start_cmd = ESP_CMD_DMA | ESP_CMD_SELA;
786 if (ent->tag[0]) {
787 *p++ = ent->tag[0];
788 *p++ = ent->tag[1];
789
790 start_cmd = ESP_CMD_DMA | ESP_CMD_SA3;
791 }
792
793 for (i = 0; i < cmd->cmd_len; i++)
794 *p++ = cmd->cmnd[i];
795
796 esp->select_state = ESP_SELECT_BASIC;
797 } else {
798 esp->cmd_bytes_left = cmd->cmd_len;
799 esp->cmd_bytes_ptr = &cmd->cmnd[0];
800
801 if (ent->tag[0]) {
802 for (i = esp->msg_out_len - 1;
803 i >= 0; i--)
804 esp->msg_out[i + 2] = esp->msg_out[i];
805 esp->msg_out[0] = ent->tag[0];
806 esp->msg_out[1] = ent->tag[1];
807 esp->msg_out_len += 2;
808 }
809
810 start_cmd = ESP_CMD_DMA | ESP_CMD_SELAS;
811 esp->select_state = ESP_SELECT_MSGOUT;
812 }
813 val = tgt;
814 if (esp->rev == FASHME)
815 val |= ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT;
816 esp_write8(val, ESP_BUSID);
817
818 esp_write_tgt_sync(esp, tgt);
819 esp_write_tgt_config3(esp, tgt);
820
821 val = (p - esp->command_block);
822
823 if (esp_debug & ESP_DEBUG_SCSICMD) {
824 printk("ESP: tgt[%d] lun[%d] scsi_cmd [ ", tgt, lun);
825 for (i = 0; i < cmd->cmd_len; i++)
826 printk("%02x ", cmd->cmnd[i]);
827 printk("]\n");
828 }
829
830 if (esp->rev == FASHME)
831 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
832 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
833 val, 16, 0, start_cmd);
834}
835
836static struct esp_cmd_entry *esp_get_ent(struct esp *esp)
837{
838 struct list_head *head = &esp->esp_cmd_pool;
839 struct esp_cmd_entry *ret;
840
841 if (list_empty(head)) {
842 ret = kzalloc(sizeof(struct esp_cmd_entry), GFP_ATOMIC);
843 } else {
844 ret = list_entry(head->next, struct esp_cmd_entry, list);
845 list_del(&ret->list);
846 memset(ret, 0, sizeof(*ret));
847 }
848 return ret;
849}
850
851static void esp_put_ent(struct esp *esp, struct esp_cmd_entry *ent)
852{
853 list_add(&ent->list, &esp->esp_cmd_pool);
854}
855
856static void esp_cmd_is_done(struct esp *esp, struct esp_cmd_entry *ent,
857 struct scsi_cmnd *cmd, unsigned int result)
858{
859 struct scsi_device *dev = cmd->device;
860 int tgt = dev->id;
861 int lun = dev->lun;
862
863 esp->active_cmd = NULL;
864 esp_unmap_dma(esp, cmd);
865 esp_free_lun_tag(ent, dev->hostdata);
866 cmd->result = result;
867
868 if (ent->eh_done) {
869 complete(ent->eh_done);
870 ent->eh_done = NULL;
871 }
872
873 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
874 esp->ops->unmap_single(esp, ent->sense_dma,
875 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
876 ent->sense_ptr = NULL;
877
878 /* Restore the message/status bytes to what we actually
879 * saw originally. Also, report that we are providing
880 * the sense data.
881 */
882 cmd->result = ((DRIVER_SENSE << 24) |
883 (DID_OK << 16) |
884 (COMMAND_COMPLETE << 8) |
885 (SAM_STAT_CHECK_CONDITION << 0));
886
887 ent->flags &= ~ESP_CMD_FLAG_AUTOSENSE;
888 if (esp_debug & ESP_DEBUG_AUTOSENSE) {
889 int i;
890
891 printk("esp%d: tgt[%d] lun[%d] AUTO SENSE[ ",
892 esp->host->unique_id, tgt, lun);
893 for (i = 0; i < 18; i++)
894 printk("%02x ", cmd->sense_buffer[i]);
895 printk("]\n");
896 }
897 }
898
899 cmd->scsi_done(cmd);
900
901 list_del(&ent->list);
902 esp_put_ent(esp, ent);
903
904 esp_maybe_execute_command(esp);
905}
906
907static unsigned int compose_result(unsigned int status, unsigned int message,
908 unsigned int driver_code)
909{
910 return (status | (message << 8) | (driver_code << 16));
911}
912
913static void esp_event_queue_full(struct esp *esp, struct esp_cmd_entry *ent)
914{
915 struct scsi_device *dev = ent->cmd->device;
916 struct esp_lun_data *lp = dev->hostdata;
917
918 scsi_track_queue_full(dev, lp->num_tagged - 1);
919}
920
921static int esp_queuecommand(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
922{
923 struct scsi_device *dev = cmd->device;
924 struct esp *esp = host_to_esp(dev->host);
925 struct esp_cmd_priv *spriv;
926 struct esp_cmd_entry *ent;
927
928 ent = esp_get_ent(esp);
929 if (!ent)
930 return SCSI_MLQUEUE_HOST_BUSY;
931
932 ent->cmd = cmd;
933
934 cmd->scsi_done = done;
935
936 spriv = ESP_CMD_PRIV(cmd);
937 spriv->u.dma_addr = ~(dma_addr_t)0x0;
938
939 list_add_tail(&ent->list, &esp->queued_cmds);
940
941 esp_maybe_execute_command(esp);
942
943 return 0;
944}
945
946static int esp_check_gross_error(struct esp *esp)
947{
948 if (esp->sreg & ESP_STAT_SPAM) {
949 /* Gross Error, could be one of:
950 * - top of fifo overwritten
951 * - top of command register overwritten
952 * - DMA programmed with wrong direction
953 * - improper phase change
954 */
955 printk(KERN_ERR PFX "esp%d: Gross error sreg[%02x]\n",
956 esp->host->unique_id, esp->sreg);
957 /* XXX Reset the chip. XXX */
958 return 1;
959 }
960 return 0;
961}
962
963static int esp_check_spur_intr(struct esp *esp)
964{
965 switch (esp->rev) {
966 case ESP100:
967 case ESP100A:
968 /* The interrupt pending bit of the status register cannot
969 * be trusted on these revisions.
970 */
971 esp->sreg &= ~ESP_STAT_INTR;
972 break;
973
974 default:
975 if (!(esp->sreg & ESP_STAT_INTR)) {
976 esp->ireg = esp_read8(ESP_INTRPT);
977 if (esp->ireg & ESP_INTR_SR)
978 return 1;
979
980 /* If the DMA is indicating interrupt pending and the
981 * ESP is not, the only possibility is a DMA error.
982 */
983 if (!esp->ops->dma_error(esp)) {
984 printk(KERN_ERR PFX "esp%d: Spurious irq, "
985 "sreg=%x.\n",
986 esp->host->unique_id, esp->sreg);
987 return -1;
988 }
989
990 printk(KERN_ERR PFX "esp%d: DMA error\n",
991 esp->host->unique_id);
992
993 /* XXX Reset the chip. XXX */
994 return -1;
995 }
996 break;
997 }
998
999 return 0;
1000}
1001
1002static void esp_schedule_reset(struct esp *esp)
1003{
1004 esp_log_reset("ESP: esp_schedule_reset() from %p\n",
1005 __builtin_return_address(0));
1006 esp->flags |= ESP_FLAG_RESETTING;
1007 esp_event(esp, ESP_EVENT_RESET);
1008}
1009
1010/* In order to avoid having to add a special half-reconnected state
1011 * into the driver we just sit here and poll through the rest of
1012 * the reselection process to get the tag message bytes.
1013 */
1014static struct esp_cmd_entry *esp_reconnect_with_tag(struct esp *esp,
1015 struct esp_lun_data *lp)
1016{
1017 struct esp_cmd_entry *ent;
1018 int i;
1019
1020 if (!lp->num_tagged) {
1021 printk(KERN_ERR PFX "esp%d: Reconnect w/num_tagged==0\n",
1022 esp->host->unique_id);
1023 return NULL;
1024 }
1025
1026 esp_log_reconnect("ESP: reconnect tag, ");
1027
1028 for (i = 0; i < ESP_QUICKIRQ_LIMIT; i++) {
1029 if (esp->ops->irq_pending(esp))
1030 break;
1031 }
1032 if (i == ESP_QUICKIRQ_LIMIT) {
1033 printk(KERN_ERR PFX "esp%d: Reconnect IRQ1 timeout\n",
1034 esp->host->unique_id);
1035 return NULL;
1036 }
1037
1038 esp->sreg = esp_read8(ESP_STATUS);
1039 esp->ireg = esp_read8(ESP_INTRPT);
1040
1041 esp_log_reconnect("IRQ(%d:%x:%x), ",
1042 i, esp->ireg, esp->sreg);
1043
1044 if (esp->ireg & ESP_INTR_DC) {
1045 printk(KERN_ERR PFX "esp%d: Reconnect, got disconnect.\n",
1046 esp->host->unique_id);
1047 return NULL;
1048 }
1049
1050 if ((esp->sreg & ESP_STAT_PMASK) != ESP_MIP) {
1051 printk(KERN_ERR PFX "esp%d: Reconnect, not MIP sreg[%02x].\n",
1052 esp->host->unique_id, esp->sreg);
1053 return NULL;
1054 }
1055
1056 /* DMA in the tag bytes... */
1057 esp->command_block[0] = 0xff;
1058 esp->command_block[1] = 0xff;
1059 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
1060 2, 2, 1, ESP_CMD_DMA | ESP_CMD_TI);
1061
1062 /* ACK the msssage. */
1063 scsi_esp_cmd(esp, ESP_CMD_MOK);
1064
1065 for (i = 0; i < ESP_RESELECT_TAG_LIMIT; i++) {
1066 if (esp->ops->irq_pending(esp)) {
1067 esp->sreg = esp_read8(ESP_STATUS);
1068 esp->ireg = esp_read8(ESP_INTRPT);
1069 if (esp->ireg & ESP_INTR_FDONE)
1070 break;
1071 }
1072 udelay(1);
1073 }
1074 if (i == ESP_RESELECT_TAG_LIMIT) {
1075 printk(KERN_ERR PFX "esp%d: Reconnect IRQ2 timeout\n",
1076 esp->host->unique_id);
1077 return NULL;
1078 }
1079 esp->ops->dma_drain(esp);
1080 esp->ops->dma_invalidate(esp);
1081
1082 esp_log_reconnect("IRQ2(%d:%x:%x) tag[%x:%x]\n",
1083 i, esp->ireg, esp->sreg,
1084 esp->command_block[0],
1085 esp->command_block[1]);
1086
1087 if (esp->command_block[0] < SIMPLE_QUEUE_TAG ||
1088 esp->command_block[0] > ORDERED_QUEUE_TAG) {
1089 printk(KERN_ERR PFX "esp%d: Reconnect, bad tag "
1090 "type %02x.\n",
1091 esp->host->unique_id, esp->command_block[0]);
1092 return NULL;
1093 }
1094
1095 ent = lp->tagged_cmds[esp->command_block[1]];
1096 if (!ent) {
1097 printk(KERN_ERR PFX "esp%d: Reconnect, no entry for "
1098 "tag %02x.\n",
1099 esp->host->unique_id, esp->command_block[1]);
1100 return NULL;
1101 }
1102
1103 return ent;
1104}
1105
1106static int esp_reconnect(struct esp *esp)
1107{
1108 struct esp_cmd_entry *ent;
1109 struct esp_target_data *tp;
1110 struct esp_lun_data *lp;
1111 struct scsi_device *dev;
1112 int target, lun;
1113
1114 BUG_ON(esp->active_cmd);
1115 if (esp->rev == FASHME) {
1116 /* FASHME puts the target and lun numbers directly
1117 * into the fifo.
1118 */
1119 target = esp->fifo[0];
1120 lun = esp->fifo[1] & 0x7;
1121 } else {
1122 u8 bits = esp_read8(ESP_FDATA);
1123
1124 /* Older chips put the lun directly into the fifo, but
1125 * the target is given as a sample of the arbitration
1126 * lines on the bus at reselection time. So we should
1127 * see the ID of the ESP and the one reconnecting target
1128 * set in the bitmap.
1129 */
1130 if (!(bits & esp->scsi_id_mask))
1131 goto do_reset;
1132 bits &= ~esp->scsi_id_mask;
1133 if (!bits || (bits & (bits - 1)))
1134 goto do_reset;
1135
1136 target = ffs(bits) - 1;
1137 lun = (esp_read8(ESP_FDATA) & 0x7);
1138
1139 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1140 if (esp->rev == ESP100) {
1141 u8 ireg = esp_read8(ESP_INTRPT);
1142 /* This chip has a bug during reselection that can
1143 * cause a spurious illegal-command interrupt, which
1144 * we simply ACK here. Another possibility is a bus
1145 * reset so we must check for that.
1146 */
1147 if (ireg & ESP_INTR_SR)
1148 goto do_reset;
1149 }
1150 scsi_esp_cmd(esp, ESP_CMD_NULL);
1151 }
1152
1153 esp_write_tgt_sync(esp, target);
1154 esp_write_tgt_config3(esp, target);
1155
1156 scsi_esp_cmd(esp, ESP_CMD_MOK);
1157
1158 if (esp->rev == FASHME)
1159 esp_write8(target | ESP_BUSID_RESELID | ESP_BUSID_CTR32BIT,
1160 ESP_BUSID);
1161
1162 tp = &esp->target[target];
1163 dev = __scsi_device_lookup_by_target(tp->starget, lun);
1164 if (!dev) {
1165 printk(KERN_ERR PFX "esp%d: Reconnect, no lp "
1166 "tgt[%u] lun[%u]\n",
1167 esp->host->unique_id, target, lun);
1168 goto do_reset;
1169 }
1170 lp = dev->hostdata;
1171
1172 ent = lp->non_tagged_cmd;
1173 if (!ent) {
1174 ent = esp_reconnect_with_tag(esp, lp);
1175 if (!ent)
1176 goto do_reset;
1177 }
1178
1179 esp->active_cmd = ent;
1180
1181 if (ent->flags & ESP_CMD_FLAG_ABORT) {
1182 esp->msg_out[0] = ABORT_TASK_SET;
1183 esp->msg_out_len = 1;
1184 scsi_esp_cmd(esp, ESP_CMD_SATN);
1185 }
1186
1187 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1188 esp_restore_pointers(esp, ent);
1189 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1190 return 1;
1191
1192do_reset:
1193 esp_schedule_reset(esp);
1194 return 0;
1195}
1196
1197static int esp_finish_select(struct esp *esp)
1198{
1199 struct esp_cmd_entry *ent;
1200 struct scsi_cmnd *cmd;
1201 u8 orig_select_state;
1202
1203 orig_select_state = esp->select_state;
1204
1205 /* No longer selecting. */
1206 esp->select_state = ESP_SELECT_NONE;
1207
1208 esp->seqreg = esp_read8(ESP_SSTEP) & ESP_STEP_VBITS;
1209 ent = esp->active_cmd;
1210 cmd = ent->cmd;
1211
1212 if (esp->ops->dma_error(esp)) {
1213 /* If we see a DMA error during or as a result of selection,
1214 * all bets are off.
1215 */
1216 esp_schedule_reset(esp);
1217 esp_cmd_is_done(esp, ent, cmd, (DID_ERROR << 16));
1218 return 0;
1219 }
1220
1221 esp->ops->dma_invalidate(esp);
1222
1223 if (esp->ireg == (ESP_INTR_RSEL | ESP_INTR_FDONE)) {
1224 struct esp_target_data *tp = &esp->target[cmd->device->id];
1225
1226 /* Carefully back out of the selection attempt. Release
1227 * resources (such as DMA mapping & TAG) and reset state (such
1228 * as message out and command delivery variables).
1229 */
1230 if (!(ent->flags & ESP_CMD_FLAG_AUTOSENSE)) {
1231 esp_unmap_dma(esp, cmd);
1232 esp_free_lun_tag(ent, cmd->device->hostdata);
1233 tp->flags &= ~(ESP_TGT_NEGO_SYNC | ESP_TGT_NEGO_WIDE);
1234 esp->flags &= ~ESP_FLAG_DOING_SLOWCMD;
1235 esp->cmd_bytes_ptr = NULL;
1236 esp->cmd_bytes_left = 0;
1237 } else {
1238 esp->ops->unmap_single(esp, ent->sense_dma,
1239 SCSI_SENSE_BUFFERSIZE,
1240 DMA_FROM_DEVICE);
1241 ent->sense_ptr = NULL;
1242 }
1243
1244 /* Now that the state is unwound properly, put back onto
1245 * the issue queue. This command is no longer active.
1246 */
1247 list_del(&ent->list);
1248 list_add(&ent->list, &esp->queued_cmds);
1249 esp->active_cmd = NULL;
1250
1251 /* Return value ignored by caller, it directly invokes
1252 * esp_reconnect().
1253 */
1254 return 0;
1255 }
1256
1257 if (esp->ireg == ESP_INTR_DC) {
1258 struct scsi_device *dev = cmd->device;
1259
1260 /* Disconnect. Make sure we re-negotiate sync and
1261 * wide parameters if this target starts responding
1262 * again in the future.
1263 */
1264 esp->target[dev->id].flags |= ESP_TGT_CHECK_NEGO;
1265
1266 scsi_esp_cmd(esp, ESP_CMD_ESEL);
1267 esp_cmd_is_done(esp, ent, cmd, (DID_BAD_TARGET << 16));
1268 return 1;
1269 }
1270
1271 if (esp->ireg == (ESP_INTR_FDONE | ESP_INTR_BSERV)) {
1272 /* Selection successful. On pre-FAST chips we have
1273 * to do a NOP and possibly clean out the FIFO.
1274 */
1275 if (esp->rev <= ESP236) {
1276 int fcnt = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
1277
1278 scsi_esp_cmd(esp, ESP_CMD_NULL);
1279
1280 if (!fcnt &&
1281 (!esp->prev_soff ||
1282 ((esp->sreg & ESP_STAT_PMASK) != ESP_DIP)))
1283 esp_flush_fifo(esp);
1284 }
1285
1286 /* If we are doing a slow command, negotiation, etc.
1287 * we'll do the right thing as we transition to the
1288 * next phase.
1289 */
1290 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1291 return 0;
1292 }
1293
1294 printk("ESP: Unexpected selection completion ireg[%x].\n",
1295 esp->ireg);
1296 esp_schedule_reset(esp);
1297 return 0;
1298}
1299
1300static int esp_data_bytes_sent(struct esp *esp, struct esp_cmd_entry *ent,
1301 struct scsi_cmnd *cmd)
1302{
1303 int fifo_cnt, ecount, bytes_sent, flush_fifo;
1304
1305 fifo_cnt = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
1306 if (esp->prev_cfg3 & ESP_CONFIG3_EWIDE)
1307 fifo_cnt <<= 1;
1308
1309 ecount = 0;
1310 if (!(esp->sreg & ESP_STAT_TCNT)) {
1311 ecount = ((unsigned int)esp_read8(ESP_TCLOW) |
1312 (((unsigned int)esp_read8(ESP_TCMED)) << 8));
1313 if (esp->rev == FASHME)
1314 ecount |= ((unsigned int)esp_read8(FAS_RLO)) << 16;
1315 }
1316
1317 bytes_sent = esp->data_dma_len;
1318 bytes_sent -= ecount;
1319
1320 if (!(ent->flags & ESP_CMD_FLAG_WRITE))
1321 bytes_sent -= fifo_cnt;
1322
1323 flush_fifo = 0;
1324 if (!esp->prev_soff) {
1325 /* Synchronous data transfer, always flush fifo. */
1326 flush_fifo = 1;
1327 } else {
1328 if (esp->rev == ESP100) {
1329 u32 fflags, phase;
1330
1331 /* ESP100 has a chip bug where in the synchronous data
1332 * phase it can mistake a final long REQ pulse from the
1333 * target as an extra data byte. Fun.
1334 *
1335 * To detect this case we resample the status register
1336 * and fifo flags. If we're still in a data phase and
1337 * we see spurious chunks in the fifo, we return error
1338 * to the caller which should reset and set things up
1339 * such that we only try future transfers to this
1340 * target in synchronous mode.
1341 */
1342 esp->sreg = esp_read8(ESP_STATUS);
1343 phase = esp->sreg & ESP_STAT_PMASK;
1344 fflags = esp_read8(ESP_FFLAGS);
1345
1346 if ((phase == ESP_DOP &&
1347 (fflags & ESP_FF_ONOTZERO)) ||
1348 (phase == ESP_DIP &&
1349 (fflags & ESP_FF_FBYTES)))
1350 return -1;
1351 }
1352 if (!(ent->flags & ESP_CMD_FLAG_WRITE))
1353 flush_fifo = 1;
1354 }
1355
1356 if (flush_fifo)
1357 esp_flush_fifo(esp);
1358
1359 return bytes_sent;
1360}
1361
1362static void esp_setsync(struct esp *esp, struct esp_target_data *tp,
1363 u8 scsi_period, u8 scsi_offset,
1364 u8 esp_stp, u8 esp_soff)
1365{
1366 spi_period(tp->starget) = scsi_period;
1367 spi_offset(tp->starget) = scsi_offset;
1368 spi_width(tp->starget) = (tp->flags & ESP_TGT_WIDE) ? 1 : 0;
1369
1370 if (esp_soff) {
1371 esp_stp &= 0x1f;
1372 esp_soff |= esp->radelay;
1373 if (esp->rev >= FAS236) {
1374 u8 bit = ESP_CONFIG3_FSCSI;
1375 if (esp->rev >= FAS100A)
1376 bit = ESP_CONFIG3_FAST;
1377
1378 if (scsi_period < 50) {
1379 if (esp->rev == FASHME)
1380 esp_soff &= ~esp->radelay;
1381 tp->esp_config3 |= bit;
1382 } else {
1383 tp->esp_config3 &= ~bit;
1384 }
1385 esp->prev_cfg3 = tp->esp_config3;
1386 esp_write8(esp->prev_cfg3, ESP_CFG3);
1387 }
1388 }
1389
1390 tp->esp_period = esp->prev_stp = esp_stp;
1391 tp->esp_offset = esp->prev_soff = esp_soff;
1392
1393 esp_write8(esp_soff, ESP_SOFF);
1394 esp_write8(esp_stp, ESP_STP);
1395
1396 tp->flags &= ~(ESP_TGT_NEGO_SYNC | ESP_TGT_CHECK_NEGO);
1397
1398 spi_display_xfer_agreement(tp->starget);
1399}
1400
1401static void esp_msgin_reject(struct esp *esp)
1402{
1403 struct esp_cmd_entry *ent = esp->active_cmd;
1404 struct scsi_cmnd *cmd = ent->cmd;
1405 struct esp_target_data *tp;
1406 int tgt;
1407
1408 tgt = cmd->device->id;
1409 tp = &esp->target[tgt];
1410
1411 if (tp->flags & ESP_TGT_NEGO_WIDE) {
1412 tp->flags &= ~(ESP_TGT_NEGO_WIDE | ESP_TGT_WIDE);
1413
1414 if (!esp_need_to_nego_sync(tp)) {
1415 tp->flags &= ~ESP_TGT_CHECK_NEGO;
1416 scsi_esp_cmd(esp, ESP_CMD_RATN);
1417 } else {
1418 esp->msg_out_len =
1419 spi_populate_sync_msg(&esp->msg_out[0],
1420 tp->nego_goal_period,
1421 tp->nego_goal_offset);
1422 tp->flags |= ESP_TGT_NEGO_SYNC;
1423 scsi_esp_cmd(esp, ESP_CMD_SATN);
1424 }
1425 return;
1426 }
1427
1428 if (tp->flags & ESP_TGT_NEGO_SYNC) {
1429 tp->flags &= ~(ESP_TGT_NEGO_SYNC | ESP_TGT_CHECK_NEGO);
1430 tp->esp_period = 0;
1431 tp->esp_offset = 0;
1432 esp_setsync(esp, tp, 0, 0, 0, 0);
1433 scsi_esp_cmd(esp, ESP_CMD_RATN);
1434 return;
1435 }
1436
1437 esp->msg_out[0] = ABORT_TASK_SET;
1438 esp->msg_out_len = 1;
1439 scsi_esp_cmd(esp, ESP_CMD_SATN);
1440}
1441
1442static void esp_msgin_sdtr(struct esp *esp, struct esp_target_data *tp)
1443{
1444 u8 period = esp->msg_in[3];
1445 u8 offset = esp->msg_in[4];
1446 u8 stp;
1447
1448 if (!(tp->flags & ESP_TGT_NEGO_SYNC))
1449 goto do_reject;
1450
1451 if (offset > 15)
1452 goto do_reject;
1453
1454 if (offset) {
1455 int rounded_up, one_clock;
1456
1457 if (period > esp->max_period) {
1458 period = offset = 0;
1459 goto do_sdtr;
1460 }
1461 if (period < esp->min_period)
1462 goto do_reject;
1463
1464 one_clock = esp->ccycle / 1000;
1465 rounded_up = (period << 2);
1466 rounded_up = (rounded_up + one_clock - 1) / one_clock;
1467 stp = rounded_up;
1468 if (stp && esp->rev >= FAS236) {
1469 if (stp >= 50)
1470 stp--;
1471 }
1472 } else {
1473 stp = 0;
1474 }
1475
1476 esp_setsync(esp, tp, period, offset, stp, offset);
1477 return;
1478
1479do_reject:
1480 esp->msg_out[0] = MESSAGE_REJECT;
1481 esp->msg_out_len = 1;
1482 scsi_esp_cmd(esp, ESP_CMD_SATN);
1483 return;
1484
1485do_sdtr:
1486 tp->nego_goal_period = period;
1487 tp->nego_goal_offset = offset;
1488 esp->msg_out_len =
1489 spi_populate_sync_msg(&esp->msg_out[0],
1490 tp->nego_goal_period,
1491 tp->nego_goal_offset);
1492 scsi_esp_cmd(esp, ESP_CMD_SATN);
1493}
1494
1495static void esp_msgin_wdtr(struct esp *esp, struct esp_target_data *tp)
1496{
1497 int size = 8 << esp->msg_in[3];
1498 u8 cfg3;
1499
1500 if (esp->rev != FASHME)
1501 goto do_reject;
1502
1503 if (size != 8 && size != 16)
1504 goto do_reject;
1505
1506 if (!(tp->flags & ESP_TGT_NEGO_WIDE))
1507 goto do_reject;
1508
1509 cfg3 = tp->esp_config3;
1510 if (size == 16) {
1511 tp->flags |= ESP_TGT_WIDE;
1512 cfg3 |= ESP_CONFIG3_EWIDE;
1513 } else {
1514 tp->flags &= ~ESP_TGT_WIDE;
1515 cfg3 &= ~ESP_CONFIG3_EWIDE;
1516 }
1517 tp->esp_config3 = cfg3;
1518 esp->prev_cfg3 = cfg3;
1519 esp_write8(cfg3, ESP_CFG3);
1520
1521 tp->flags &= ~ESP_TGT_NEGO_WIDE;
1522
1523 spi_period(tp->starget) = 0;
1524 spi_offset(tp->starget) = 0;
1525 if (!esp_need_to_nego_sync(tp)) {
1526 tp->flags &= ~ESP_TGT_CHECK_NEGO;
1527 scsi_esp_cmd(esp, ESP_CMD_RATN);
1528 } else {
1529 esp->msg_out_len =
1530 spi_populate_sync_msg(&esp->msg_out[0],
1531 tp->nego_goal_period,
1532 tp->nego_goal_offset);
1533 tp->flags |= ESP_TGT_NEGO_SYNC;
1534 scsi_esp_cmd(esp, ESP_CMD_SATN);
1535 }
1536 return;
1537
1538do_reject:
1539 esp->msg_out[0] = MESSAGE_REJECT;
1540 esp->msg_out_len = 1;
1541 scsi_esp_cmd(esp, ESP_CMD_SATN);
1542}
1543
1544static void esp_msgin_extended(struct esp *esp)
1545{
1546 struct esp_cmd_entry *ent = esp->active_cmd;
1547 struct scsi_cmnd *cmd = ent->cmd;
1548 struct esp_target_data *tp;
1549 int tgt = cmd->device->id;
1550
1551 tp = &esp->target[tgt];
1552 if (esp->msg_in[2] == EXTENDED_SDTR) {
1553 esp_msgin_sdtr(esp, tp);
1554 return;
1555 }
1556 if (esp->msg_in[2] == EXTENDED_WDTR) {
1557 esp_msgin_wdtr(esp, tp);
1558 return;
1559 }
1560
1561 printk("ESP: Unexpected extended msg type %x\n",
1562 esp->msg_in[2]);
1563
1564 esp->msg_out[0] = ABORT_TASK_SET;
1565 esp->msg_out_len = 1;
1566 scsi_esp_cmd(esp, ESP_CMD_SATN);
1567}
1568
1569/* Analyze msgin bytes received from target so far. Return non-zero
1570 * if there are more bytes needed to complete the message.
1571 */
1572static int esp_msgin_process(struct esp *esp)
1573{
1574 u8 msg0 = esp->msg_in[0];
1575 int len = esp->msg_in_len;
1576
1577 if (msg0 & 0x80) {
1578 /* Identify */
1579 printk("ESP: Unexpected msgin identify\n");
1580 return 0;
1581 }
1582
1583 switch (msg0) {
1584 case EXTENDED_MESSAGE:
1585 if (len == 1)
1586 return 1;
1587 if (len < esp->msg_in[1] + 2)
1588 return 1;
1589 esp_msgin_extended(esp);
1590 return 0;
1591
1592 case IGNORE_WIDE_RESIDUE: {
1593 struct esp_cmd_entry *ent;
1594 struct esp_cmd_priv *spriv;
1595 if (len == 1)
1596 return 1;
1597
1598 if (esp->msg_in[1] != 1)
1599 goto do_reject;
1600
1601 ent = esp->active_cmd;
1602 spriv = ESP_CMD_PRIV(ent->cmd);
1603
1604 if (spriv->cur_residue == sg_dma_len(spriv->cur_sg)) {
1605 spriv->cur_sg--;
1606 spriv->cur_residue = 1;
1607 } else
1608 spriv->cur_residue++;
1609 spriv->tot_residue++;
1610 return 0;
1611 }
1612 case NOP:
1613 return 0;
1614 case RESTORE_POINTERS:
1615 esp_restore_pointers(esp, esp->active_cmd);
1616 return 0;
1617 case SAVE_POINTERS:
1618 esp_save_pointers(esp, esp->active_cmd);
1619 return 0;
1620
1621 case COMMAND_COMPLETE:
1622 case DISCONNECT: {
1623 struct esp_cmd_entry *ent = esp->active_cmd;
1624
1625 ent->message = msg0;
1626 esp_event(esp, ESP_EVENT_FREE_BUS);
1627 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1628 return 0;
1629 }
1630 case MESSAGE_REJECT:
1631 esp_msgin_reject(esp);
1632 return 0;
1633
1634 default:
1635 do_reject:
1636 esp->msg_out[0] = MESSAGE_REJECT;
1637 esp->msg_out_len = 1;
1638 scsi_esp_cmd(esp, ESP_CMD_SATN);
1639 return 0;
1640 }
1641}
1642
1643static int esp_process_event(struct esp *esp)
1644{
1645 int write;
1646
1647again:
1648 write = 0;
1649 switch (esp->event) {
1650 case ESP_EVENT_CHECK_PHASE:
1651 switch (esp->sreg & ESP_STAT_PMASK) {
1652 case ESP_DOP:
1653 esp_event(esp, ESP_EVENT_DATA_OUT);
1654 break;
1655 case ESP_DIP:
1656 esp_event(esp, ESP_EVENT_DATA_IN);
1657 break;
1658 case ESP_STATP:
1659 esp_flush_fifo(esp);
1660 scsi_esp_cmd(esp, ESP_CMD_ICCSEQ);
1661 esp_event(esp, ESP_EVENT_STATUS);
1662 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1663 return 1;
1664
1665 case ESP_MOP:
1666 esp_event(esp, ESP_EVENT_MSGOUT);
1667 break;
1668
1669 case ESP_MIP:
1670 esp_event(esp, ESP_EVENT_MSGIN);
1671 break;
1672
1673 case ESP_CMDP:
1674 esp_event(esp, ESP_EVENT_CMD_START);
1675 break;
1676
1677 default:
1678 printk("ESP: Unexpected phase, sreg=%02x\n",
1679 esp->sreg);
1680 esp_schedule_reset(esp);
1681 return 0;
1682 }
1683 goto again;
1684 break;
1685
1686 case ESP_EVENT_DATA_IN:
1687 write = 1;
1688 /* fallthru */
1689
1690 case ESP_EVENT_DATA_OUT: {
1691 struct esp_cmd_entry *ent = esp->active_cmd;
1692 struct scsi_cmnd *cmd = ent->cmd;
1693 dma_addr_t dma_addr = esp_cur_dma_addr(ent, cmd);
1694 unsigned int dma_len = esp_cur_dma_len(ent, cmd);
1695
1696 if (esp->rev == ESP100)
1697 scsi_esp_cmd(esp, ESP_CMD_NULL);
1698
1699 if (write)
1700 ent->flags |= ESP_CMD_FLAG_WRITE;
1701 else
1702 ent->flags &= ~ESP_CMD_FLAG_WRITE;
1703
1704 dma_len = esp_dma_length_limit(esp, dma_addr, dma_len);
1705 esp->data_dma_len = dma_len;
1706
1707 if (!dma_len) {
1708 printk(KERN_ERR PFX "esp%d: DMA length is zero!\n",
1709 esp->host->unique_id);
1710 printk(KERN_ERR PFX "esp%d: cur adr[%08llx] len[%08x]\n",
1711 esp->host->unique_id,
1712 (unsigned long long)esp_cur_dma_addr(ent, cmd),
1713 esp_cur_dma_len(ent, cmd));
1714 esp_schedule_reset(esp);
1715 return 0;
1716 }
1717
1718 esp_log_datastart("ESP: start data addr[%08llx] len[%u] "
1719 "write(%d)\n",
1720 (unsigned long long)dma_addr, dma_len, write);
1721
1722 esp->ops->send_dma_cmd(esp, dma_addr, dma_len, dma_len,
1723 write, ESP_CMD_DMA | ESP_CMD_TI);
1724 esp_event(esp, ESP_EVENT_DATA_DONE);
1725 break;
1726 }
1727 case ESP_EVENT_DATA_DONE: {
1728 struct esp_cmd_entry *ent = esp->active_cmd;
1729 struct scsi_cmnd *cmd = ent->cmd;
1730 int bytes_sent;
1731
1732 if (esp->ops->dma_error(esp)) {
1733 printk("ESP: data done, DMA error, resetting\n");
1734 esp_schedule_reset(esp);
1735 return 0;
1736 }
1737
1738 if (ent->flags & ESP_CMD_FLAG_WRITE) {
1739 /* XXX parity errors, etc. XXX */
1740
1741 esp->ops->dma_drain(esp);
1742 }
1743 esp->ops->dma_invalidate(esp);
1744
1745 if (esp->ireg != ESP_INTR_BSERV) {
1746 /* We should always see exactly a bus-service
1747 * interrupt at the end of a successful transfer.
1748 */
1749 printk("ESP: data done, not BSERV, resetting\n");
1750 esp_schedule_reset(esp);
1751 return 0;
1752 }
1753
1754 bytes_sent = esp_data_bytes_sent(esp, ent, cmd);
1755
1756 esp_log_datadone("ESP: data done flgs[%x] sent[%d]\n",
1757 ent->flags, bytes_sent);
1758
1759 if (bytes_sent < 0) {
1760 /* XXX force sync mode for this target XXX */
1761 esp_schedule_reset(esp);
1762 return 0;
1763 }
1764
1765 esp_advance_dma(esp, ent, cmd, bytes_sent);
1766 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1767 goto again;
1768 break;
1769 }
1770
1771 case ESP_EVENT_STATUS: {
1772 struct esp_cmd_entry *ent = esp->active_cmd;
1773
1774 if (esp->ireg & ESP_INTR_FDONE) {
1775 ent->status = esp_read8(ESP_FDATA);
1776 ent->message = esp_read8(ESP_FDATA);
1777 scsi_esp_cmd(esp, ESP_CMD_MOK);
1778 } else if (esp->ireg == ESP_INTR_BSERV) {
1779 ent->status = esp_read8(ESP_FDATA);
1780 ent->message = 0xff;
1781 esp_event(esp, ESP_EVENT_MSGIN);
1782 return 0;
1783 }
1784
1785 if (ent->message != COMMAND_COMPLETE) {
1786 printk("ESP: Unexpected message %x in status\n",
1787 ent->message);
1788 esp_schedule_reset(esp);
1789 return 0;
1790 }
1791
1792 esp_event(esp, ESP_EVENT_FREE_BUS);
1793 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1794 break;
1795 }
1796 case ESP_EVENT_FREE_BUS: {
1797 struct esp_cmd_entry *ent = esp->active_cmd;
1798 struct scsi_cmnd *cmd = ent->cmd;
1799
1800 if (ent->message == COMMAND_COMPLETE ||
1801 ent->message == DISCONNECT)
1802 scsi_esp_cmd(esp, ESP_CMD_ESEL);
1803
1804 if (ent->message == COMMAND_COMPLETE) {
1805 esp_log_cmddone("ESP: Command done status[%x] "
1806 "message[%x]\n",
1807 ent->status, ent->message);
1808 if (ent->status == SAM_STAT_TASK_SET_FULL)
1809 esp_event_queue_full(esp, ent);
1810
1811 if (ent->status == SAM_STAT_CHECK_CONDITION &&
1812 !(ent->flags & ESP_CMD_FLAG_AUTOSENSE)) {
1813 ent->flags |= ESP_CMD_FLAG_AUTOSENSE;
1814 esp_autosense(esp, ent);
1815 } else {
1816 esp_cmd_is_done(esp, ent, cmd,
1817 compose_result(ent->status,
1818 ent->message,
1819 DID_OK));
1820 }
1821 } else if (ent->message == DISCONNECT) {
1822 esp_log_disconnect("ESP: Disconnecting tgt[%d] "
1823 "tag[%x:%x]\n",
1824 cmd->device->id,
1825 ent->tag[0], ent->tag[1]);
1826
1827 esp->active_cmd = NULL;
1828 esp_maybe_execute_command(esp);
1829 } else {
1830 printk("ESP: Unexpected message %x in freebus\n",
1831 ent->message);
1832 esp_schedule_reset(esp);
1833 return 0;
1834 }
1835 if (esp->active_cmd)
1836 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1837 break;
1838 }
1839 case ESP_EVENT_MSGOUT: {
1840 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1841
1842 if (esp_debug & ESP_DEBUG_MSGOUT) {
1843 int i;
1844 printk("ESP: Sending message [ ");
1845 for (i = 0; i < esp->msg_out_len; i++)
1846 printk("%02x ", esp->msg_out[i]);
1847 printk("]\n");
1848 }
1849
1850 if (esp->rev == FASHME) {
1851 int i;
1852
1853 /* Always use the fifo. */
1854 for (i = 0; i < esp->msg_out_len; i++) {
1855 esp_write8(esp->msg_out[i], ESP_FDATA);
1856 esp_write8(0, ESP_FDATA);
1857 }
1858 scsi_esp_cmd(esp, ESP_CMD_TI);
1859 } else {
1860 if (esp->msg_out_len == 1) {
1861 esp_write8(esp->msg_out[0], ESP_FDATA);
1862 scsi_esp_cmd(esp, ESP_CMD_TI);
1863 } else {
1864 /* Use DMA. */
1865 memcpy(esp->command_block,
1866 esp->msg_out,
1867 esp->msg_out_len);
1868
1869 esp->ops->send_dma_cmd(esp,
1870 esp->command_block_dma,
1871 esp->msg_out_len,
1872 esp->msg_out_len,
1873 0,
1874 ESP_CMD_DMA|ESP_CMD_TI);
1875 }
1876 }
1877 esp_event(esp, ESP_EVENT_MSGOUT_DONE);
1878 break;
1879 }
1880 case ESP_EVENT_MSGOUT_DONE:
1881 if (esp->rev == FASHME) {
1882 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1883 } else {
1884 if (esp->msg_out_len > 1)
1885 esp->ops->dma_invalidate(esp);
1886 }
1887
1888 if (!(esp->ireg & ESP_INTR_DC)) {
1889 if (esp->rev != FASHME)
1890 scsi_esp_cmd(esp, ESP_CMD_NULL);
1891 }
1892 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1893 goto again;
1894 case ESP_EVENT_MSGIN:
1895 if (esp->ireg & ESP_INTR_BSERV) {
1896 if (esp->rev == FASHME) {
1897 if (!(esp_read8(ESP_STATUS2) &
1898 ESP_STAT2_FEMPTY))
1899 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1900 } else {
1901 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1902 if (esp->rev == ESP100)
1903 scsi_esp_cmd(esp, ESP_CMD_NULL);
1904 }
1905 scsi_esp_cmd(esp, ESP_CMD_TI);
1906 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1907 return 1;
1908 }
1909 if (esp->ireg & ESP_INTR_FDONE) {
1910 u8 val;
1911
1912 if (esp->rev == FASHME)
1913 val = esp->fifo[0];
1914 else
1915 val = esp_read8(ESP_FDATA);
1916 esp->msg_in[esp->msg_in_len++] = val;
1917
1918 esp_log_msgin("ESP: Got msgin byte %x\n", val);
1919
1920 if (!esp_msgin_process(esp))
1921 esp->msg_in_len = 0;
1922
1923 if (esp->rev == FASHME)
1924 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1925
1926 scsi_esp_cmd(esp, ESP_CMD_MOK);
1927
1928 if (esp->event != ESP_EVENT_FREE_BUS)
1929 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1930 } else {
1931 printk("ESP: MSGIN neither BSERV not FDON, resetting");
1932 esp_schedule_reset(esp);
1933 return 0;
1934 }
1935 break;
1936 case ESP_EVENT_CMD_START:
1937 memcpy(esp->command_block, esp->cmd_bytes_ptr,
1938 esp->cmd_bytes_left);
1939 if (esp->rev == FASHME)
1940 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
1941 esp->ops->send_dma_cmd(esp, esp->command_block_dma,
1942 esp->cmd_bytes_left, 16, 0,
1943 ESP_CMD_DMA | ESP_CMD_TI);
1944 esp_event(esp, ESP_EVENT_CMD_DONE);
1945 esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
1946 break;
1947 case ESP_EVENT_CMD_DONE:
1948 esp->ops->dma_invalidate(esp);
1949 if (esp->ireg & ESP_INTR_BSERV) {
1950 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1951 goto again;
1952 }
1953 esp_schedule_reset(esp);
1954 return 0;
1955 break;
1956
1957 case ESP_EVENT_RESET:
1958 scsi_esp_cmd(esp, ESP_CMD_RS);
1959 break;
1960
1961 default:
1962 printk("ESP: Unexpected event %x, resetting\n",
1963 esp->event);
1964 esp_schedule_reset(esp);
1965 return 0;
1966 break;
1967 }
1968 return 1;
1969}
1970
1971static void esp_reset_cleanup_one(struct esp *esp, struct esp_cmd_entry *ent)
1972{
1973 struct scsi_cmnd *cmd = ent->cmd;
1974
1975 esp_unmap_dma(esp, cmd);
1976 esp_free_lun_tag(ent, cmd->device->hostdata);
1977 cmd->result = DID_RESET << 16;
1978
1979 if (ent->flags & ESP_CMD_FLAG_AUTOSENSE) {
1980 esp->ops->unmap_single(esp, ent->sense_dma,
1981 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
1982 ent->sense_ptr = NULL;
1983 }
1984
1985 cmd->scsi_done(cmd);
1986 list_del(&ent->list);
1987 esp_put_ent(esp, ent);
1988}
1989
1990static void esp_clear_hold(struct scsi_device *dev, void *data)
1991{
1992 struct esp_lun_data *lp = dev->hostdata;
1993
1994 BUG_ON(lp->num_tagged);
1995 lp->hold = 0;
1996}
1997
1998static void esp_reset_cleanup(struct esp *esp)
1999{
2000 struct esp_cmd_entry *ent, *tmp;
2001 int i;
2002
2003 list_for_each_entry_safe(ent, tmp, &esp->queued_cmds, list) {
2004 struct scsi_cmnd *cmd = ent->cmd;
2005
2006 list_del(&ent->list);
2007 cmd->result = DID_RESET << 16;
2008 cmd->scsi_done(cmd);
2009 esp_put_ent(esp, ent);
2010 }
2011
2012 list_for_each_entry_safe(ent, tmp, &esp->active_cmds, list) {
2013 if (ent == esp->active_cmd)
2014 esp->active_cmd = NULL;
2015 esp_reset_cleanup_one(esp, ent);
2016 }
2017
2018 BUG_ON(esp->active_cmd != NULL);
2019
2020 /* Force renegotiation of sync/wide transfers. */
2021 for (i = 0; i < ESP_MAX_TARGET; i++) {
2022 struct esp_target_data *tp = &esp->target[i];
2023
2024 tp->esp_period = 0;
2025 tp->esp_offset = 0;
2026 tp->esp_config3 &= ~(ESP_CONFIG3_EWIDE |
2027 ESP_CONFIG3_FSCSI |
2028 ESP_CONFIG3_FAST);
2029 tp->flags &= ~ESP_TGT_WIDE;
2030 tp->flags |= ESP_TGT_CHECK_NEGO;
2031
2032 if (tp->starget)
2033 starget_for_each_device(tp->starget, NULL,
2034 esp_clear_hold);
2035 }
2036}
2037
2038/* Runs under host->lock */
2039static void __esp_interrupt(struct esp *esp)
2040{
2041 int finish_reset, intr_done;
2042 u8 phase;
2043
2044 esp->sreg = esp_read8(ESP_STATUS);
2045
2046 if (esp->flags & ESP_FLAG_RESETTING) {
2047 finish_reset = 1;
2048 } else {
2049 if (esp_check_gross_error(esp))
2050 return;
2051
2052 finish_reset = esp_check_spur_intr(esp);
2053 if (finish_reset < 0)
2054 return;
2055 }
2056
2057 esp->ireg = esp_read8(ESP_INTRPT);
2058
2059 if (esp->ireg & ESP_INTR_SR)
2060 finish_reset = 1;
2061
2062 if (finish_reset) {
2063 esp_reset_cleanup(esp);
2064 if (esp->eh_reset) {
2065 complete(esp->eh_reset);
2066 esp->eh_reset = NULL;
2067 }
2068 return;
2069 }
2070
2071 phase = (esp->sreg & ESP_STAT_PMASK);
2072 if (esp->rev == FASHME) {
2073 if (((phase != ESP_DIP && phase != ESP_DOP) &&
2074 esp->select_state == ESP_SELECT_NONE &&
2075 esp->event != ESP_EVENT_STATUS &&
2076 esp->event != ESP_EVENT_DATA_DONE) ||
2077 (esp->ireg & ESP_INTR_RSEL)) {
2078 esp->sreg2 = esp_read8(ESP_STATUS2);
2079 if (!(esp->sreg2 & ESP_STAT2_FEMPTY) ||
2080 (esp->sreg2 & ESP_STAT2_F1BYTE))
2081 hme_read_fifo(esp);
2082 }
2083 }
2084
2085 esp_log_intr("ESP: intr sreg[%02x] seqreg[%02x] "
2086 "sreg2[%02x] ireg[%02x]\n",
2087 esp->sreg, esp->seqreg, esp->sreg2, esp->ireg);
2088
2089 intr_done = 0;
2090
2091 if (esp->ireg & (ESP_INTR_S | ESP_INTR_SATN | ESP_INTR_IC)) {
2092 printk("ESP: unexpected IREG %02x\n", esp->ireg);
2093 if (esp->ireg & ESP_INTR_IC)
2094 esp_dump_cmd_log(esp);
2095
2096 esp_schedule_reset(esp);
2097 } else {
2098 if (!(esp->ireg & ESP_INTR_RSEL)) {
2099 /* Some combination of FDONE, BSERV, DC. */
2100 if (esp->select_state != ESP_SELECT_NONE)
2101 intr_done = esp_finish_select(esp);
2102 } else if (esp->ireg & ESP_INTR_RSEL) {
2103 if (esp->active_cmd)
2104 (void) esp_finish_select(esp);
2105 intr_done = esp_reconnect(esp);
2106 }
2107 }
2108 while (!intr_done)
2109 intr_done = esp_process_event(esp);
2110}
2111
2112irqreturn_t scsi_esp_intr(int irq, void *dev_id)
2113{
2114 struct esp *esp = dev_id;
2115 unsigned long flags;
2116 irqreturn_t ret;
2117
2118 spin_lock_irqsave(esp->host->host_lock, flags);
2119 ret = IRQ_NONE;
2120 if (esp->ops->irq_pending(esp)) {
2121 ret = IRQ_HANDLED;
2122 for (;;) {
2123 int i;
2124
2125 __esp_interrupt(esp);
2126 if (!(esp->flags & ESP_FLAG_QUICKIRQ_CHECK))
2127 break;
2128 esp->flags &= ~ESP_FLAG_QUICKIRQ_CHECK;
2129
2130 for (i = 0; i < ESP_QUICKIRQ_LIMIT; i++) {
2131 if (esp->ops->irq_pending(esp))
2132 break;
2133 }
2134 if (i == ESP_QUICKIRQ_LIMIT)
2135 break;
2136 }
2137 }
2138 spin_unlock_irqrestore(esp->host->host_lock, flags);
2139
2140 return ret;
2141}
2142EXPORT_SYMBOL(scsi_esp_intr);
2143
2144static void __devinit esp_get_revision(struct esp *esp)
2145{
2146 u8 val;
2147
2148 esp->config1 = (ESP_CONFIG1_PENABLE | (esp->scsi_id & 7));
2149 esp->config2 = (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY);
2150 esp_write8(esp->config2, ESP_CFG2);
2151
2152 val = esp_read8(ESP_CFG2);
2153 val &= ~ESP_CONFIG2_MAGIC;
2154 if (val != (ESP_CONFIG2_SCSI2ENAB | ESP_CONFIG2_REGPARITY)) {
2155 /* If what we write to cfg2 does not come back, cfg2 is not
2156 * implemented, therefore this must be a plain esp100.
2157 */
2158 esp->rev = ESP100;
2159 } else {
2160 esp->config2 = 0;
2161 esp_set_all_config3(esp, 5);
2162 esp->prev_cfg3 = 5;
2163 esp_write8(esp->config2, ESP_CFG2);
2164 esp_write8(0, ESP_CFG3);
2165 esp_write8(esp->prev_cfg3, ESP_CFG3);
2166
2167 val = esp_read8(ESP_CFG3);
2168 if (val != 5) {
2169 /* The cfg2 register is implemented, however
2170 * cfg3 is not, must be esp100a.
2171 */
2172 esp->rev = ESP100A;
2173 } else {
2174 esp_set_all_config3(esp, 0);
2175 esp->prev_cfg3 = 0;
2176 esp_write8(esp->prev_cfg3, ESP_CFG3);
2177
2178 /* All of cfg{1,2,3} implemented, must be one of
2179 * the fas variants, figure out which one.
2180 */
2181 if (esp->cfact == 0 || esp->cfact > ESP_CCF_F5) {
2182 esp->rev = FAST;
2183 esp->sync_defp = SYNC_DEFP_FAST;
2184 } else {
2185 esp->rev = ESP236;
2186 }
2187 esp->config2 = 0;
2188 esp_write8(esp->config2, ESP_CFG2);
2189 }
2190 }
2191}
2192
2193static void __devinit esp_init_swstate(struct esp *esp)
2194{
2195 int i;
2196
2197 INIT_LIST_HEAD(&esp->queued_cmds);
2198 INIT_LIST_HEAD(&esp->active_cmds);
2199 INIT_LIST_HEAD(&esp->esp_cmd_pool);
2200
2201 /* Start with a clear state, domain validation (via ->slave_configure,
2202 * spi_dv_device()) will attempt to enable SYNC, WIDE, and tagged
2203 * commands.
2204 */
2205 for (i = 0 ; i < ESP_MAX_TARGET; i++) {
2206 esp->target[i].flags = 0;
2207 esp->target[i].nego_goal_period = 0;
2208 esp->target[i].nego_goal_offset = 0;
2209 esp->target[i].nego_goal_width = 0;
2210 esp->target[i].nego_goal_tags = 0;
2211 }
2212}
2213
2214/* This places the ESP into a known state at boot time. */
2215static void __devinit esp_bootup_reset(struct esp *esp)
2216{
2217 u8 val;
2218
2219 /* Reset the DMA */
2220 esp->ops->reset_dma(esp);
2221
2222 /* Reset the ESP */
2223 esp_reset_esp(esp);
2224
2225 /* Reset the SCSI bus, but tell ESP not to generate an irq */
2226 val = esp_read8(ESP_CFG1);
2227 val |= ESP_CONFIG1_SRRDISAB;
2228 esp_write8(val, ESP_CFG1);
2229
2230 scsi_esp_cmd(esp, ESP_CMD_RS);
2231 udelay(400);
2232
2233 esp_write8(esp->config1, ESP_CFG1);
2234
2235 /* Eat any bitrot in the chip and we are done... */
2236 esp_read8(ESP_INTRPT);
2237}
2238
2239static void __devinit esp_set_clock_params(struct esp *esp)
2240{
2241 int fmhz;
2242 u8 ccf;
2243
2244 /* This is getting messy but it has to be done correctly or else
2245 * you get weird behavior all over the place. We are trying to
2246 * basically figure out three pieces of information.
2247 *
2248 * a) Clock Conversion Factor
2249 *
2250 * This is a representation of the input crystal clock frequency
2251 * going into the ESP on this machine. Any operation whose timing
2252 * is longer than 400ns depends on this value being correct. For
2253 * example, you'll get blips for arbitration/selection during high
2254 * load or with multiple targets if this is not set correctly.
2255 *
2256 * b) Selection Time-Out
2257 *
2258 * The ESP isn't very bright and will arbitrate for the bus and try
2259 * to select a target forever if you let it. This value tells the
2260 * ESP when it has taken too long to negotiate and that it should
2261 * interrupt the CPU so we can see what happened. The value is
2262 * computed as follows (from NCR/Symbios chip docs).
2263 *
2264 * (Time Out Period) * (Input Clock)
2265 * STO = ----------------------------------
2266 * (8192) * (Clock Conversion Factor)
2267 *
2268 * We use a time out period of 250ms (ESP_BUS_TIMEOUT).
2269 *
2270 * c) Imperical constants for synchronous offset and transfer period
2271 * register values
2272 *
2273 * This entails the smallest and largest sync period we could ever
2274 * handle on this ESP.
2275 */
2276 fmhz = esp->cfreq;
2277
2278 ccf = ((fmhz / 1000000) + 4) / 5;
2279 if (ccf == 1)
2280 ccf = 2;
2281
2282 /* If we can't find anything reasonable, just assume 20MHZ.
2283 * This is the clock frequency of the older sun4c's where I've
2284 * been unable to find the clock-frequency PROM property. All
2285 * other machines provide useful values it seems.
2286 */
2287 if (fmhz <= 5000000 || ccf < 1 || ccf > 8) {
2288 fmhz = 20000000;
2289 ccf = 4;
2290 }
2291
2292 esp->cfact = (ccf == 8 ? 0 : ccf);
2293 esp->cfreq = fmhz;
2294 esp->ccycle = ESP_MHZ_TO_CYCLE(fmhz);
2295 esp->ctick = ESP_TICK(ccf, esp->ccycle);
2296 esp->neg_defp = ESP_NEG_DEFP(fmhz, ccf);
2297 esp->sync_defp = SYNC_DEFP_SLOW;
2298}
2299
2300static const char *esp_chip_names[] = {
2301 "ESP100",
2302 "ESP100A",
2303 "ESP236",
2304 "FAS236",
2305 "FAS100A",
2306 "FAST",
2307 "FASHME",
2308};
2309
2310static struct scsi_transport_template *esp_transport_template;
2311
2312int __devinit scsi_esp_register(struct esp *esp, struct device *dev)
2313{
2314 static int instance;
2315 int err;
2316
2317 esp->host->transportt = esp_transport_template;
2318 esp->host->max_lun = ESP_MAX_LUN;
2319 esp->host->cmd_per_lun = 2;
2320
2321 esp_set_clock_params(esp);
2322
2323 esp_get_revision(esp);
2324
2325 esp_init_swstate(esp);
2326
2327 esp_bootup_reset(esp);
2328
2329 printk(KERN_INFO PFX "esp%u, regs[%1p:%1p] irq[%u]\n",
2330 esp->host->unique_id, esp->regs, esp->dma_regs,
2331 esp->host->irq);
2332 printk(KERN_INFO PFX "esp%u is a %s, %u MHz (ccf=%u), SCSI ID %u\n",
2333 esp->host->unique_id, esp_chip_names[esp->rev],
2334 esp->cfreq / 1000000, esp->cfact, esp->scsi_id);
2335
2336 /* Let the SCSI bus reset settle. */
2337 ssleep(esp_bus_reset_settle);
2338
2339 err = scsi_add_host(esp->host, dev);
2340 if (err)
2341 return err;
2342
2343 esp->host->unique_id = instance++;
2344
2345 scsi_scan_host(esp->host);
2346
2347 return 0;
2348}
2349EXPORT_SYMBOL(scsi_esp_register);
2350
2351void __devexit scsi_esp_unregister(struct esp *esp)
2352{
2353 scsi_remove_host(esp->host);
2354}
2355EXPORT_SYMBOL(scsi_esp_unregister);
2356
2357static int esp_slave_alloc(struct scsi_device *dev)
2358{
2359 struct esp *esp = host_to_esp(dev->host);
2360 struct esp_target_data *tp = &esp->target[dev->id];
2361 struct esp_lun_data *lp;
2362
2363 lp = kzalloc(sizeof(*lp), GFP_KERNEL);
2364 if (!lp)
2365 return -ENOMEM;
2366 dev->hostdata = lp;
2367
2368 tp->starget = dev->sdev_target;
2369
2370 spi_min_period(tp->starget) = esp->min_period;
2371 spi_max_offset(tp->starget) = 15;
2372
2373 if (esp->flags & ESP_FLAG_WIDE_CAPABLE)
2374 spi_max_width(tp->starget) = 1;
2375 else
2376 spi_max_width(tp->starget) = 0;
2377
2378 return 0;
2379}
2380
2381static int esp_slave_configure(struct scsi_device *dev)
2382{
2383 struct esp *esp = host_to_esp(dev->host);
2384 struct esp_target_data *tp = &esp->target[dev->id];
2385 int goal_tags, queue_depth;
2386
2387 goal_tags = 0;
2388
2389 if (dev->tagged_supported) {
2390 /* XXX make this configurable somehow XXX */
2391 goal_tags = ESP_DEFAULT_TAGS;
2392
2393 if (goal_tags > ESP_MAX_TAG)
2394 goal_tags = ESP_MAX_TAG;
2395 }
2396
2397 queue_depth = goal_tags;
2398 if (queue_depth < dev->host->cmd_per_lun)
2399 queue_depth = dev->host->cmd_per_lun;
2400
2401 if (goal_tags) {
2402 scsi_set_tag_type(dev, MSG_ORDERED_TAG);
2403 scsi_activate_tcq(dev, queue_depth);
2404 } else {
2405 scsi_deactivate_tcq(dev, queue_depth);
2406 }
2407 tp->flags |= ESP_TGT_DISCONNECT;
2408
2409 if (!spi_initial_dv(dev->sdev_target))
2410 spi_dv_device(dev);
2411
2412 return 0;
2413}
2414
2415static void esp_slave_destroy(struct scsi_device *dev)
2416{
2417 struct esp_lun_data *lp = dev->hostdata;
2418
2419 kfree(lp);
2420 dev->hostdata = NULL;
2421}
2422
2423static int esp_eh_abort_handler(struct scsi_cmnd *cmd)
2424{
2425 struct esp *esp = host_to_esp(cmd->device->host);
2426 struct esp_cmd_entry *ent, *tmp;
2427 struct completion eh_done;
2428 unsigned long flags;
2429
2430 /* XXX This helps a lot with debugging but might be a bit
2431 * XXX much for the final driver.
2432 */
2433 spin_lock_irqsave(esp->host->host_lock, flags);
2434 printk(KERN_ERR PFX "esp%d: Aborting command [%p:%02x]\n",
2435 esp->host->unique_id, cmd, cmd->cmnd[0]);
2436 ent = esp->active_cmd;
2437 if (ent)
2438 printk(KERN_ERR PFX "esp%d: Current command [%p:%02x]\n",
2439 esp->host->unique_id, ent->cmd, ent->cmd->cmnd[0]);
2440 list_for_each_entry(ent, &esp->queued_cmds, list) {
2441 printk(KERN_ERR PFX "esp%d: Queued command [%p:%02x]\n",
2442 esp->host->unique_id, ent->cmd, ent->cmd->cmnd[0]);
2443 }
2444 list_for_each_entry(ent, &esp->active_cmds, list) {
2445 printk(KERN_ERR PFX "esp%d: Active command [%p:%02x]\n",
2446 esp->host->unique_id, ent->cmd, ent->cmd->cmnd[0]);
2447 }
2448 esp_dump_cmd_log(esp);
2449 spin_unlock_irqrestore(esp->host->host_lock, flags);
2450
2451 spin_lock_irqsave(esp->host->host_lock, flags);
2452
2453 ent = NULL;
2454 list_for_each_entry(tmp, &esp->queued_cmds, list) {
2455 if (tmp->cmd == cmd) {
2456 ent = tmp;
2457 break;
2458 }
2459 }
2460
2461 if (ent) {
2462 /* Easiest case, we didn't even issue the command
2463 * yet so it is trivial to abort.
2464 */
2465 list_del(&ent->list);
2466
2467 cmd->result = DID_ABORT << 16;
2468 cmd->scsi_done(cmd);
2469
2470 esp_put_ent(esp, ent);
2471
2472 goto out_success;
2473 }
2474
2475 init_completion(&eh_done);
2476
2477 ent = esp->active_cmd;
2478 if (ent && ent->cmd == cmd) {
2479 /* Command is the currently active command on
2480 * the bus. If we already have an output message
2481 * pending, no dice.
2482 */
2483 if (esp->msg_out_len)
2484 goto out_failure;
2485
2486 /* Send out an abort, encouraging the target to
2487 * go to MSGOUT phase by asserting ATN.
2488 */
2489 esp->msg_out[0] = ABORT_TASK_SET;
2490 esp->msg_out_len = 1;
2491 ent->eh_done = &eh_done;
2492
2493 scsi_esp_cmd(esp, ESP_CMD_SATN);
2494 } else {
2495 /* The command is disconnected. This is not easy to
2496 * abort. For now we fail and let the scsi error
2497 * handling layer go try a scsi bus reset or host
2498 * reset.
2499 *
2500 * What we could do is put together a scsi command
2501 * solely for the purpose of sending an abort message
2502 * to the target. Coming up with all the code to
2503 * cook up scsi commands, special case them everywhere,
2504 * etc. is for questionable gain and it would be better
2505 * if the generic scsi error handling layer could do at
2506 * least some of that for us.
2507 *
2508 * Anyways this is an area for potential future improvement
2509 * in this driver.
2510 */
2511 goto out_failure;
2512 }
2513
2514 spin_unlock_irqrestore(esp->host->host_lock, flags);
2515
2516 if (!wait_for_completion_timeout(&eh_done, 5 * HZ)) {
2517 spin_lock_irqsave(esp->host->host_lock, flags);
2518 ent->eh_done = NULL;
2519 spin_unlock_irqrestore(esp->host->host_lock, flags);
2520
2521 return FAILED;
2522 }
2523
2524 return SUCCESS;
2525
2526out_success:
2527 spin_unlock_irqrestore(esp->host->host_lock, flags);
2528 return SUCCESS;
2529
2530out_failure:
2531 /* XXX This might be a good location to set ESP_TGT_BROKEN
2532 * XXX since we know which target/lun in particular is
2533 * XXX causing trouble.
2534 */
2535 spin_unlock_irqrestore(esp->host->host_lock, flags);
2536 return FAILED;
2537}
2538
2539static int esp_eh_bus_reset_handler(struct scsi_cmnd *cmd)
2540{
2541 struct esp *esp = host_to_esp(cmd->device->host);
2542 struct completion eh_reset;
2543 unsigned long flags;
2544
2545 init_completion(&eh_reset);
2546
2547 spin_lock_irqsave(esp->host->host_lock, flags);
2548
2549 esp->eh_reset = &eh_reset;
2550
2551 /* XXX This is too simple... We should add lots of
2552 * XXX checks here so that if we find that the chip is
2553 * XXX very wedged we return failure immediately so
2554 * XXX that we can perform a full chip reset.
2555 */
2556 esp->flags |= ESP_FLAG_RESETTING;
2557 scsi_esp_cmd(esp, ESP_CMD_RS);
2558
2559 spin_unlock_irqrestore(esp->host->host_lock, flags);
2560
2561 ssleep(esp_bus_reset_settle);
2562
2563 if (!wait_for_completion_timeout(&eh_reset, 5 * HZ)) {
2564 spin_lock_irqsave(esp->host->host_lock, flags);
2565 esp->eh_reset = NULL;
2566 spin_unlock_irqrestore(esp->host->host_lock, flags);
2567
2568 return FAILED;
2569 }
2570
2571 return SUCCESS;
2572}
2573
2574/* All bets are off, reset the entire device. */
2575static int esp_eh_host_reset_handler(struct scsi_cmnd *cmd)
2576{
2577 struct esp *esp = host_to_esp(cmd->device->host);
2578 unsigned long flags;
2579
2580 spin_lock_irqsave(esp->host->host_lock, flags);
2581 esp_bootup_reset(esp);
2582 esp_reset_cleanup(esp);
2583 spin_unlock_irqrestore(esp->host->host_lock, flags);
2584
2585 ssleep(esp_bus_reset_settle);
2586
2587 return SUCCESS;
2588}
2589
2590static const char *esp_info(struct Scsi_Host *host)
2591{
2592 return "esp";
2593}
2594
2595struct scsi_host_template scsi_esp_template = {
2596 .module = THIS_MODULE,
2597 .name = "esp",
2598 .info = esp_info,
2599 .queuecommand = esp_queuecommand,
2600 .slave_alloc = esp_slave_alloc,
2601 .slave_configure = esp_slave_configure,
2602 .slave_destroy = esp_slave_destroy,
2603 .eh_abort_handler = esp_eh_abort_handler,
2604 .eh_bus_reset_handler = esp_eh_bus_reset_handler,
2605 .eh_host_reset_handler = esp_eh_host_reset_handler,
2606 .can_queue = 7,
2607 .this_id = 7,
2608 .sg_tablesize = SG_ALL,
2609 .use_clustering = ENABLE_CLUSTERING,
2610 .max_sectors = 0xffff,
2611 .skip_settle_delay = 1,
2612};
2613EXPORT_SYMBOL(scsi_esp_template);
2614
2615static void esp_get_signalling(struct Scsi_Host *host)
2616{
2617 struct esp *esp = host_to_esp(host);
2618 enum spi_signal_type type;
2619
2620 if (esp->flags & ESP_FLAG_DIFFERENTIAL)
2621 type = SPI_SIGNAL_HVD;
2622 else
2623 type = SPI_SIGNAL_SE;
2624
2625 spi_signalling(host) = type;
2626}
2627
2628static void esp_set_offset(struct scsi_target *target, int offset)
2629{
2630 struct Scsi_Host *host = dev_to_shost(target->dev.parent);
2631 struct esp *esp = host_to_esp(host);
2632 struct esp_target_data *tp = &esp->target[target->id];
2633
2634 tp->nego_goal_offset = offset;
2635 tp->flags |= ESP_TGT_CHECK_NEGO;
2636}
2637
2638static void esp_set_period(struct scsi_target *target, int period)
2639{
2640 struct Scsi_Host *host = dev_to_shost(target->dev.parent);
2641 struct esp *esp = host_to_esp(host);
2642 struct esp_target_data *tp = &esp->target[target->id];
2643
2644 tp->nego_goal_period = period;
2645 tp->flags |= ESP_TGT_CHECK_NEGO;
2646}
2647
2648static void esp_set_width(struct scsi_target *target, int width)
2649{
2650 struct Scsi_Host *host = dev_to_shost(target->dev.parent);
2651 struct esp *esp = host_to_esp(host);
2652 struct esp_target_data *tp = &esp->target[target->id];
2653
2654 tp->nego_goal_width = (width ? 1 : 0);
2655 tp->flags |= ESP_TGT_CHECK_NEGO;
2656}
2657
2658static struct spi_function_template esp_transport_ops = {
2659 .set_offset = esp_set_offset,
2660 .show_offset = 1,
2661 .set_period = esp_set_period,
2662 .show_period = 1,
2663 .set_width = esp_set_width,
2664 .show_width = 1,
2665 .get_signalling = esp_get_signalling,
2666};
2667
2668static int __init esp_init(void)
2669{
2670 BUILD_BUG_ON(sizeof(struct scsi_pointer) <
2671 sizeof(struct esp_cmd_priv));
2672
2673 esp_transport_template = spi_attach_transport(&esp_transport_ops);
2674 if (!esp_transport_template)
2675 return -ENODEV;
2676
2677 return 0;
2678}
2679
2680static void __exit esp_exit(void)
2681{
2682 spi_release_transport(esp_transport_template);
2683}
2684
2685MODULE_DESCRIPTION("ESP SCSI driver core");
2686MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
2687MODULE_LICENSE("GPL");
2688MODULE_VERSION(DRV_VERSION);
2689
2690module_param(esp_bus_reset_settle, int, 0);
2691MODULE_PARM_DESC(esp_bus_reset_settle,
2692 "ESP scsi bus reset delay in seconds");
2693
2694module_param(esp_debug, int, 0);
2695MODULE_PARM_DESC(esp_debug,
2696"ESP bitmapped debugging message enable value:\n"
2697" 0x00000001 Log interrupt events\n"
2698" 0x00000002 Log scsi commands\n"
2699" 0x00000004 Log resets\n"
2700" 0x00000008 Log message in events\n"
2701" 0x00000010 Log message out events\n"
2702" 0x00000020 Log command completion\n"
2703" 0x00000040 Log disconnects\n"
2704" 0x00000080 Log data start\n"
2705" 0x00000100 Log data done\n"
2706" 0x00000200 Log reconnects\n"
2707" 0x00000400 Log auto-sense data\n"
2708);
2709
2710module_init(esp_init);
2711module_exit(esp_exit);
diff --git a/drivers/scsi/esp_scsi.h b/drivers/scsi/esp_scsi.h
new file mode 100644
index 000000000000..8d4a6690401f
--- /dev/null
+++ b/drivers/scsi/esp_scsi.h
@@ -0,0 +1,560 @@
1/* esp_scsi.h: Defines and structures for the ESP drier.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _ESP_SCSI_H
7#define _ESP_SCSI_H
8
9 /* Access Description Offset */
10#define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
11#define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
12#define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */
13#define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */
14#define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */
15#define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */
16#define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */
17#define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */
18#define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */
19#define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */
20#define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */
21#define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
22#define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */
23#define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */
24#define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
25#define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */
26#define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */
27#define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */
28#define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */
29#define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
30#define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
31#define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */
32#define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
33
34#define SBUS_ESP_REG_SIZE 0x40UL
35
36/* Bitfield meanings for the above registers. */
37
38/* ESP config reg 1, read-write, found on all ESP chips */
39#define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
40#define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
41#define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
42#define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
43#define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
44#define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
45
46/* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
47#define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
48#define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
49#define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
50#define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
51#define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
52#define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
53#define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
54#define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
55#define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */
56#define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
57#define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
58#define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
59#define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
60
61/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
62#define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
63#define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
64#define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
65#define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
66#define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
67#define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
68#define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
69#define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
70#define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
71#define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
72#define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
73#define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
74#define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
75#define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
76#define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
77#define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
78
79/* ESP command register read-write */
80/* Group 1 commands: These may be sent at any point in time to the ESP
81 * chip. None of them can generate interrupts 'cept
82 * the "SCSI bus reset" command if you have not disabled
83 * SCSI reset interrupts in the config1 ESP register.
84 */
85#define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
86#define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
87#define ESP_CMD_RC 0x02 /* Chip reset */
88#define ESP_CMD_RS 0x03 /* SCSI bus reset */
89
90/* Group 2 commands: ESP must be an initiator and connected to a target
91 * for these commands to work.
92 */
93#define ESP_CMD_TI 0x10 /* Transfer Information */
94#define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
95#define ESP_CMD_MOK 0x12 /* Message okie-dokie */
96#define ESP_CMD_TPAD 0x18 /* Transfer Pad */
97#define ESP_CMD_SATN 0x1a /* Set ATN */
98#define ESP_CMD_RATN 0x1b /* De-assert ATN */
99
100/* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
101 * to a target as the initiator for these commands to work.
102 */
103#define ESP_CMD_SMSG 0x20 /* Send message */
104#define ESP_CMD_SSTAT 0x21 /* Send status */
105#define ESP_CMD_SDATA 0x22 /* Send data */
106#define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
107#define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
108#define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
109#define ESP_CMD_DCNCT 0x27 /* Disconnect */
110#define ESP_CMD_RMSG 0x28 /* Receive Message */
111#define ESP_CMD_RCMD 0x29 /* Receive Command */
112#define ESP_CMD_RDATA 0x2a /* Receive Data */
113#define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
114
115/* Group 4 commands: The ESP must be in the disconnected state and must
116 * not be connected to any targets as initiator for
117 * these commands to work.
118 */
119#define ESP_CMD_RSEL 0x40 /* Reselect */
120#define ESP_CMD_SEL 0x41 /* Select w/o ATN */
121#define ESP_CMD_SELA 0x42 /* Select w/ATN */
122#define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
123#define ESP_CMD_ESEL 0x44 /* Enable selection */
124#define ESP_CMD_DSEL 0x45 /* Disable selections */
125#define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
126#define ESP_CMD_RSEL3 0x47 /* Reselect3 */
127
128/* This bit enables the ESP's DMA on the SBus */
129#define ESP_CMD_DMA 0x80 /* Do DMA? */
130
131/* ESP status register read-only */
132#define ESP_STAT_PIO 0x01 /* IO phase bit */
133#define ESP_STAT_PCD 0x02 /* CD phase bit */
134#define ESP_STAT_PMSG 0x04 /* MSG phase bit */
135#define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
136#define ESP_STAT_TDONE 0x08 /* Transfer Completed */
137#define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
138#define ESP_STAT_PERR 0x20 /* Parity error */
139#define ESP_STAT_SPAM 0x40 /* Real bad error */
140/* This indicates the 'interrupt pending' condition on esp236, it is a reserved
141 * bit on other revs of the ESP.
142 */
143#define ESP_STAT_INTR 0x80 /* Interrupt */
144
145/* The status register can be masked with ESP_STAT_PMASK and compared
146 * with the following values to determine the current phase the ESP
147 * (at least thinks it) is in. For our purposes we also add our own
148 * software 'done' bit for our phase management engine.
149 */
150#define ESP_DOP (0) /* Data Out */
151#define ESP_DIP (ESP_STAT_PIO) /* Data In */
152#define ESP_CMDP (ESP_STAT_PCD) /* Command */
153#define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
154#define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
155#define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
156
157/* HME only: status 2 register */
158#define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
159#define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
160#define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
161#define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
162#define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
163#define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
164#define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
165#define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
166
167/* ESP interrupt register read-only */
168#define ESP_INTR_S 0x01 /* Select w/o ATN */
169#define ESP_INTR_SATN 0x02 /* Select w/ATN */
170#define ESP_INTR_RSEL 0x04 /* Reselected */
171#define ESP_INTR_FDONE 0x08 /* Function done */
172#define ESP_INTR_BSERV 0x10 /* Bus service */
173#define ESP_INTR_DC 0x20 /* Disconnect */
174#define ESP_INTR_IC 0x40 /* Illegal command given */
175#define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
176
177/* ESP sequence step register read-only */
178#define ESP_STEP_VBITS 0x07 /* Valid bits */
179#define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
180#define ESP_STEP_SID 0x01 /* One msg byte sent */
181#define ESP_STEP_NCMD 0x02 /* Was not in command phase */
182#define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
183 * bytes to be lost
184 */
185#define ESP_STEP_FINI4 0x04 /* Command was sent ok */
186
187/* Ho hum, some ESP's set the step register to this as well... */
188#define ESP_STEP_FINI5 0x05
189#define ESP_STEP_FINI6 0x06
190#define ESP_STEP_FINI7 0x07
191
192/* ESP chip-test register read-write */
193#define ESP_TEST_TARG 0x01 /* Target test mode */
194#define ESP_TEST_INI 0x02 /* Initiator test mode */
195#define ESP_TEST_TS 0x04 /* Tristate test mode */
196
197/* ESP unique ID register read-only, found on fas236+fas100a only */
198#define ESP_UID_F100A 0x00 /* ESP FAS100A */
199#define ESP_UID_F236 0x02 /* ESP FAS236 */
200#define ESP_UID_REV 0x07 /* ESP revision */
201#define ESP_UID_FAM 0xf8 /* ESP family */
202
203/* ESP fifo flags register read-only */
204/* Note that the following implies a 16 byte FIFO on the ESP. */
205#define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
206#define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
207#define ESP_FF_SSTEP 0xe0 /* Sequence step */
208
209/* ESP clock conversion factor register write-only */
210#define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
211#define ESP_CCF_NEVER 0x01 /* Set it to this and die */
212#define ESP_CCF_F2 0x02 /* 10MHz */
213#define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
214#define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
215#define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
216#define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
217#define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
218
219/* HME only... */
220#define ESP_BUSID_RESELID 0x10
221#define ESP_BUSID_CTR32BIT 0x40
222
223#define ESP_BUS_TIMEOUT 250 /* In milli-seconds */
224#define ESP_TIMEO_CONST 8192
225#define ESP_NEG_DEFP(mhz, cfact) \
226 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
227#define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
228#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
229
230/* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
231 * input clock rates we try to do 10mb/s although I don't think a transfer can
232 * even run that fast with an ESP even with DMA2 scatter gather pipelining.
233 */
234#define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
235#define SYNC_DEFP_FAST 0x19 /* 10mb/s */
236
237struct esp_cmd_priv {
238 union {
239 dma_addr_t dma_addr;
240 int num_sg;
241 } u;
242
243 unsigned int cur_residue;
244 struct scatterlist *cur_sg;
245 unsigned int tot_residue;
246};
247#define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp))
248
249enum esp_rev {
250 ESP100 = 0x00, /* NCR53C90 - very broken */
251 ESP100A = 0x01, /* NCR53C90A */
252 ESP236 = 0x02,
253 FAS236 = 0x03,
254 FAS100A = 0x04,
255 FAST = 0x05,
256 FASHME = 0x06,
257};
258
259struct esp_cmd_entry {
260 struct list_head list;
261
262 struct scsi_cmnd *cmd;
263
264 unsigned int saved_cur_residue;
265 struct scatterlist *saved_cur_sg;
266 unsigned int saved_tot_residue;
267
268 u8 flags;
269#define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */
270#define ESP_CMD_FLAG_ABORT 0x02 /* being aborted */
271#define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */
272
273 u8 tag[2];
274
275 u8 status;
276 u8 message;
277
278 unsigned char *sense_ptr;
279 unsigned char *saved_sense_ptr;
280 dma_addr_t sense_dma;
281
282 struct completion *eh_done;
283};
284
285/* XXX make this configurable somehow XXX */
286#define ESP_DEFAULT_TAGS 16
287
288#define ESP_MAX_TARGET 16
289#define ESP_MAX_LUN 8
290#define ESP_MAX_TAG 256
291
292struct esp_lun_data {
293 struct esp_cmd_entry *non_tagged_cmd;
294 int num_tagged;
295 int hold;
296 struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG];
297};
298
299struct esp_target_data {
300 /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which
301 * match the currently negotiated settings for this target. The SCSI
302 * protocol values are maintained in spi_{offset,period,wide}(starget).
303 */
304 u8 esp_period;
305 u8 esp_offset;
306 u8 esp_config3;
307
308 u8 flags;
309#define ESP_TGT_WIDE 0x01
310#define ESP_TGT_DISCONNECT 0x02
311#define ESP_TGT_NEGO_WIDE 0x04
312#define ESP_TGT_NEGO_SYNC 0x08
313#define ESP_TGT_CHECK_NEGO 0x40
314#define ESP_TGT_BROKEN 0x80
315
316 /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this
317 * device we will try to negotiate the following parameters.
318 */
319 u8 nego_goal_period;
320 u8 nego_goal_offset;
321 u8 nego_goal_width;
322 u8 nego_goal_tags;
323
324 struct scsi_target *starget;
325};
326
327struct esp_event_ent {
328 u8 type;
329#define ESP_EVENT_TYPE_EVENT 0x01
330#define ESP_EVENT_TYPE_CMD 0x02
331 u8 val;
332
333 u8 sreg;
334 u8 seqreg;
335 u8 sreg2;
336 u8 ireg;
337 u8 select_state;
338 u8 event;
339 u8 __pad;
340};
341
342struct esp;
343struct esp_driver_ops {
344 /* Read and write the ESP 8-bit registers. On some
345 * applications of the ESP chip the registers are at 4-byte
346 * instead of 1-byte intervals.
347 */
348 void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg);
349 u8 (*esp_read8)(struct esp *esp, unsigned long reg);
350
351 /* Map and unmap DMA memory. Eventually the driver will be
352 * converted to the generic DMA API as soon as SBUS is able to
353 * cope with that. At such time we can remove this.
354 */
355 dma_addr_t (*map_single)(struct esp *esp, void *buf,
356 size_t sz, int dir);
357 int (*map_sg)(struct esp *esp, struct scatterlist *sg,
358 int num_sg, int dir);
359 void (*unmap_single)(struct esp *esp, dma_addr_t addr,
360 size_t sz, int dir);
361 void (*unmap_sg)(struct esp *esp, struct scatterlist *sg,
362 int num_sg, int dir);
363
364 /* Return non-zero if there is an IRQ pending. Usually this
365 * status bit lives in the DMA controller sitting in front of
366 * the ESP. This has to be accurate or else the ESP interrupt
367 * handler will not run.
368 */
369 int (*irq_pending)(struct esp *esp);
370
371 /* Reset the DMA engine entirely. On return, ESP interrupts
372 * should be enabled. Often the interrupt enabling is
373 * controlled in the DMA engine.
374 */
375 void (*reset_dma)(struct esp *esp);
376
377 /* Drain any pending DMA in the DMA engine after a transfer.
378 * This is for writes to memory.
379 */
380 void (*dma_drain)(struct esp *esp);
381
382 /* Invalidate the DMA engine after a DMA transfer. */
383 void (*dma_invalidate)(struct esp *esp);
384
385 /* Setup an ESP command that will use a DMA transfer.
386 * The 'esp_count' specifies what transfer length should be
387 * programmed into the ESP transfer counter registers, whereas
388 * the 'dma_count' is the length that should be programmed into
389 * the DMA controller. Usually they are the same. If 'write'
390 * is non-zero, this transfer is a write into memory. 'cmd'
391 * holds the ESP command that should be issued by calling
392 * scsi_esp_cmd() at the appropriate time while programming
393 * the DMA hardware.
394 */
395 void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count,
396 u32 dma_count, int write, u8 cmd);
397
398 /* Return non-zero if the DMA engine is reporting an error
399 * currently.
400 */
401 int (*dma_error)(struct esp *esp);
402};
403
404#define ESP_MAX_MSG_SZ 8
405#define ESP_EVENT_LOG_SZ 32
406
407#define ESP_QUICKIRQ_LIMIT 100
408#define ESP_RESELECT_TAG_LIMIT 2500
409
410struct esp {
411 void __iomem *regs;
412 void __iomem *dma_regs;
413
414 const struct esp_driver_ops *ops;
415
416 struct Scsi_Host *host;
417 void *dev;
418
419 struct esp_cmd_entry *active_cmd;
420
421 struct list_head queued_cmds;
422 struct list_head active_cmds;
423
424 u8 *command_block;
425 dma_addr_t command_block_dma;
426
427 unsigned int data_dma_len;
428
429 /* The following are used to determine the cause of an IRQ. Upon every
430 * IRQ entry we synchronize these with the hardware registers.
431 */
432 u8 sreg;
433 u8 seqreg;
434 u8 sreg2;
435 u8 ireg;
436
437 u32 prev_hme_dmacsr;
438 u8 prev_soff;
439 u8 prev_stp;
440 u8 prev_cfg3;
441 u8 __pad;
442
443 struct list_head esp_cmd_pool;
444
445 struct esp_target_data target[ESP_MAX_TARGET];
446
447 int fifo_cnt;
448 u8 fifo[16];
449
450 struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ];
451 int esp_event_cur;
452
453 u8 msg_out[ESP_MAX_MSG_SZ];
454 int msg_out_len;
455
456 u8 msg_in[ESP_MAX_MSG_SZ];
457 int msg_in_len;
458
459 u8 bursts;
460 u8 config1;
461 u8 config2;
462
463 u8 scsi_id;
464 u32 scsi_id_mask;
465
466 enum esp_rev rev;
467
468 u32 flags;
469#define ESP_FLAG_DIFFERENTIAL 0x00000001
470#define ESP_FLAG_RESETTING 0x00000002
471#define ESP_FLAG_DOING_SLOWCMD 0x00000004
472#define ESP_FLAG_WIDE_CAPABLE 0x00000008
473#define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
474
475 u8 select_state;
476#define ESP_SELECT_NONE 0x00 /* Not selecting */
477#define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */
478#define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */
479
480 /* When we are not selecting, we are expecting an event. */
481 u8 event;
482#define ESP_EVENT_NONE 0x00
483#define ESP_EVENT_CMD_START 0x01
484#define ESP_EVENT_CMD_DONE 0x02
485#define ESP_EVENT_DATA_IN 0x03
486#define ESP_EVENT_DATA_OUT 0x04
487#define ESP_EVENT_DATA_DONE 0x05
488#define ESP_EVENT_MSGIN 0x06
489#define ESP_EVENT_MSGIN_MORE 0x07
490#define ESP_EVENT_MSGIN_DONE 0x08
491#define ESP_EVENT_MSGOUT 0x09
492#define ESP_EVENT_MSGOUT_DONE 0x0a
493#define ESP_EVENT_STATUS 0x0b
494#define ESP_EVENT_FREE_BUS 0x0c
495#define ESP_EVENT_CHECK_PHASE 0x0d
496#define ESP_EVENT_RESET 0x10
497
498 /* Probed in esp_get_clock_params() */
499 u32 cfact;
500 u32 cfreq;
501 u32 ccycle;
502 u32 ctick;
503 u32 neg_defp;
504 u32 sync_defp;
505
506 /* Computed in esp_reset_esp() */
507 u32 max_period;
508 u32 min_period;
509 u32 radelay;
510
511 /* Slow command state. */
512 u8 *cmd_bytes_ptr;
513 int cmd_bytes_left;
514
515 struct completion *eh_reset;
516
517 struct sbus_dma *dma;
518};
519
520#define host_to_esp(host) ((struct esp *)(host)->hostdata)
521
522/* A front-end driver for the ESP chip should do the following in
523 * it's device probe routine:
524 * 1) Allocate the host and private area using scsi_host_alloc()
525 * with size 'sizeof(struct esp)'. The first argument to
526 * scsi_host_alloc() should be &scsi_esp_template.
527 * 2) Set host->max_id as appropriate.
528 * 3) Set esp->host to the scsi_host itself, and esp->dev
529 * to the device object pointer.
530 * 4) Hook up esp->ops to the front-end implementation.
531 * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE
532 * in esp->flags.
533 * 6) Map the DMA and ESP chip registers.
534 * 7) DMA map the ESP command block, store the DMA address
535 * in esp->command_block_dma.
536 * 8) Register the scsi_esp_intr() interrupt handler.
537 * 9) Probe for and provide the following chip properties:
538 * esp->scsi_id (assign to esp->host->this_id too)
539 * esp->scsi_id_mask
540 * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL
541 * esp->cfreq
542 * DMA burst bit mask in esp->bursts, if necessary
543 * 10) Perform any actions necessary before the ESP device can
544 * be programmed for the first time. On some configs, for
545 * example, the DMA engine has to be reset before ESP can
546 * be programmed.
547 * 11) If necessary, call dev_set_drvdata() as needed.
548 * 12) Call scsi_esp_register() with prepared 'esp' structure
549 * and a device pointer if possible.
550 * 13) Check scsi_esp_register() return value, release all resources
551 * if an error was returned.
552 */
553extern struct scsi_host_template scsi_esp_template;
554extern int scsi_esp_register(struct esp *, struct device *);
555
556extern void scsi_esp_unregister(struct esp *);
557extern irqreturn_t scsi_esp_intr(int, void *);
558extern void scsi_esp_cmd(struct esp *, u8);
559
560#endif /* !(_ESP_SCSI_H) */
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c
index 38c3a291efac..bd8e7f323c69 100644
--- a/drivers/scsi/hosts.c
+++ b/drivers/scsi/hosts.c
@@ -435,7 +435,7 @@ struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
435 struct class_device *cdev; 435 struct class_device *cdev;
436 struct Scsi_Host *shost = ERR_PTR(-ENXIO), *p; 436 struct Scsi_Host *shost = ERR_PTR(-ENXIO), *p;
437 437
438 down_read(&class->subsys.rwsem); 438 down(&class->sem);
439 list_for_each_entry(cdev, &class->children, node) { 439 list_for_each_entry(cdev, &class->children, node) {
440 p = class_to_shost(cdev); 440 p = class_to_shost(cdev);
441 if (p->host_no == hostnum) { 441 if (p->host_no == hostnum) {
@@ -443,7 +443,7 @@ struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
443 break; 443 break;
444 } 444 }
445 } 445 }
446 up_read(&class->subsys.rwsem); 446 up(&class->sem);
447 447
448 return shost; 448 return shost;
449} 449}
diff --git a/drivers/scsi/qlogicpti.c b/drivers/scsi/qlogicpti.c
index 9b827ceec501..c4195ea869e9 100644
--- a/drivers/scsi/qlogicpti.c
+++ b/drivers/scsi/qlogicpti.c
@@ -1281,7 +1281,7 @@ static struct scsi_cmnd *qlogicpti_intr_handler(struct qlogicpti *qpti)
1281 (struct scatterlist *)Cmnd->request_buffer, 1281 (struct scatterlist *)Cmnd->request_buffer,
1282 Cmnd->use_sg, 1282 Cmnd->use_sg,
1283 Cmnd->sc_data_direction); 1283 Cmnd->sc_data_direction);
1284 } else { 1284 } else if (Cmnd->request_bufflen) {
1285 sbus_unmap_single(qpti->sdev, 1285 sbus_unmap_single(qpti->sdev,
1286 (__u32)((unsigned long)Cmnd->SCp.ptr), 1286 (__u32)((unsigned long)Cmnd->SCp.ptr),
1287 Cmnd->request_bufflen, 1287 Cmnd->request_bufflen,
@@ -1403,7 +1403,7 @@ static int __devinit qpti_sbus_probe(struct of_device *dev, const struct of_devi
1403 struct scsi_host_template *tpnt = match->data; 1403 struct scsi_host_template *tpnt = match->data;
1404 struct Scsi_Host *host; 1404 struct Scsi_Host *host;
1405 struct qlogicpti *qpti; 1405 struct qlogicpti *qpti;
1406 char *fcode; 1406 const char *fcode;
1407 1407
1408 /* Sometimes Antares cards come up not completely 1408 /* Sometimes Antares cards come up not completely
1409 * setup, and we get a report of a zero IRQ. 1409 * setup, and we get a report of a zero IRQ.
diff --git a/drivers/scsi/scsi_netlink.c b/drivers/scsi/scsi_netlink.c
index 1b59b27e887f..4bf9aa547c78 100644
--- a/drivers/scsi/scsi_netlink.c
+++ b/drivers/scsi/scsi_netlink.c
@@ -50,7 +50,7 @@ scsi_nl_rcv_msg(struct sk_buff *skb)
50 while (skb->len >= NLMSG_SPACE(0)) { 50 while (skb->len >= NLMSG_SPACE(0)) {
51 err = 0; 51 err = 0;
52 52
53 nlh = (struct nlmsghdr *) skb->data; 53 nlh = nlmsg_hdr(skb);
54 if ((nlh->nlmsg_len < (sizeof(*nlh) + sizeof(*hdr))) || 54 if ((nlh->nlmsg_len < (sizeof(*nlh) + sizeof(*hdr))) ||
55 (skb->len < nlh->nlmsg_len)) { 55 (skb->len < nlh->nlmsg_len)) {
56 printk(KERN_WARNING "%s: discarding partial skb\n", 56 printk(KERN_WARNING "%s: discarding partial skb\n",
@@ -168,7 +168,8 @@ scsi_netlink_init(void)
168 } 168 }
169 169
170 scsi_nl_sock = netlink_kernel_create(NETLINK_SCSITRANSPORT, 170 scsi_nl_sock = netlink_kernel_create(NETLINK_SCSITRANSPORT,
171 SCSI_NL_GRP_CNT, scsi_nl_rcv, THIS_MODULE); 171 SCSI_NL_GRP_CNT, scsi_nl_rcv, NULL,
172 THIS_MODULE);
172 if (!scsi_nl_sock) { 173 if (!scsi_nl_sock) {
173 printk(KERN_ERR "%s: register of recieve handler failed\n", 174 printk(KERN_ERR "%s: register of recieve handler failed\n",
174 __FUNCTION__); 175 __FUNCTION__);
diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c
index ce0d14af33c8..aabaa0576ab4 100644
--- a/drivers/scsi/scsi_transport_iscsi.c
+++ b/drivers/scsi/scsi_transport_iscsi.c
@@ -1081,7 +1081,7 @@ iscsi_if_rx(struct sock *sk, int len)
1081 struct nlmsghdr *nlh; 1081 struct nlmsghdr *nlh;
1082 struct iscsi_uevent *ev; 1082 struct iscsi_uevent *ev;
1083 1083
1084 nlh = (struct nlmsghdr *)skb->data; 1084 nlh = nlmsg_hdr(skb);
1085 if (nlh->nlmsg_len < sizeof(*nlh) || 1085 if (nlh->nlmsg_len < sizeof(*nlh) ||
1086 skb->len < nlh->nlmsg_len) { 1086 skb->len < nlh->nlmsg_len) {
1087 break; 1087 break;
@@ -1435,7 +1435,7 @@ static __init int iscsi_transport_init(void)
1435 if (err) 1435 if (err)
1436 goto unregister_conn_class; 1436 goto unregister_conn_class;
1437 1437
1438 nls = netlink_kernel_create(NETLINK_ISCSI, 1, iscsi_if_rx, 1438 nls = netlink_kernel_create(NETLINK_ISCSI, 1, iscsi_if_rx, NULL,
1439 THIS_MODULE); 1439 THIS_MODULE);
1440 if (!nls) { 1440 if (!nls) {
1441 err = -ENOBUFS; 1441 err = -ENOBUFS;
diff --git a/drivers/scsi/sun_esp.c b/drivers/scsi/sun_esp.c
new file mode 100644
index 000000000000..8c766bcd1095
--- /dev/null
+++ b/drivers/scsi/sun_esp.c
@@ -0,0 +1,634 @@
1/* sun_esp.c: ESP front-end for Sparc SBUS systems.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/module.h>
9#include <linux/init.h>
10
11#include <asm/irq.h>
12#include <asm/io.h>
13#include <asm/dma.h>
14
15#include <asm/sbus.h>
16
17#include <scsi/scsi_host.h>
18
19#include "esp_scsi.h"
20
21#define DRV_MODULE_NAME "sun_esp"
22#define PFX DRV_MODULE_NAME ": "
23#define DRV_VERSION "1.000"
24#define DRV_MODULE_RELDATE "April 19, 2007"
25
26#define dma_read32(REG) \
27 sbus_readl(esp->dma_regs + (REG))
28#define dma_write32(VAL, REG) \
29 sbus_writel((VAL), esp->dma_regs + (REG))
30
31static int __devinit esp_sbus_find_dma(struct esp *esp, struct sbus_dev *dma_sdev)
32{
33 struct sbus_dev *sdev = esp->dev;
34 struct sbus_dma *dma;
35
36 if (dma_sdev != NULL) {
37 for_each_dvma(dma) {
38 if (dma->sdev == dma_sdev)
39 break;
40 }
41 } else {
42 for_each_dvma(dma) {
43 if (dma->sdev == NULL)
44 break;
45
46 /* If bus + slot are the same and it has the
47 * correct OBP name, it's ours.
48 */
49 if (sdev->bus == dma->sdev->bus &&
50 sdev->slot == dma->sdev->slot &&
51 (!strcmp(dma->sdev->prom_name, "dma") ||
52 !strcmp(dma->sdev->prom_name, "espdma")))
53 break;
54 }
55 }
56
57 if (dma == NULL) {
58 printk(KERN_ERR PFX "[%s] Cannot find dma.\n",
59 sdev->ofdev.node->full_name);
60 return -ENODEV;
61 }
62 esp->dma = dma;
63 esp->dma_regs = dma->regs;
64
65 return 0;
66
67}
68
69static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
70{
71 struct sbus_dev *sdev = esp->dev;
72 struct resource *res;
73
74 /* On HME, two reg sets exist, first is DVMA,
75 * second is ESP registers.
76 */
77 if (hme)
78 res = &sdev->resource[1];
79 else
80 res = &sdev->resource[0];
81
82 esp->regs = sbus_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
83 if (!esp->regs)
84 return -ENOMEM;
85
86 return 0;
87}
88
89static int __devinit esp_sbus_map_command_block(struct esp *esp)
90{
91 struct sbus_dev *sdev = esp->dev;
92
93 esp->command_block = sbus_alloc_consistent(sdev, 16,
94 &esp->command_block_dma);
95 if (!esp->command_block)
96 return -ENOMEM;
97 return 0;
98}
99
100static int __devinit esp_sbus_register_irq(struct esp *esp)
101{
102 struct Scsi_Host *host = esp->host;
103 struct sbus_dev *sdev = esp->dev;
104
105 host->irq = sdev->irqs[0];
106 return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
107}
108
109static void __devinit esp_get_scsi_id(struct esp *esp)
110{
111 struct sbus_dev *sdev = esp->dev;
112 struct device_node *dp = sdev->ofdev.node;
113
114 esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
115 if (esp->scsi_id != 0xff)
116 goto done;
117
118 esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
119 if (esp->scsi_id != 0xff)
120 goto done;
121
122 if (!sdev->bus) {
123 /* SUN4 */
124 esp->scsi_id = 7;
125 goto done;
126 }
127
128 esp->scsi_id = of_getintprop_default(sdev->bus->ofdev.node,
129 "scsi-initiator-id", 7);
130
131done:
132 esp->host->this_id = esp->scsi_id;
133 esp->scsi_id_mask = (1 << esp->scsi_id);
134}
135
136static void __devinit esp_get_differential(struct esp *esp)
137{
138 struct sbus_dev *sdev = esp->dev;
139 struct device_node *dp = sdev->ofdev.node;
140
141 if (of_find_property(dp, "differential", NULL))
142 esp->flags |= ESP_FLAG_DIFFERENTIAL;
143 else
144 esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
145}
146
147static void __devinit esp_get_clock_params(struct esp *esp)
148{
149 struct sbus_dev *sdev = esp->dev;
150 struct device_node *dp = sdev->ofdev.node;
151 struct device_node *bus_dp;
152 int fmhz;
153
154 bus_dp = NULL;
155 if (sdev != NULL && sdev->bus != NULL)
156 bus_dp = sdev->bus->ofdev.node;
157
158 fmhz = of_getintprop_default(dp, "clock-frequency", 0);
159 if (fmhz == 0)
160 fmhz = (!bus_dp) ? 0 :
161 of_getintprop_default(bus_dp, "clock-frequency", 0);
162
163 esp->cfreq = fmhz;
164}
165
166static void __devinit esp_get_bursts(struct esp *esp, struct sbus_dev *dma)
167{
168 struct sbus_dev *sdev = esp->dev;
169 struct device_node *dp = sdev->ofdev.node;
170 u8 bursts;
171
172 bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
173 if (dma) {
174 struct device_node *dma_dp = dma->ofdev.node;
175 u8 val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
176 if (val != 0xff)
177 bursts &= val;
178 }
179
180 if (sdev->bus) {
181 u8 val = of_getintprop_default(sdev->bus->ofdev.node,
182 "burst-sizes", 0xff);
183 if (val != 0xff)
184 bursts &= val;
185 }
186
187 if (bursts == 0xff ||
188 (bursts & DMA_BURST16) == 0 ||
189 (bursts & DMA_BURST32) == 0)
190 bursts = (DMA_BURST32 - 1);
191
192 esp->bursts = bursts;
193}
194
195static void __devinit esp_sbus_get_props(struct esp *esp, struct sbus_dev *espdma)
196{
197 esp_get_scsi_id(esp);
198 esp_get_differential(esp);
199 esp_get_clock_params(esp);
200 esp_get_bursts(esp, espdma);
201}
202
203static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
204{
205 sbus_writeb(val, esp->regs + (reg * 4UL));
206}
207
208static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
209{
210 return sbus_readb(esp->regs + (reg * 4UL));
211}
212
213static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf,
214 size_t sz, int dir)
215{
216 return sbus_map_single(esp->dev, buf, sz, dir);
217}
218
219static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg,
220 int num_sg, int dir)
221{
222 return sbus_map_sg(esp->dev, sg, num_sg, dir);
223}
224
225static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
226 size_t sz, int dir)
227{
228 sbus_unmap_single(esp->dev, addr, sz, dir);
229}
230
231static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
232 int num_sg, int dir)
233{
234 sbus_unmap_sg(esp->dev, sg, num_sg, dir);
235}
236
237static int sbus_esp_irq_pending(struct esp *esp)
238{
239 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
240 return 1;
241 return 0;
242}
243
244static void sbus_esp_reset_dma(struct esp *esp)
245{
246 int can_do_burst16, can_do_burst32, can_do_burst64;
247 int can_do_sbus64, lim;
248 u32 val;
249
250 can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
251 can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
252 can_do_burst64 = 0;
253 can_do_sbus64 = 0;
254 if (sbus_can_dma_64bit(esp->dev))
255 can_do_sbus64 = 1;
256 if (sbus_can_burst64(esp->sdev))
257 can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
258
259 /* Put the DVMA into a known state. */
260 if (esp->dma->revision != dvmahme) {
261 val = dma_read32(DMA_CSR);
262 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
263 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
264 }
265 switch (esp->dma->revision) {
266 case dvmahme:
267 dma_write32(DMA_RESET_FAS366, DMA_CSR);
268 dma_write32(DMA_RST_SCSI, DMA_CSR);
269
270 esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
271 DMA_SCSI_DISAB | DMA_INT_ENAB);
272
273 esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
274 DMA_BRST_SZ);
275
276 if (can_do_burst64)
277 esp->prev_hme_dmacsr |= DMA_BRST64;
278 else if (can_do_burst32)
279 esp->prev_hme_dmacsr |= DMA_BRST32;
280
281 if (can_do_sbus64) {
282 esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
283 sbus_set_sbus64(esp->dev, esp->bursts);
284 }
285
286 lim = 1000;
287 while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
288 if (--lim == 0) {
289 printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
290 "will not clear!\n",
291 esp->host->unique_id);
292 break;
293 }
294 udelay(1);
295 }
296
297 dma_write32(0, DMA_CSR);
298 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
299
300 dma_write32(0, DMA_ADDR);
301 break;
302
303 case dvmarev2:
304 if (esp->rev != ESP100) {
305 val = dma_read32(DMA_CSR);
306 dma_write32(val | DMA_3CLKS, DMA_CSR);
307 }
308 break;
309
310 case dvmarev3:
311 val = dma_read32(DMA_CSR);
312 val &= ~DMA_3CLKS;
313 val |= DMA_2CLKS;
314 if (can_do_burst32) {
315 val &= ~DMA_BRST_SZ;
316 val |= DMA_BRST32;
317 }
318 dma_write32(val, DMA_CSR);
319 break;
320
321 case dvmaesc1:
322 val = dma_read32(DMA_CSR);
323 val |= DMA_ADD_ENABLE;
324 val &= ~DMA_BCNT_ENAB;
325 if (!can_do_burst32 && can_do_burst16) {
326 val |= DMA_ESC_BURST;
327 } else {
328 val &= ~(DMA_ESC_BURST);
329 }
330 dma_write32(val, DMA_CSR);
331 break;
332
333 default:
334 break;
335 }
336
337 /* Enable interrupts. */
338 val = dma_read32(DMA_CSR);
339 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
340}
341
342static void sbus_esp_dma_drain(struct esp *esp)
343{
344 u32 csr;
345 int lim;
346
347 if (esp->dma->revision == dvmahme)
348 return;
349
350 csr = dma_read32(DMA_CSR);
351 if (!(csr & DMA_FIFO_ISDRAIN))
352 return;
353
354 if (esp->dma->revision != dvmarev3 && esp->dma->revision != dvmaesc1)
355 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
356
357 lim = 1000;
358 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
359 if (--lim == 0) {
360 printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
361 esp->host->unique_id);
362 break;
363 }
364 udelay(1);
365 }
366}
367
368static void sbus_esp_dma_invalidate(struct esp *esp)
369{
370 if (esp->dma->revision == dvmahme) {
371 dma_write32(DMA_RST_SCSI, DMA_CSR);
372
373 esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
374 (DMA_PARITY_OFF | DMA_2CLKS |
375 DMA_SCSI_DISAB | DMA_INT_ENAB)) &
376 ~(DMA_ST_WRITE | DMA_ENABLE));
377
378 dma_write32(0, DMA_CSR);
379 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
380
381 /* This is necessary to avoid having the SCSI channel
382 * engine lock up on us.
383 */
384 dma_write32(0, DMA_ADDR);
385 } else {
386 u32 val;
387 int lim;
388
389 lim = 1000;
390 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
391 if (--lim == 0) {
392 printk(KERN_ALERT PFX "esp%d: DMA will not "
393 "invalidate!\n", esp->host->unique_id);
394 break;
395 }
396 udelay(1);
397 }
398
399 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
400 val |= DMA_FIFO_INV;
401 dma_write32(val, DMA_CSR);
402 val &= ~DMA_FIFO_INV;
403 dma_write32(val, DMA_CSR);
404 }
405}
406
407static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
408 u32 dma_count, int write, u8 cmd)
409{
410 u32 csr;
411
412 BUG_ON(!(cmd & ESP_CMD_DMA));
413
414 sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
415 sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
416 if (esp->rev == FASHME) {
417 sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
418 sbus_esp_write8(esp, 0, FAS_RHI);
419
420 scsi_esp_cmd(esp, cmd);
421
422 csr = esp->prev_hme_dmacsr;
423 csr |= DMA_SCSI_DISAB | DMA_ENABLE;
424 if (write)
425 csr |= DMA_ST_WRITE;
426 else
427 csr &= ~DMA_ST_WRITE;
428 esp->prev_hme_dmacsr = csr;
429
430 dma_write32(dma_count, DMA_COUNT);
431 dma_write32(addr, DMA_ADDR);
432 dma_write32(csr, DMA_CSR);
433 } else {
434 csr = dma_read32(DMA_CSR);
435 csr |= DMA_ENABLE;
436 if (write)
437 csr |= DMA_ST_WRITE;
438 else
439 csr &= ~DMA_ST_WRITE;
440 dma_write32(csr, DMA_CSR);
441 if (esp->dma->revision == dvmaesc1) {
442 u32 end = PAGE_ALIGN(addr + dma_count + 16U);
443 dma_write32(end - addr, DMA_COUNT);
444 }
445 dma_write32(addr, DMA_ADDR);
446
447 scsi_esp_cmd(esp, cmd);
448 }
449
450}
451
452static int sbus_esp_dma_error(struct esp *esp)
453{
454 u32 csr = dma_read32(DMA_CSR);
455
456 if (csr & DMA_HNDL_ERROR)
457 return 1;
458
459 return 0;
460}
461
462static const struct esp_driver_ops sbus_esp_ops = {
463 .esp_write8 = sbus_esp_write8,
464 .esp_read8 = sbus_esp_read8,
465 .map_single = sbus_esp_map_single,
466 .map_sg = sbus_esp_map_sg,
467 .unmap_single = sbus_esp_unmap_single,
468 .unmap_sg = sbus_esp_unmap_sg,
469 .irq_pending = sbus_esp_irq_pending,
470 .reset_dma = sbus_esp_reset_dma,
471 .dma_drain = sbus_esp_dma_drain,
472 .dma_invalidate = sbus_esp_dma_invalidate,
473 .send_dma_cmd = sbus_esp_send_dma_cmd,
474 .dma_error = sbus_esp_dma_error,
475};
476
477static int __devinit esp_sbus_probe_one(struct device *dev,
478 struct sbus_dev *esp_dev,
479 struct sbus_dev *espdma,
480 struct sbus_bus *sbus,
481 int hme)
482{
483 struct scsi_host_template *tpnt = &scsi_esp_template;
484 struct Scsi_Host *host;
485 struct esp *esp;
486 int err;
487
488 host = scsi_host_alloc(tpnt, sizeof(struct esp));
489
490 err = -ENOMEM;
491 if (!host)
492 goto fail;
493
494 host->max_id = (hme ? 16 : 8);
495 esp = host_to_esp(host);
496
497 esp->host = host;
498 esp->dev = esp_dev;
499 esp->ops = &sbus_esp_ops;
500
501 if (hme)
502 esp->flags |= ESP_FLAG_WIDE_CAPABLE;
503
504 err = esp_sbus_find_dma(esp, espdma);
505 if (err < 0)
506 goto fail_unlink;
507
508 err = esp_sbus_map_regs(esp, hme);
509 if (err < 0)
510 goto fail_unlink;
511
512 err = esp_sbus_map_command_block(esp);
513 if (err < 0)
514 goto fail_unmap_regs;
515
516 err = esp_sbus_register_irq(esp);
517 if (err < 0)
518 goto fail_unmap_command_block;
519
520 esp_sbus_get_props(esp, espdma);
521
522 /* Before we try to touch the ESP chip, ESC1 dma can
523 * come up with the reset bit set, so make sure that
524 * is clear first.
525 */
526 if (esp->dma->revision == dvmaesc1) {
527 u32 val = dma_read32(DMA_CSR);
528
529 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
530 }
531
532 dev_set_drvdata(&esp_dev->ofdev.dev, esp);
533
534 err = scsi_esp_register(esp, dev);
535 if (err)
536 goto fail_free_irq;
537
538 return 0;
539
540fail_free_irq:
541 free_irq(host->irq, esp);
542fail_unmap_command_block:
543 sbus_free_consistent(esp->dev, 16,
544 esp->command_block,
545 esp->command_block_dma);
546fail_unmap_regs:
547 sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
548fail_unlink:
549 scsi_host_put(host);
550fail:
551 return err;
552}
553
554static int __devinit esp_sbus_probe(struct of_device *dev, const struct of_device_id *match)
555{
556 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
557 struct device_node *dp = dev->node;
558 struct sbus_dev *dma_sdev = NULL;
559 int hme = 0;
560
561 if (dp->parent &&
562 (!strcmp(dp->parent->name, "espdma") ||
563 !strcmp(dp->parent->name, "dma")))
564 dma_sdev = sdev->parent;
565 else if (!strcmp(dp->name, "SUNW,fas")) {
566 dma_sdev = sdev;
567 hme = 1;
568 }
569
570 return esp_sbus_probe_one(&dev->dev, sdev, dma_sdev,
571 sdev->bus, hme);
572}
573
574static int __devexit esp_sbus_remove(struct of_device *dev)
575{
576 struct esp *esp = dev_get_drvdata(&dev->dev);
577 unsigned int irq = esp->host->irq;
578 u32 val;
579
580 scsi_esp_unregister(esp);
581
582 /* Disable interrupts. */
583 val = dma_read32(DMA_CSR);
584 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
585
586 free_irq(irq, esp);
587 sbus_free_consistent(esp->dev, 16,
588 esp->command_block,
589 esp->command_block_dma);
590 sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
591
592 scsi_host_put(esp->host);
593
594 return 0;
595}
596
597static struct of_device_id esp_match[] = {
598 {
599 .name = "SUNW,esp",
600 },
601 {
602 .name = "SUNW,fas",
603 },
604 {
605 .name = "esp",
606 },
607 {},
608};
609MODULE_DEVICE_TABLE(of, esp_match);
610
611static struct of_platform_driver esp_sbus_driver = {
612 .name = "esp",
613 .match_table = esp_match,
614 .probe = esp_sbus_probe,
615 .remove = __devexit_p(esp_sbus_remove),
616};
617
618static int __init sunesp_init(void)
619{
620 return of_register_driver(&esp_sbus_driver, &sbus_bus_type);
621}
622
623static void __exit sunesp_exit(void)
624{
625 of_unregister_driver(&esp_sbus_driver);
626}
627
628MODULE_DESCRIPTION("Sun ESP SCSI driver");
629MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
630MODULE_LICENSE("GPL");
631MODULE_VERSION(DRV_VERSION);
632
633module_init(sunesp_init);
634module_exit(sunesp_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 05:31:40 -0500