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authorLinus Torvalds <torvalds@linux-foundation.org>2008-04-27 14:25:00 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-27 14:25:00 -0400
commit064922a805ec7aadfafdd27aa6b4908d737c3c1d (patch)
tree922d058f751964ccf73f5705d7c492b6d45a9425 /drivers/scsi
parent42cadc86008aae0fd9ff31642dc01ed50723cf32 (diff)
parentecc1241e80a0bdc854b1602a44be3ad106753d4f (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6: (40 commits) [SCSI] jazz_esp, sgiwd93, sni_53c710, sun3x_esp: fix platform driver hotplug/coldplug [SCSI] aic7xxx: add const [SCSI] aic7xxx: add static [SCSI] aic7xxx: Update _shipped files [SCSI] aic7xxx: teach aicasm to not emit unused debug code/data [SCSI] qla2xxx: Update version number to 8.02.01-k2. [SCSI] qla2xxx: Correct regression in relogin code. [SCSI] qla2xxx: Correct misc. endian and byte-ordering issues. [SCSI] qla2xxx: make qla2x00_issue_iocb_timeout() static [SCSI] qla2xxx: qla_os.c, make 2 functions static [SCSI] qla2xxx: Re-register FDMI information after a LIP. [SCSI] qla2xxx: Correct SRB usage-after-completion/free issues. [SCSI] qla2xxx: Correct ISP84XX verify-chip response handling. [SCSI] qla2xxx: Wakeup DPC thread to process any deferred-work requests. [SCSI] qla2xxx: Collapse RISC-RAM retrieval code during a firmware-dump. [SCSI] m68k: new mac_esp scsi driver [SCSI] zfcp: Add some statistics provided by the FCP adapter to the sysfs [SCSI] zfcp: Print some messages only during ERP [SCSI] zfcp: Wait for free SBAL during exchange config [SCSI] scsi_transport_fc: fc_user_scan correction ...
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/FlashPoint.c2
-rw-r--r--drivers/scsi/Kconfig10
-rw-r--r--drivers/scsi/Makefile1
-rw-r--r--drivers/scsi/aha152x.c7
-rw-r--r--drivers/scsi/aha1542.c26
-rw-r--r--drivers/scsi/aic7xxx/aic79xx.h23
-rw-r--r--drivers/scsi/aic7xxx/aic79xx.reg115
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_core.c835
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_inline.h859
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_osm.c181
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_osm.h177
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_osm_pci.c33
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_pci.c8
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_proc.c2
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg.h_shipped1145
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped1555
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_seq.h_shipped6
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx.h55
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx.reg45
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_93cx6.c16
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_core.c676
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_inline.h616
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_osm.c95
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_osm.h142
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_osm_pci.c73
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_pci.c9
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_proc.c4
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped233
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped6
-rw-r--r--drivers/scsi/aic7xxx/aicasm/aicasm.c6
-rw-r--r--drivers/scsi/aic7xxx/aicasm/aicasm_gram.y105
-rw-r--r--drivers/scsi/aic7xxx/aicasm/aicasm_scan.l19
-rw-r--r--drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c25
-rw-r--r--drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h1
-rw-r--r--drivers/scsi/eata.c11
-rw-r--r--drivers/scsi/esp_scsi.c35
-rw-r--r--drivers/scsi/esp_scsi.h13
-rw-r--r--drivers/scsi/hosts.c29
-rw-r--r--drivers/scsi/jazz_esp.c4
-rw-r--r--drivers/scsi/lpfc/lpfc_attr.c10
-rw-r--r--drivers/scsi/mac_esp.c657
-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c8
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c394
-rw-r--r--drivers/scsi/qla2xxx/qla_fw.h26
-rw-r--r--drivers/scsi/qla2xxx/qla_gbl.h4
-rw-r--r--drivers/scsi/qla2xxx/qla_gs.c4
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c2
-rw-r--r--drivers/scsi/qla2xxx/qla_isr.c4
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c19
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c12
-rw-r--r--drivers/scsi/qla2xxx/qla_version.h2
-rw-r--r--drivers/scsi/scsi_priv.h1
-rw-r--r--drivers/scsi/scsi_proc.c7
-rw-r--r--drivers/scsi/scsi_scan.c84
-rw-r--r--drivers/scsi/scsi_sysfs.c142
-rw-r--r--drivers/scsi/scsi_transport_fc.c60
-rw-r--r--drivers/scsi/scsi_transport_sas.c22
-rw-r--r--drivers/scsi/scsi_transport_spi.c33
-rw-r--r--drivers/scsi/sgiwd93.c4
-rw-r--r--drivers/scsi/sni_53c710.c2
-rw-r--r--drivers/scsi/st.c10
-rw-r--r--drivers/scsi/sun3x_esp.c2
-rw-r--r--drivers/scsi/u14-34f.c9
63 files changed, 3687 insertions, 5034 deletions
diff --git a/drivers/scsi/FlashPoint.c b/drivers/scsi/FlashPoint.c
index b374e457e5e2..b898d382b7b0 100644
--- a/drivers/scsi/FlashPoint.c
+++ b/drivers/scsi/FlashPoint.c
@@ -1499,7 +1499,7 @@ static void FlashPoint_StartCCB(unsigned long pCurrCard, struct sccb *p_Sccb)
1499 thisCard = ((struct sccb_card *)pCurrCard)->cardIndex; 1499 thisCard = ((struct sccb_card *)pCurrCard)->cardIndex;
1500 ioport = ((struct sccb_card *)pCurrCard)->ioPort; 1500 ioport = ((struct sccb_card *)pCurrCard)->ioPort;
1501 1501
1502 if ((p_Sccb->TargID > MAX_SCSI_TAR) || (p_Sccb->Lun > MAX_LUN)) { 1502 if ((p_Sccb->TargID >= MAX_SCSI_TAR) || (p_Sccb->Lun >= MAX_LUN)) {
1503 1503
1504 p_Sccb->HostStatus = SCCB_COMPLETE; 1504 p_Sccb->HostStatus = SCCB_COMPLETE;
1505 p_Sccb->SccbStatus = SCCB_ERROR; 1505 p_Sccb->SccbStatus = SCCB_ERROR;
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 7f78e3ea517d..99c57b0c1d54 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -1677,6 +1677,16 @@ config MAC_SCSI
1677 SCSI-HOWTO, available from 1677 SCSI-HOWTO, available from
1678 <http://www.tldp.org/docs.html#howto>. 1678 <http://www.tldp.org/docs.html#howto>.
1679 1679
1680config SCSI_MAC_ESP
1681 tristate "Macintosh NCR53c9[46] SCSI"
1682 depends on MAC && SCSI
1683 help
1684 This is the NCR 53c9x SCSI controller found on most of the 68040
1685 based Macintoshes.
1686
1687 To compile this driver as a module, choose M here: the module
1688 will be called mac_esp.
1689
1680config MVME147_SCSI 1690config MVME147_SCSI
1681 bool "WD33C93 SCSI driver for MVME147" 1691 bool "WD33C93 SCSI driver for MVME147"
1682 depends on MVME147 && SCSI=y 1692 depends on MVME147 && SCSI=y
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 23e6ecbd4778..6c775e350c98 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MVME147_SCSI) += mvme147.o wd33c93.o
46obj-$(CONFIG_SGIWD93_SCSI) += sgiwd93.o wd33c93.o 46obj-$(CONFIG_SGIWD93_SCSI) += sgiwd93.o wd33c93.o
47obj-$(CONFIG_ATARI_SCSI) += atari_scsi.o 47obj-$(CONFIG_ATARI_SCSI) += atari_scsi.o
48obj-$(CONFIG_MAC_SCSI) += mac_scsi.o 48obj-$(CONFIG_MAC_SCSI) += mac_scsi.o
49obj-$(CONFIG_SCSI_MAC_ESP) += esp_scsi.o mac_esp.o
49obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o sun3_scsi_vme.o 50obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o sun3_scsi_vme.o
50obj-$(CONFIG_MVME16x_SCSI) += 53c700.o mvme16x_scsi.o 51obj-$(CONFIG_MVME16x_SCSI) += 53c700.o mvme16x_scsi.o
51obj-$(CONFIG_BVME6000_SCSI) += 53c700.o bvme6000_scsi.o 52obj-$(CONFIG_BVME6000_SCSI) += 53c700.o bvme6000_scsi.o
diff --git a/drivers/scsi/aha152x.c b/drivers/scsi/aha152x.c
index 6ccdc96cc480..a09b2d3fdf5a 100644
--- a/drivers/scsi/aha152x.c
+++ b/drivers/scsi/aha152x.c
@@ -1432,15 +1432,10 @@ static void run(struct work_struct *work)
1432 */ 1432 */
1433static irqreturn_t intr(int irqno, void *dev_id) 1433static irqreturn_t intr(int irqno, void *dev_id)
1434{ 1434{
1435 struct Scsi_Host *shpnt = (struct Scsi_Host *)dev_id; 1435 struct Scsi_Host *shpnt = dev_id;
1436 unsigned long flags; 1436 unsigned long flags;
1437 unsigned char rev, dmacntrl0; 1437 unsigned char rev, dmacntrl0;
1438 1438
1439 if (!shpnt) {
1440 printk(KERN_ERR "aha152x: catched interrupt %d for unknown controller.\n", irqno);
1441 return IRQ_NONE;
1442 }
1443
1444 /* 1439 /*
1445 * Read a couple of registers that are known to not be all 1's. If 1440 * Read a couple of registers that are known to not be all 1's. If
1446 * we read all 1's (-1), that means that either: 1441 * we read all 1's (-1), that means that either:
diff --git a/drivers/scsi/aha1542.c b/drivers/scsi/aha1542.c
index 5a1471c370fa..80594947c6f6 100644
--- a/drivers/scsi/aha1542.c
+++ b/drivers/scsi/aha1542.c
@@ -153,8 +153,6 @@ struct aha1542_hostdata {
153 153
154#define HOSTDATA(host) ((struct aha1542_hostdata *) &host->hostdata) 154#define HOSTDATA(host) ((struct aha1542_hostdata *) &host->hostdata)
155 155
156static struct Scsi_Host *aha_host[7]; /* One for each IRQ level (9-15) */
157
158static DEFINE_SPINLOCK(aha1542_lock); 156static DEFINE_SPINLOCK(aha1542_lock);
159 157
160 158
@@ -163,8 +161,7 @@ static DEFINE_SPINLOCK(aha1542_lock);
163 161
164static void setup_mailboxes(int base_io, struct Scsi_Host *shpnt); 162static void setup_mailboxes(int base_io, struct Scsi_Host *shpnt);
165static int aha1542_restart(struct Scsi_Host *shost); 163static int aha1542_restart(struct Scsi_Host *shost);
166static void aha1542_intr_handle(struct Scsi_Host *shost, void *dev_id); 164static void aha1542_intr_handle(struct Scsi_Host *shost);
167static irqreturn_t do_aha1542_intr_handle(int irq, void *dev_id);
168 165
169#define aha1542_intr_reset(base) outb(IRST, CONTROL(base)) 166#define aha1542_intr_reset(base) outb(IRST, CONTROL(base))
170 167
@@ -404,23 +401,19 @@ fail:
404} 401}
405 402
406/* A quick wrapper for do_aha1542_intr_handle to grab the spin lock */ 403/* A quick wrapper for do_aha1542_intr_handle to grab the spin lock */
407static irqreturn_t do_aha1542_intr_handle(int irq, void *dev_id) 404static irqreturn_t do_aha1542_intr_handle(int dummy, void *dev_id)
408{ 405{
409 unsigned long flags; 406 unsigned long flags;
410 struct Scsi_Host *shost; 407 struct Scsi_Host *shost = dev_id;
411
412 shost = aha_host[irq - 9];
413 if (!shost)
414 panic("Splunge!");
415 408
416 spin_lock_irqsave(shost->host_lock, flags); 409 spin_lock_irqsave(shost->host_lock, flags);
417 aha1542_intr_handle(shost, dev_id); 410 aha1542_intr_handle(shost);
418 spin_unlock_irqrestore(shost->host_lock, flags); 411 spin_unlock_irqrestore(shost->host_lock, flags);
419 return IRQ_HANDLED; 412 return IRQ_HANDLED;
420} 413}
421 414
422/* A "high" level interrupt handler */ 415/* A "high" level interrupt handler */
423static void aha1542_intr_handle(struct Scsi_Host *shost, void *dev_id) 416static void aha1542_intr_handle(struct Scsi_Host *shost)
424{ 417{
425 void (*my_done) (Scsi_Cmnd *) = NULL; 418 void (*my_done) (Scsi_Cmnd *) = NULL;
426 int errstatus, mbi, mbo, mbistatus; 419 int errstatus, mbi, mbo, mbistatus;
@@ -1197,7 +1190,8 @@ fail:
1197 1190
1198 DEB(printk("aha1542_detect: enable interrupt channel %d\n", irq_level)); 1191 DEB(printk("aha1542_detect: enable interrupt channel %d\n", irq_level));
1199 spin_lock_irqsave(&aha1542_lock, flags); 1192 spin_lock_irqsave(&aha1542_lock, flags);
1200 if (request_irq(irq_level, do_aha1542_intr_handle, 0, "aha1542", NULL)) { 1193 if (request_irq(irq_level, do_aha1542_intr_handle, 0,
1194 "aha1542", shpnt)) {
1201 printk(KERN_ERR "Unable to allocate IRQ for adaptec controller.\n"); 1195 printk(KERN_ERR "Unable to allocate IRQ for adaptec controller.\n");
1202 spin_unlock_irqrestore(&aha1542_lock, flags); 1196 spin_unlock_irqrestore(&aha1542_lock, flags);
1203 goto unregister; 1197 goto unregister;
@@ -1205,7 +1199,7 @@ fail:
1205 if (dma_chan != 0xFF) { 1199 if (dma_chan != 0xFF) {
1206 if (request_dma(dma_chan, "aha1542")) { 1200 if (request_dma(dma_chan, "aha1542")) {
1207 printk(KERN_ERR "Unable to allocate DMA channel for Adaptec.\n"); 1201 printk(KERN_ERR "Unable to allocate DMA channel for Adaptec.\n");
1208 free_irq(irq_level, NULL); 1202 free_irq(irq_level, shpnt);
1209 spin_unlock_irqrestore(&aha1542_lock, flags); 1203 spin_unlock_irqrestore(&aha1542_lock, flags);
1210 goto unregister; 1204 goto unregister;
1211 } 1205 }
@@ -1214,7 +1208,7 @@ fail:
1214 enable_dma(dma_chan); 1208 enable_dma(dma_chan);
1215 } 1209 }
1216 } 1210 }
1217 aha_host[irq_level - 9] = shpnt; 1211
1218 shpnt->this_id = scsi_id; 1212 shpnt->this_id = scsi_id;
1219 shpnt->unique_id = base_io; 1213 shpnt->unique_id = base_io;
1220 shpnt->io_port = base_io; 1214 shpnt->io_port = base_io;
@@ -1276,7 +1270,7 @@ unregister:
1276static int aha1542_release(struct Scsi_Host *shost) 1270static int aha1542_release(struct Scsi_Host *shost)
1277{ 1271{
1278 if (shost->irq) 1272 if (shost->irq)
1279 free_irq(shost->irq, NULL); 1273 free_irq(shost->irq, shost);
1280 if (shost->dma_channel != 0xff) 1274 if (shost->dma_channel != 0xff)
1281 free_dma(shost->dma_channel); 1275 free_dma(shost->dma_channel);
1282 if (shost->io_port && shost->n_io_port) 1276 if (shost->io_port && shost->n_io_port)
diff --git a/drivers/scsi/aic7xxx/aic79xx.h b/drivers/scsi/aic7xxx/aic79xx.h
index 2f00467b6b8c..be5558ab84ea 100644
--- a/drivers/scsi/aic7xxx/aic79xx.h
+++ b/drivers/scsi/aic7xxx/aic79xx.h
@@ -815,7 +815,7 @@ struct ahd_tmode_tstate {
815struct ahd_phase_table_entry { 815struct ahd_phase_table_entry {
816 uint8_t phase; 816 uint8_t phase;
817 uint8_t mesg_out; /* Message response to parity errors */ 817 uint8_t mesg_out; /* Message response to parity errors */
818 char *phasemsg; 818 const char *phasemsg;
819}; 819};
820 820
821/************************** Serial EEPROM Format ******************************/ 821/************************** Serial EEPROM Format ******************************/
@@ -1314,7 +1314,7 @@ typedef int (ahd_device_setup_t)(struct ahd_softc *);
1314struct ahd_pci_identity { 1314struct ahd_pci_identity {
1315 uint64_t full_id; 1315 uint64_t full_id;
1316 uint64_t id_mask; 1316 uint64_t id_mask;
1317 char *name; 1317 const char *name;
1318 ahd_device_setup_t *setup; 1318 ahd_device_setup_t *setup;
1319}; 1319};
1320 1320
@@ -1322,7 +1322,7 @@ struct ahd_pci_identity {
1322struct aic7770_identity { 1322struct aic7770_identity {
1323 uint32_t full_id; 1323 uint32_t full_id;
1324 uint32_t id_mask; 1324 uint32_t id_mask;
1325 char *name; 1325 const char *name;
1326 ahd_device_setup_t *setup; 1326 ahd_device_setup_t *setup;
1327}; 1327};
1328extern struct aic7770_identity aic7770_ident_table []; 1328extern struct aic7770_identity aic7770_ident_table [];
@@ -1333,12 +1333,11 @@ extern const int ahd_num_aic7770_devs;
1333 1333
1334/*************************** Function Declarations ****************************/ 1334/*************************** Function Declarations ****************************/
1335/******************************************************************************/ 1335/******************************************************************************/
1336void ahd_reset_cmds_pending(struct ahd_softc *ahd);
1337 1336
1338/***************************** PCI Front End *********************************/ 1337/***************************** PCI Front End *********************************/
1339struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1338const struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1340int ahd_pci_config(struct ahd_softc *, 1339int ahd_pci_config(struct ahd_softc *,
1341 struct ahd_pci_identity *); 1340 const struct ahd_pci_identity *);
1342int ahd_pci_test_register_access(struct ahd_softc *); 1341int ahd_pci_test_register_access(struct ahd_softc *);
1343#ifdef CONFIG_PM 1342#ifdef CONFIG_PM
1344void ahd_pci_suspend(struct ahd_softc *); 1343void ahd_pci_suspend(struct ahd_softc *);
@@ -1376,16 +1375,6 @@ int ahd_write_flexport(struct ahd_softc *ahd,
1376int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1375int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1377 uint8_t *value); 1376 uint8_t *value);
1378 1377
1379/*************************** Interrupt Services *******************************/
1380void ahd_run_qoutfifo(struct ahd_softc *ahd);
1381#ifdef AHD_TARGET_MODE
1382void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1383#endif
1384void ahd_handle_hwerrint(struct ahd_softc *ahd);
1385void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1386void ahd_handle_scsiint(struct ahd_softc *ahd,
1387 u_int intstat);
1388
1389/***************************** Error Recovery *********************************/ 1378/***************************** Error Recovery *********************************/
1390typedef enum { 1379typedef enum {
1391 SEARCH_COMPLETE, 1380 SEARCH_COMPLETE,
@@ -1479,7 +1468,7 @@ extern uint32_t ahd_debug;
1479void ahd_print_devinfo(struct ahd_softc *ahd, 1468void ahd_print_devinfo(struct ahd_softc *ahd,
1480 struct ahd_devinfo *devinfo); 1469 struct ahd_devinfo *devinfo);
1481void ahd_dump_card_state(struct ahd_softc *ahd); 1470void ahd_dump_card_state(struct ahd_softc *ahd);
1482int ahd_print_register(ahd_reg_parse_entry_t *table, 1471int ahd_print_register(const ahd_reg_parse_entry_t *table,
1483 u_int num_entries, 1472 u_int num_entries,
1484 const char *name, 1473 const char *name,
1485 u_int address, 1474 u_int address,
diff --git a/drivers/scsi/aic7xxx/aic79xx.reg b/drivers/scsi/aic7xxx/aic79xx.reg
index be14e2ecb8f7..cca16fc5b4ad 100644
--- a/drivers/scsi/aic7xxx/aic79xx.reg
+++ b/drivers/scsi/aic7xxx/aic79xx.reg
@@ -198,6 +198,7 @@ register SEQINTCODE {
198register CLRINT { 198register CLRINT {
199 address 0x003 199 address 0x003
200 access_mode WO 200 access_mode WO
201 count 19
201 field CLRHWERRINT 0x80 /* Rev B or greater */ 202 field CLRHWERRINT 0x80 /* Rev B or greater */
202 field CLRBRKADRINT 0x40 203 field CLRBRKADRINT 0x40
203 field CLRSWTMINT 0x20 204 field CLRSWTMINT 0x20
@@ -245,6 +246,7 @@ register CLRERR {
245register HCNTRL { 246register HCNTRL {
246 address 0x005 247 address 0x005
247 access_mode RW 248 access_mode RW
249 count 12
248 field SEQ_RESET 0x80 /* Rev B or greater */ 250 field SEQ_RESET 0x80 /* Rev B or greater */
249 field POWRDN 0x40 251 field POWRDN 0x40
250 field SWINT 0x10 252 field SWINT 0x10
@@ -262,6 +264,7 @@ register HNSCB_QOFF {
262 address 0x006 264 address 0x006
263 access_mode RW 265 access_mode RW
264 size 2 266 size 2
267 count 2
265} 268}
266 269
267/* 270/*
@@ -270,6 +273,7 @@ register HNSCB_QOFF {
270register HESCB_QOFF { 273register HESCB_QOFF {
271 address 0x008 274 address 0x008
272 access_mode RW 275 access_mode RW
276 count 2
273} 277}
274 278
275/* 279/*
@@ -287,6 +291,7 @@ register HS_MAILBOX {
287 */ 291 */
288register SEQINTSTAT { 292register SEQINTSTAT {
289 address 0x00C 293 address 0x00C
294 count 1
290 access_mode RO 295 access_mode RO
291 field SEQ_SWTMRTO 0x10 296 field SEQ_SWTMRTO 0x10
292 field SEQ_SEQINT 0x08 297 field SEQ_SEQINT 0x08
@@ -332,6 +337,7 @@ register SNSCB_QOFF {
332 */ 337 */
333register SESCB_QOFF { 338register SESCB_QOFF {
334 address 0x012 339 address 0x012
340 count 2
335 access_mode RW 341 access_mode RW
336 modes M_CCHAN 342 modes M_CCHAN
337} 343}
@@ -397,6 +403,7 @@ register DFCNTRL {
397 address 0x019 403 address 0x019
398 access_mode RW 404 access_mode RW
399 modes M_DFF0, M_DFF1 405 modes M_DFF0, M_DFF1
406 count 11
400 field PRELOADEN 0x80 407 field PRELOADEN 0x80
401 field SCSIENWRDIS 0x40 /* Rev B only. */ 408 field SCSIENWRDIS 0x40 /* Rev B only. */
402 field SCSIEN 0x20 409 field SCSIEN 0x20
@@ -415,6 +422,7 @@ register DFCNTRL {
415 */ 422 */
416register DSCOMMAND0 { 423register DSCOMMAND0 {
417 address 0x019 424 address 0x019
425 count 1
418 access_mode RW 426 access_mode RW
419 modes M_CFG 427 modes M_CFG
420 field CACHETHEN 0x80 /* Cache Threshold enable */ 428 field CACHETHEN 0x80 /* Cache Threshold enable */
@@ -580,6 +588,7 @@ register DFF_THRSH {
580 address 0x088 588 address 0x088
581 access_mode RW 589 access_mode RW
582 modes M_CFG 590 modes M_CFG
591 count 1
583 field WR_DFTHRSH 0x70 { 592 field WR_DFTHRSH 0x70 {
584 WR_DFTHRSH_MIN, 593 WR_DFTHRSH_MIN,
585 WR_DFTHRSH_25, 594 WR_DFTHRSH_25,
@@ -800,6 +809,7 @@ register PCIXCTL {
800 address 0x093 809 address 0x093
801 access_mode RW 810 access_mode RW
802 modes M_CFG 811 modes M_CFG
812 count 1
803 field SERRPULSE 0x80 813 field SERRPULSE 0x80
804 field UNEXPSCIEN 0x20 814 field UNEXPSCIEN 0x20
805 field SPLTSMADIS 0x10 815 field SPLTSMADIS 0x10
@@ -844,6 +854,7 @@ register DCHSPLTSTAT0 {
844 address 0x096 854 address 0x096
845 access_mode RW 855 access_mode RW
846 modes M_DFF0, M_DFF1 856 modes M_DFF0, M_DFF1
857 count 2
847 field STAETERM 0x80 858 field STAETERM 0x80
848 field SCBCERR 0x40 859 field SCBCERR 0x40
849 field SCADERR 0x20 860 field SCADERR 0x20
@@ -895,6 +906,7 @@ register DCHSPLTSTAT1 {
895 address 0x097 906 address 0x097
896 access_mode RW 907 access_mode RW
897 modes M_DFF0, M_DFF1 908 modes M_DFF0, M_DFF1
909 count 2
898 field RXDATABUCKET 0x01 910 field RXDATABUCKET 0x01
899} 911}
900 912
@@ -1048,6 +1060,7 @@ register SGSPLTSTAT0 {
1048 address 0x09E 1060 address 0x09E
1049 access_mode RW 1061 access_mode RW
1050 modes M_DFF0, M_DFF1 1062 modes M_DFF0, M_DFF1
1063 count 2
1051 field STAETERM 0x80 1064 field STAETERM 0x80
1052 field SCBCERR 0x40 1065 field SCBCERR 0x40
1053 field SCADERR 0x20 1066 field SCADERR 0x20
@@ -1065,6 +1078,7 @@ register SGSPLTSTAT1 {
1065 address 0x09F 1078 address 0x09F
1066 access_mode RW 1079 access_mode RW
1067 modes M_DFF0, M_DFF1 1080 modes M_DFF0, M_DFF1
1081 count 2
1068 field RXDATABUCKET 0x01 1082 field RXDATABUCKET 0x01
1069} 1083}
1070 1084
@@ -1086,6 +1100,7 @@ register DF0PCISTAT {
1086 address 0x0A0 1100 address 0x0A0
1087 access_mode RW 1101 access_mode RW
1088 modes M_CFG 1102 modes M_CFG
1103 count 1
1089 field DPE 0x80 1104 field DPE 0x80
1090 field SSE 0x40 1105 field SSE 0x40
1091 field RMA 0x20 1106 field RMA 0x20
@@ -1184,6 +1199,7 @@ register TARGPCISTAT {
1184 address 0x0A7 1199 address 0x0A7
1185 access_mode RW 1200 access_mode RW
1186 modes M_CFG 1201 modes M_CFG
1202 count 5
1187 field DPE 0x80 1203 field DPE 0x80
1188 field SSE 0x40 1204 field SSE 0x40
1189 field STA 0x08 1205 field STA 0x08
@@ -1198,6 +1214,7 @@ register LQIN {
1198 address 0x020 1214 address 0x020
1199 access_mode RW 1215 access_mode RW
1200 size 20 1216 size 20
1217 count 2
1201 modes M_DFF0, M_DFF1, M_SCSI 1218 modes M_DFF0, M_DFF1, M_SCSI
1202} 1219}
1203 1220
@@ -1229,6 +1246,7 @@ register LUNPTR {
1229 address 0x022 1246 address 0x022
1230 access_mode RW 1247 access_mode RW
1231 modes M_CFG 1248 modes M_CFG
1249 count 2
1232} 1250}
1233 1251
1234/* 1252/*
@@ -1259,6 +1277,7 @@ register CMDLENPTR {
1259 address 0x025 1277 address 0x025
1260 access_mode RW 1278 access_mode RW
1261 modes M_CFG 1279 modes M_CFG
1280 count 1
1262} 1281}
1263 1282
1264/* 1283/*
@@ -1270,6 +1289,7 @@ register ATTRPTR {
1270 address 0x026 1289 address 0x026
1271 access_mode RW 1290 access_mode RW
1272 modes M_CFG 1291 modes M_CFG
1292 count 1
1273} 1293}
1274 1294
1275/* 1295/*
@@ -1281,6 +1301,7 @@ register FLAGPTR {
1281 address 0x027 1301 address 0x027
1282 access_mode RW 1302 access_mode RW
1283 modes M_CFG 1303 modes M_CFG
1304 count 1
1284} 1305}
1285 1306
1286/* 1307/*
@@ -1291,6 +1312,7 @@ register CMDPTR {
1291 address 0x028 1312 address 0x028
1292 access_mode RW 1313 access_mode RW
1293 modes M_CFG 1314 modes M_CFG
1315 count 1
1294} 1316}
1295 1317
1296/* 1318/*
@@ -1301,6 +1323,7 @@ register QNEXTPTR {
1301 address 0x029 1323 address 0x029
1302 access_mode RW 1324 access_mode RW
1303 modes M_CFG 1325 modes M_CFG
1326 count 1
1304} 1327}
1305 1328
1306/* 1329/*
@@ -1323,6 +1346,7 @@ register ABRTBYTEPTR {
1323 address 0x02B 1346 address 0x02B
1324 access_mode RW 1347 access_mode RW
1325 modes M_CFG 1348 modes M_CFG
1349 count 1
1326} 1350}
1327 1351
1328/* 1352/*
@@ -1333,6 +1357,7 @@ register ABRTBITPTR {
1333 address 0x02C 1357 address 0x02C
1334 access_mode RW 1358 access_mode RW
1335 modes M_CFG 1359 modes M_CFG
1360 count 1
1336} 1361}
1337 1362
1338/* 1363/*
@@ -1370,6 +1395,7 @@ register LUNLEN {
1370 address 0x030 1395 address 0x030
1371 access_mode RW 1396 access_mode RW
1372 modes M_CFG 1397 modes M_CFG
1398 count 2
1373 mask ILUNLEN 0x0F 1399 mask ILUNLEN 0x0F
1374 mask TLUNLEN 0xF0 1400 mask TLUNLEN 0xF0
1375} 1401}
@@ -1383,6 +1409,7 @@ register CDBLIMIT {
1383 address 0x031 1409 address 0x031
1384 access_mode RW 1410 access_mode RW
1385 modes M_CFG 1411 modes M_CFG
1412 count 1
1386} 1413}
1387 1414
1388/* 1415/*
@@ -1394,6 +1421,7 @@ register MAXCMD {
1394 address 0x032 1421 address 0x032
1395 access_mode RW 1422 access_mode RW
1396 modes M_CFG 1423 modes M_CFG
1424 count 9
1397} 1425}
1398 1426
1399/* 1427/*
@@ -1458,6 +1486,7 @@ register LQCTL1 {
1458 address 0x038 1486 address 0x038
1459 access_mode RW 1487 access_mode RW
1460 modes M_DFF0, M_DFF1, M_SCSI 1488 modes M_DFF0, M_DFF1, M_SCSI
1489 count 2
1461 field PCI2PCI 0x04 1490 field PCI2PCI 0x04
1462 field SINGLECMD 0x02 1491 field SINGLECMD 0x02
1463 field ABORTPENDING 0x01 1492 field ABORTPENDING 0x01
@@ -1470,6 +1499,7 @@ register LQCTL2 {
1470 address 0x039 1499 address 0x039
1471 access_mode RW 1500 access_mode RW
1472 modes M_DFF0, M_DFF1, M_SCSI 1501 modes M_DFF0, M_DFF1, M_SCSI
1502 count 5
1473 field LQIRETRY 0x80 1503 field LQIRETRY 0x80
1474 field LQICONTINUE 0x40 1504 field LQICONTINUE 0x40
1475 field LQITOIDLE 0x20 1505 field LQITOIDLE 0x20
@@ -1528,6 +1558,7 @@ register SCSISEQ1 {
1528 address 0x03B 1558 address 0x03B
1529 access_mode RW 1559 access_mode RW
1530 modes M_DFF0, M_DFF1, M_SCSI 1560 modes M_DFF0, M_DFF1, M_SCSI
1561 count 8
1531 field MANUALCTL 0x40 1562 field MANUALCTL 0x40
1532 field ENSELI 0x20 1563 field ENSELI 0x20
1533 field ENRSELI 0x10 1564 field ENRSELI 0x10
@@ -1667,6 +1698,9 @@ register SCSISIGO {
1667 } 1698 }
1668} 1699}
1669 1700
1701/*
1702 * SCSI Control Signal In
1703 */
1670register SCSISIGI { 1704register SCSISIGI {
1671 address 0x041 1705 address 0x041
1672 access_mode RO 1706 access_mode RO
@@ -1703,6 +1737,7 @@ register MULTARGID {
1703 access_mode RW 1737 access_mode RW
1704 modes M_CFG 1738 modes M_CFG
1705 size 2 1739 size 2
1740 count 2
1706} 1741}
1707 1742
1708/* 1743/*
@@ -1758,6 +1793,7 @@ register TARGIDIN {
1758 address 0x048 1793 address 0x048
1759 access_mode RO 1794 access_mode RO
1760 modes M_DFF0, M_DFF1, M_SCSI 1795 modes M_DFF0, M_DFF1, M_SCSI
1796 count 2
1761 field CLKOUT 0x80 1797 field CLKOUT 0x80
1762 field TARGID 0x0F 1798 field TARGID 0x0F
1763} 1799}
@@ -1798,6 +1834,7 @@ register OPTIONMODE {
1798 address 0x04A 1834 address 0x04A
1799 access_mode RW 1835 access_mode RW
1800 modes M_CFG 1836 modes M_CFG
1837 count 4
1801 field BIOSCANCTL 0x80 1838 field BIOSCANCTL 0x80
1802 field AUTOACKEN 0x40 1839 field AUTOACKEN 0x40
1803 field BIASCANCTL 0x20 1840 field BIASCANCTL 0x20
@@ -1850,6 +1887,7 @@ register SIMODE0 {
1850 address 0x04B 1887 address 0x04B
1851 access_mode RW 1888 access_mode RW
1852 modes M_CFG 1889 modes M_CFG
1890 count 8
1853 field ENSELDO 0x40 1891 field ENSELDO 0x40
1854 field ENSELDI 0x20 1892 field ENSELDI 0x20
1855 field ENSELINGO 0x10 1893 field ENSELINGO 0x10
@@ -1945,6 +1983,7 @@ register PERRDIAG {
1945 address 0x04E 1983 address 0x04E
1946 access_mode RO 1984 access_mode RO
1947 modes M_DFF0, M_DFF1, M_SCSI 1985 modes M_DFF0, M_DFF1, M_SCSI
1986 count 3
1948 field HIZERO 0x80 1987 field HIZERO 0x80
1949 field HIPERR 0x40 1988 field HIPERR 0x40
1950 field PREVPHASE 0x20 1989 field PREVPHASE 0x20
@@ -1962,6 +2001,7 @@ register LQISTATE {
1962 address 0x04E 2001 address 0x04E
1963 access_mode RO 2002 access_mode RO
1964 modes M_CFG 2003 modes M_CFG
2004 count 6
1965} 2005}
1966 2006
1967/* 2007/*
@@ -1971,6 +2011,7 @@ register SOFFCNT {
1971 address 0x04F 2011 address 0x04F
1972 access_mode RO 2012 access_mode RO
1973 modes M_DFF0, M_DFF1, M_SCSI 2013 modes M_DFF0, M_DFF1, M_SCSI
2014 count 1
1974} 2015}
1975 2016
1976/* 2017/*
@@ -1980,6 +2021,7 @@ register LQOSTATE {
1980 address 0x04F 2021 address 0x04F
1981 access_mode RO 2022 access_mode RO
1982 modes M_CFG 2023 modes M_CFG
2024 count 2
1983} 2025}
1984 2026
1985/* 2027/*
@@ -1989,6 +2031,7 @@ register LQISTAT0 {
1989 address 0x050 2031 address 0x050
1990 access_mode RO 2032 access_mode RO
1991 modes M_DFF0, M_DFF1, M_SCSI 2033 modes M_DFF0, M_DFF1, M_SCSI
2034 count 2
1992 field LQIATNQAS 0x20 2035 field LQIATNQAS 0x20
1993 field LQICRCT1 0x10 2036 field LQICRCT1 0x10
1994 field LQICRCT2 0x08 2037 field LQICRCT2 0x08
@@ -2004,6 +2047,7 @@ register CLRLQIINT0 {
2004 address 0x050 2047 address 0x050
2005 access_mode WO 2048 access_mode WO
2006 modes M_DFF0, M_DFF1, M_SCSI 2049 modes M_DFF0, M_DFF1, M_SCSI
2050 count 1
2007 field CLRLQIATNQAS 0x20 2051 field CLRLQIATNQAS 0x20
2008 field CLRLQICRCT1 0x10 2052 field CLRLQICRCT1 0x10
2009 field CLRLQICRCT2 0x08 2053 field CLRLQICRCT2 0x08
@@ -2019,6 +2063,7 @@ register LQIMODE0 {
2019 address 0x050 2063 address 0x050
2020 access_mode RW 2064 access_mode RW
2021 modes M_CFG 2065 modes M_CFG
2066 count 3
2022 field ENLQIATNQASK 0x20 2067 field ENLQIATNQASK 0x20
2023 field ENLQICRCT1 0x10 2068 field ENLQICRCT1 0x10
2024 field ENLQICRCT2 0x08 2069 field ENLQICRCT2 0x08
@@ -2034,6 +2079,7 @@ register LQISTAT1 {
2034 address 0x051 2079 address 0x051
2035 access_mode RO 2080 access_mode RO
2036 modes M_DFF0, M_DFF1, M_SCSI 2081 modes M_DFF0, M_DFF1, M_SCSI
2082 count 3
2037 field LQIPHASE_LQ 0x80 2083 field LQIPHASE_LQ 0x80
2038 field LQIPHASE_NLQ 0x40 2084 field LQIPHASE_NLQ 0x40
2039 field LQIABORT 0x20 2085 field LQIABORT 0x20
@@ -2051,6 +2097,7 @@ register CLRLQIINT1 {
2051 address 0x051 2097 address 0x051
2052 access_mode WO 2098 access_mode WO
2053 modes M_DFF0, M_DFF1, M_SCSI 2099 modes M_DFF0, M_DFF1, M_SCSI
2100 count 4
2054 field CLRLQIPHASE_LQ 0x80 2101 field CLRLQIPHASE_LQ 0x80
2055 field CLRLQIPHASE_NLQ 0x40 2102 field CLRLQIPHASE_NLQ 0x40
2056 field CLRLIQABORT 0x20 2103 field CLRLIQABORT 0x20
@@ -2068,6 +2115,7 @@ register LQIMODE1 {
2068 address 0x051 2115 address 0x051
2069 access_mode RW 2116 access_mode RW
2070 modes M_CFG 2117 modes M_CFG
2118 count 4
2071 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2119 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */
2072 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2120 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */
2073 field ENLIQABORT 0x20 2121 field ENLIQABORT 0x20
@@ -2102,6 +2150,7 @@ register SSTAT3 {
2102 address 0x053 2150 address 0x053
2103 access_mode RO 2151 access_mode RO
2104 modes M_DFF0, M_DFF1, M_SCSI 2152 modes M_DFF0, M_DFF1, M_SCSI
2153 count 3
2105 field NTRAMPERR 0x02 2154 field NTRAMPERR 0x02
2106 field OSRAMPERR 0x01 2155 field OSRAMPERR 0x01
2107} 2156}
@@ -2113,6 +2162,7 @@ register CLRSINT3 {
2113 address 0x053 2162 address 0x053
2114 access_mode WO 2163 access_mode WO
2115 modes M_DFF0, M_DFF1, M_SCSI 2164 modes M_DFF0, M_DFF1, M_SCSI
2165 count 3
2116 field CLRNTRAMPERR 0x02 2166 field CLRNTRAMPERR 0x02
2117 field CLROSRAMPERR 0x01 2167 field CLROSRAMPERR 0x01
2118} 2168}
@@ -2124,6 +2174,7 @@ register SIMODE3 {
2124 address 0x053 2174 address 0x053
2125 access_mode RW 2175 access_mode RW
2126 modes M_CFG 2176 modes M_CFG
2177 count 4
2127 field ENNTRAMPERR 0x02 2178 field ENNTRAMPERR 0x02
2128 field ENOSRAMPERR 0x01 2179 field ENOSRAMPERR 0x01
2129} 2180}
@@ -2135,6 +2186,7 @@ register LQOSTAT0 {
2135 address 0x054 2186 address 0x054
2136 access_mode RO 2187 access_mode RO
2137 modes M_DFF0, M_DFF1, M_SCSI 2188 modes M_DFF0, M_DFF1, M_SCSI
2189 count 2
2138 field LQOTARGSCBPERR 0x10 2190 field LQOTARGSCBPERR 0x10
2139 field LQOSTOPT2 0x08 2191 field LQOSTOPT2 0x08
2140 field LQOATNLQ 0x04 2192 field LQOATNLQ 0x04
@@ -2149,6 +2201,7 @@ register CLRLQOINT0 {
2149 address 0x054 2201 address 0x054
2150 access_mode WO 2202 access_mode WO
2151 modes M_DFF0, M_DFF1, M_SCSI 2203 modes M_DFF0, M_DFF1, M_SCSI
2204 count 3
2152 field CLRLQOTARGSCBPERR 0x10 2205 field CLRLQOTARGSCBPERR 0x10
2153 field CLRLQOSTOPT2 0x08 2206 field CLRLQOSTOPT2 0x08
2154 field CLRLQOATNLQ 0x04 2207 field CLRLQOATNLQ 0x04
@@ -2163,6 +2216,7 @@ register LQOMODE0 {
2163 address 0x054 2216 address 0x054
2164 access_mode RW 2217 access_mode RW
2165 modes M_CFG 2218 modes M_CFG
2219 count 4
2166 field ENLQOTARGSCBPERR 0x10 2220 field ENLQOTARGSCBPERR 0x10
2167 field ENLQOSTOPT2 0x08 2221 field ENLQOSTOPT2 0x08
2168 field ENLQOATNLQ 0x04 2222 field ENLQOATNLQ 0x04
@@ -2191,6 +2245,7 @@ register CLRLQOINT1 {
2191 address 0x055 2245 address 0x055
2192 access_mode WO 2246 access_mode WO
2193 modes M_DFF0, M_DFF1, M_SCSI 2247 modes M_DFF0, M_DFF1, M_SCSI
2248 count 7
2194 field CLRLQOINITSCBPERR 0x10 2249 field CLRLQOINITSCBPERR 0x10
2195 field CLRLQOSTOPI2 0x08 2250 field CLRLQOSTOPI2 0x08
2196 field CLRLQOBADQAS 0x04 2251 field CLRLQOBADQAS 0x04
@@ -2205,6 +2260,7 @@ register LQOMODE1 {
2205 address 0x055 2260 address 0x055
2206 access_mode RW 2261 access_mode RW
2207 modes M_CFG 2262 modes M_CFG
2263 count 4
2208 field ENLQOINITSCBPERR 0x10 2264 field ENLQOINITSCBPERR 0x10
2209 field ENLQOSTOPI2 0x08 2265 field ENLQOSTOPI2 0x08
2210 field ENLQOBADQAS 0x04 2266 field ENLQOBADQAS 0x04
@@ -2232,6 +2288,7 @@ register OS_SPACE_CNT {
2232 address 0x056 2288 address 0x056
2233 access_mode RO 2289 access_mode RO
2234 modes M_CFG 2290 modes M_CFG
2291 count 2
2235} 2292}
2236 2293
2237/* 2294/*
@@ -2286,13 +2343,19 @@ register NEXTSCB {
2286 modes M_SCSI 2343 modes M_SCSI
2287} 2344}
2288 2345
2289/* Rev B only. */ 2346/*
2347 * LQO SCSI Control
2348 * (Rev B only.)
2349 */
2290register LQOSCSCTL { 2350register LQOSCSCTL {
2291 address 0x05A 2351 address 0x05A
2292 access_mode RW 2352 access_mode RW
2293 size 1 2353 size 1
2294 modes M_CFG 2354 modes M_CFG
2355 count 1
2295 field LQOH2A_VERSION 0x80 2356 field LQOH2A_VERSION 0x80
2357 field LQOBUSETDLY 0x40
2358 field LQONOHOLDLACK 0x02
2296 field LQONOCHKOVER 0x01 2359 field LQONOCHKOVER 0x01
2297} 2360}
2298 2361
@@ -2459,6 +2522,7 @@ register NEGPERIOD {
2459 address 0x061 2522 address 0x061
2460 access_mode RW 2523 access_mode RW
2461 modes M_SCSI 2524 modes M_SCSI
2525 count 1
2462} 2526}
2463 2527
2464/* 2528/*
@@ -2478,6 +2542,7 @@ register NEGOFFSET {
2478 address 0x062 2542 address 0x062
2479 access_mode RW 2543 access_mode RW
2480 modes M_SCSI 2544 modes M_SCSI
2545 count 1
2481} 2546}
2482 2547
2483/* 2548/*
@@ -2487,6 +2552,7 @@ register NEGPPROPTS {
2487 address 0x063 2552 address 0x063
2488 access_mode RW 2553 access_mode RW
2489 modes M_SCSI 2554 modes M_SCSI
2555 count 1
2490 field PPROPT_PACE 0x08 2556 field PPROPT_PACE 0x08
2491 field PPROPT_QAS 0x04 2557 field PPROPT_QAS 0x04
2492 field PPROPT_DT 0x02 2558 field PPROPT_DT 0x02
@@ -2516,12 +2582,19 @@ register ANNEXCOL {
2516 address 0x065 2582 address 0x065
2517 access_mode RW 2583 access_mode RW
2518 modes M_SCSI 2584 modes M_SCSI
2585 count 7
2519} 2586}
2520 2587
2588/*
2589 * SCSI Check
2590 * (Rev. B only)
2591 */
2521register SCSCHKN { 2592register SCSCHKN {
2522 address 0x066 2593 address 0x066
2523 access_mode RW 2594 access_mode RW
2524 modes M_CFG 2595 modes M_CFG
2596 count 1
2597 field BIDICHKDIS 0x80
2525 field STSELSKIDDIS 0x40 2598 field STSELSKIDDIS 0x40
2526 field CURRFIFODEF 0x20 2599 field CURRFIFODEF 0x20
2527 field WIDERESEN 0x10 2600 field WIDERESEN 0x10
@@ -2561,6 +2634,7 @@ register ANNEXDAT {
2561 address 0x066 2634 address 0x066
2562 access_mode RW 2635 access_mode RW
2563 modes M_SCSI 2636 modes M_SCSI
2637 count 3
2564} 2638}
2565 2639
2566/* 2640/*
@@ -2596,6 +2670,7 @@ register TOWNID {
2596 address 0x069 2670 address 0x069
2597 access_mode RW 2671 access_mode RW
2598 modes M_SCSI 2672 modes M_SCSI
2673 count 2
2599} 2674}
2600 2675
2601/* 2676/*
@@ -2737,6 +2812,7 @@ register SCBAUTOPTR {
2737 address 0x0AB 2812 address 0x0AB
2738 access_mode RW 2813 access_mode RW
2739 modes M_CFG 2814 modes M_CFG
2815 count 1
2740 field AUSCBPTR_EN 0x80 2816 field AUSCBPTR_EN 0x80
2741 field SCBPTR_ADDR 0x38 2817 field SCBPTR_ADDR 0x38
2742 field SCBPTR_OFF 0x07 2818 field SCBPTR_OFF 0x07
@@ -2881,6 +2957,7 @@ register BRDDAT {
2881 address 0x0B8 2957 address 0x0B8
2882 access_mode RW 2958 access_mode RW
2883 modes M_SCSI 2959 modes M_SCSI
2960 count 2
2884} 2961}
2885 2962
2886/* 2963/*
@@ -2890,6 +2967,7 @@ register BRDCTL {
2890 address 0x0B9 2967 address 0x0B9
2891 access_mode RW 2968 access_mode RW
2892 modes M_SCSI 2969 modes M_SCSI
2970 count 7
2893 field FLXARBACK 0x80 2971 field FLXARBACK 0x80
2894 field FLXARBREQ 0x40 2972 field FLXARBREQ 0x40
2895 field BRDADDR 0x38 2973 field BRDADDR 0x38
@@ -2905,6 +2983,7 @@ register SEEADR {
2905 address 0x0BA 2983 address 0x0BA
2906 access_mode RW 2984 access_mode RW
2907 modes M_SCSI 2985 modes M_SCSI
2986 count 4
2908} 2987}
2909 2988
2910/* 2989/*
@@ -2915,6 +2994,7 @@ register SEEDAT {
2915 access_mode RW 2994 access_mode RW
2916 size 2 2995 size 2
2917 modes M_SCSI 2996 modes M_SCSI
2997 count 4
2918} 2998}
2919 2999
2920/* 3000/*
@@ -2924,6 +3004,7 @@ register SEESTAT {
2924 address 0x0BE 3004 address 0x0BE
2925 access_mode RO 3005 access_mode RO
2926 modes M_SCSI 3006 modes M_SCSI
3007 count 1
2927 field INIT_DONE 0x80 3008 field INIT_DONE 0x80
2928 field SEEOPCODE 0x70 3009 field SEEOPCODE 0x70
2929 field LDALTID_L 0x08 3010 field LDALTID_L 0x08
@@ -2939,6 +3020,7 @@ register SEECTL {
2939 address 0x0BE 3020 address 0x0BE
2940 access_mode RW 3021 access_mode RW
2941 modes M_SCSI 3022 modes M_SCSI
3023 count 4
2942 field SEEOPCODE 0x70 { 3024 field SEEOPCODE 0x70 {
2943 SEEOP_ERASE 0x70, 3025 SEEOP_ERASE 0x70,
2944 SEEOP_READ 0x60, 3026 SEEOP_READ 0x60,
@@ -3000,6 +3082,7 @@ register DSPDATACTL {
3000 address 0x0C1 3082 address 0x0C1
3001 access_mode RW 3083 access_mode RW
3002 modes M_CFG 3084 modes M_CFG
3085 count 3
3003 field BYPASSENAB 0x80 3086 field BYPASSENAB 0x80
3004 field DESQDIS 0x10 3087 field DESQDIS 0x10
3005 field RCVROFFSTDIS 0x04 3088 field RCVROFFSTDIS 0x04
@@ -3058,6 +3141,7 @@ register DSPSELECT {
3058 address 0x0C4 3141 address 0x0C4
3059 access_mode RW 3142 access_mode RW
3060 modes M_CFG 3143 modes M_CFG
3144 count 1
3061 field AUTOINCEN 0x80 3145 field AUTOINCEN 0x80
3062 field DSPSEL 0x1F 3146 field DSPSEL 0x1F
3063} 3147}
@@ -3071,6 +3155,7 @@ register WRTBIASCTL {
3071 address 0x0C5 3155 address 0x0C5
3072 access_mode WO 3156 access_mode WO
3073 modes M_CFG 3157 modes M_CFG
3158 count 3
3074 field AUTOXBCDIS 0x80 3159 field AUTOXBCDIS 0x80
3075 field XMITMANVAL 0x3F 3160 field XMITMANVAL 0x3F
3076} 3161}
@@ -3196,7 +3281,8 @@ register OVLYADDR {
3196 */ 3281 */
3197register SEQCTL0 { 3282register SEQCTL0 {
3198 address 0x0D6 3283 address 0x0D6
3199 access_mode RW 3284 access_mode RW
3285 count 11
3200 field PERRORDIS 0x80 3286 field PERRORDIS 0x80
3201 field PAUSEDIS 0x40 3287 field PAUSEDIS 0x40
3202 field FAILDIS 0x20 3288 field FAILDIS 0x20
@@ -3226,7 +3312,8 @@ register SEQCTL1 {
3226 */ 3312 */
3227register FLAGS { 3313register FLAGS {
3228 address 0x0D8 3314 address 0x0D8
3229 access_mode RO 3315 access_mode RO
3316 count 23
3230 field ZERO 0x02 3317 field ZERO 0x02
3231 field CARRY 0x01 3318 field CARRY 0x01
3232} 3319}
@@ -3255,7 +3342,8 @@ register SEQINTCTL {
3255 */ 3342 */
3256register SEQRAM { 3343register SEQRAM {
3257 address 0x0DA 3344 address 0x0DA
3258 access_mode RW 3345 access_mode RW
3346 count 2
3259} 3347}
3260 3348
3261/* 3349/*
@@ -3266,6 +3354,7 @@ register PRGMCNT {
3266 address 0x0DE 3354 address 0x0DE
3267 access_mode RW 3355 access_mode RW
3268 size 2 3356 size 2
3357 count 5
3269} 3358}
3270 3359
3271/* 3360/*
@@ -3273,7 +3362,7 @@ register PRGMCNT {
3273 */ 3362 */
3274register ACCUM { 3363register ACCUM {
3275 address 0x0E0 3364 address 0x0E0
3276 access_mode RW 3365 access_mode RW
3277 accumulator 3366 accumulator
3278} 3367}
3279 3368
@@ -3401,6 +3490,7 @@ register INTVEC1_ADDR {
3401 access_mode RW 3490 access_mode RW
3402 size 2 3491 size 2
3403 modes M_CFG 3492 modes M_CFG
3493 count 1
3404} 3494}
3405 3495
3406/* 3496/*
@@ -3412,6 +3502,7 @@ register CURADDR {
3412 access_mode RW 3502 access_mode RW
3413 size 2 3503 size 2
3414 modes M_SCSI 3504 modes M_SCSI
3505 count 2
3415} 3506}
3416 3507
3417/* 3508/*
@@ -3423,6 +3514,7 @@ register INTVEC2_ADDR {
3423 access_mode RW 3514 access_mode RW
3424 size 2 3515 size 2
3425 modes M_CFG 3516 modes M_CFG
3517 count 1
3426} 3518}
3427 3519
3428/* 3520/*
@@ -3579,6 +3671,7 @@ scratch_ram {
3579 /* Parameters for DMA Logic */ 3671 /* Parameters for DMA Logic */
3580 DMAPARAMS { 3672 DMAPARAMS {
3581 size 1 3673 size 1
3674 count 8
3582 field PRELOADEN 0x80 3675 field PRELOADEN 0x80
3583 field WIDEODD 0x40 3676 field WIDEODD 0x40
3584 field SCSIEN 0x20 3677 field SCSIEN 0x20
@@ -3648,9 +3741,11 @@ scratch_ram {
3648 */ 3741 */
3649 KERNEL_TQINPOS { 3742 KERNEL_TQINPOS {
3650 size 1 3743 size 1
3744 count 1
3651 } 3745 }
3652 TQINPOS { 3746 TQINPOS {
3653 size 1 3747 size 1
3748 count 8
3654 } 3749 }
3655 /* 3750 /*
3656 * Base address of our shared data with the kernel driver in host 3751 * Base address of our shared data with the kernel driver in host
@@ -3681,6 +3776,7 @@ scratch_ram {
3681 } 3776 }
3682 ARG_2 { 3777 ARG_2 {
3683 size 1 3778 size 1
3779 count 1
3684 alias RETURN_2 3780 alias RETURN_2
3685 } 3781 }
3686 3782
@@ -3698,6 +3794,7 @@ scratch_ram {
3698 */ 3794 */
3699 SCSISEQ_TEMPLATE { 3795 SCSISEQ_TEMPLATE {
3700 size 1 3796 size 1
3797 count 7
3701 field MANUALCTL 0x40 3798 field MANUALCTL 0x40
3702 field ENSELI 0x20 3799 field ENSELI 0x20
3703 field ENRSELI 0x10 3800 field ENRSELI 0x10
@@ -3711,6 +3808,7 @@ scratch_ram {
3711 */ 3808 */
3712 INITIATOR_TAG { 3809 INITIATOR_TAG {
3713 size 1 3810 size 1
3811 count 1
3714 } 3812 }
3715 3813
3716 SEQ_FLAGS2 { 3814 SEQ_FLAGS2 {
@@ -3777,6 +3875,7 @@ scratch_ram {
3777 */ 3875 */
3778 CMDSIZE_TABLE { 3876 CMDSIZE_TABLE {
3779 size 8 3877 size 8
3878 count 8
3780 } 3879 }
3781 /* 3880 /*
3782 * When an SCB with the MK_MESSAGE flag is 3881 * When an SCB with the MK_MESSAGE flag is
@@ -3803,8 +3902,8 @@ scratch_ram {
3803/************************* Hardware SCB Definition ****************************/ 3902/************************* Hardware SCB Definition ****************************/
3804scb { 3903scb {
3805 address 0x180 3904 address 0x180
3806 size 64 3905 size 64
3807 modes 0, 1, 2, 3 3906 modes 0, 1, 2, 3
3808 SCB_RESIDUAL_DATACNT { 3907 SCB_RESIDUAL_DATACNT {
3809 size 4 3908 size 4
3810 alias SCB_CDB_STORE 3909 alias SCB_CDB_STORE
diff --git a/drivers/scsi/aic7xxx/aic79xx_core.c b/drivers/scsi/aic7xxx/aic79xx_core.c
index ade0fb8fbdb2..55508b0fcec4 100644
--- a/drivers/scsi/aic7xxx/aic79xx_core.c
+++ b/drivers/scsi/aic7xxx/aic79xx_core.c
@@ -52,7 +52,7 @@
52 52
53 53
54/***************************** Lookup Tables **********************************/ 54/***************************** Lookup Tables **********************************/
55static char *ahd_chip_names[] = 55static const char *const ahd_chip_names[] =
56{ 56{
57 "NONE", 57 "NONE",
58 "aic7901", 58 "aic7901",
@@ -66,10 +66,10 @@ static const u_int num_chip_names = ARRAY_SIZE(ahd_chip_names);
66 */ 66 */
67struct ahd_hard_error_entry { 67struct ahd_hard_error_entry {
68 uint8_t errno; 68 uint8_t errno;
69 char *errmesg; 69 const char *errmesg;
70}; 70};
71 71
72static struct ahd_hard_error_entry ahd_hard_errors[] = { 72static const struct ahd_hard_error_entry ahd_hard_errors[] = {
73 { DSCTMOUT, "Discard Timer has timed out" }, 73 { DSCTMOUT, "Discard Timer has timed out" },
74 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 74 { ILLOPCODE, "Illegal Opcode in sequencer program" },
75 { SQPARERR, "Sequencer Parity Error" }, 75 { SQPARERR, "Sequencer Parity Error" },
@@ -79,7 +79,7 @@ static struct ahd_hard_error_entry ahd_hard_errors[] = {
79}; 79};
80static const u_int num_errors = ARRAY_SIZE(ahd_hard_errors); 80static const u_int num_errors = ARRAY_SIZE(ahd_hard_errors);
81 81
82static struct ahd_phase_table_entry ahd_phase_table[] = 82static const struct ahd_phase_table_entry ahd_phase_table[] =
83{ 83{
84 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 84 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
85 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 85 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
@@ -213,7 +213,7 @@ static void ahd_dumpseq(struct ahd_softc *ahd);
213#endif 213#endif
214static void ahd_loadseq(struct ahd_softc *ahd); 214static void ahd_loadseq(struct ahd_softc *ahd);
215static int ahd_check_patch(struct ahd_softc *ahd, 215static int ahd_check_patch(struct ahd_softc *ahd,
216 struct patch **start_patch, 216 const struct patch **start_patch,
217 u_int start_instr, u_int *skip_addr); 217 u_int start_instr, u_int *skip_addr);
218static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 218static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
219 u_int address); 219 u_int address);
@@ -254,7 +254,7 @@ static void ahd_freeze_devq(struct ahd_softc *ahd,
254 struct scb *scb); 254 struct scb *scb);
255static void ahd_handle_scb_status(struct ahd_softc *ahd, 255static void ahd_handle_scb_status(struct ahd_softc *ahd,
256 struct scb *scb); 256 struct scb *scb);
257static struct ahd_phase_table_entry* ahd_lookup_phase_entry(int phase); 257static const struct ahd_phase_table_entry* ahd_lookup_phase_entry(int phase);
258static void ahd_shutdown(void *arg); 258static void ahd_shutdown(void *arg);
259static void ahd_update_coalescing_values(struct ahd_softc *ahd, 259static void ahd_update_coalescing_values(struct ahd_softc *ahd,
260 u_int timer, 260 u_int timer,
@@ -266,8 +266,774 @@ static int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
266 int target, char channel, int lun, 266 int target, char channel, int lun,
267 u_int tag, role_t role); 267 u_int tag, role_t role);
268 268
269/******************************** Private Inlines *****************************/ 269static void ahd_reset_cmds_pending(struct ahd_softc *ahd);
270
271/*************************** Interrupt Services *******************************/
272static void ahd_run_qoutfifo(struct ahd_softc *ahd);
273#ifdef AHD_TARGET_MODE
274static void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
275#endif
276static void ahd_handle_hwerrint(struct ahd_softc *ahd);
277static void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
278static void ahd_handle_scsiint(struct ahd_softc *ahd,
279 u_int intstat);
280
281/************************ Sequencer Execution Control *************************/
282void
283ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
284{
285 if (ahd->src_mode == src && ahd->dst_mode == dst)
286 return;
287#ifdef AHD_DEBUG
288 if (ahd->src_mode == AHD_MODE_UNKNOWN
289 || ahd->dst_mode == AHD_MODE_UNKNOWN)
290 panic("Setting mode prior to saving it.\n");
291 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
292 printf("%s: Setting mode 0x%x\n", ahd_name(ahd),
293 ahd_build_mode_state(ahd, src, dst));
294#endif
295 ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst));
296 ahd->src_mode = src;
297 ahd->dst_mode = dst;
298}
299
300static void
301ahd_update_modes(struct ahd_softc *ahd)
302{
303 ahd_mode_state mode_ptr;
304 ahd_mode src;
305 ahd_mode dst;
306
307 mode_ptr = ahd_inb(ahd, MODE_PTR);
308#ifdef AHD_DEBUG
309 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
310 printf("Reading mode 0x%x\n", mode_ptr);
311#endif
312 ahd_extract_mode_state(ahd, mode_ptr, &src, &dst);
313 ahd_known_modes(ahd, src, dst);
314}
315
316static void
317ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
318 ahd_mode dstmode, const char *file, int line)
319{
320#ifdef AHD_DEBUG
321 if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0
322 || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) {
323 panic("%s:%s:%d: Mode assertion failed.\n",
324 ahd_name(ahd), file, line);
325 }
326#endif
327}
328
329#define AHD_ASSERT_MODES(ahd, source, dest) \
330 ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__);
331
332ahd_mode_state
333ahd_save_modes(struct ahd_softc *ahd)
334{
335 if (ahd->src_mode == AHD_MODE_UNKNOWN
336 || ahd->dst_mode == AHD_MODE_UNKNOWN)
337 ahd_update_modes(ahd);
338
339 return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode));
340}
341
342void
343ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state)
344{
345 ahd_mode src;
346 ahd_mode dst;
347
348 ahd_extract_mode_state(ahd, state, &src, &dst);
349 ahd_set_modes(ahd, src, dst);
350}
351
352/*
353 * Determine whether the sequencer has halted code execution.
354 * Returns non-zero status if the sequencer is stopped.
355 */
356int
357ahd_is_paused(struct ahd_softc *ahd)
358{
359 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0);
360}
361
362/*
363 * Request that the sequencer stop and wait, indefinitely, for it
364 * to stop. The sequencer will only acknowledge that it is paused
365 * once it has reached an instruction boundary and PAUSEDIS is
366 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
367 * for critical sections.
368 */
369void
370ahd_pause(struct ahd_softc *ahd)
371{
372 ahd_outb(ahd, HCNTRL, ahd->pause);
373
374 /*
375 * Since the sequencer can disable pausing in a critical section, we
376 * must loop until it actually stops.
377 */
378 while (ahd_is_paused(ahd) == 0)
379 ;
380}
381
382/*
383 * Allow the sequencer to continue program execution.
384 * We check here to ensure that no additional interrupt
385 * sources that would cause the sequencer to halt have been
386 * asserted. If, for example, a SCSI bus reset is detected
387 * while we are fielding a different, pausing, interrupt type,
388 * we don't want to release the sequencer before going back
389 * into our interrupt handler and dealing with this new
390 * condition.
391 */
392void
393ahd_unpause(struct ahd_softc *ahd)
394{
395 /*
396 * Automatically restore our modes to those saved
397 * prior to the first change of the mode.
398 */
399 if (ahd->saved_src_mode != AHD_MODE_UNKNOWN
400 && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) {
401 if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0)
402 ahd_reset_cmds_pending(ahd);
403 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
404 }
405
406 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0)
407 ahd_outb(ahd, HCNTRL, ahd->unpause);
408
409 ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN);
410}
411
412/*********************** Scatter Gather List Handling *************************/
413void *
414ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
415 void *sgptr, dma_addr_t addr, bus_size_t len, int last)
416{
417 scb->sg_count++;
418 if (sizeof(dma_addr_t) > 4
419 && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
420 struct ahd_dma64_seg *sg;
421
422 sg = (struct ahd_dma64_seg *)sgptr;
423 sg->addr = ahd_htole64(addr);
424 sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0));
425 return (sg + 1);
426 } else {
427 struct ahd_dma_seg *sg;
270 428
429 sg = (struct ahd_dma_seg *)sgptr;
430 sg->addr = ahd_htole32(addr & 0xFFFFFFFF);
431 sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000)
432 | (last ? AHD_DMA_LAST_SEG : 0));
433 return (sg + 1);
434 }
435}
436
437static void
438ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb)
439{
440 /* XXX Handle target mode SCBs. */
441 scb->crc_retry_count = 0;
442 if ((scb->flags & SCB_PACKETIZED) != 0) {
443 /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */
444 scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE;
445 } else {
446 if (ahd_get_transfer_length(scb) & 0x01)
447 scb->hscb->task_attribute = SCB_XFERLEN_ODD;
448 else
449 scb->hscb->task_attribute = 0;
450 }
451
452 if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR
453 || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0)
454 scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr =
455 ahd_htole32(scb->sense_busaddr);
456}
457
458static void
459ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb)
460{
461 /*
462 * Copy the first SG into the "current" data ponter area.
463 */
464 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
465 struct ahd_dma64_seg *sg;
466
467 sg = (struct ahd_dma64_seg *)scb->sg_list;
468 scb->hscb->dataptr = sg->addr;
469 scb->hscb->datacnt = sg->len;
470 } else {
471 struct ahd_dma_seg *sg;
472 uint32_t *dataptr_words;
473
474 sg = (struct ahd_dma_seg *)scb->sg_list;
475 dataptr_words = (uint32_t*)&scb->hscb->dataptr;
476 dataptr_words[0] = sg->addr;
477 dataptr_words[1] = 0;
478 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
479 uint64_t high_addr;
480
481 high_addr = ahd_le32toh(sg->len) & 0x7F000000;
482 scb->hscb->dataptr |= ahd_htole64(high_addr << 8);
483 }
484 scb->hscb->datacnt = sg->len;
485 }
486 /*
487 * Note where to find the SG entries in bus space.
488 * We also set the full residual flag which the
489 * sequencer will clear as soon as a data transfer
490 * occurs.
491 */
492 scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID);
493}
494
495static void
496ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb)
497{
498 scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL);
499 scb->hscb->dataptr = 0;
500 scb->hscb->datacnt = 0;
501}
502
503/************************** Memory mapping routines ***************************/
504static void *
505ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)
506{
507 dma_addr_t sg_offset;
508
509 /* sg_list_phys points to entry 1, not 0 */
510 sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd));
511 return ((uint8_t *)scb->sg_list + sg_offset);
512}
513
514static uint32_t
515ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg)
516{
517 dma_addr_t sg_offset;
518
519 /* sg_list_phys points to entry 1, not 0 */
520 sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)
521 - ahd_sg_size(ahd);
522
523 return (scb->sg_list_busaddr + sg_offset);
524}
525
526static void
527ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op)
528{
529 ahd_dmamap_sync(ahd, ahd->scb_data.hscb_dmat,
530 scb->hscb_map->dmamap,
531 /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,
532 /*len*/sizeof(*scb->hscb), op);
533}
534
535void
536ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op)
537{
538 if (scb->sg_count == 0)
539 return;
540
541 ahd_dmamap_sync(ahd, ahd->scb_data.sg_dmat,
542 scb->sg_map->dmamap,
543 /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd),
544 /*len*/ahd_sg_size(ahd) * scb->sg_count, op);
545}
546
547static void
548ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op)
549{
550 ahd_dmamap_sync(ahd, ahd->scb_data.sense_dmat,
551 scb->sense_map->dmamap,
552 /*offset*/scb->sense_busaddr,
553 /*len*/AHD_SENSE_BUFSIZE, op);
554}
555
556#ifdef AHD_TARGET_MODE
557static uint32_t
558ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
559{
560 return (((uint8_t *)&ahd->targetcmds[index])
561 - (uint8_t *)ahd->qoutfifo);
562}
563#endif
564
565/*********************** Miscelaneous Support Functions ***********************/
566/*
567 * Return pointers to the transfer negotiation information
568 * for the specified our_id/remote_id pair.
569 */
570struct ahd_initiator_tinfo *
571ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
572 u_int remote_id, struct ahd_tmode_tstate **tstate)
573{
574 /*
575 * Transfer data structures are stored from the perspective
576 * of the target role. Since the parameters for a connection
577 * in the initiator role to a given target are the same as
578 * when the roles are reversed, we pretend we are the target.
579 */
580 if (channel == 'B')
581 our_id += 8;
582 *tstate = ahd->enabled_targets[our_id];
583 return (&(*tstate)->transinfo[remote_id]);
584}
585
586uint16_t
587ahd_inw(struct ahd_softc *ahd, u_int port)
588{
589 /*
590 * Read high byte first as some registers increment
591 * or have other side effects when the low byte is
592 * read.
593 */
594 uint16_t r = ahd_inb(ahd, port+1) << 8;
595 return r | ahd_inb(ahd, port);
596}
597
598void
599ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
600{
601 /*
602 * Write low byte first to accomodate registers
603 * such as PRGMCNT where the order maters.
604 */
605 ahd_outb(ahd, port, value & 0xFF);
606 ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
607}
608
609uint32_t
610ahd_inl(struct ahd_softc *ahd, u_int port)
611{
612 return ((ahd_inb(ahd, port))
613 | (ahd_inb(ahd, port+1) << 8)
614 | (ahd_inb(ahd, port+2) << 16)
615 | (ahd_inb(ahd, port+3) << 24));
616}
617
618void
619ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)
620{
621 ahd_outb(ahd, port, (value) & 0xFF);
622 ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF);
623 ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF);
624 ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF);
625}
626
627uint64_t
628ahd_inq(struct ahd_softc *ahd, u_int port)
629{
630 return ((ahd_inb(ahd, port))
631 | (ahd_inb(ahd, port+1) << 8)
632 | (ahd_inb(ahd, port+2) << 16)
633 | (ahd_inb(ahd, port+3) << 24)
634 | (((uint64_t)ahd_inb(ahd, port+4)) << 32)
635 | (((uint64_t)ahd_inb(ahd, port+5)) << 40)
636 | (((uint64_t)ahd_inb(ahd, port+6)) << 48)
637 | (((uint64_t)ahd_inb(ahd, port+7)) << 56));
638}
639
640void
641ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value)
642{
643 ahd_outb(ahd, port, value & 0xFF);
644 ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
645 ahd_outb(ahd, port+2, (value >> 16) & 0xFF);
646 ahd_outb(ahd, port+3, (value >> 24) & 0xFF);
647 ahd_outb(ahd, port+4, (value >> 32) & 0xFF);
648 ahd_outb(ahd, port+5, (value >> 40) & 0xFF);
649 ahd_outb(ahd, port+6, (value >> 48) & 0xFF);
650 ahd_outb(ahd, port+7, (value >> 56) & 0xFF);
651}
652
653u_int
654ahd_get_scbptr(struct ahd_softc *ahd)
655{
656 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
657 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
658 return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8));
659}
660
661void
662ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr)
663{
664 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
665 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
666 ahd_outb(ahd, SCBPTR, scbptr & 0xFF);
667 ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF);
668}
669
670#if 0 /* unused */
671static u_int
672ahd_get_hnscb_qoff(struct ahd_softc *ahd)
673{
674 return (ahd_inw_atomic(ahd, HNSCB_QOFF));
675}
676#endif
677
678static void
679ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value)
680{
681 ahd_outw_atomic(ahd, HNSCB_QOFF, value);
682}
683
684#if 0 /* unused */
685static u_int
686ahd_get_hescb_qoff(struct ahd_softc *ahd)
687{
688 return (ahd_inb(ahd, HESCB_QOFF));
689}
690#endif
691
692static void
693ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value)
694{
695 ahd_outb(ahd, HESCB_QOFF, value);
696}
697
698static u_int
699ahd_get_snscb_qoff(struct ahd_softc *ahd)
700{
701 u_int oldvalue;
702
703 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
704 oldvalue = ahd_inw(ahd, SNSCB_QOFF);
705 ahd_outw(ahd, SNSCB_QOFF, oldvalue);
706 return (oldvalue);
707}
708
709static void
710ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value)
711{
712 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
713 ahd_outw(ahd, SNSCB_QOFF, value);
714}
715
716#if 0 /* unused */
717static u_int
718ahd_get_sescb_qoff(struct ahd_softc *ahd)
719{
720 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
721 return (ahd_inb(ahd, SESCB_QOFF));
722}
723#endif
724
725static void
726ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value)
727{
728 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
729 ahd_outb(ahd, SESCB_QOFF, value);
730}
731
732#if 0 /* unused */
733static u_int
734ahd_get_sdscb_qoff(struct ahd_softc *ahd)
735{
736 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
737 return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8));
738}
739#endif
740
741static void
742ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value)
743{
744 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
745 ahd_outb(ahd, SDSCB_QOFF, value & 0xFF);
746 ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF);
747}
748
749u_int
750ahd_inb_scbram(struct ahd_softc *ahd, u_int offset)
751{
752 u_int value;
753
754 /*
755 * Workaround PCI-X Rev A. hardware bug.
756 * After a host read of SCB memory, the chip
757 * may become confused into thinking prefetch
758 * was required. This starts the discard timer
759 * running and can cause an unexpected discard
760 * timer interrupt. The work around is to read
761 * a normal register prior to the exhaustion of
762 * the discard timer. The mode pointer register
763 * has no side effects and so serves well for
764 * this purpose.
765 *
766 * Razor #528
767 */
768 value = ahd_inb(ahd, offset);
769 if ((ahd->bugs & AHD_PCIX_SCBRAM_RD_BUG) != 0)
770 ahd_inb(ahd, MODE_PTR);
771 return (value);
772}
773
774u_int
775ahd_inw_scbram(struct ahd_softc *ahd, u_int offset)
776{
777 return (ahd_inb_scbram(ahd, offset)
778 | (ahd_inb_scbram(ahd, offset+1) << 8));
779}
780
781static uint32_t
782ahd_inl_scbram(struct ahd_softc *ahd, u_int offset)
783{
784 return (ahd_inw_scbram(ahd, offset)
785 | (ahd_inw_scbram(ahd, offset+2) << 16));
786}
787
788static uint64_t
789ahd_inq_scbram(struct ahd_softc *ahd, u_int offset)
790{
791 return (ahd_inl_scbram(ahd, offset)
792 | ((uint64_t)ahd_inl_scbram(ahd, offset+4)) << 32);
793}
794
795struct scb *
796ahd_lookup_scb(struct ahd_softc *ahd, u_int tag)
797{
798 struct scb* scb;
799
800 if (tag >= AHD_SCB_MAX)
801 return (NULL);
802 scb = ahd->scb_data.scbindex[tag];
803 if (scb != NULL)
804 ahd_sync_scb(ahd, scb,
805 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
806 return (scb);
807}
808
809static void
810ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb)
811{
812 struct hardware_scb *q_hscb;
813 struct map_node *q_hscb_map;
814 uint32_t saved_hscb_busaddr;
815
816 /*
817 * Our queuing method is a bit tricky. The card
818 * knows in advance which HSCB (by address) to download,
819 * and we can't disappoint it. To achieve this, the next
820 * HSCB to download is saved off in ahd->next_queued_hscb.
821 * When we are called to queue "an arbitrary scb",
822 * we copy the contents of the incoming HSCB to the one
823 * the sequencer knows about, swap HSCB pointers and
824 * finally assign the SCB to the tag indexed location
825 * in the scb_array. This makes sure that we can still
826 * locate the correct SCB by SCB_TAG.
827 */
828 q_hscb = ahd->next_queued_hscb;
829 q_hscb_map = ahd->next_queued_hscb_map;
830 saved_hscb_busaddr = q_hscb->hscb_busaddr;
831 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
832 q_hscb->hscb_busaddr = saved_hscb_busaddr;
833 q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
834
835 /* Now swap HSCB pointers. */
836 ahd->next_queued_hscb = scb->hscb;
837 ahd->next_queued_hscb_map = scb->hscb_map;
838 scb->hscb = q_hscb;
839 scb->hscb_map = q_hscb_map;
840
841 /* Now define the mapping from tag to SCB in the scbindex */
842 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb;
843}
844
845/*
846 * Tell the sequencer about a new transaction to execute.
847 */
848void
849ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb)
850{
851 ahd_swap_with_next_hscb(ahd, scb);
852
853 if (SCBID_IS_NULL(SCB_GET_TAG(scb)))
854 panic("Attempt to queue invalid SCB tag %x\n",
855 SCB_GET_TAG(scb));
856
857 /*
858 * Keep a history of SCBs we've downloaded in the qinfifo.
859 */
860 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
861 ahd->qinfifonext++;
862
863 if (scb->sg_count != 0)
864 ahd_setup_data_scb(ahd, scb);
865 else
866 ahd_setup_noxfer_scb(ahd, scb);
867 ahd_setup_scb_common(ahd, scb);
868
869 /*
870 * Make sure our data is consistent from the
871 * perspective of the adapter.
872 */
873 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
874
875#ifdef AHD_DEBUG
876 if ((ahd_debug & AHD_SHOW_QUEUE) != 0) {
877 uint64_t host_dataptr;
878
879 host_dataptr = ahd_le64toh(scb->hscb->dataptr);
880 printf("%s: Queueing SCB %d:0x%x bus addr 0x%x - 0x%x%x/0x%x\n",
881 ahd_name(ahd),
882 SCB_GET_TAG(scb), scb->hscb->scsiid,
883 ahd_le32toh(scb->hscb->hscb_busaddr),
884 (u_int)((host_dataptr >> 32) & 0xFFFFFFFF),
885 (u_int)(host_dataptr & 0xFFFFFFFF),
886 ahd_le32toh(scb->hscb->datacnt));
887 }
888#endif
889 /* Tell the adapter about the newly queued SCB */
890 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
891}
892
893/************************** Interrupt Processing ******************************/
894static void
895ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
896{
897 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
898 /*offset*/0,
899 /*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
900}
901
902static void
903ahd_sync_tqinfifo(struct ahd_softc *ahd, int op)
904{
905#ifdef AHD_TARGET_MODE
906 if ((ahd->flags & AHD_TARGETROLE) != 0) {
907 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
908 ahd->shared_data_map.dmamap,
909 ahd_targetcmd_offset(ahd, 0),
910 sizeof(struct target_cmd) * AHD_TMODE_CMDS,
911 op);
912 }
913#endif
914}
915
916/*
917 * See if the firmware has posted any completed commands
918 * into our in-core command complete fifos.
919 */
920#define AHD_RUN_QOUTFIFO 0x1
921#define AHD_RUN_TQINFIFO 0x2
922static u_int
923ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
924{
925 u_int retval;
926
927 retval = 0;
928 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
929 /*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
930 /*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
931 if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
932 == ahd->qoutfifonext_valid_tag)
933 retval |= AHD_RUN_QOUTFIFO;
934#ifdef AHD_TARGET_MODE
935 if ((ahd->flags & AHD_TARGETROLE) != 0
936 && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) {
937 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
938 ahd->shared_data_map.dmamap,
939 ahd_targetcmd_offset(ahd, ahd->tqinfifofnext),
940 /*len*/sizeof(struct target_cmd),
941 BUS_DMASYNC_POSTREAD);
942 if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0)
943 retval |= AHD_RUN_TQINFIFO;
944 }
945#endif
946 return (retval);
947}
948
949/*
950 * Catch an interrupt from the adapter
951 */
952int
953ahd_intr(struct ahd_softc *ahd)
954{
955 u_int intstat;
956
957 if ((ahd->pause & INTEN) == 0) {
958 /*
959 * Our interrupt is not enabled on the chip
960 * and may be disabled for re-entrancy reasons,
961 * so just return. This is likely just a shared
962 * interrupt.
963 */
964 return (0);
965 }
966
967 /*
968 * Instead of directly reading the interrupt status register,
969 * infer the cause of the interrupt by checking our in-core
970 * completion queues. This avoids a costly PCI bus read in
971 * most cases.
972 */
973 if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0
974 && (ahd_check_cmdcmpltqueues(ahd) != 0))
975 intstat = CMDCMPLT;
976 else
977 intstat = ahd_inb(ahd, INTSTAT);
978
979 if ((intstat & INT_PEND) == 0)
980 return (0);
981
982 if (intstat & CMDCMPLT) {
983 ahd_outb(ahd, CLRINT, CLRCMDINT);
984
985 /*
986 * Ensure that the chip sees that we've cleared
987 * this interrupt before we walk the output fifo.
988 * Otherwise, we may, due to posted bus writes,
989 * clear the interrupt after we finish the scan,
990 * and after the sequencer has added new entries
991 * and asserted the interrupt again.
992 */
993 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
994 if (ahd_is_paused(ahd)) {
995 /*
996 * Potentially lost SEQINT.
997 * If SEQINTCODE is non-zero,
998 * simulate the SEQINT.
999 */
1000 if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT)
1001 intstat |= SEQINT;
1002 }
1003 } else {
1004 ahd_flush_device_writes(ahd);
1005 }
1006 ahd_run_qoutfifo(ahd);
1007 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++;
1008 ahd->cmdcmplt_total++;
1009#ifdef AHD_TARGET_MODE
1010 if ((ahd->flags & AHD_TARGETROLE) != 0)
1011 ahd_run_tqinfifo(ahd, /*paused*/FALSE);
1012#endif
1013 }
1014
1015 /*
1016 * Handle statuses that may invalidate our cached
1017 * copy of INTSTAT separately.
1018 */
1019 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) {
1020 /* Hot eject. Do nothing */
1021 } else if (intstat & HWERRINT) {
1022 ahd_handle_hwerrint(ahd);
1023 } else if ((intstat & (PCIINT|SPLTINT)) != 0) {
1024 ahd->bus_intr(ahd);
1025 } else {
1026
1027 if ((intstat & SEQINT) != 0)
1028 ahd_handle_seqint(ahd, intstat);
1029
1030 if ((intstat & SCSIINT) != 0)
1031 ahd_handle_scsiint(ahd, intstat);
1032 }
1033 return (1);
1034}
1035
1036/******************************** Private Inlines *****************************/
271static __inline void 1037static __inline void
272ahd_assert_atn(struct ahd_softc *ahd) 1038ahd_assert_atn(struct ahd_softc *ahd)
273{ 1039{
@@ -280,7 +1046,7 @@ ahd_assert_atn(struct ahd_softc *ahd)
280 * are currently in a packetized transfer. We could 1046 * are currently in a packetized transfer. We could
281 * just as easily be sending or receiving a message. 1047 * just as easily be sending or receiving a message.
282 */ 1048 */
283static __inline int 1049static int
284ahd_currently_packetized(struct ahd_softc *ahd) 1050ahd_currently_packetized(struct ahd_softc *ahd)
285{ 1051{
286 ahd_mode_state saved_modes; 1052 ahd_mode_state saved_modes;
@@ -896,7 +1662,7 @@ clrchn:
896 * a copy of the first byte (little endian) of the sgptr 1662 * a copy of the first byte (little endian) of the sgptr
897 * hscb field. 1663 * hscb field.
898 */ 1664 */
899void 1665static void
900ahd_run_qoutfifo(struct ahd_softc *ahd) 1666ahd_run_qoutfifo(struct ahd_softc *ahd)
901{ 1667{
902 struct ahd_completion *completion; 1668 struct ahd_completion *completion;
@@ -935,7 +1701,7 @@ ahd_run_qoutfifo(struct ahd_softc *ahd)
935} 1701}
936 1702
937/************************* Interrupt Handling *********************************/ 1703/************************* Interrupt Handling *********************************/
938void 1704static void
939ahd_handle_hwerrint(struct ahd_softc *ahd) 1705ahd_handle_hwerrint(struct ahd_softc *ahd)
940{ 1706{
941 /* 1707 /*
@@ -1009,7 +1775,7 @@ ahd_dump_sglist(struct scb *scb)
1009} 1775}
1010#endif /* AHD_DEBUG */ 1776#endif /* AHD_DEBUG */
1011 1777
1012void 1778static void
1013ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 1779ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
1014{ 1780{
1015 u_int seqintcode; 1781 u_int seqintcode;
@@ -1621,7 +2387,7 @@ ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
1621 ahd_unpause(ahd); 2387 ahd_unpause(ahd);
1622} 2388}
1623 2389
1624void 2390static void
1625ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 2391ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1626{ 2392{
1627 struct scb *scb; 2393 struct scb *scb;
@@ -3571,11 +4337,11 @@ ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3571 devinfo->target, devinfo->lun); 4337 devinfo->target, devinfo->lun);
3572} 4338}
3573 4339
3574static struct ahd_phase_table_entry* 4340static const struct ahd_phase_table_entry*
3575ahd_lookup_phase_entry(int phase) 4341ahd_lookup_phase_entry(int phase)
3576{ 4342{
3577 struct ahd_phase_table_entry *entry; 4343 const struct ahd_phase_table_entry *entry;
3578 struct ahd_phase_table_entry *last_entry; 4344 const struct ahd_phase_table_entry *last_entry;
3579 4345
3580 /* 4346 /*
3581 * num_phases doesn't include the default entry which 4347 * num_phases doesn't include the default entry which
@@ -3941,7 +4707,7 @@ ahd_clear_msg_state(struct ahd_softc *ahd)
3941 */ 4707 */
3942static void 4708static void
3943ahd_handle_message_phase(struct ahd_softc *ahd) 4709ahd_handle_message_phase(struct ahd_softc *ahd)
3944{ 4710{
3945 struct ahd_devinfo devinfo; 4711 struct ahd_devinfo devinfo;
3946 u_int bus_phase; 4712 u_int bus_phase;
3947 int end_session; 4713 int end_session;
@@ -5983,8 +6749,7 @@ found:
5983 */ 6749 */
5984void 6750void
5985ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 6751ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5986{ 6752{
5987
5988 /* Clean up for the next user */ 6753 /* Clean up for the next user */
5989 scb->flags = SCB_FLAG_NONE; 6754 scb->flags = SCB_FLAG_NONE;
5990 scb->hscb->control = 0; 6755 scb->hscb->control = 0;
@@ -6272,6 +7037,24 @@ static const char *termstat_strings[] = {
6272 "Not Configured" 7037 "Not Configured"
6273}; 7038};
6274 7039
7040/***************************** Timer Facilities *******************************/
7041#define ahd_timer_init init_timer
7042#define ahd_timer_stop del_timer_sync
7043typedef void ahd_linux_callback_t (u_long);
7044
7045static void
7046ahd_timer_reset(ahd_timer_t *timer, int usec, ahd_callback_t *func, void *arg)
7047{
7048 struct ahd_softc *ahd;
7049
7050 ahd = (struct ahd_softc *)arg;
7051 del_timer(timer);
7052 timer->data = (u_long)arg;
7053 timer->expires = jiffies + (usec * HZ)/1000000;
7054 timer->function = (ahd_linux_callback_t*)func;
7055 add_timer(timer);
7056}
7057
6275/* 7058/*
6276 * Start the board, ready for normal operation 7059 * Start the board, ready for normal operation
6277 */ 7060 */
@@ -7370,7 +8153,7 @@ ahd_qinfifo_count(struct ahd_softc *ahd)
7370 + ARRAY_SIZE(ahd->qinfifo) - wrap_qinpos); 8153 + ARRAY_SIZE(ahd->qinfifo) - wrap_qinpos);
7371} 8154}
7372 8155
7373void 8156static void
7374ahd_reset_cmds_pending(struct ahd_softc *ahd) 8157ahd_reset_cmds_pending(struct ahd_softc *ahd)
7375{ 8158{
7376 struct scb *scb; 8159 struct scb *scb;
@@ -8571,7 +9354,7 @@ ahd_loadseq(struct ahd_softc *ahd)
8571 struct cs cs_table[num_critical_sections]; 9354 struct cs cs_table[num_critical_sections];
8572 u_int begin_set[num_critical_sections]; 9355 u_int begin_set[num_critical_sections];
8573 u_int end_set[num_critical_sections]; 9356 u_int end_set[num_critical_sections];
8574 struct patch *cur_patch; 9357 const struct patch *cur_patch;
8575 u_int cs_count; 9358 u_int cs_count;
8576 u_int cur_cs; 9359 u_int cur_cs;
8577 u_int i; 9360 u_int i;
@@ -8726,11 +9509,11 @@ ahd_loadseq(struct ahd_softc *ahd)
8726} 9509}
8727 9510
8728static int 9511static int
8729ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 9512ahd_check_patch(struct ahd_softc *ahd, const struct patch **start_patch,
8730 u_int start_instr, u_int *skip_addr) 9513 u_int start_instr, u_int *skip_addr)
8731{ 9514{
8732 struct patch *cur_patch; 9515 const struct patch *cur_patch;
8733 struct patch *last_patch; 9516 const struct patch *last_patch;
8734 u_int num_patches; 9517 u_int num_patches;
8735 9518
8736 num_patches = ARRAY_SIZE(patches); 9519 num_patches = ARRAY_SIZE(patches);
@@ -8764,7 +9547,7 @@ ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8764static u_int 9547static u_int
8765ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 9548ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8766{ 9549{
8767 struct patch *cur_patch; 9550 const struct patch *cur_patch;
8768 int address_offset; 9551 int address_offset;
8769 u_int skip_addr; 9552 u_int skip_addr;
8770 u_int i; 9553 u_int i;
@@ -8895,7 +9678,7 @@ sized:
8895} 9678}
8896 9679
8897int 9680int
8898ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 9681ahd_print_register(const ahd_reg_parse_entry_t *table, u_int num_entries,
8899 const char *name, u_int address, u_int value, 9682 const char *name, u_int address, u_int value,
8900 u_int *cur_column, u_int wrap_point) 9683 u_int *cur_column, u_int wrap_point)
8901{ 9684{
@@ -9886,7 +10669,7 @@ ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
9886#endif 10669#endif
9887} 10670}
9888 10671
9889void 10672static void
9890ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 10673ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
9891{ 10674{
9892 struct target_cmd *cmd; 10675 struct target_cmd *cmd;
diff --git a/drivers/scsi/aic7xxx/aic79xx_inline.h b/drivers/scsi/aic7xxx/aic79xx_inline.h
index 45e55575a0fa..5f12cf9d99d0 100644
--- a/drivers/scsi/aic7xxx/aic79xx_inline.h
+++ b/drivers/scsi/aic7xxx/aic79xx_inline.h
@@ -63,18 +63,15 @@ static __inline ahd_mode_state ahd_build_mode_state(struct ahd_softc *ahd,
63static __inline void ahd_extract_mode_state(struct ahd_softc *ahd, 63static __inline void ahd_extract_mode_state(struct ahd_softc *ahd,
64 ahd_mode_state state, 64 ahd_mode_state state,
65 ahd_mode *src, ahd_mode *dst); 65 ahd_mode *src, ahd_mode *dst);
66static __inline void ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, 66
67 ahd_mode dst); 67void ahd_set_modes(struct ahd_softc *ahd, ahd_mode src,
68static __inline void ahd_update_modes(struct ahd_softc *ahd); 68 ahd_mode dst);
69static __inline void ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode, 69ahd_mode_state ahd_save_modes(struct ahd_softc *ahd);
70 ahd_mode dstmode, const char *file, 70void ahd_restore_modes(struct ahd_softc *ahd,
71 int line); 71 ahd_mode_state state);
72static __inline ahd_mode_state ahd_save_modes(struct ahd_softc *ahd); 72int ahd_is_paused(struct ahd_softc *ahd);
73static __inline void ahd_restore_modes(struct ahd_softc *ahd, 73void ahd_pause(struct ahd_softc *ahd);
74 ahd_mode_state state); 74void ahd_unpause(struct ahd_softc *ahd);
75static __inline int ahd_is_paused(struct ahd_softc *ahd);
76static __inline void ahd_pause(struct ahd_softc *ahd);
77static __inline void ahd_unpause(struct ahd_softc *ahd);
78 75
79static __inline void 76static __inline void
80ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 77ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
@@ -99,256 +96,16 @@ ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state,
99 *dst = (state & DST_MODE) >> DST_MODE_SHIFT; 96 *dst = (state & DST_MODE) >> DST_MODE_SHIFT;
100} 97}
101 98
102static __inline void
103ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
104{
105 if (ahd->src_mode == src && ahd->dst_mode == dst)
106 return;
107#ifdef AHD_DEBUG
108 if (ahd->src_mode == AHD_MODE_UNKNOWN
109 || ahd->dst_mode == AHD_MODE_UNKNOWN)
110 panic("Setting mode prior to saving it.\n");
111 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
112 printf("%s: Setting mode 0x%x\n", ahd_name(ahd),
113 ahd_build_mode_state(ahd, src, dst));
114#endif
115 ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst));
116 ahd->src_mode = src;
117 ahd->dst_mode = dst;
118}
119
120static __inline void
121ahd_update_modes(struct ahd_softc *ahd)
122{
123 ahd_mode_state mode_ptr;
124 ahd_mode src;
125 ahd_mode dst;
126
127 mode_ptr = ahd_inb(ahd, MODE_PTR);
128#ifdef AHD_DEBUG
129 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
130 printf("Reading mode 0x%x\n", mode_ptr);
131#endif
132 ahd_extract_mode_state(ahd, mode_ptr, &src, &dst);
133 ahd_known_modes(ahd, src, dst);
134}
135
136static __inline void
137ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
138 ahd_mode dstmode, const char *file, int line)
139{
140#ifdef AHD_DEBUG
141 if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0
142 || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) {
143 panic("%s:%s:%d: Mode assertion failed.\n",
144 ahd_name(ahd), file, line);
145 }
146#endif
147}
148
149static __inline ahd_mode_state
150ahd_save_modes(struct ahd_softc *ahd)
151{
152 if (ahd->src_mode == AHD_MODE_UNKNOWN
153 || ahd->dst_mode == AHD_MODE_UNKNOWN)
154 ahd_update_modes(ahd);
155
156 return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode));
157}
158
159static __inline void
160ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state)
161{
162 ahd_mode src;
163 ahd_mode dst;
164
165 ahd_extract_mode_state(ahd, state, &src, &dst);
166 ahd_set_modes(ahd, src, dst);
167}
168
169#define AHD_ASSERT_MODES(ahd, source, dest) \
170 ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__);
171
172/*
173 * Determine whether the sequencer has halted code execution.
174 * Returns non-zero status if the sequencer is stopped.
175 */
176static __inline int
177ahd_is_paused(struct ahd_softc *ahd)
178{
179 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0);
180}
181
182/*
183 * Request that the sequencer stop and wait, indefinitely, for it
184 * to stop. The sequencer will only acknowledge that it is paused
185 * once it has reached an instruction boundary and PAUSEDIS is
186 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
187 * for critical sections.
188 */
189static __inline void
190ahd_pause(struct ahd_softc *ahd)
191{
192 ahd_outb(ahd, HCNTRL, ahd->pause);
193
194 /*
195 * Since the sequencer can disable pausing in a critical section, we
196 * must loop until it actually stops.
197 */
198 while (ahd_is_paused(ahd) == 0)
199 ;
200}
201
202/*
203 * Allow the sequencer to continue program execution.
204 * We check here to ensure that no additional interrupt
205 * sources that would cause the sequencer to halt have been
206 * asserted. If, for example, a SCSI bus reset is detected
207 * while we are fielding a different, pausing, interrupt type,
208 * we don't want to release the sequencer before going back
209 * into our interrupt handler and dealing with this new
210 * condition.
211 */
212static __inline void
213ahd_unpause(struct ahd_softc *ahd)
214{
215 /*
216 * Automatically restore our modes to those saved
217 * prior to the first change of the mode.
218 */
219 if (ahd->saved_src_mode != AHD_MODE_UNKNOWN
220 && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) {
221 if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0)
222 ahd_reset_cmds_pending(ahd);
223 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
224 }
225
226 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0)
227 ahd_outb(ahd, HCNTRL, ahd->unpause);
228
229 ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN);
230}
231
232/*********************** Scatter Gather List Handling *************************/ 99/*********************** Scatter Gather List Handling *************************/
233static __inline void *ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb, 100void *ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
234 void *sgptr, dma_addr_t addr, 101 void *sgptr, dma_addr_t addr,
235 bus_size_t len, int last); 102 bus_size_t len, int last);
236static __inline void ahd_setup_scb_common(struct ahd_softc *ahd,
237 struct scb *scb);
238static __inline void ahd_setup_data_scb(struct ahd_softc *ahd,
239 struct scb *scb);
240static __inline void ahd_setup_noxfer_scb(struct ahd_softc *ahd,
241 struct scb *scb);
242
243static __inline void *
244ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
245 void *sgptr, dma_addr_t addr, bus_size_t len, int last)
246{
247 scb->sg_count++;
248 if (sizeof(dma_addr_t) > 4
249 && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
250 struct ahd_dma64_seg *sg;
251
252 sg = (struct ahd_dma64_seg *)sgptr;
253 sg->addr = ahd_htole64(addr);
254 sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0));
255 return (sg + 1);
256 } else {
257 struct ahd_dma_seg *sg;
258
259 sg = (struct ahd_dma_seg *)sgptr;
260 sg->addr = ahd_htole32(addr & 0xFFFFFFFF);
261 sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000)
262 | (last ? AHD_DMA_LAST_SEG : 0));
263 return (sg + 1);
264 }
265}
266
267static __inline void
268ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb)
269{
270 /* XXX Handle target mode SCBs. */
271 scb->crc_retry_count = 0;
272 if ((scb->flags & SCB_PACKETIZED) != 0) {
273 /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */
274 scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE;
275 } else {
276 if (ahd_get_transfer_length(scb) & 0x01)
277 scb->hscb->task_attribute = SCB_XFERLEN_ODD;
278 else
279 scb->hscb->task_attribute = 0;
280 }
281
282 if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR
283 || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0)
284 scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr =
285 ahd_htole32(scb->sense_busaddr);
286}
287
288static __inline void
289ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb)
290{
291 /*
292 * Copy the first SG into the "current" data ponter area.
293 */
294 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
295 struct ahd_dma64_seg *sg;
296
297 sg = (struct ahd_dma64_seg *)scb->sg_list;
298 scb->hscb->dataptr = sg->addr;
299 scb->hscb->datacnt = sg->len;
300 } else {
301 struct ahd_dma_seg *sg;
302 uint32_t *dataptr_words;
303
304 sg = (struct ahd_dma_seg *)scb->sg_list;
305 dataptr_words = (uint32_t*)&scb->hscb->dataptr;
306 dataptr_words[0] = sg->addr;
307 dataptr_words[1] = 0;
308 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
309 uint64_t high_addr;
310
311 high_addr = ahd_le32toh(sg->len) & 0x7F000000;
312 scb->hscb->dataptr |= ahd_htole64(high_addr << 8);
313 }
314 scb->hscb->datacnt = sg->len;
315 }
316 /*
317 * Note where to find the SG entries in bus space.
318 * We also set the full residual flag which the
319 * sequencer will clear as soon as a data transfer
320 * occurs.
321 */
322 scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID);
323}
324
325static __inline void
326ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb)
327{
328 scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL);
329 scb->hscb->dataptr = 0;
330 scb->hscb->datacnt = 0;
331}
332 103
333/************************** Memory mapping routines ***************************/ 104/************************** Memory mapping routines ***************************/
334static __inline size_t ahd_sg_size(struct ahd_softc *ahd); 105static __inline size_t ahd_sg_size(struct ahd_softc *ahd);
335static __inline void * 106
336 ahd_sg_bus_to_virt(struct ahd_softc *ahd, 107void ahd_sync_sglist(struct ahd_softc *ahd,
337 struct scb *scb, 108 struct scb *scb, int op);
338 uint32_t sg_busaddr);
339static __inline uint32_t
340 ahd_sg_virt_to_bus(struct ahd_softc *ahd,
341 struct scb *scb,
342 void *sg);
343static __inline void ahd_sync_scb(struct ahd_softc *ahd,
344 struct scb *scb, int op);
345static __inline void ahd_sync_sglist(struct ahd_softc *ahd,
346 struct scb *scb, int op);
347static __inline void ahd_sync_sense(struct ahd_softc *ahd,
348 struct scb *scb, int op);
349static __inline uint32_t
350 ahd_targetcmd_offset(struct ahd_softc *ahd,
351 u_int index);
352 109
353static __inline size_t 110static __inline size_t
354ahd_sg_size(struct ahd_softc *ahd) 111ahd_sg_size(struct ahd_softc *ahd)
@@ -358,104 +115,32 @@ ahd_sg_size(struct ahd_softc *ahd)
358 return (sizeof(struct ahd_dma_seg)); 115 return (sizeof(struct ahd_dma_seg));
359} 116}
360 117
361static __inline void *
362ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)
363{
364 dma_addr_t sg_offset;
365
366 /* sg_list_phys points to entry 1, not 0 */
367 sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd));
368 return ((uint8_t *)scb->sg_list + sg_offset);
369}
370
371static __inline uint32_t
372ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg)
373{
374 dma_addr_t sg_offset;
375
376 /* sg_list_phys points to entry 1, not 0 */
377 sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)
378 - ahd_sg_size(ahd);
379
380 return (scb->sg_list_busaddr + sg_offset);
381}
382
383static __inline void
384ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op)
385{
386 ahd_dmamap_sync(ahd, ahd->scb_data.hscb_dmat,
387 scb->hscb_map->dmamap,
388 /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,
389 /*len*/sizeof(*scb->hscb), op);
390}
391
392static __inline void
393ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op)
394{
395 if (scb->sg_count == 0)
396 return;
397
398 ahd_dmamap_sync(ahd, ahd->scb_data.sg_dmat,
399 scb->sg_map->dmamap,
400 /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd),
401 /*len*/ahd_sg_size(ahd) * scb->sg_count, op);
402}
403
404static __inline void
405ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op)
406{
407 ahd_dmamap_sync(ahd, ahd->scb_data.sense_dmat,
408 scb->sense_map->dmamap,
409 /*offset*/scb->sense_busaddr,
410 /*len*/AHD_SENSE_BUFSIZE, op);
411}
412
413static __inline uint32_t
414ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
415{
416 return (((uint8_t *)&ahd->targetcmds[index])
417 - (uint8_t *)ahd->qoutfifo);
418}
419
420/*********************** Miscellaneous Support Functions ***********************/ 118/*********************** Miscellaneous Support Functions ***********************/
421static __inline struct ahd_initiator_tinfo * 119struct ahd_initiator_tinfo *
422 ahd_fetch_transinfo(struct ahd_softc *ahd, 120 ahd_fetch_transinfo(struct ahd_softc *ahd,
423 char channel, u_int our_id, 121 char channel, u_int our_id,
424 u_int remote_id, 122 u_int remote_id,
425 struct ahd_tmode_tstate **tstate); 123 struct ahd_tmode_tstate **tstate);
426static __inline uint16_t 124uint16_t
427 ahd_inw(struct ahd_softc *ahd, u_int port); 125 ahd_inw(struct ahd_softc *ahd, u_int port);
428static __inline void ahd_outw(struct ahd_softc *ahd, u_int port, 126void ahd_outw(struct ahd_softc *ahd, u_int port,
429 u_int value); 127 u_int value);
430static __inline uint32_t 128uint32_t
431 ahd_inl(struct ahd_softc *ahd, u_int port); 129 ahd_inl(struct ahd_softc *ahd, u_int port);
432static __inline void ahd_outl(struct ahd_softc *ahd, u_int port, 130void ahd_outl(struct ahd_softc *ahd, u_int port,
433 uint32_t value); 131 uint32_t value);
434static __inline uint64_t 132uint64_t
435 ahd_inq(struct ahd_softc *ahd, u_int port); 133 ahd_inq(struct ahd_softc *ahd, u_int port);
436static __inline void ahd_outq(struct ahd_softc *ahd, u_int port, 134void ahd_outq(struct ahd_softc *ahd, u_int port,
437 uint64_t value); 135 uint64_t value);
438static __inline u_int ahd_get_scbptr(struct ahd_softc *ahd); 136u_int ahd_get_scbptr(struct ahd_softc *ahd);
439static __inline void ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr); 137void ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr);
440static __inline u_int ahd_get_hnscb_qoff(struct ahd_softc *ahd); 138u_int ahd_inb_scbram(struct ahd_softc *ahd, u_int offset);
441static __inline void ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value); 139u_int ahd_inw_scbram(struct ahd_softc *ahd, u_int offset);
442static __inline u_int ahd_get_hescb_qoff(struct ahd_softc *ahd); 140struct scb *
443static __inline void ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value); 141 ahd_lookup_scb(struct ahd_softc *ahd, u_int tag);
444static __inline u_int ahd_get_snscb_qoff(struct ahd_softc *ahd); 142void ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb);
445static __inline void ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value); 143
446static __inline u_int ahd_get_sescb_qoff(struct ahd_softc *ahd);
447static __inline void ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value);
448static __inline u_int ahd_get_sdscb_qoff(struct ahd_softc *ahd);
449static __inline void ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value);
450static __inline u_int ahd_inb_scbram(struct ahd_softc *ahd, u_int offset);
451static __inline u_int ahd_inw_scbram(struct ahd_softc *ahd, u_int offset);
452static __inline uint32_t
453 ahd_inl_scbram(struct ahd_softc *ahd, u_int offset);
454static __inline uint64_t
455 ahd_inq_scbram(struct ahd_softc *ahd, u_int offset);
456static __inline void ahd_swap_with_next_hscb(struct ahd_softc *ahd,
457 struct scb *scb);
458static __inline void ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb);
459static __inline uint8_t * 144static __inline uint8_t *
460 ahd_get_sense_buf(struct ahd_softc *ahd, 145 ahd_get_sense_buf(struct ahd_softc *ahd,
461 struct scb *scb); 146 struct scb *scb);
@@ -463,25 +148,7 @@ static __inline uint32_t
463 ahd_get_sense_bufaddr(struct ahd_softc *ahd, 148 ahd_get_sense_bufaddr(struct ahd_softc *ahd,
464 struct scb *scb); 149 struct scb *scb);
465 150
466/* 151#if 0 /* unused */
467 * Return pointers to the transfer negotiation information
468 * for the specified our_id/remote_id pair.
469 */
470static __inline struct ahd_initiator_tinfo *
471ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
472 u_int remote_id, struct ahd_tmode_tstate **tstate)
473{
474 /*
475 * Transfer data structures are stored from the perspective
476 * of the target role. Since the parameters for a connection
477 * in the initiator role to a given target are the same as
478 * when the roles are reversed, we pretend we are the target.
479 */
480 if (channel == 'B')
481 our_id += 8;
482 *tstate = ahd->enabled_targets[our_id];
483 return (&(*tstate)->transinfo[remote_id]);
484}
485 152
486#define AHD_COPY_COL_IDX(dst, src) \ 153#define AHD_COPY_COL_IDX(dst, src) \
487do { \ 154do { \
@@ -489,304 +156,7 @@ do { \
489 dst->hscb->lun = src->hscb->lun; \ 156 dst->hscb->lun = src->hscb->lun; \
490} while (0) 157} while (0)
491 158
492static __inline uint16_t
493ahd_inw(struct ahd_softc *ahd, u_int port)
494{
495 /*
496 * Read high byte first as some registers increment
497 * or have other side effects when the low byte is
498 * read.
499 */
500 uint16_t r = ahd_inb(ahd, port+1) << 8;
501 return r | ahd_inb(ahd, port);
502}
503
504static __inline void
505ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
506{
507 /*
508 * Write low byte first to accomodate registers
509 * such as PRGMCNT where the order maters.
510 */
511 ahd_outb(ahd, port, value & 0xFF);
512 ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
513}
514
515static __inline uint32_t
516ahd_inl(struct ahd_softc *ahd, u_int port)
517{
518 return ((ahd_inb(ahd, port))
519 | (ahd_inb(ahd, port+1) << 8)
520 | (ahd_inb(ahd, port+2) << 16)
521 | (ahd_inb(ahd, port+3) << 24));
522}
523
524static __inline void
525ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)
526{
527 ahd_outb(ahd, port, (value) & 0xFF);
528 ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF);
529 ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF);
530 ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF);
531}
532
533static __inline uint64_t
534ahd_inq(struct ahd_softc *ahd, u_int port)
535{
536 return ((ahd_inb(ahd, port))
537 | (ahd_inb(ahd, port+1) << 8)
538 | (ahd_inb(ahd, port+2) << 16)
539 | (ahd_inb(ahd, port+3) << 24)
540 | (((uint64_t)ahd_inb(ahd, port+4)) << 32)
541 | (((uint64_t)ahd_inb(ahd, port+5)) << 40)
542 | (((uint64_t)ahd_inb(ahd, port+6)) << 48)
543 | (((uint64_t)ahd_inb(ahd, port+7)) << 56));
544}
545
546static __inline void
547ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value)
548{
549 ahd_outb(ahd, port, value & 0xFF);
550 ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
551 ahd_outb(ahd, port+2, (value >> 16) & 0xFF);
552 ahd_outb(ahd, port+3, (value >> 24) & 0xFF);
553 ahd_outb(ahd, port+4, (value >> 32) & 0xFF);
554 ahd_outb(ahd, port+5, (value >> 40) & 0xFF);
555 ahd_outb(ahd, port+6, (value >> 48) & 0xFF);
556 ahd_outb(ahd, port+7, (value >> 56) & 0xFF);
557}
558
559static __inline u_int
560ahd_get_scbptr(struct ahd_softc *ahd)
561{
562 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
563 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
564 return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8));
565}
566
567static __inline void
568ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr)
569{
570 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
571 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
572 ahd_outb(ahd, SCBPTR, scbptr & 0xFF);
573 ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF);
574}
575
576static __inline u_int
577ahd_get_hnscb_qoff(struct ahd_softc *ahd)
578{
579 return (ahd_inw_atomic(ahd, HNSCB_QOFF));
580}
581
582static __inline void
583ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value)
584{
585 ahd_outw_atomic(ahd, HNSCB_QOFF, value);
586}
587
588static __inline u_int
589ahd_get_hescb_qoff(struct ahd_softc *ahd)
590{
591 return (ahd_inb(ahd, HESCB_QOFF));
592}
593
594static __inline void
595ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value)
596{
597 ahd_outb(ahd, HESCB_QOFF, value);
598}
599
600static __inline u_int
601ahd_get_snscb_qoff(struct ahd_softc *ahd)
602{
603 u_int oldvalue;
604
605 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
606 oldvalue = ahd_inw(ahd, SNSCB_QOFF);
607 ahd_outw(ahd, SNSCB_QOFF, oldvalue);
608 return (oldvalue);
609}
610
611static __inline void
612ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value)
613{
614 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
615 ahd_outw(ahd, SNSCB_QOFF, value);
616}
617
618static __inline u_int
619ahd_get_sescb_qoff(struct ahd_softc *ahd)
620{
621 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
622 return (ahd_inb(ahd, SESCB_QOFF));
623}
624
625static __inline void
626ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value)
627{
628 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
629 ahd_outb(ahd, SESCB_QOFF, value);
630}
631
632static __inline u_int
633ahd_get_sdscb_qoff(struct ahd_softc *ahd)
634{
635 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
636 return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8));
637}
638
639static __inline void
640ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value)
641{
642 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
643 ahd_outb(ahd, SDSCB_QOFF, value & 0xFF);
644 ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF);
645}
646
647static __inline u_int
648ahd_inb_scbram(struct ahd_softc *ahd, u_int offset)
649{
650 u_int value;
651
652 /*
653 * Workaround PCI-X Rev A. hardware bug.
654 * After a host read of SCB memory, the chip
655 * may become confused into thinking prefetch
656 * was required. This starts the discard timer
657 * running and can cause an unexpected discard
658 * timer interrupt. The work around is to read
659 * a normal register prior to the exhaustion of
660 * the discard timer. The mode pointer register
661 * has no side effects and so serves well for
662 * this purpose.
663 *
664 * Razor #528
665 */
666 value = ahd_inb(ahd, offset);
667 if ((ahd->bugs & AHD_PCIX_SCBRAM_RD_BUG) != 0)
668 ahd_inb(ahd, MODE_PTR);
669 return (value);
670}
671
672static __inline u_int
673ahd_inw_scbram(struct ahd_softc *ahd, u_int offset)
674{
675 return (ahd_inb_scbram(ahd, offset)
676 | (ahd_inb_scbram(ahd, offset+1) << 8));
677}
678
679static __inline uint32_t
680ahd_inl_scbram(struct ahd_softc *ahd, u_int offset)
681{
682 return (ahd_inw_scbram(ahd, offset)
683 | (ahd_inw_scbram(ahd, offset+2) << 16));
684}
685
686static __inline uint64_t
687ahd_inq_scbram(struct ahd_softc *ahd, u_int offset)
688{
689 return (ahd_inl_scbram(ahd, offset)
690 | ((uint64_t)ahd_inl_scbram(ahd, offset+4)) << 32);
691}
692
693static __inline struct scb *
694ahd_lookup_scb(struct ahd_softc *ahd, u_int tag)
695{
696 struct scb* scb;
697
698 if (tag >= AHD_SCB_MAX)
699 return (NULL);
700 scb = ahd->scb_data.scbindex[tag];
701 if (scb != NULL)
702 ahd_sync_scb(ahd, scb,
703 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
704 return (scb);
705}
706
707static __inline void
708ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb)
709{
710 struct hardware_scb *q_hscb;
711 struct map_node *q_hscb_map;
712 uint32_t saved_hscb_busaddr;
713
714 /*
715 * Our queuing method is a bit tricky. The card
716 * knows in advance which HSCB (by address) to download,
717 * and we can't disappoint it. To achieve this, the next
718 * HSCB to download is saved off in ahd->next_queued_hscb.
719 * When we are called to queue "an arbitrary scb",
720 * we copy the contents of the incoming HSCB to the one
721 * the sequencer knows about, swap HSCB pointers and
722 * finally assign the SCB to the tag indexed location
723 * in the scb_array. This makes sure that we can still
724 * locate the correct SCB by SCB_TAG.
725 */
726 q_hscb = ahd->next_queued_hscb;
727 q_hscb_map = ahd->next_queued_hscb_map;
728 saved_hscb_busaddr = q_hscb->hscb_busaddr;
729 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
730 q_hscb->hscb_busaddr = saved_hscb_busaddr;
731 q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
732
733 /* Now swap HSCB pointers. */
734 ahd->next_queued_hscb = scb->hscb;
735 ahd->next_queued_hscb_map = scb->hscb_map;
736 scb->hscb = q_hscb;
737 scb->hscb_map = q_hscb_map;
738
739 /* Now define the mapping from tag to SCB in the scbindex */
740 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb;
741}
742
743/*
744 * Tell the sequencer about a new transaction to execute.
745 */
746static __inline void
747ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb)
748{
749 ahd_swap_with_next_hscb(ahd, scb);
750
751 if (SCBID_IS_NULL(SCB_GET_TAG(scb)))
752 panic("Attempt to queue invalid SCB tag %x\n",
753 SCB_GET_TAG(scb));
754
755 /*
756 * Keep a history of SCBs we've downloaded in the qinfifo.
757 */
758 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
759 ahd->qinfifonext++;
760
761 if (scb->sg_count != 0)
762 ahd_setup_data_scb(ahd, scb);
763 else
764 ahd_setup_noxfer_scb(ahd, scb);
765 ahd_setup_scb_common(ahd, scb);
766
767 /*
768 * Make sure our data is consistent from the
769 * perspective of the adapter.
770 */
771 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
772
773#ifdef AHD_DEBUG
774 if ((ahd_debug & AHD_SHOW_QUEUE) != 0) {
775 uint64_t host_dataptr;
776
777 host_dataptr = ahd_le64toh(scb->hscb->dataptr);
778 printf("%s: Queueing SCB %d:0x%x bus addr 0x%x - 0x%x%x/0x%x\n",
779 ahd_name(ahd),
780 SCB_GET_TAG(scb), scb->hscb->scsiid,
781 ahd_le32toh(scb->hscb->hscb_busaddr),
782 (u_int)((host_dataptr >> 32) & 0xFFFFFFFF),
783 (u_int)(host_dataptr & 0xFFFFFFFF),
784 ahd_le32toh(scb->hscb->datacnt));
785 }
786#endif 159#endif
787 /* Tell the adapter about the newly queued SCB */
788 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
789}
790 160
791static __inline uint8_t * 161static __inline uint8_t *
792ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb) 162ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb)
@@ -801,151 +171,6 @@ ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb)
801} 171}
802 172
803/************************** Interrupt Processing ******************************/ 173/************************** Interrupt Processing ******************************/
804static __inline void ahd_sync_qoutfifo(struct ahd_softc *ahd, int op); 174int ahd_intr(struct ahd_softc *ahd);
805static __inline void ahd_sync_tqinfifo(struct ahd_softc *ahd, int op);
806static __inline u_int ahd_check_cmdcmpltqueues(struct ahd_softc *ahd);
807static __inline int ahd_intr(struct ahd_softc *ahd);
808
809static __inline void
810ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
811{
812 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
813 /*offset*/0,
814 /*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
815}
816
817static __inline void
818ahd_sync_tqinfifo(struct ahd_softc *ahd, int op)
819{
820#ifdef AHD_TARGET_MODE
821 if ((ahd->flags & AHD_TARGETROLE) != 0) {
822 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
823 ahd->shared_data_map.dmamap,
824 ahd_targetcmd_offset(ahd, 0),
825 sizeof(struct target_cmd) * AHD_TMODE_CMDS,
826 op);
827 }
828#endif
829}
830
831/*
832 * See if the firmware has posted any completed commands
833 * into our in-core command complete fifos.
834 */
835#define AHD_RUN_QOUTFIFO 0x1
836#define AHD_RUN_TQINFIFO 0x2
837static __inline u_int
838ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
839{
840 u_int retval;
841
842 retval = 0;
843 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
844 /*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
845 /*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
846 if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
847 == ahd->qoutfifonext_valid_tag)
848 retval |= AHD_RUN_QOUTFIFO;
849#ifdef AHD_TARGET_MODE
850 if ((ahd->flags & AHD_TARGETROLE) != 0
851 && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) {
852 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
853 ahd->shared_data_map.dmamap,
854 ahd_targetcmd_offset(ahd, ahd->tqinfifofnext),
855 /*len*/sizeof(struct target_cmd),
856 BUS_DMASYNC_POSTREAD);
857 if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0)
858 retval |= AHD_RUN_TQINFIFO;
859 }
860#endif
861 return (retval);
862}
863
864/*
865 * Catch an interrupt from the adapter
866 */
867static __inline int
868ahd_intr(struct ahd_softc *ahd)
869{
870 u_int intstat;
871
872 if ((ahd->pause & INTEN) == 0) {
873 /*
874 * Our interrupt is not enabled on the chip
875 * and may be disabled for re-entrancy reasons,
876 * so just return. This is likely just a shared
877 * interrupt.
878 */
879 return (0);
880 }
881
882 /*
883 * Instead of directly reading the interrupt status register,
884 * infer the cause of the interrupt by checking our in-core
885 * completion queues. This avoids a costly PCI bus read in
886 * most cases.
887 */
888 if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0
889 && (ahd_check_cmdcmpltqueues(ahd) != 0))
890 intstat = CMDCMPLT;
891 else
892 intstat = ahd_inb(ahd, INTSTAT);
893
894 if ((intstat & INT_PEND) == 0)
895 return (0);
896
897 if (intstat & CMDCMPLT) {
898 ahd_outb(ahd, CLRINT, CLRCMDINT);
899
900 /*
901 * Ensure that the chip sees that we've cleared
902 * this interrupt before we walk the output fifo.
903 * Otherwise, we may, due to posted bus writes,
904 * clear the interrupt after we finish the scan,
905 * and after the sequencer has added new entries
906 * and asserted the interrupt again.
907 */
908 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
909 if (ahd_is_paused(ahd)) {
910 /*
911 * Potentially lost SEQINT.
912 * If SEQINTCODE is non-zero,
913 * simulate the SEQINT.
914 */
915 if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT)
916 intstat |= SEQINT;
917 }
918 } else {
919 ahd_flush_device_writes(ahd);
920 }
921 ahd_run_qoutfifo(ahd);
922 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++;
923 ahd->cmdcmplt_total++;
924#ifdef AHD_TARGET_MODE
925 if ((ahd->flags & AHD_TARGETROLE) != 0)
926 ahd_run_tqinfifo(ahd, /*paused*/FALSE);
927#endif
928 }
929
930 /*
931 * Handle statuses that may invalidate our cached
932 * copy of INTSTAT separately.
933 */
934 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) {
935 /* Hot eject. Do nothing */
936 } else if (intstat & HWERRINT) {
937 ahd_handle_hwerrint(ahd);
938 } else if ((intstat & (PCIINT|SPLTINT)) != 0) {
939 ahd->bus_intr(ahd);
940 } else {
941
942 if ((intstat & SEQINT) != 0)
943 ahd_handle_seqint(ahd, intstat);
944
945 if ((intstat & SCSIINT) != 0)
946 ahd_handle_scsiint(ahd, intstat);
947 }
948 return (1);
949}
950 175
951#endif /* _AIC79XX_INLINE_H_ */ 176#endif /* _AIC79XX_INLINE_H_ */
diff --git a/drivers/scsi/aic7xxx/aic79xx_osm.c b/drivers/scsi/aic7xxx/aic79xx_osm.c
index 0081aa357c8b..0f829b3b8ab7 100644
--- a/drivers/scsi/aic7xxx/aic79xx_osm.c
+++ b/drivers/scsi/aic7xxx/aic79xx_osm.c
@@ -193,7 +193,7 @@ struct ahd_linux_iocell_opts
193#define AIC79XX_PRECOMP_INDEX 0 193#define AIC79XX_PRECOMP_INDEX 0
194#define AIC79XX_SLEWRATE_INDEX 1 194#define AIC79XX_SLEWRATE_INDEX 1
195#define AIC79XX_AMPLITUDE_INDEX 2 195#define AIC79XX_AMPLITUDE_INDEX 2
196static struct ahd_linux_iocell_opts aic79xx_iocell_info[] = 196static const struct ahd_linux_iocell_opts aic79xx_iocell_info[] =
197{ 197{
198 AIC79XX_DEFAULT_IOOPTS, 198 AIC79XX_DEFAULT_IOOPTS,
199 AIC79XX_DEFAULT_IOOPTS, 199 AIC79XX_DEFAULT_IOOPTS,
@@ -369,10 +369,167 @@ static void ahd_release_simq(struct ahd_softc *ahd);
369static int ahd_linux_unit; 369static int ahd_linux_unit;
370 370
371 371
372/************************** OS Utility Wrappers *******************************/
373void ahd_delay(long);
374void
375ahd_delay(long usec)
376{
377 /*
378 * udelay on Linux can have problems for
379 * multi-millisecond waits. Wait at most
380 * 1024us per call.
381 */
382 while (usec > 0) {
383 udelay(usec % 1024);
384 usec -= 1024;
385 }
386}
387
388
389/***************************** Low Level I/O **********************************/
390uint8_t ahd_inb(struct ahd_softc * ahd, long port);
391void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val);
392void ahd_outw_atomic(struct ahd_softc * ahd,
393 long port, uint16_t val);
394void ahd_outsb(struct ahd_softc * ahd, long port,
395 uint8_t *, int count);
396void ahd_insb(struct ahd_softc * ahd, long port,
397 uint8_t *, int count);
398
399uint8_t
400ahd_inb(struct ahd_softc * ahd, long port)
401{
402 uint8_t x;
403
404 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
405 x = readb(ahd->bshs[0].maddr + port);
406 } else {
407 x = inb(ahd->bshs[(port) >> 8].ioport + ((port) & 0xFF));
408 }
409 mb();
410 return (x);
411}
412
413#if 0 /* unused */
414static uint16_t
415ahd_inw_atomic(struct ahd_softc * ahd, long port)
416{
417 uint8_t x;
418
419 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
420 x = readw(ahd->bshs[0].maddr + port);
421 } else {
422 x = inw(ahd->bshs[(port) >> 8].ioport + ((port) & 0xFF));
423 }
424 mb();
425 return (x);
426}
427#endif
428
429void
430ahd_outb(struct ahd_softc * ahd, long port, uint8_t val)
431{
432 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
433 writeb(val, ahd->bshs[0].maddr + port);
434 } else {
435 outb(val, ahd->bshs[(port) >> 8].ioport + (port & 0xFF));
436 }
437 mb();
438}
439
440void
441ahd_outw_atomic(struct ahd_softc * ahd, long port, uint16_t val)
442{
443 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
444 writew(val, ahd->bshs[0].maddr + port);
445 } else {
446 outw(val, ahd->bshs[(port) >> 8].ioport + (port & 0xFF));
447 }
448 mb();
449}
450
451void
452ahd_outsb(struct ahd_softc * ahd, long port, uint8_t *array, int count)
453{
454 int i;
455
456 /*
457 * There is probably a more efficient way to do this on Linux
458 * but we don't use this for anything speed critical and this
459 * should work.
460 */
461 for (i = 0; i < count; i++)
462 ahd_outb(ahd, port, *array++);
463}
464
465void
466ahd_insb(struct ahd_softc * ahd, long port, uint8_t *array, int count)
467{
468 int i;
469
470 /*
471 * There is probably a more efficient way to do this on Linux
472 * but we don't use this for anything speed critical and this
473 * should work.
474 */
475 for (i = 0; i < count; i++)
476 *array++ = ahd_inb(ahd, port);
477}
478
479/******************************* PCI Routines *********************************/
480uint32_t
481ahd_pci_read_config(ahd_dev_softc_t pci, int reg, int width)
482{
483 switch (width) {
484 case 1:
485 {
486 uint8_t retval;
487
488 pci_read_config_byte(pci, reg, &retval);
489 return (retval);
490 }
491 case 2:
492 {
493 uint16_t retval;
494 pci_read_config_word(pci, reg, &retval);
495 return (retval);
496 }
497 case 4:
498 {
499 uint32_t retval;
500 pci_read_config_dword(pci, reg, &retval);
501 return (retval);
502 }
503 default:
504 panic("ahd_pci_read_config: Read size too big");
505 /* NOTREACHED */
506 return (0);
507 }
508}
509
510void
511ahd_pci_write_config(ahd_dev_softc_t pci, int reg, uint32_t value, int width)
512{
513 switch (width) {
514 case 1:
515 pci_write_config_byte(pci, reg, value);
516 break;
517 case 2:
518 pci_write_config_word(pci, reg, value);
519 break;
520 case 4:
521 pci_write_config_dword(pci, reg, value);
522 break;
523 default:
524 panic("ahd_pci_write_config: Write size too big");
525 /* NOTREACHED */
526 }
527}
528
372/****************************** Inlines ***************************************/ 529/****************************** Inlines ***************************************/
373static __inline void ahd_linux_unmap_scb(struct ahd_softc*, struct scb*); 530static void ahd_linux_unmap_scb(struct ahd_softc*, struct scb*);
374 531
375static __inline void 532static void
376ahd_linux_unmap_scb(struct ahd_softc *ahd, struct scb *scb) 533ahd_linux_unmap_scb(struct ahd_softc *ahd, struct scb *scb)
377{ 534{
378 struct scsi_cmnd *cmd; 535 struct scsi_cmnd *cmd;
@@ -400,13 +557,11 @@ ahd_linux_info(struct Scsi_Host *host)
400 bp = &buffer[0]; 557 bp = &buffer[0];
401 ahd = *(struct ahd_softc **)host->hostdata; 558 ahd = *(struct ahd_softc **)host->hostdata;
402 memset(bp, 0, sizeof(buffer)); 559 memset(bp, 0, sizeof(buffer));
403 strcpy(bp, "Adaptec AIC79XX PCI-X SCSI HBA DRIVER, Rev "); 560 strcpy(bp, "Adaptec AIC79XX PCI-X SCSI HBA DRIVER, Rev " AIC79XX_DRIVER_VERSION "\n"
404 strcat(bp, AIC79XX_DRIVER_VERSION); 561 " <");
405 strcat(bp, "\n");
406 strcat(bp, " <");
407 strcat(bp, ahd->description); 562 strcat(bp, ahd->description);
408 strcat(bp, ">\n"); 563 strcat(bp, ">\n"
409 strcat(bp, " "); 564 " ");
410 ahd_controller_info(ahd, ahd_info); 565 ahd_controller_info(ahd, ahd_info);
411 strcat(bp, ahd_info); 566 strcat(bp, ahd_info);
412 567
@@ -432,7 +587,7 @@ ahd_linux_queue(struct scsi_cmnd * cmd, void (*scsi_done) (struct scsi_cmnd *))
432 return rtn; 587 return rtn;
433} 588}
434 589
435static inline struct scsi_target ** 590static struct scsi_target **
436ahd_linux_target_in_softc(struct scsi_target *starget) 591ahd_linux_target_in_softc(struct scsi_target *starget)
437{ 592{
438 struct ahd_softc *ahd = 593 struct ahd_softc *ahd =
@@ -991,7 +1146,7 @@ aic79xx_setup(char *s)
991 char *p; 1146 char *p;
992 char *end; 1147 char *end;
993 1148
994 static struct { 1149 static const struct {
995 const char *name; 1150 const char *name;
996 uint32_t *flag; 1151 uint32_t *flag;
997 } options[] = { 1152 } options[] = {
@@ -1223,7 +1378,7 @@ ahd_platform_init(struct ahd_softc *ahd)
1223 * Lookup and commit any modified IO Cell options. 1378 * Lookup and commit any modified IO Cell options.
1224 */ 1379 */
1225 if (ahd->unit < ARRAY_SIZE(aic79xx_iocell_info)) { 1380 if (ahd->unit < ARRAY_SIZE(aic79xx_iocell_info)) {
1226 struct ahd_linux_iocell_opts *iocell_opts; 1381 const struct ahd_linux_iocell_opts *iocell_opts;
1227 1382
1228 iocell_opts = &aic79xx_iocell_info[ahd->unit]; 1383 iocell_opts = &aic79xx_iocell_info[ahd->unit];
1229 if (iocell_opts->precomp != AIC79XX_DEFAULT_PRECOMP) 1384 if (iocell_opts->precomp != AIC79XX_DEFAULT_PRECOMP)
@@ -2613,7 +2768,7 @@ static void ahd_linux_set_pcomp_en(struct scsi_target *starget, int pcomp)
2613 uint8_t precomp; 2768 uint8_t precomp;
2614 2769
2615 if (ahd->unit < ARRAY_SIZE(aic79xx_iocell_info)) { 2770 if (ahd->unit < ARRAY_SIZE(aic79xx_iocell_info)) {
2616 struct ahd_linux_iocell_opts *iocell_opts; 2771 const struct ahd_linux_iocell_opts *iocell_opts;
2617 2772
2618 iocell_opts = &aic79xx_iocell_info[ahd->unit]; 2773 iocell_opts = &aic79xx_iocell_info[ahd->unit];
2619 precomp = iocell_opts->precomp; 2774 precomp = iocell_opts->precomp;
diff --git a/drivers/scsi/aic7xxx/aic79xx_osm.h b/drivers/scsi/aic7xxx/aic79xx_osm.h
index 853998be1474..8d6612c19922 100644
--- a/drivers/scsi/aic7xxx/aic79xx_osm.h
+++ b/drivers/scsi/aic7xxx/aic79xx_osm.h
@@ -222,22 +222,6 @@ typedef struct timer_list ahd_timer_t;
222/***************************** Timer Facilities *******************************/ 222/***************************** Timer Facilities *******************************/
223#define ahd_timer_init init_timer 223#define ahd_timer_init init_timer
224#define ahd_timer_stop del_timer_sync 224#define ahd_timer_stop del_timer_sync
225typedef void ahd_linux_callback_t (u_long);
226static __inline void ahd_timer_reset(ahd_timer_t *timer, int usec,
227 ahd_callback_t *func, void *arg);
228
229static __inline void
230ahd_timer_reset(ahd_timer_t *timer, int usec, ahd_callback_t *func, void *arg)
231{
232 struct ahd_softc *ahd;
233
234 ahd = (struct ahd_softc *)arg;
235 del_timer(timer);
236 timer->data = (u_long)arg;
237 timer->expires = jiffies + (usec * HZ)/1000000;
238 timer->function = (ahd_linux_callback_t*)func;
239 add_timer(timer);
240}
241 225
242/***************************** SMP support ************************************/ 226/***************************** SMP support ************************************/
243#include <linux/spinlock.h> 227#include <linux/spinlock.h>
@@ -376,7 +360,7 @@ struct ahd_platform_data {
376#define AHD_LINUX_NOIRQ ((uint32_t)~0) 360#define AHD_LINUX_NOIRQ ((uint32_t)~0)
377 uint32_t irq; /* IRQ for this adapter */ 361 uint32_t irq; /* IRQ for this adapter */
378 uint32_t bios_address; 362 uint32_t bios_address;
379 uint32_t mem_busaddr; /* Mem Base Addr */ 363 resource_size_t mem_busaddr; /* Mem Base Addr */
380}; 364};
381 365
382/************************** OS Utility Wrappers *******************************/ 366/************************** OS Utility Wrappers *******************************/
@@ -386,111 +370,18 @@ struct ahd_platform_data {
386#define malloc(size, type, flags) kmalloc(size, flags) 370#define malloc(size, type, flags) kmalloc(size, flags)
387#define free(ptr, type) kfree(ptr) 371#define free(ptr, type) kfree(ptr)
388 372
389static __inline void ahd_delay(long); 373void ahd_delay(long);
390static __inline void
391ahd_delay(long usec)
392{
393 /*
394 * udelay on Linux can have problems for
395 * multi-millisecond waits. Wait at most
396 * 1024us per call.
397 */
398 while (usec > 0) {
399 udelay(usec % 1024);
400 usec -= 1024;
401 }
402}
403
404 374
405/***************************** Low Level I/O **********************************/ 375/***************************** Low Level I/O **********************************/
406static __inline uint8_t ahd_inb(struct ahd_softc * ahd, long port); 376uint8_t ahd_inb(struct ahd_softc * ahd, long port);
407static __inline uint16_t ahd_inw_atomic(struct ahd_softc * ahd, long port); 377void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val);
408static __inline void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val); 378void ahd_outw_atomic(struct ahd_softc * ahd,
409static __inline void ahd_outw_atomic(struct ahd_softc * ahd,
410 long port, uint16_t val); 379 long port, uint16_t val);
411static __inline void ahd_outsb(struct ahd_softc * ahd, long port, 380void ahd_outsb(struct ahd_softc * ahd, long port,
412 uint8_t *, int count); 381 uint8_t *, int count);
413static __inline void ahd_insb(struct ahd_softc * ahd, long port, 382void ahd_insb(struct ahd_softc * ahd, long port,
414 uint8_t *, int count); 383 uint8_t *, int count);
415 384
416static __inline uint8_t
417ahd_inb(struct ahd_softc * ahd, long port)
418{
419 uint8_t x;
420
421 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
422 x = readb(ahd->bshs[0].maddr + port);
423 } else {
424 x = inb(ahd->bshs[(port) >> 8].ioport + ((port) & 0xFF));
425 }
426 mb();
427 return (x);
428}
429
430static __inline uint16_t
431ahd_inw_atomic(struct ahd_softc * ahd, long port)
432{
433 uint8_t x;
434
435 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
436 x = readw(ahd->bshs[0].maddr + port);
437 } else {
438 x = inw(ahd->bshs[(port) >> 8].ioport + ((port) & 0xFF));
439 }
440 mb();
441 return (x);
442}
443
444static __inline void
445ahd_outb(struct ahd_softc * ahd, long port, uint8_t val)
446{
447 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
448 writeb(val, ahd->bshs[0].maddr + port);
449 } else {
450 outb(val, ahd->bshs[(port) >> 8].ioport + (port & 0xFF));
451 }
452 mb();
453}
454
455static __inline void
456ahd_outw_atomic(struct ahd_softc * ahd, long port, uint16_t val)
457{
458 if (ahd->tags[0] == BUS_SPACE_MEMIO) {
459 writew(val, ahd->bshs[0].maddr + port);
460 } else {
461 outw(val, ahd->bshs[(port) >> 8].ioport + (port & 0xFF));
462 }
463 mb();
464}
465
466static __inline void
467ahd_outsb(struct ahd_softc * ahd, long port, uint8_t *array, int count)
468{
469 int i;
470
471 /*
472 * There is probably a more efficient way to do this on Linux
473 * but we don't use this for anything speed critical and this
474 * should work.
475 */
476 for (i = 0; i < count; i++)
477 ahd_outb(ahd, port, *array++);
478}
479
480static __inline void
481ahd_insb(struct ahd_softc * ahd, long port, uint8_t *array, int count)
482{
483 int i;
484
485 /*
486 * There is probably a more efficient way to do this on Linux
487 * but we don't use this for anything speed critical and this
488 * should work.
489 */
490 for (i = 0; i < count; i++)
491 *array++ = ahd_inb(ahd, port);
492}
493
494/**************************** Initialization **********************************/ 385/**************************** Initialization **********************************/
495int ahd_linux_register_host(struct ahd_softc *, 386int ahd_linux_register_host(struct ahd_softc *,
496 struct scsi_host_template *); 387 struct scsi_host_template *);
@@ -593,62 +484,12 @@ void ahd_linux_pci_exit(void);
593int ahd_pci_map_registers(struct ahd_softc *ahd); 484int ahd_pci_map_registers(struct ahd_softc *ahd);
594int ahd_pci_map_int(struct ahd_softc *ahd); 485int ahd_pci_map_int(struct ahd_softc *ahd);
595 486
596static __inline uint32_t ahd_pci_read_config(ahd_dev_softc_t pci, 487uint32_t ahd_pci_read_config(ahd_dev_softc_t pci,
597 int reg, int width); 488 int reg, int width);
598 489void ahd_pci_write_config(ahd_dev_softc_t pci,
599static __inline uint32_t
600ahd_pci_read_config(ahd_dev_softc_t pci, int reg, int width)
601{
602 switch (width) {
603 case 1:
604 {
605 uint8_t retval;
606
607 pci_read_config_byte(pci, reg, &retval);
608 return (retval);
609 }
610 case 2:
611 {
612 uint16_t retval;
613 pci_read_config_word(pci, reg, &retval);
614 return (retval);
615 }
616 case 4:
617 {
618 uint32_t retval;
619 pci_read_config_dword(pci, reg, &retval);
620 return (retval);
621 }
622 default:
623 panic("ahd_pci_read_config: Read size too big");
624 /* NOTREACHED */
625 return (0);
626 }
627}
628
629static __inline void ahd_pci_write_config(ahd_dev_softc_t pci,
630 int reg, uint32_t value, 490 int reg, uint32_t value,
631 int width); 491 int width);
632 492
633static __inline void
634ahd_pci_write_config(ahd_dev_softc_t pci, int reg, uint32_t value, int width)
635{
636 switch (width) {
637 case 1:
638 pci_write_config_byte(pci, reg, value);
639 break;
640 case 2:
641 pci_write_config_word(pci, reg, value);
642 break;
643 case 4:
644 pci_write_config_dword(pci, reg, value);
645 break;
646 default:
647 panic("ahd_pci_write_config: Write size too big");
648 /* NOTREACHED */
649 }
650}
651
652static __inline int ahd_get_pci_function(ahd_dev_softc_t); 493static __inline int ahd_get_pci_function(ahd_dev_softc_t);
653static __inline int 494static __inline int
654ahd_get_pci_function(ahd_dev_softc_t pci) 495ahd_get_pci_function(ahd_dev_softc_t pci)
diff --git a/drivers/scsi/aic7xxx/aic79xx_osm_pci.c b/drivers/scsi/aic7xxx/aic79xx_osm_pci.c
index dfaaae5e73ae..6593056867f6 100644
--- a/drivers/scsi/aic7xxx/aic79xx_osm_pci.c
+++ b/drivers/scsi/aic7xxx/aic79xx_osm_pci.c
@@ -49,7 +49,7 @@
49 ID2C(x), \ 49 ID2C(x), \
50 ID2C(IDIROC(x)) 50 ID2C(IDIROC(x))
51 51
52static struct pci_device_id ahd_linux_pci_id_table[] = { 52static const struct pci_device_id ahd_linux_pci_id_table[] = {
53 /* aic7901 based controllers */ 53 /* aic7901 based controllers */
54 ID(ID_AHA_29320A), 54 ID(ID_AHA_29320A),
55 ID(ID_AHA_29320ALP), 55 ID(ID_AHA_29320ALP),
@@ -159,7 +159,7 @@ ahd_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
159 char buf[80]; 159 char buf[80];
160 struct ahd_softc *ahd; 160 struct ahd_softc *ahd;
161 ahd_dev_softc_t pci; 161 ahd_dev_softc_t pci;
162 struct ahd_pci_identity *entry; 162 const struct ahd_pci_identity *entry;
163 char *name; 163 char *name;
164 int error; 164 int error;
165 struct device *dev = &pdev->dev; 165 struct device *dev = &pdev->dev;
@@ -249,8 +249,8 @@ ahd_linux_pci_exit(void)
249} 249}
250 250
251static int 251static int
252ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, u_long *base, 252ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, resource_size_t *base,
253 u_long *base2) 253 resource_size_t *base2)
254{ 254{
255 *base = pci_resource_start(ahd->dev_softc, 0); 255 *base = pci_resource_start(ahd->dev_softc, 0);
256 /* 256 /*
@@ -272,11 +272,11 @@ ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, u_long *base,
272 272
273static int 273static int
274ahd_linux_pci_reserve_mem_region(struct ahd_softc *ahd, 274ahd_linux_pci_reserve_mem_region(struct ahd_softc *ahd,
275 u_long *bus_addr, 275 resource_size_t *bus_addr,
276 uint8_t __iomem **maddr) 276 uint8_t __iomem **maddr)
277{ 277{
278 u_long start; 278 resource_size_t start;
279 u_long base_page; 279 resource_size_t base_page;
280 u_long base_offset; 280 u_long base_offset;
281 int error = 0; 281 int error = 0;
282 282
@@ -310,7 +310,7 @@ int
310ahd_pci_map_registers(struct ahd_softc *ahd) 310ahd_pci_map_registers(struct ahd_softc *ahd)
311{ 311{
312 uint32_t command; 312 uint32_t command;
313 u_long base; 313 resource_size_t base;
314 uint8_t __iomem *maddr; 314 uint8_t __iomem *maddr;
315 int error; 315 int error;
316 316
@@ -346,31 +346,32 @@ ahd_pci_map_registers(struct ahd_softc *ahd)
346 } else 346 } else
347 command |= PCIM_CMD_MEMEN; 347 command |= PCIM_CMD_MEMEN;
348 } else if (bootverbose) { 348 } else if (bootverbose) {
349 printf("aic79xx: PCI%d:%d:%d MEM region 0x%lx " 349 printf("aic79xx: PCI%d:%d:%d MEM region 0x%llx "
350 "unavailable. Cannot memory map device.\n", 350 "unavailable. Cannot memory map device.\n",
351 ahd_get_pci_bus(ahd->dev_softc), 351 ahd_get_pci_bus(ahd->dev_softc),
352 ahd_get_pci_slot(ahd->dev_softc), 352 ahd_get_pci_slot(ahd->dev_softc),
353 ahd_get_pci_function(ahd->dev_softc), 353 ahd_get_pci_function(ahd->dev_softc),
354 base); 354 (unsigned long long)base);
355 } 355 }
356 356
357 if (maddr == NULL) { 357 if (maddr == NULL) {
358 u_long base2; 358 resource_size_t base2;
359 359
360 error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2); 360 error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2);
361 if (error == 0) { 361 if (error == 0) {
362 ahd->tags[0] = BUS_SPACE_PIO; 362 ahd->tags[0] = BUS_SPACE_PIO;
363 ahd->tags[1] = BUS_SPACE_PIO; 363 ahd->tags[1] = BUS_SPACE_PIO;
364 ahd->bshs[0].ioport = base; 364 ahd->bshs[0].ioport = (u_long)base;
365 ahd->bshs[1].ioport = base2; 365 ahd->bshs[1].ioport = (u_long)base2;
366 command |= PCIM_CMD_PORTEN; 366 command |= PCIM_CMD_PORTEN;
367 } else { 367 } else {
368 printf("aic79xx: PCI%d:%d:%d IO regions 0x%lx and 0x%lx" 368 printf("aic79xx: PCI%d:%d:%d IO regions 0x%llx and "
369 "unavailable. Cannot map device.\n", 369 "0x%llx unavailable. Cannot map device.\n",
370 ahd_get_pci_bus(ahd->dev_softc), 370 ahd_get_pci_bus(ahd->dev_softc),
371 ahd_get_pci_slot(ahd->dev_softc), 371 ahd_get_pci_slot(ahd->dev_softc),
372 ahd_get_pci_function(ahd->dev_softc), 372 ahd_get_pci_function(ahd->dev_softc),
373 base, base2); 373 (unsigned long long)base,
374 (unsigned long long)base2);
374 } 375 }
375 } 376 }
376 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 4); 377 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 4);
diff --git a/drivers/scsi/aic7xxx/aic79xx_pci.c b/drivers/scsi/aic7xxx/aic79xx_pci.c
index c9f79fdf9131..c25b6adffbf9 100644
--- a/drivers/scsi/aic7xxx/aic79xx_pci.c
+++ b/drivers/scsi/aic7xxx/aic79xx_pci.c
@@ -97,7 +97,7 @@ static ahd_device_setup_t ahd_aic7901A_setup;
97static ahd_device_setup_t ahd_aic7902_setup; 97static ahd_device_setup_t ahd_aic7902_setup;
98static ahd_device_setup_t ahd_aic790X_setup; 98static ahd_device_setup_t ahd_aic790X_setup;
99 99
100static struct ahd_pci_identity ahd_pci_ident_table [] = 100static const struct ahd_pci_identity ahd_pci_ident_table[] =
101{ 101{
102 /* aic7901 based controllers */ 102 /* aic7901 based controllers */
103 { 103 {
@@ -253,7 +253,7 @@ static void ahd_configure_termination(struct ahd_softc *ahd,
253static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 253static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
254static void ahd_pci_intr(struct ahd_softc *ahd); 254static void ahd_pci_intr(struct ahd_softc *ahd);
255 255
256struct ahd_pci_identity * 256const struct ahd_pci_identity *
257ahd_find_pci_device(ahd_dev_softc_t pci) 257ahd_find_pci_device(ahd_dev_softc_t pci)
258{ 258{
259 uint64_t full_id; 259 uint64_t full_id;
@@ -261,7 +261,7 @@ ahd_find_pci_device(ahd_dev_softc_t pci)
261 uint16_t vendor; 261 uint16_t vendor;
262 uint16_t subdevice; 262 uint16_t subdevice;
263 uint16_t subvendor; 263 uint16_t subvendor;
264 struct ahd_pci_identity *entry; 264 const struct ahd_pci_identity *entry;
265 u_int i; 265 u_int i;
266 266
267 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 267 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
@@ -292,7 +292,7 @@ ahd_find_pci_device(ahd_dev_softc_t pci)
292} 292}
293 293
294int 294int
295ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 295ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry)
296{ 296{
297 struct scb_data *shared_scb_data; 297 struct scb_data *shared_scb_data;
298 u_int command; 298 u_int command;
diff --git a/drivers/scsi/aic7xxx/aic79xx_proc.c b/drivers/scsi/aic7xxx/aic79xx_proc.c
index 6b28bebcbca0..014bed716e7c 100644
--- a/drivers/scsi/aic7xxx/aic79xx_proc.c
+++ b/drivers/scsi/aic7xxx/aic79xx_proc.c
@@ -57,7 +57,7 @@ static int ahd_proc_write_seeprom(struct ahd_softc *ahd,
57 * Table of syncrates that don't follow the "divisible by 4" 57 * Table of syncrates that don't follow the "divisible by 4"
58 * rule. This table will be expanded in future SCSI specs. 58 * rule. This table will be expanded in future SCSI specs.
59 */ 59 */
60static struct { 60static const struct {
61 u_int period_factor; 61 u_int period_factor;
62 u_int period; /* in 100ths of ns */ 62 u_int period; /* in 100ths of ns */
63} scsi_syncrates[] = { 63} scsi_syncrates[] = {
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
index 2068e00d2c75..c21ceab8e913 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
@@ -48,13 +48,6 @@ ahd_reg_print_t ahd_error_print;
48#endif 48#endif
49 49
50#if AIC_DEBUG_REGISTERS 50#if AIC_DEBUG_REGISTERS
51ahd_reg_print_t ahd_clrerr_print;
52#else
53#define ahd_clrerr_print(regvalue, cur_col, wrap) \
54 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap)
55#endif
56
57#if AIC_DEBUG_REGISTERS
58ahd_reg_print_t ahd_hcntrl_print; 51ahd_reg_print_t ahd_hcntrl_print;
59#else 52#else
60#define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 53#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
@@ -167,13 +160,6 @@ ahd_reg_print_t ahd_sg_cache_shadow_print;
167#endif 160#endif
168 161
169#if AIC_DEBUG_REGISTERS 162#if AIC_DEBUG_REGISTERS
170ahd_reg_print_t ahd_arbctl_print;
171#else
172#define ahd_arbctl_print(regvalue, cur_col, wrap) \
173 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
174#endif
175
176#if AIC_DEBUG_REGISTERS
177ahd_reg_print_t ahd_sg_cache_pre_print; 163ahd_reg_print_t ahd_sg_cache_pre_print;
178#else 164#else
179#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 165#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
@@ -188,20 +174,6 @@ ahd_reg_print_t ahd_lqin_print;
188#endif 174#endif
189 175
190#if AIC_DEBUG_REGISTERS 176#if AIC_DEBUG_REGISTERS
191ahd_reg_print_t ahd_typeptr_print;
192#else
193#define ahd_typeptr_print(regvalue, cur_col, wrap) \
194 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
195#endif
196
197#if AIC_DEBUG_REGISTERS
198ahd_reg_print_t ahd_tagptr_print;
199#else
200#define ahd_tagptr_print(regvalue, cur_col, wrap) \
201 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap)
202#endif
203
204#if AIC_DEBUG_REGISTERS
205ahd_reg_print_t ahd_lunptr_print; 177ahd_reg_print_t ahd_lunptr_print;
206#else 178#else
207#define ahd_lunptr_print(regvalue, cur_col, wrap) \ 179#define ahd_lunptr_print(regvalue, cur_col, wrap) \
@@ -209,20 +181,6 @@ ahd_reg_print_t ahd_lunptr_print;
209#endif 181#endif
210 182
211#if AIC_DEBUG_REGISTERS 183#if AIC_DEBUG_REGISTERS
212ahd_reg_print_t ahd_datalenptr_print;
213#else
214#define ahd_datalenptr_print(regvalue, cur_col, wrap) \
215 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap)
216#endif
217
218#if AIC_DEBUG_REGISTERS
219ahd_reg_print_t ahd_statlenptr_print;
220#else
221#define ahd_statlenptr_print(regvalue, cur_col, wrap) \
222 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap)
223#endif
224
225#if AIC_DEBUG_REGISTERS
226ahd_reg_print_t ahd_cmdlenptr_print; 184ahd_reg_print_t ahd_cmdlenptr_print;
227#else 185#else
228#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 186#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
@@ -258,13 +216,6 @@ ahd_reg_print_t ahd_qnextptr_print;
258#endif 216#endif
259 217
260#if AIC_DEBUG_REGISTERS 218#if AIC_DEBUG_REGISTERS
261ahd_reg_print_t ahd_idptr_print;
262#else
263#define ahd_idptr_print(regvalue, cur_col, wrap) \
264 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap)
265#endif
266
267#if AIC_DEBUG_REGISTERS
268ahd_reg_print_t ahd_abrtbyteptr_print; 219ahd_reg_print_t ahd_abrtbyteptr_print;
269#else 220#else
270#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 221#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
@@ -279,27 +230,6 @@ ahd_reg_print_t ahd_abrtbitptr_print;
279#endif 230#endif
280 231
281#if AIC_DEBUG_REGISTERS 232#if AIC_DEBUG_REGISTERS
282ahd_reg_print_t ahd_maxcmdbytes_print;
283#else
284#define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \
285 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap)
286#endif
287
288#if AIC_DEBUG_REGISTERS
289ahd_reg_print_t ahd_maxcmd2rcv_print;
290#else
291#define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \
292 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap)
293#endif
294
295#if AIC_DEBUG_REGISTERS
296ahd_reg_print_t ahd_shortthresh_print;
297#else
298#define ahd_shortthresh_print(regvalue, cur_col, wrap) \
299 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahd_reg_print_t ahd_lunlen_print; 233ahd_reg_print_t ahd_lunlen_print;
304#else 234#else
305#define ahd_lunlen_print(regvalue, cur_col, wrap) \ 235#define ahd_lunlen_print(regvalue, cur_col, wrap) \
@@ -328,41 +258,6 @@ ahd_reg_print_t ahd_maxcmdcnt_print;
328#endif 258#endif
329 259
330#if AIC_DEBUG_REGISTERS 260#if AIC_DEBUG_REGISTERS
331ahd_reg_print_t ahd_lqrsvd01_print;
332#else
333#define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \
334 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap)
335#endif
336
337#if AIC_DEBUG_REGISTERS
338ahd_reg_print_t ahd_lqrsvd16_print;
339#else
340#define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \
341 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap)
342#endif
343
344#if AIC_DEBUG_REGISTERS
345ahd_reg_print_t ahd_lqrsvd17_print;
346#else
347#define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \
348 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap)
349#endif
350
351#if AIC_DEBUG_REGISTERS
352ahd_reg_print_t ahd_cmdrsvd0_print;
353#else
354#define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \
355 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap)
356#endif
357
358#if AIC_DEBUG_REGISTERS
359ahd_reg_print_t ahd_lqctl0_print;
360#else
361#define ahd_lqctl0_print(regvalue, cur_col, wrap) \
362 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap)
363#endif
364
365#if AIC_DEBUG_REGISTERS
366ahd_reg_print_t ahd_lqctl1_print; 261ahd_reg_print_t ahd_lqctl1_print;
367#else 262#else
368#define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 263#define ahd_lqctl1_print(regvalue, cur_col, wrap) \
@@ -370,13 +265,6 @@ ahd_reg_print_t ahd_lqctl1_print;
370#endif 265#endif
371 266
372#if AIC_DEBUG_REGISTERS 267#if AIC_DEBUG_REGISTERS
373ahd_reg_print_t ahd_scsbist0_print;
374#else
375#define ahd_scsbist0_print(regvalue, cur_col, wrap) \
376 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap)
377#endif
378
379#if AIC_DEBUG_REGISTERS
380ahd_reg_print_t ahd_lqctl2_print; 268ahd_reg_print_t ahd_lqctl2_print;
381#else 269#else
382#define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 270#define ahd_lqctl2_print(regvalue, cur_col, wrap) \
@@ -384,13 +272,6 @@ ahd_reg_print_t ahd_lqctl2_print;
384#endif 272#endif
385 273
386#if AIC_DEBUG_REGISTERS 274#if AIC_DEBUG_REGISTERS
387ahd_reg_print_t ahd_scsbist1_print;
388#else
389#define ahd_scsbist1_print(regvalue, cur_col, wrap) \
390 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap)
391#endif
392
393#if AIC_DEBUG_REGISTERS
394ahd_reg_print_t ahd_scsiseq0_print; 275ahd_reg_print_t ahd_scsiseq0_print;
395#else 276#else
396#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 277#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
@@ -412,20 +293,6 @@ ahd_reg_print_t ahd_sxfrctl0_print;
412#endif 293#endif
413 294
414#if AIC_DEBUG_REGISTERS 295#if AIC_DEBUG_REGISTERS
415ahd_reg_print_t ahd_dlcount_print;
416#else
417#define ahd_dlcount_print(regvalue, cur_col, wrap) \
418 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
419#endif
420
421#if AIC_DEBUG_REGISTERS
422ahd_reg_print_t ahd_businitid_print;
423#else
424#define ahd_businitid_print(regvalue, cur_col, wrap) \
425 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap)
426#endif
427
428#if AIC_DEBUG_REGISTERS
429ahd_reg_print_t ahd_sxfrctl1_print; 296ahd_reg_print_t ahd_sxfrctl1_print;
430#else 297#else
431#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 298#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
@@ -433,20 +300,6 @@ ahd_reg_print_t ahd_sxfrctl1_print;
433#endif 300#endif
434 301
435#if AIC_DEBUG_REGISTERS 302#if AIC_DEBUG_REGISTERS
436ahd_reg_print_t ahd_bustargid_print;
437#else
438#define ahd_bustargid_print(regvalue, cur_col, wrap) \
439 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap)
440#endif
441
442#if AIC_DEBUG_REGISTERS
443ahd_reg_print_t ahd_sxfrctl2_print;
444#else
445#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
446 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
447#endif
448
449#if AIC_DEBUG_REGISTERS
450ahd_reg_print_t ahd_dffstat_print; 303ahd_reg_print_t ahd_dffstat_print;
451#else 304#else
452#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 305#define ahd_dffstat_print(regvalue, cur_col, wrap) \
@@ -454,17 +307,17 @@ ahd_reg_print_t ahd_dffstat_print;
454#endif 307#endif
455 308
456#if AIC_DEBUG_REGISTERS 309#if AIC_DEBUG_REGISTERS
457ahd_reg_print_t ahd_scsisigo_print; 310ahd_reg_print_t ahd_multargid_print;
458#else 311#else
459#define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 312#define ahd_multargid_print(regvalue, cur_col, wrap) \
460 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 313 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
461#endif 314#endif
462 315
463#if AIC_DEBUG_REGISTERS 316#if AIC_DEBUG_REGISTERS
464ahd_reg_print_t ahd_multargid_print; 317ahd_reg_print_t ahd_scsisigo_print;
465#else 318#else
466#define ahd_multargid_print(regvalue, cur_col, wrap) \ 319#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
467 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 320 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
468#endif 321#endif
469 322
470#if AIC_DEBUG_REGISTERS 323#if AIC_DEBUG_REGISTERS
@@ -482,13 +335,6 @@ ahd_reg_print_t ahd_scsiphase_print;
482#endif 335#endif
483 336
484#if AIC_DEBUG_REGISTERS 337#if AIC_DEBUG_REGISTERS
485ahd_reg_print_t ahd_scsidat0_img_print;
486#else
487#define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \
488 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap)
489#endif
490
491#if AIC_DEBUG_REGISTERS
492ahd_reg_print_t ahd_scsidat_print; 338ahd_reg_print_t ahd_scsidat_print;
493#else 339#else
494#define ahd_scsidat_print(regvalue, cur_col, wrap) \ 340#define ahd_scsidat_print(regvalue, cur_col, wrap) \
@@ -531,13 +377,6 @@ ahd_reg_print_t ahd_sblkctl_print;
531#endif 377#endif
532 378
533#if AIC_DEBUG_REGISTERS 379#if AIC_DEBUG_REGISTERS
534ahd_reg_print_t ahd_clrsint0_print;
535#else
536#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
537 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
538#endif
539
540#if AIC_DEBUG_REGISTERS
541ahd_reg_print_t ahd_sstat0_print; 380ahd_reg_print_t ahd_sstat0_print;
542#else 381#else
543#define ahd_sstat0_print(regvalue, cur_col, wrap) \ 382#define ahd_sstat0_print(regvalue, cur_col, wrap) \
@@ -552,10 +391,10 @@ ahd_reg_print_t ahd_simode0_print;
552#endif 391#endif
553 392
554#if AIC_DEBUG_REGISTERS 393#if AIC_DEBUG_REGISTERS
555ahd_reg_print_t ahd_clrsint1_print; 394ahd_reg_print_t ahd_clrsint0_print;
556#else 395#else
557#define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 396#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
558 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 397 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
559#endif 398#endif
560 399
561#if AIC_DEBUG_REGISTERS 400#if AIC_DEBUG_REGISTERS
@@ -566,17 +405,17 @@ ahd_reg_print_t ahd_sstat1_print;
566#endif 405#endif
567 406
568#if AIC_DEBUG_REGISTERS 407#if AIC_DEBUG_REGISTERS
569ahd_reg_print_t ahd_sstat2_print; 408ahd_reg_print_t ahd_clrsint1_print;
570#else 409#else
571#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 410#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
572 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 411 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
573#endif 412#endif
574 413
575#if AIC_DEBUG_REGISTERS 414#if AIC_DEBUG_REGISTERS
576ahd_reg_print_t ahd_simode2_print; 415ahd_reg_print_t ahd_sstat2_print;
577#else 416#else
578#define ahd_simode2_print(regvalue, cur_col, wrap) \ 417#define ahd_sstat2_print(regvalue, cur_col, wrap) \
579 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 418 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
580#endif 419#endif
581 420
582#if AIC_DEBUG_REGISTERS 421#if AIC_DEBUG_REGISTERS
@@ -622,17 +461,17 @@ ahd_reg_print_t ahd_lqistat0_print;
622#endif 461#endif
623 462
624#if AIC_DEBUG_REGISTERS 463#if AIC_DEBUG_REGISTERS
625ahd_reg_print_t ahd_clrlqiint0_print; 464ahd_reg_print_t ahd_lqimode0_print;
626#else 465#else
627#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 466#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
628 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 467 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
629#endif 468#endif
630 469
631#if AIC_DEBUG_REGISTERS 470#if AIC_DEBUG_REGISTERS
632ahd_reg_print_t ahd_lqimode0_print; 471ahd_reg_print_t ahd_clrlqiint0_print;
633#else 472#else
634#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 473#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
635 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 474 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
636#endif 475#endif
637 476
638#if AIC_DEBUG_REGISTERS 477#if AIC_DEBUG_REGISTERS
@@ -790,13 +629,6 @@ ahd_reg_print_t ahd_seqintsrc_print;
790#endif 629#endif
791 630
792#if AIC_DEBUG_REGISTERS 631#if AIC_DEBUG_REGISTERS
793ahd_reg_print_t ahd_currscb_print;
794#else
795#define ahd_currscb_print(regvalue, cur_col, wrap) \
796 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
797#endif
798
799#if AIC_DEBUG_REGISTERS
800ahd_reg_print_t ahd_seqimode_print; 632ahd_reg_print_t ahd_seqimode_print;
801#else 633#else
802#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 634#define ahd_seqimode_print(regvalue, cur_col, wrap) \
@@ -804,24 +636,17 @@ ahd_reg_print_t ahd_seqimode_print;
804#endif 636#endif
805 637
806#if AIC_DEBUG_REGISTERS 638#if AIC_DEBUG_REGISTERS
807ahd_reg_print_t ahd_mdffstat_print; 639ahd_reg_print_t ahd_currscb_print;
808#else
809#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
810 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
811#endif
812
813#if AIC_DEBUG_REGISTERS
814ahd_reg_print_t ahd_crccontrol_print;
815#else 640#else
816#define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 641#define ahd_currscb_print(regvalue, cur_col, wrap) \
817 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 642 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
818#endif 643#endif
819 644
820#if AIC_DEBUG_REGISTERS 645#if AIC_DEBUG_REGISTERS
821ahd_reg_print_t ahd_dfftag_print; 646ahd_reg_print_t ahd_mdffstat_print;
822#else 647#else
823#define ahd_dfftag_print(regvalue, cur_col, wrap) \ 648#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
824 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 649 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
825#endif 650#endif
826 651
827#if AIC_DEBUG_REGISTERS 652#if AIC_DEBUG_REGISTERS
@@ -832,20 +657,6 @@ ahd_reg_print_t ahd_lastscb_print;
832#endif 657#endif
833 658
834#if AIC_DEBUG_REGISTERS 659#if AIC_DEBUG_REGISTERS
835ahd_reg_print_t ahd_scsitest_print;
836#else
837#define ahd_scsitest_print(regvalue, cur_col, wrap) \
838 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap)
839#endif
840
841#if AIC_DEBUG_REGISTERS
842ahd_reg_print_t ahd_iopdnctl_print;
843#else
844#define ahd_iopdnctl_print(regvalue, cur_col, wrap) \
845 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap)
846#endif
847
848#if AIC_DEBUG_REGISTERS
849ahd_reg_print_t ahd_shaddr_print; 660ahd_reg_print_t ahd_shaddr_print;
850#else 661#else
851#define ahd_shaddr_print(regvalue, cur_col, wrap) \ 662#define ahd_shaddr_print(regvalue, cur_col, wrap) \
@@ -860,13 +671,6 @@ ahd_reg_print_t ahd_negoaddr_print;
860#endif 671#endif
861 672
862#if AIC_DEBUG_REGISTERS 673#if AIC_DEBUG_REGISTERS
863ahd_reg_print_t ahd_dgrpcrci_print;
864#else
865#define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \
866 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap)
867#endif
868
869#if AIC_DEBUG_REGISTERS
870ahd_reg_print_t ahd_negperiod_print; 674ahd_reg_print_t ahd_negperiod_print;
871#else 675#else
872#define ahd_negperiod_print(regvalue, cur_col, wrap) \ 676#define ahd_negperiod_print(regvalue, cur_col, wrap) \
@@ -874,13 +678,6 @@ ahd_reg_print_t ahd_negperiod_print;
874#endif 678#endif
875 679
876#if AIC_DEBUG_REGISTERS 680#if AIC_DEBUG_REGISTERS
877ahd_reg_print_t ahd_packcrci_print;
878#else
879#define ahd_packcrci_print(regvalue, cur_col, wrap) \
880 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap)
881#endif
882
883#if AIC_DEBUG_REGISTERS
884ahd_reg_print_t ahd_negoffset_print; 681ahd_reg_print_t ahd_negoffset_print;
885#else 682#else
886#define ahd_negoffset_print(regvalue, cur_col, wrap) \ 683#define ahd_negoffset_print(regvalue, cur_col, wrap) \
@@ -930,13 +727,6 @@ ahd_reg_print_t ahd_iownid_print;
930#endif 727#endif
931 728
932#if AIC_DEBUG_REGISTERS 729#if AIC_DEBUG_REGISTERS
933ahd_reg_print_t ahd_pll960ctl0_print;
934#else
935#define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \
936 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahd_reg_print_t ahd_shcnt_print; 730ahd_reg_print_t ahd_shcnt_print;
941#else 731#else
942#define ahd_shcnt_print(regvalue, cur_col, wrap) \ 732#define ahd_shcnt_print(regvalue, cur_col, wrap) \
@@ -951,27 +741,6 @@ ahd_reg_print_t ahd_townid_print;
951#endif 741#endif
952 742
953#if AIC_DEBUG_REGISTERS 743#if AIC_DEBUG_REGISTERS
954ahd_reg_print_t ahd_pll960ctl1_print;
955#else
956#define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \
957 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap)
958#endif
959
960#if AIC_DEBUG_REGISTERS
961ahd_reg_print_t ahd_pll960cnt0_print;
962#else
963#define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \
964 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap)
965#endif
966
967#if AIC_DEBUG_REGISTERS
968ahd_reg_print_t ahd_xsig_print;
969#else
970#define ahd_xsig_print(regvalue, cur_col, wrap) \
971 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap)
972#endif
973
974#if AIC_DEBUG_REGISTERS
975ahd_reg_print_t ahd_seloid_print; 744ahd_reg_print_t ahd_seloid_print;
976#else 745#else
977#define ahd_seloid_print(regvalue, cur_col, wrap) \ 746#define ahd_seloid_print(regvalue, cur_col, wrap) \
@@ -979,41 +748,6 @@ ahd_reg_print_t ahd_seloid_print;
979#endif 748#endif
980 749
981#if AIC_DEBUG_REGISTERS 750#if AIC_DEBUG_REGISTERS
982ahd_reg_print_t ahd_pll400ctl0_print;
983#else
984#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
985 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
986#endif
987
988#if AIC_DEBUG_REGISTERS
989ahd_reg_print_t ahd_fairness_print;
990#else
991#define ahd_fairness_print(regvalue, cur_col, wrap) \
992 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
993#endif
994
995#if AIC_DEBUG_REGISTERS
996ahd_reg_print_t ahd_pll400ctl1_print;
997#else
998#define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \
999 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap)
1000#endif
1001
1002#if AIC_DEBUG_REGISTERS
1003ahd_reg_print_t ahd_unfairness_print;
1004#else
1005#define ahd_unfairness_print(regvalue, cur_col, wrap) \
1006 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahd_reg_print_t ahd_pll400cnt0_print;
1011#else
1012#define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \
1013 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap)
1014#endif
1015
1016#if AIC_DEBUG_REGISTERS
1017ahd_reg_print_t ahd_haddr_print; 751ahd_reg_print_t ahd_haddr_print;
1018#else 752#else
1019#define ahd_haddr_print(regvalue, cur_col, wrap) \ 753#define ahd_haddr_print(regvalue, cur_col, wrap) \
@@ -1021,27 +755,6 @@ ahd_reg_print_t ahd_haddr_print;
1021#endif 755#endif
1022 756
1023#if AIC_DEBUG_REGISTERS 757#if AIC_DEBUG_REGISTERS
1024ahd_reg_print_t ahd_plldelay_print;
1025#else
1026#define ahd_plldelay_print(regvalue, cur_col, wrap) \
1027 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap)
1028#endif
1029
1030#if AIC_DEBUG_REGISTERS
1031ahd_reg_print_t ahd_hodmaadr_print;
1032#else
1033#define ahd_hodmaadr_print(regvalue, cur_col, wrap) \
1034 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahd_reg_print_t ahd_hodmacnt_print;
1039#else
1040#define ahd_hodmacnt_print(regvalue, cur_col, wrap) \
1041 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahd_reg_print_t ahd_hcnt_print; 758ahd_reg_print_t ahd_hcnt_print;
1046#else 759#else
1047#define ahd_hcnt_print(regvalue, cur_col, wrap) \ 760#define ahd_hcnt_print(regvalue, cur_col, wrap) \
@@ -1049,10 +762,10 @@ ahd_reg_print_t ahd_hcnt_print;
1049#endif 762#endif
1050 763
1051#if AIC_DEBUG_REGISTERS 764#if AIC_DEBUG_REGISTERS
1052ahd_reg_print_t ahd_hodmaen_print; 765ahd_reg_print_t ahd_sghaddr_print;
1053#else 766#else
1054#define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 767#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
1055 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 768 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
1056#endif 769#endif
1057 770
1058#if AIC_DEBUG_REGISTERS 771#if AIC_DEBUG_REGISTERS
@@ -1063,10 +776,10 @@ ahd_reg_print_t ahd_scbhaddr_print;
1063#endif 776#endif
1064 777
1065#if AIC_DEBUG_REGISTERS 778#if AIC_DEBUG_REGISTERS
1066ahd_reg_print_t ahd_sghaddr_print; 779ahd_reg_print_t ahd_sghcnt_print;
1067#else 780#else
1068#define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 781#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1069 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 782 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1070#endif 783#endif
1071 784
1072#if AIC_DEBUG_REGISTERS 785#if AIC_DEBUG_REGISTERS
@@ -1077,13 +790,6 @@ ahd_reg_print_t ahd_scbhcnt_print;
1077#endif 790#endif
1078 791
1079#if AIC_DEBUG_REGISTERS 792#if AIC_DEBUG_REGISTERS
1080ahd_reg_print_t ahd_sghcnt_print;
1081#else
1082#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1083 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1084#endif
1085
1086#if AIC_DEBUG_REGISTERS
1087ahd_reg_print_t ahd_dff_thrsh_print; 793ahd_reg_print_t ahd_dff_thrsh_print;
1088#else 794#else
1089#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 795#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
@@ -1091,132 +797,6 @@ ahd_reg_print_t ahd_dff_thrsh_print;
1091#endif 797#endif
1092 798
1093#if AIC_DEBUG_REGISTERS 799#if AIC_DEBUG_REGISTERS
1094ahd_reg_print_t ahd_romaddr_print;
1095#else
1096#define ahd_romaddr_print(regvalue, cur_col, wrap) \
1097 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap)
1098#endif
1099
1100#if AIC_DEBUG_REGISTERS
1101ahd_reg_print_t ahd_romcntrl_print;
1102#else
1103#define ahd_romcntrl_print(regvalue, cur_col, wrap) \
1104 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap)
1105#endif
1106
1107#if AIC_DEBUG_REGISTERS
1108ahd_reg_print_t ahd_romdata_print;
1109#else
1110#define ahd_romdata_print(regvalue, cur_col, wrap) \
1111 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap)
1112#endif
1113
1114#if AIC_DEBUG_REGISTERS
1115ahd_reg_print_t ahd_cmcrxmsg0_print;
1116#else
1117#define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \
1118 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap)
1119#endif
1120
1121#if AIC_DEBUG_REGISTERS
1122ahd_reg_print_t ahd_roenable_print;
1123#else
1124#define ahd_roenable_print(regvalue, cur_col, wrap) \
1125 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
1126#endif
1127
1128#if AIC_DEBUG_REGISTERS
1129ahd_reg_print_t ahd_ovlyrxmsg0_print;
1130#else
1131#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
1132 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap)
1133#endif
1134
1135#if AIC_DEBUG_REGISTERS
1136ahd_reg_print_t ahd_dchrxmsg0_print;
1137#else
1138#define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \
1139 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap)
1140#endif
1141
1142#if AIC_DEBUG_REGISTERS
1143ahd_reg_print_t ahd_ovlyrxmsg1_print;
1144#else
1145#define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \
1146 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap)
1147#endif
1148
1149#if AIC_DEBUG_REGISTERS
1150ahd_reg_print_t ahd_nsenable_print;
1151#else
1152#define ahd_nsenable_print(regvalue, cur_col, wrap) \
1153 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
1154#endif
1155
1156#if AIC_DEBUG_REGISTERS
1157ahd_reg_print_t ahd_cmcrxmsg1_print;
1158#else
1159#define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \
1160 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap)
1161#endif
1162
1163#if AIC_DEBUG_REGISTERS
1164ahd_reg_print_t ahd_dchrxmsg1_print;
1165#else
1166#define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \
1167 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap)
1168#endif
1169
1170#if AIC_DEBUG_REGISTERS
1171ahd_reg_print_t ahd_dchrxmsg2_print;
1172#else
1173#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
1174 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap)
1175#endif
1176
1177#if AIC_DEBUG_REGISTERS
1178ahd_reg_print_t ahd_cmcrxmsg2_print;
1179#else
1180#define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \
1181 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap)
1182#endif
1183
1184#if AIC_DEBUG_REGISTERS
1185ahd_reg_print_t ahd_ost_print;
1186#else
1187#define ahd_ost_print(regvalue, cur_col, wrap) \
1188 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap)
1189#endif
1190
1191#if AIC_DEBUG_REGISTERS
1192ahd_reg_print_t ahd_ovlyrxmsg2_print;
1193#else
1194#define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \
1195 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap)
1196#endif
1197
1198#if AIC_DEBUG_REGISTERS
1199ahd_reg_print_t ahd_dchrxmsg3_print;
1200#else
1201#define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \
1202 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap)
1203#endif
1204
1205#if AIC_DEBUG_REGISTERS
1206ahd_reg_print_t ahd_ovlyrxmsg3_print;
1207#else
1208#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
1209 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
1210#endif
1211
1212#if AIC_DEBUG_REGISTERS
1213ahd_reg_print_t ahd_cmcrxmsg3_print;
1214#else
1215#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
1216 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap)
1217#endif
1218
1219#if AIC_DEBUG_REGISTERS
1220ahd_reg_print_t ahd_pcixctl_print; 800ahd_reg_print_t ahd_pcixctl_print;
1221#else 801#else
1222#define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 802#define ahd_pcixctl_print(regvalue, cur_col, wrap) \
@@ -1224,34 +804,6 @@ ahd_reg_print_t ahd_pcixctl_print;
1224#endif 804#endif
1225 805
1226#if AIC_DEBUG_REGISTERS 806#if AIC_DEBUG_REGISTERS
1227ahd_reg_print_t ahd_ovlyseqbcnt_print;
1228#else
1229#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
1230 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap)
1231#endif
1232
1233#if AIC_DEBUG_REGISTERS
1234ahd_reg_print_t ahd_dchseqbcnt_print;
1235#else
1236#define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \
1237 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap)
1238#endif
1239
1240#if AIC_DEBUG_REGISTERS
1241ahd_reg_print_t ahd_cmcseqbcnt_print;
1242#else
1243#define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \
1244 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap)
1245#endif
1246
1247#if AIC_DEBUG_REGISTERS
1248ahd_reg_print_t ahd_cmcspltstat0_print;
1249#else
1250#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
1251 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1252#endif
1253
1254#if AIC_DEBUG_REGISTERS
1255ahd_reg_print_t ahd_dchspltstat0_print; 807ahd_reg_print_t ahd_dchspltstat0_print;
1256#else 808#else
1257#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 809#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
@@ -1259,27 +811,6 @@ ahd_reg_print_t ahd_dchspltstat0_print;
1259#endif 811#endif
1260 812
1261#if AIC_DEBUG_REGISTERS 813#if AIC_DEBUG_REGISTERS
1262ahd_reg_print_t ahd_ovlyspltstat0_print;
1263#else
1264#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
1265 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1266#endif
1267
1268#if AIC_DEBUG_REGISTERS
1269ahd_reg_print_t ahd_cmcspltstat1_print;
1270#else
1271#define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \
1272 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1273#endif
1274
1275#if AIC_DEBUG_REGISTERS
1276ahd_reg_print_t ahd_ovlyspltstat1_print;
1277#else
1278#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
1279 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1280#endif
1281
1282#if AIC_DEBUG_REGISTERS
1283ahd_reg_print_t ahd_dchspltstat1_print; 814ahd_reg_print_t ahd_dchspltstat1_print;
1284#else 815#else
1285#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 816#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
@@ -1287,90 +818,6 @@ ahd_reg_print_t ahd_dchspltstat1_print;
1287#endif 818#endif
1288 819
1289#if AIC_DEBUG_REGISTERS 820#if AIC_DEBUG_REGISTERS
1290ahd_reg_print_t ahd_sgrxmsg0_print;
1291#else
1292#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
1293 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap)
1294#endif
1295
1296#if AIC_DEBUG_REGISTERS
1297ahd_reg_print_t ahd_slvspltoutadr0_print;
1298#else
1299#define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \
1300 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap)
1301#endif
1302
1303#if AIC_DEBUG_REGISTERS
1304ahd_reg_print_t ahd_sgrxmsg1_print;
1305#else
1306#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
1307 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap)
1308#endif
1309
1310#if AIC_DEBUG_REGISTERS
1311ahd_reg_print_t ahd_slvspltoutadr1_print;
1312#else
1313#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
1314 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
1315#endif
1316
1317#if AIC_DEBUG_REGISTERS
1318ahd_reg_print_t ahd_sgrxmsg2_print;
1319#else
1320#define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \
1321 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap)
1322#endif
1323
1324#if AIC_DEBUG_REGISTERS
1325ahd_reg_print_t ahd_slvspltoutadr2_print;
1326#else
1327#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
1328 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
1329#endif
1330
1331#if AIC_DEBUG_REGISTERS
1332ahd_reg_print_t ahd_sgrxmsg3_print;
1333#else
1334#define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \
1335 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap)
1336#endif
1337
1338#if AIC_DEBUG_REGISTERS
1339ahd_reg_print_t ahd_slvspltoutadr3_print;
1340#else
1341#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
1342 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap)
1343#endif
1344
1345#if AIC_DEBUG_REGISTERS
1346ahd_reg_print_t ahd_sgseqbcnt_print;
1347#else
1348#define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \
1349 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap)
1350#endif
1351
1352#if AIC_DEBUG_REGISTERS
1353ahd_reg_print_t ahd_slvspltoutattr0_print;
1354#else
1355#define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \
1356 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap)
1357#endif
1358
1359#if AIC_DEBUG_REGISTERS
1360ahd_reg_print_t ahd_slvspltoutattr1_print;
1361#else
1362#define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \
1363 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap)
1364#endif
1365
1366#if AIC_DEBUG_REGISTERS
1367ahd_reg_print_t ahd_slvspltoutattr2_print;
1368#else
1369#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
1370 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
1371#endif
1372
1373#if AIC_DEBUG_REGISTERS
1374ahd_reg_print_t ahd_sgspltstat0_print; 821ahd_reg_print_t ahd_sgspltstat0_print;
1375#else 822#else
1376#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 823#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
@@ -1385,13 +832,6 @@ ahd_reg_print_t ahd_sgspltstat1_print;
1385#endif 832#endif
1386 833
1387#if AIC_DEBUG_REGISTERS 834#if AIC_DEBUG_REGISTERS
1388ahd_reg_print_t ahd_sfunct_print;
1389#else
1390#define ahd_sfunct_print(regvalue, cur_col, wrap) \
1391 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
1392#endif
1393
1394#if AIC_DEBUG_REGISTERS
1395ahd_reg_print_t ahd_df0pcistat_print; 835ahd_reg_print_t ahd_df0pcistat_print;
1396#else 836#else
1397#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 837#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
@@ -1406,41 +846,6 @@ ahd_reg_print_t ahd_reg0_print;
1406#endif 846#endif
1407 847
1408#if AIC_DEBUG_REGISTERS 848#if AIC_DEBUG_REGISTERS
1409ahd_reg_print_t ahd_df1pcistat_print;
1410#else
1411#define ahd_df1pcistat_print(regvalue, cur_col, wrap) \
1412 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap)
1413#endif
1414
1415#if AIC_DEBUG_REGISTERS
1416ahd_reg_print_t ahd_sgpcistat_print;
1417#else
1418#define ahd_sgpcistat_print(regvalue, cur_col, wrap) \
1419 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap)
1420#endif
1421
1422#if AIC_DEBUG_REGISTERS
1423ahd_reg_print_t ahd_reg1_print;
1424#else
1425#define ahd_reg1_print(regvalue, cur_col, wrap) \
1426 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap)
1427#endif
1428
1429#if AIC_DEBUG_REGISTERS
1430ahd_reg_print_t ahd_cmcpcistat_print;
1431#else
1432#define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \
1433 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap)
1434#endif
1435
1436#if AIC_DEBUG_REGISTERS
1437ahd_reg_print_t ahd_ovlypcistat_print;
1438#else
1439#define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \
1440 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap)
1441#endif
1442
1443#if AIC_DEBUG_REGISTERS
1444ahd_reg_print_t ahd_reg_isr_print; 849ahd_reg_print_t ahd_reg_isr_print;
1445#else 850#else
1446#define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 851#define ahd_reg_isr_print(regvalue, cur_col, wrap) \
@@ -1455,13 +860,6 @@ ahd_reg_print_t ahd_sg_state_print;
1455#endif 860#endif
1456 861
1457#if AIC_DEBUG_REGISTERS 862#if AIC_DEBUG_REGISTERS
1458ahd_reg_print_t ahd_msipcistat_print;
1459#else
1460#define ahd_msipcistat_print(regvalue, cur_col, wrap) \
1461 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap)
1462#endif
1463
1464#if AIC_DEBUG_REGISTERS
1465ahd_reg_print_t ahd_targpcistat_print; 863ahd_reg_print_t ahd_targpcistat_print;
1466#else 864#else
1467#define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 865#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
@@ -1469,13 +867,6 @@ ahd_reg_print_t ahd_targpcistat_print;
1469#endif 867#endif
1470 868
1471#if AIC_DEBUG_REGISTERS 869#if AIC_DEBUG_REGISTERS
1472ahd_reg_print_t ahd_data_count_odd_print;
1473#else
1474#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
1475 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
1476#endif
1477
1478#if AIC_DEBUG_REGISTERS
1479ahd_reg_print_t ahd_scbptr_print; 870ahd_reg_print_t ahd_scbptr_print;
1480#else 871#else
1481#define ahd_scbptr_print(regvalue, cur_col, wrap) \ 872#define ahd_scbptr_print(regvalue, cur_col, wrap) \
@@ -1483,13 +874,6 @@ ahd_reg_print_t ahd_scbptr_print;
1483#endif 874#endif
1484 875
1485#if AIC_DEBUG_REGISTERS 876#if AIC_DEBUG_REGISTERS
1486ahd_reg_print_t ahd_ccscbacnt_print;
1487#else
1488#define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \
1489 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap)
1490#endif
1491
1492#if AIC_DEBUG_REGISTERS
1493ahd_reg_print_t ahd_scbautoptr_print; 877ahd_reg_print_t ahd_scbautoptr_print;
1494#else 878#else
1495#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 879#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
@@ -1504,13 +888,6 @@ ahd_reg_print_t ahd_ccsgaddr_print;
1504#endif 888#endif
1505 889
1506#if AIC_DEBUG_REGISTERS 890#if AIC_DEBUG_REGISTERS
1507ahd_reg_print_t ahd_ccscbadr_bk_print;
1508#else
1509#define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \
1510 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap)
1511#endif
1512
1513#if AIC_DEBUG_REGISTERS
1514ahd_reg_print_t ahd_ccscbaddr_print; 891ahd_reg_print_t ahd_ccscbaddr_print;
1515#else 892#else
1516#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 893#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
@@ -1518,13 +895,6 @@ ahd_reg_print_t ahd_ccscbaddr_print;
1518#endif 895#endif
1519 896
1520#if AIC_DEBUG_REGISTERS 897#if AIC_DEBUG_REGISTERS
1521ahd_reg_print_t ahd_cmc_rambist_print;
1522#else
1523#define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \
1524 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap)
1525#endif
1526
1527#if AIC_DEBUG_REGISTERS
1528ahd_reg_print_t ahd_ccscbctl_print; 898ahd_reg_print_t ahd_ccscbctl_print;
1529#else 899#else
1530#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 900#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
@@ -1546,13 +916,6 @@ ahd_reg_print_t ahd_ccsgram_print;
1546#endif 916#endif
1547 917
1548#if AIC_DEBUG_REGISTERS 918#if AIC_DEBUG_REGISTERS
1549ahd_reg_print_t ahd_flexadr_print;
1550#else
1551#define ahd_flexadr_print(regvalue, cur_col, wrap) \
1552 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap)
1553#endif
1554
1555#if AIC_DEBUG_REGISTERS
1556ahd_reg_print_t ahd_ccscbram_print; 919ahd_reg_print_t ahd_ccscbram_print;
1557#else 920#else
1558#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 921#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
@@ -1560,27 +923,6 @@ ahd_reg_print_t ahd_ccscbram_print;
1560#endif 923#endif
1561 924
1562#if AIC_DEBUG_REGISTERS 925#if AIC_DEBUG_REGISTERS
1563ahd_reg_print_t ahd_flexcnt_print;
1564#else
1565#define ahd_flexcnt_print(regvalue, cur_col, wrap) \
1566 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap)
1567#endif
1568
1569#if AIC_DEBUG_REGISTERS
1570ahd_reg_print_t ahd_flexdmastat_print;
1571#else
1572#define ahd_flexdmastat_print(regvalue, cur_col, wrap) \
1573 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap)
1574#endif
1575
1576#if AIC_DEBUG_REGISTERS
1577ahd_reg_print_t ahd_flexdata_print;
1578#else
1579#define ahd_flexdata_print(regvalue, cur_col, wrap) \
1580 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap)
1581#endif
1582
1583#if AIC_DEBUG_REGISTERS
1584ahd_reg_print_t ahd_brddat_print; 926ahd_reg_print_t ahd_brddat_print;
1585#else 927#else
1586#define ahd_brddat_print(regvalue, cur_col, wrap) \ 928#define ahd_brddat_print(regvalue, cur_col, wrap) \
@@ -1623,27 +965,6 @@ ahd_reg_print_t ahd_seestat_print;
1623#endif 965#endif
1624 966
1625#if AIC_DEBUG_REGISTERS 967#if AIC_DEBUG_REGISTERS
1626ahd_reg_print_t ahd_scbcnt_print;
1627#else
1628#define ahd_scbcnt_print(regvalue, cur_col, wrap) \
1629 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap)
1630#endif
1631
1632#if AIC_DEBUG_REGISTERS
1633ahd_reg_print_t ahd_dfwaddr_print;
1634#else
1635#define ahd_dfwaddr_print(regvalue, cur_col, wrap) \
1636 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap)
1637#endif
1638
1639#if AIC_DEBUG_REGISTERS
1640ahd_reg_print_t ahd_dspfltrctl_print;
1641#else
1642#define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \
1643 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap)
1644#endif
1645
1646#if AIC_DEBUG_REGISTERS
1647ahd_reg_print_t ahd_dspdatactl_print; 968ahd_reg_print_t ahd_dspdatactl_print;
1648#else 969#else
1649#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 970#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
@@ -1651,27 +972,6 @@ ahd_reg_print_t ahd_dspdatactl_print;
1651#endif 972#endif
1652 973
1653#if AIC_DEBUG_REGISTERS 974#if AIC_DEBUG_REGISTERS
1654ahd_reg_print_t ahd_dfraddr_print;
1655#else
1656#define ahd_dfraddr_print(regvalue, cur_col, wrap) \
1657 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap)
1658#endif
1659
1660#if AIC_DEBUG_REGISTERS
1661ahd_reg_print_t ahd_dspreqctl_print;
1662#else
1663#define ahd_dspreqctl_print(regvalue, cur_col, wrap) \
1664 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap)
1665#endif
1666
1667#if AIC_DEBUG_REGISTERS
1668ahd_reg_print_t ahd_dspackctl_print;
1669#else
1670#define ahd_dspackctl_print(regvalue, cur_col, wrap) \
1671 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap)
1672#endif
1673
1674#if AIC_DEBUG_REGISTERS
1675ahd_reg_print_t ahd_dfdat_print; 975ahd_reg_print_t ahd_dfdat_print;
1676#else 976#else
1677#define ahd_dfdat_print(regvalue, cur_col, wrap) \ 977#define ahd_dfdat_print(regvalue, cur_col, wrap) \
@@ -1693,76 +993,6 @@ ahd_reg_print_t ahd_wrtbiasctl_print;
1693#endif 993#endif
1694 994
1695#if AIC_DEBUG_REGISTERS 995#if AIC_DEBUG_REGISTERS
1696ahd_reg_print_t ahd_rcvrbiosctl_print;
1697#else
1698#define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \
1699 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap)
1700#endif
1701
1702#if AIC_DEBUG_REGISTERS
1703ahd_reg_print_t ahd_wrtbiascalc_print;
1704#else
1705#define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \
1706 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap)
1707#endif
1708
1709#if AIC_DEBUG_REGISTERS
1710ahd_reg_print_t ahd_rcvrbiascalc_print;
1711#else
1712#define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \
1713 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap)
1714#endif
1715
1716#if AIC_DEBUG_REGISTERS
1717ahd_reg_print_t ahd_dfptrs_print;
1718#else
1719#define ahd_dfptrs_print(regvalue, cur_col, wrap) \
1720 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap)
1721#endif
1722
1723#if AIC_DEBUG_REGISTERS
1724ahd_reg_print_t ahd_skewcalc_print;
1725#else
1726#define ahd_skewcalc_print(regvalue, cur_col, wrap) \
1727 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap)
1728#endif
1729
1730#if AIC_DEBUG_REGISTERS
1731ahd_reg_print_t ahd_dfbkptr_print;
1732#else
1733#define ahd_dfbkptr_print(regvalue, cur_col, wrap) \
1734 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap)
1735#endif
1736
1737#if AIC_DEBUG_REGISTERS
1738ahd_reg_print_t ahd_dfdbctl_print;
1739#else
1740#define ahd_dfdbctl_print(regvalue, cur_col, wrap) \
1741 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap)
1742#endif
1743
1744#if AIC_DEBUG_REGISTERS
1745ahd_reg_print_t ahd_dfscnt_print;
1746#else
1747#define ahd_dfscnt_print(regvalue, cur_col, wrap) \
1748 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap)
1749#endif
1750
1751#if AIC_DEBUG_REGISTERS
1752ahd_reg_print_t ahd_dfbcnt_print;
1753#else
1754#define ahd_dfbcnt_print(regvalue, cur_col, wrap) \
1755 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap)
1756#endif
1757
1758#if AIC_DEBUG_REGISTERS
1759ahd_reg_print_t ahd_ovlyaddr_print;
1760#else
1761#define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \
1762 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap)
1763#endif
1764
1765#if AIC_DEBUG_REGISTERS
1766ahd_reg_print_t ahd_seqctl0_print; 996ahd_reg_print_t ahd_seqctl0_print;
1767#else 997#else
1768#define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 998#define ahd_seqctl0_print(regvalue, cur_col, wrap) \
@@ -1770,13 +1000,6 @@ ahd_reg_print_t ahd_seqctl0_print;
1770#endif 1000#endif
1771 1001
1772#if AIC_DEBUG_REGISTERS 1002#if AIC_DEBUG_REGISTERS
1773ahd_reg_print_t ahd_seqctl1_print;
1774#else
1775#define ahd_seqctl1_print(regvalue, cur_col, wrap) \
1776 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap)
1777#endif
1778
1779#if AIC_DEBUG_REGISTERS
1780ahd_reg_print_t ahd_flags_print; 1003ahd_reg_print_t ahd_flags_print;
1781#else 1004#else
1782#define ahd_flags_print(regvalue, cur_col, wrap) \ 1005#define ahd_flags_print(regvalue, cur_col, wrap) \
@@ -1826,20 +1049,6 @@ ahd_reg_print_t ahd_dindex_print;
1826#endif 1049#endif
1827 1050
1828#if AIC_DEBUG_REGISTERS 1051#if AIC_DEBUG_REGISTERS
1829ahd_reg_print_t ahd_brkaddr0_print;
1830#else
1831#define ahd_brkaddr0_print(regvalue, cur_col, wrap) \
1832 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap)
1833#endif
1834
1835#if AIC_DEBUG_REGISTERS
1836ahd_reg_print_t ahd_brkaddr1_print;
1837#else
1838#define ahd_brkaddr1_print(regvalue, cur_col, wrap) \
1839 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap)
1840#endif
1841
1842#if AIC_DEBUG_REGISTERS
1843ahd_reg_print_t ahd_allones_print; 1052ahd_reg_print_t ahd_allones_print;
1844#else 1053#else
1845#define ahd_allones_print(regvalue, cur_col, wrap) \ 1054#define ahd_allones_print(regvalue, cur_col, wrap) \
@@ -1875,13 +1084,6 @@ ahd_reg_print_t ahd_dindir_print;
1875#endif 1084#endif
1876 1085
1877#if AIC_DEBUG_REGISTERS 1086#if AIC_DEBUG_REGISTERS
1878ahd_reg_print_t ahd_function1_print;
1879#else
1880#define ahd_function1_print(regvalue, cur_col, wrap) \
1881 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap)
1882#endif
1883
1884#if AIC_DEBUG_REGISTERS
1885ahd_reg_print_t ahd_stack_print; 1087ahd_reg_print_t ahd_stack_print;
1886#else 1088#else
1887#define ahd_stack_print(regvalue, cur_col, wrap) \ 1089#define ahd_stack_print(regvalue, cur_col, wrap) \
@@ -1903,13 +1105,6 @@ ahd_reg_print_t ahd_curaddr_print;
1903#endif 1105#endif
1904 1106
1905#if AIC_DEBUG_REGISTERS 1107#if AIC_DEBUG_REGISTERS
1906ahd_reg_print_t ahd_lastaddr_print;
1907#else
1908#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
1909 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
1910#endif
1911
1912#if AIC_DEBUG_REGISTERS
1913ahd_reg_print_t ahd_intvec2_addr_print; 1108ahd_reg_print_t ahd_intvec2_addr_print;
1914#else 1109#else
1915#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1110#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
@@ -1931,24 +1126,17 @@ ahd_reg_print_t ahd_accum_save_print;
1931#endif 1126#endif
1932 1127
1933#if AIC_DEBUG_REGISTERS 1128#if AIC_DEBUG_REGISTERS
1934ahd_reg_print_t ahd_waiting_scb_tails_print; 1129ahd_reg_print_t ahd_sram_base_print;
1935#else
1936#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1937 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1938#endif
1939
1940#if AIC_DEBUG_REGISTERS
1941ahd_reg_print_t ahd_ahd_pci_config_base_print;
1942#else 1130#else
1943#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1131#define ahd_sram_base_print(regvalue, cur_col, wrap) \
1944 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1132 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1945#endif 1133#endif
1946 1134
1947#if AIC_DEBUG_REGISTERS 1135#if AIC_DEBUG_REGISTERS
1948ahd_reg_print_t ahd_sram_base_print; 1136ahd_reg_print_t ahd_waiting_scb_tails_print;
1949#else 1137#else
1950#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1138#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1951 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1139 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1952#endif 1140#endif
1953 1141
1954#if AIC_DEBUG_REGISTERS 1142#if AIC_DEBUG_REGISTERS
@@ -2218,17 +1406,17 @@ ahd_reg_print_t ahd_mk_message_scsiid_print;
2218#endif 1406#endif
2219 1407
2220#if AIC_DEBUG_REGISTERS 1408#if AIC_DEBUG_REGISTERS
2221ahd_reg_print_t ahd_scb_base_print; 1409ahd_reg_print_t ahd_scb_residual_datacnt_print;
2222#else 1410#else
2223#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 1411#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
2224 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 1412 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
2225#endif 1413#endif
2226 1414
2227#if AIC_DEBUG_REGISTERS 1415#if AIC_DEBUG_REGISTERS
2228ahd_reg_print_t ahd_scb_residual_datacnt_print; 1416ahd_reg_print_t ahd_scb_base_print;
2229#else 1417#else
2230#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 1418#define ahd_scb_base_print(regvalue, cur_col, wrap) \
2231 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 1419 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
2232#endif 1420#endif
2233 1421
2234#if AIC_DEBUG_REGISTERS 1422#if AIC_DEBUG_REGISTERS
@@ -2246,27 +1434,6 @@ ahd_reg_print_t ahd_scb_scsi_status_print;
2246#endif 1434#endif
2247 1435
2248#if AIC_DEBUG_REGISTERS 1436#if AIC_DEBUG_REGISTERS
2249ahd_reg_print_t ahd_scb_target_phases_print;
2250#else
2251#define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \
2252 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap)
2253#endif
2254
2255#if AIC_DEBUG_REGISTERS
2256ahd_reg_print_t ahd_scb_target_data_dir_print;
2257#else
2258#define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \
2259 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap)
2260#endif
2261
2262#if AIC_DEBUG_REGISTERS
2263ahd_reg_print_t ahd_scb_target_itag_print;
2264#else
2265#define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \
2266 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap)
2267#endif
2268
2269#if AIC_DEBUG_REGISTERS
2270ahd_reg_print_t ahd_scb_sense_busaddr_print; 1437ahd_reg_print_t ahd_scb_sense_busaddr_print;
2271#else 1438#else
2272#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 1439#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
@@ -2365,13 +1532,6 @@ ahd_reg_print_t ahd_scb_next2_print;
2365#endif 1532#endif
2366 1533
2367#if AIC_DEBUG_REGISTERS 1534#if AIC_DEBUG_REGISTERS
2368ahd_reg_print_t ahd_scb_spare_print;
2369#else
2370#define ahd_scb_spare_print(regvalue, cur_col, wrap) \
2371 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap)
2372#endif
2373
2374#if AIC_DEBUG_REGISTERS
2375ahd_reg_print_t ahd_scb_disconnected_lists_print; 1535ahd_reg_print_t ahd_scb_disconnected_lists_print;
2376#else 1536#else
2377#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 1537#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
@@ -2557,10 +1717,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2557 1717
2558#define SG_CACHE_PRE 0x1b 1718#define SG_CACHE_PRE 0x1b
2559 1719
2560#define LQIN 0x20
2561
2562#define TYPEPTR 0x20 1720#define TYPEPTR 0x20
2563 1721
1722#define LQIN 0x20
1723
2564#define TAGPTR 0x21 1724#define TAGPTR 0x21
2565 1725
2566#define LUNPTR 0x22 1726#define LUNPTR 0x22
@@ -2620,14 +1780,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2620#define SINGLECMD 0x02 1780#define SINGLECMD 0x02
2621#define ABORTPENDING 0x01 1781#define ABORTPENDING 0x01
2622 1782
2623#define SCSBIST0 0x39
2624#define GSBISTERR 0x40
2625#define GSBISTDONE 0x20
2626#define GSBISTRUN 0x10
2627#define OSBISTERR 0x04
2628#define OSBISTDONE 0x02
2629#define OSBISTRUN 0x01
2630
2631#define LQCTL2 0x39 1783#define LQCTL2 0x39
2632#define LQIRETRY 0x80 1784#define LQIRETRY 0x80
2633#define LQICONTINUE 0x40 1785#define LQICONTINUE 0x40
@@ -2638,10 +1790,13 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2638#define LQOTOIDLE 0x02 1790#define LQOTOIDLE 0x02
2639#define LQOPAUSE 0x01 1791#define LQOPAUSE 0x01
2640 1792
2641#define SCSBIST1 0x3a 1793#define SCSBIST0 0x39
2642#define NTBISTERR 0x04 1794#define GSBISTERR 0x40
2643#define NTBISTDONE 0x02 1795#define GSBISTDONE 0x20
2644#define NTBISTRUN 0x01 1796#define GSBISTRUN 0x10
1797#define OSBISTERR 0x04
1798#define OSBISTDONE 0x02
1799#define OSBISTRUN 0x01
2645 1800
2646#define SCSISEQ0 0x3a 1801#define SCSISEQ0 0x3a
2647#define TEMODEO 0x80 1802#define TEMODEO 0x80
@@ -2650,8 +1805,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2650#define FORCEBUSFREE 0x10 1805#define FORCEBUSFREE 0x10
2651#define SCSIRSTO 0x01 1806#define SCSIRSTO 0x01
2652 1807
1808#define SCSBIST1 0x3a
1809#define NTBISTERR 0x04
1810#define NTBISTDONE 0x02
1811#define NTBISTRUN 0x01
1812
2653#define SCSISEQ1 0x3b 1813#define SCSISEQ1 0x3b
2654 1814
1815#define BUSINITID 0x3c
1816
2655#define SXFRCTL0 0x3c 1817#define SXFRCTL0 0x3c
2656#define DFON 0x80 1818#define DFON 0x80
2657#define DFPEXP 0x40 1819#define DFPEXP 0x40
@@ -2660,8 +1822,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2660 1822
2661#define DLCOUNT 0x3c 1823#define DLCOUNT 0x3c
2662 1824
2663#define BUSINITID 0x3c
2664
2665#define SXFRCTL1 0x3d 1825#define SXFRCTL1 0x3d
2666#define BITBUCKET 0x80 1826#define BITBUCKET 0x80
2667#define ENSACHK 0x40 1827#define ENSACHK 0x40
@@ -2686,6 +1846,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2686#define CURRFIFO_1 0x01 1846#define CURRFIFO_1 0x01
2687#define CURRFIFO_0 0x00 1847#define CURRFIFO_0 0x00
2688 1848
1849#define MULTARGID 0x40
1850
2689#define SCSISIGO 0x40 1851#define SCSISIGO 0x40
2690#define CDO 0x80 1852#define CDO 0x80
2691#define IOO 0x40 1853#define IOO 0x40
@@ -2696,8 +1858,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2696#define REQO 0x02 1858#define REQO 0x02
2697#define ACKO 0x01 1859#define ACKO 0x01
2698 1860
2699#define MULTARGID 0x40
2700
2701#define SCSISIGI 0x41 1861#define SCSISIGI 0x41
2702#define ATNI 0x10 1862#define ATNI 0x10
2703#define SELI 0x08 1863#define SELI 0x08
@@ -2744,15 +1904,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2744#define ENAB20 0x04 1904#define ENAB20 0x04
2745#define SELWIDE 0x02 1905#define SELWIDE 0x02
2746 1906
2747#define CLRSINT0 0x4b
2748#define CLRSELDO 0x40
2749#define CLRSELDI 0x20
2750#define CLRSELINGO 0x10
2751#define CLRIOERR 0x08
2752#define CLROVERRUN 0x04
2753#define CLRSPIORDY 0x02
2754#define CLRARBDO 0x01
2755
2756#define SSTAT0 0x4b 1907#define SSTAT0 0x4b
2757#define TARGET 0x80 1908#define TARGET 0x80
2758#define SELDO 0x40 1909#define SELDO 0x40
@@ -2772,14 +1923,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2772#define ENSPIORDY 0x02 1923#define ENSPIORDY 0x02
2773#define ENARBDO 0x01 1924#define ENARBDO 0x01
2774 1925
2775#define CLRSINT1 0x4c 1926#define CLRSINT0 0x4b
2776#define CLRSELTIMEO 0x80 1927#define CLRSELDO 0x40
2777#define CLRATNO 0x40 1928#define CLRSELDI 0x20
2778#define CLRSCSIRSTI 0x20 1929#define CLRSELINGO 0x10
2779#define CLRBUSFREE 0x08 1930#define CLRIOERR 0x08
2780#define CLRSCSIPERR 0x04 1931#define CLROVERRUN 0x04
2781#define CLRSTRB2FAST 0x02 1932#define CLRSPIORDY 0x02
2782#define CLRREQINIT 0x01 1933#define CLRARBDO 0x01
2783 1934
2784#define SSTAT1 0x4c 1935#define SSTAT1 0x4c
2785#define SELTO 0x80 1936#define SELTO 0x80
@@ -2791,6 +1942,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2791#define STRB2FAST 0x02 1942#define STRB2FAST 0x02
2792#define REQINIT 0x01 1943#define REQINIT 0x01
2793 1944
1945#define CLRSINT1 0x4c
1946#define CLRSELTIMEO 0x80
1947#define CLRATNO 0x40
1948#define CLRSCSIRSTI 0x20
1949#define CLRBUSFREE 0x08
1950#define CLRSCSIPERR 0x04
1951#define CLRSTRB2FAST 0x02
1952#define CLRREQINIT 0x01
1953
2794#define SSTAT2 0x4d 1954#define SSTAT2 0x4d
2795#define BUSFREETIME 0xc0 1955#define BUSFREETIME 0xc0
2796#define NONPACKREQ 0x20 1956#define NONPACKREQ 0x20
@@ -2838,14 +1998,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2838#define LQIATNLQ 0x02 1998#define LQIATNLQ 0x02
2839#define LQIATNCMD 0x01 1999#define LQIATNCMD 0x01
2840 2000
2841#define CLRLQIINT0 0x50
2842#define CLRLQIATNQAS 0x20
2843#define CLRLQICRCT1 0x10
2844#define CLRLQICRCT2 0x08
2845#define CLRLQIBADLQT 0x04
2846#define CLRLQIATNLQ 0x02
2847#define CLRLQIATNCMD 0x01
2848
2849#define LQIMODE0 0x50 2001#define LQIMODE0 0x50
2850#define ENLQIATNQASK 0x20 2002#define ENLQIATNQASK 0x20
2851#define ENLQICRCT1 0x10 2003#define ENLQICRCT1 0x10
@@ -2854,6 +2006,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2854#define ENLQIATNLQ 0x02 2006#define ENLQIATNLQ 0x02
2855#define ENLQIATNCMD 0x01 2007#define ENLQIATNCMD 0x01
2856 2008
2009#define CLRLQIINT0 0x50
2010#define CLRLQIATNQAS 0x20
2011#define CLRLQICRCT1 0x10
2012#define CLRLQICRCT2 0x08
2013#define CLRLQIBADLQT 0x04
2014#define CLRLQIATNLQ 0x02
2015#define CLRLQIATNCMD 0x01
2016
2857#define LQIMODE1 0x51 2017#define LQIMODE1 0x51
2858#define ENLQIPHASE_LQ 0x80 2018#define ENLQIPHASE_LQ 0x80
2859#define ENLQIPHASE_NLQ 0x40 2019#define ENLQIPHASE_NLQ 0x40
@@ -2976,6 +2136,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2976 2136
2977#define LQOSCSCTL 0x5a 2137#define LQOSCSCTL 0x5a
2978#define LQOH2A_VERSION 0x80 2138#define LQOH2A_VERSION 0x80
2139#define LQOBUSETDLY 0x40
2140#define LQONOHOLDLACK 0x02
2979#define LQONOCHKOVER 0x01 2141#define LQONOCHKOVER 0x01
2980 2142
2981#define NEXTSCB 0x5a 2143#define NEXTSCB 0x5a
@@ -2998,8 +2160,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2998#define CFG4ICMD 0x02 2160#define CFG4ICMD 0x02
2999#define CFG4TCMD 0x01 2161#define CFG4TCMD 0x01
3000 2162
3001#define CURRSCB 0x5c
3002
3003#define SEQIMODE 0x5c 2163#define SEQIMODE 0x5c
3004#define ENCTXTDONE 0x40 2164#define ENCTXTDONE 0x40
3005#define ENSAVEPTRS 0x20 2165#define ENSAVEPTRS 0x20
@@ -3009,6 +2169,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3009#define ENCFG4ICMD 0x02 2169#define ENCFG4ICMD 0x02
3010#define ENCFG4TCMD 0x01 2170#define ENCFG4TCMD 0x01
3011 2171
2172#define CURRSCB 0x5c
2173
3012#define MDFFSTAT 0x5d 2174#define MDFFSTAT 0x5d
3013#define SHCNTNEGATIVE 0x40 2175#define SHCNTNEGATIVE 0x40
3014#define SHCNTMINUS1 0x20 2176#define SHCNTMINUS1 0x20
@@ -3023,29 +2185,29 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3023 2185
3024#define DFFTAG 0x5e 2186#define DFFTAG 0x5e
3025 2187
3026#define LASTSCB 0x5e
3027
3028#define SCSITEST 0x5e 2188#define SCSITEST 0x5e
3029#define CNTRTEST 0x08 2189#define CNTRTEST 0x08
3030#define SEL_TXPLL_DEBUG 0x04 2190#define SEL_TXPLL_DEBUG 0x04
3031 2191
2192#define LASTSCB 0x5e
2193
3032#define IOPDNCTL 0x5f 2194#define IOPDNCTL 0x5f
3033#define DISABLE_OE 0x80 2195#define DISABLE_OE 0x80
3034#define PDN_IDIST 0x04 2196#define PDN_IDIST 0x04
3035#define PDN_DIFFSENSE 0x01 2197#define PDN_DIFFSENSE 0x01
3036 2198
2199#define DGRPCRCI 0x60
2200
3037#define SHADDR 0x60 2201#define SHADDR 0x60
3038 2202
3039#define NEGOADDR 0x60 2203#define NEGOADDR 0x60
3040 2204
3041#define DGRPCRCI 0x60
3042
3043#define NEGPERIOD 0x61 2205#define NEGPERIOD 0x61
3044 2206
3045#define PACKCRCI 0x62
3046
3047#define NEGOFFSET 0x62 2207#define NEGOFFSET 0x62
3048 2208
2209#define PACKCRCI 0x62
2210
3049#define NEGPPROPTS 0x63 2211#define NEGPPROPTS 0x63
3050#define PPROPT_PACE 0x08 2212#define PPROPT_PACE 0x08
3051#define PPROPT_QAS 0x04 2213#define PPROPT_QAS 0x04
@@ -3066,6 +2228,7 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3066#define ANNEXDAT 0x66 2228#define ANNEXDAT 0x66
3067 2229
3068#define SCSCHKN 0x66 2230#define SCSCHKN 0x66
2231#define BIDICHKDIS 0x80
3069#define STSELSKIDDIS 0x40 2232#define STSELSKIDDIS 0x40
3070#define CURRFIFODEF 0x20 2233#define CURRFIFODEF 0x20
3071#define WIDERESEN 0x10 2234#define WIDERESEN 0x10
@@ -3090,6 +2253,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3090 2253
3091#define SELOID 0x6b 2254#define SELOID 0x6b
3092 2255
2256#define FAIRNESS 0x6c
2257
3093#define PLL400CTL0 0x6c 2258#define PLL400CTL0 0x6c
3094#define PLL_VCOSEL 0x80 2259#define PLL_VCOSEL 0x80
3095#define PLL_PWDN 0x40 2260#define PLL_PWDN 0x40
@@ -3099,8 +2264,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3099#define PLL_DLPF 0x02 2264#define PLL_DLPF 0x02
3100#define PLL_ENFBM 0x01 2265#define PLL_ENFBM 0x01
3101 2266
3102#define FAIRNESS 0x6c
3103
3104#define PLL400CTL1 0x6d 2267#define PLL400CTL1 0x6d
3105#define PLL_CNTEN 0x80 2268#define PLL_CNTEN 0x80
3106#define PLL_CNTCLR 0x40 2269#define PLL_CNTCLR 0x40
@@ -3112,25 +2275,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3112 2275
3113#define HADDR 0x70 2276#define HADDR 0x70
3114 2277
2278#define HODMAADR 0x70
2279
3115#define PLLDELAY 0x70 2280#define PLLDELAY 0x70
3116#define SPLIT_DROP_REQ 0x80 2281#define SPLIT_DROP_REQ 0x80
3117 2282
3118#define HODMAADR 0x70 2283#define HCNT 0x78
3119 2284
3120#define HODMACNT 0x78 2285#define HODMACNT 0x78
3121 2286
3122#define HCNT 0x78
3123
3124#define HODMAEN 0x7a 2287#define HODMAEN 0x7a
3125 2288
3126#define SCBHADDR 0x7c
3127
3128#define SGHADDR 0x7c 2289#define SGHADDR 0x7c
3129 2290
3130#define SCBHCNT 0x84 2291#define SCBHADDR 0x7c
3131 2292
3132#define SGHCNT 0x84 2293#define SGHCNT 0x84
3133 2294
2295#define SCBHCNT 0x84
2296
3134#define DFF_THRSH 0x88 2297#define DFF_THRSH 0x88
3135#define WR_DFTHRSH 0x70 2298#define WR_DFTHRSH 0x70
3136#define RD_DFTHRSH 0x07 2299#define RD_DFTHRSH 0x07
@@ -3163,6 +2326,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3163 2326
3164#define CMCRXMSG0 0x90 2327#define CMCRXMSG0 0x90
3165 2328
2329#define OVLYRXMSG0 0x90
2330
2331#define DCHRXMSG0 0x90
2332
3166#define ROENABLE 0x90 2333#define ROENABLE 0x90
3167#define MSIROEN 0x20 2334#define MSIROEN 0x20
3168#define OVLYROEN 0x10 2335#define OVLYROEN 0x10
@@ -3171,11 +2338,11 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3171#define DCH1ROEN 0x02 2338#define DCH1ROEN 0x02
3172#define DCH0ROEN 0x01 2339#define DCH0ROEN 0x01
3173 2340
3174#define OVLYRXMSG0 0x90 2341#define OVLYRXMSG1 0x91
3175 2342
3176#define DCHRXMSG0 0x90 2343#define CMCRXMSG1 0x91
3177 2344
3178#define OVLYRXMSG1 0x91 2345#define DCHRXMSG1 0x91
3179 2346
3180#define NSENABLE 0x91 2347#define NSENABLE 0x91
3181#define MSINSEN 0x20 2348#define MSINSEN 0x20
@@ -3185,10 +2352,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3185#define DCH1NSEN 0x02 2352#define DCH1NSEN 0x02
3186#define DCH0NSEN 0x01 2353#define DCH0NSEN 0x01
3187 2354
3188#define CMCRXMSG1 0x91
3189
3190#define DCHRXMSG1 0x91
3191
3192#define DCHRXMSG2 0x92 2355#define DCHRXMSG2 0x92
3193 2356
3194#define CMCRXMSG2 0x92 2357#define CMCRXMSG2 0x92
@@ -3212,24 +2375,24 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3212#define TSCSERREN 0x02 2375#define TSCSERREN 0x02
3213#define CMPABCDIS 0x01 2376#define CMPABCDIS 0x01
3214 2377
2378#define CMCSEQBCNT 0x94
2379
3215#define OVLYSEQBCNT 0x94 2380#define OVLYSEQBCNT 0x94
3216 2381
3217#define DCHSEQBCNT 0x94 2382#define DCHSEQBCNT 0x94
3218 2383
3219#define CMCSEQBCNT 0x94
3220
3221#define CMCSPLTSTAT0 0x96
3222
3223#define DCHSPLTSTAT0 0x96 2384#define DCHSPLTSTAT0 0x96
3224 2385
3225#define OVLYSPLTSTAT0 0x96 2386#define OVLYSPLTSTAT0 0x96
3226 2387
3227#define CMCSPLTSTAT1 0x97 2388#define CMCSPLTSTAT0 0x96
3228 2389
3229#define OVLYSPLTSTAT1 0x97 2390#define OVLYSPLTSTAT1 0x97
3230 2391
3231#define DCHSPLTSTAT1 0x97 2392#define DCHSPLTSTAT1 0x97
3232 2393
2394#define CMCSPLTSTAT1 0x97
2395
3233#define SGRXMSG0 0x98 2396#define SGRXMSG0 0x98
3234#define CDNUM 0xf8 2397#define CDNUM 0xf8
3235#define CFNUM 0x07 2398#define CFNUM 0x07
@@ -3257,18 +2420,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3257#define TAG_NUM 0x1f 2420#define TAG_NUM 0x1f
3258#define RLXORD 0x10 2421#define RLXORD 0x10
3259 2422
3260#define SGSEQBCNT 0x9c
3261
3262#define SLVSPLTOUTATTR0 0x9c 2423#define SLVSPLTOUTATTR0 0x9c
3263#define LOWER_BCNT 0xff 2424#define LOWER_BCNT 0xff
3264 2425
2426#define SGSEQBCNT 0x9c
2427
3265#define SLVSPLTOUTATTR1 0x9d 2428#define SLVSPLTOUTATTR1 0x9d
3266#define CMPLT_DNUM 0xf8 2429#define CMPLT_DNUM 0xf8
3267#define CMPLT_FNUM 0x07 2430#define CMPLT_FNUM 0x07
3268 2431
3269#define SLVSPLTOUTATTR2 0x9e
3270#define CMPLT_BNUM 0xff
3271
3272#define SGSPLTSTAT0 0x9e 2432#define SGSPLTSTAT0 0x9e
3273#define STAETERM 0x80 2433#define STAETERM 0x80
3274#define SCBCERR 0x40 2434#define SCBCERR 0x40
@@ -3279,6 +2439,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3279#define RXSCEMSG 0x02 2439#define RXSCEMSG 0x02
3280#define RXSPLTRSP 0x01 2440#define RXSPLTRSP 0x01
3281 2441
2442#define SLVSPLTOUTATTR2 0x9e
2443#define CMPLT_BNUM 0xff
2444
3282#define SGSPLTSTAT1 0x9f 2445#define SGSPLTSTAT1 0x9f
3283#define RXDATABUCKET 0x01 2446#define RXDATABUCKET 0x01
3284 2447
@@ -3334,10 +2497,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3334 2497
3335#define CCSGADDR 0xac 2498#define CCSGADDR 0xac
3336 2499
3337#define CCSCBADR_BK 0xac
3338
3339#define CCSCBADDR 0xac 2500#define CCSCBADDR 0xac
3340 2501
2502#define CCSCBADR_BK 0xac
2503
3341#define CMC_RAMBIST 0xad 2504#define CMC_RAMBIST 0xad
3342#define SG_ELEMENT_SIZE 0x80 2505#define SG_ELEMENT_SIZE 0x80
3343#define SCBRAMBIST_FAIL 0x40 2506#define SCBRAMBIST_FAIL 0x40
@@ -3391,9 +2554,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3391#define SEEDAT 0xbc 2554#define SEEDAT 0xbc
3392 2555
3393#define SEECTL 0xbe 2556#define SEECTL 0xbe
2557#define SEEOP_EWDS 0x40
3394#define SEEOP_WALL 0x40 2558#define SEEOP_WALL 0x40
3395#define SEEOP_EWEN 0x40 2559#define SEEOP_EWEN 0x40
3396#define SEEOP_EWDS 0x40
3397#define SEEOPCODE 0x70 2560#define SEEOPCODE 0x70
3398#define SEERST 0x02 2561#define SEERST 0x02
3399#define SEESTART 0x01 2562#define SEESTART 0x01
@@ -3410,25 +2573,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3410 2573
3411#define SCBCNT 0xbf 2574#define SCBCNT 0xbf
3412 2575
3413#define DFWADDR 0xc0
3414
3415#define DSPFLTRCTL 0xc0 2576#define DSPFLTRCTL 0xc0
3416#define FLTRDISABLE 0x20 2577#define FLTRDISABLE 0x20
3417#define EDGESENSE 0x10 2578#define EDGESENSE 0x10
3418#define DSPFCNTSEL 0x0f 2579#define DSPFCNTSEL 0x0f
3419 2580
2581#define DFWADDR 0xc0
2582
3420#define DSPDATACTL 0xc1 2583#define DSPDATACTL 0xc1
3421#define BYPASSENAB 0x80 2584#define BYPASSENAB 0x80
3422#define DESQDIS 0x10 2585#define DESQDIS 0x10
3423#define RCVROFFSTDIS 0x04 2586#define RCVROFFSTDIS 0x04
3424#define XMITOFFSTDIS 0x02 2587#define XMITOFFSTDIS 0x02
3425 2588
3426#define DFRADDR 0xc2
3427
3428#define DSPREQCTL 0xc2 2589#define DSPREQCTL 0xc2
3429#define MANREQCTL 0xc0 2590#define MANREQCTL 0xc0
3430#define MANREQDLY 0x3f 2591#define MANREQDLY 0x3f
3431 2592
2593#define DFRADDR 0xc2
2594
3432#define DSPACKCTL 0xc3 2595#define DSPACKCTL 0xc3
3433#define MANACKCTL 0xc0 2596#define MANACKCTL 0xc0
3434#define MANACKDLY 0x3f 2597#define MANACKDLY 0x3f
@@ -3449,14 +2612,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3449 2612
3450#define WRTBIASCALC 0xc7 2613#define WRTBIASCALC 0xc7
3451 2614
3452#define RCVRBIASCALC 0xc8
3453
3454#define DFPTRS 0xc8 2615#define DFPTRS 0xc8
3455 2616
3456#define SKEWCALC 0xc9 2617#define RCVRBIASCALC 0xc8
3457 2618
3458#define DFBKPTR 0xc9 2619#define DFBKPTR 0xc9
3459 2620
2621#define SKEWCALC 0xc9
2622
3460#define DFDBCTL 0xcb 2623#define DFDBCTL 0xcb
3461#define DFF_CIO_WR_RDY 0x20 2624#define DFF_CIO_WR_RDY 0x20
3462#define DFF_CIO_RD_RDY 0x10 2625#define DFF_CIO_RD_RDY 0x10
@@ -3541,12 +2704,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3541 2704
3542#define ACCUM_SAVE 0xfa 2705#define ACCUM_SAVE 0xfa
3543 2706
3544#define WAITING_SCB_TAILS 0x100
3545
3546#define AHD_PCI_CONFIG_BASE 0x100 2707#define AHD_PCI_CONFIG_BASE 0x100
3547 2708
3548#define SRAM_BASE 0x100 2709#define SRAM_BASE 0x100
3549 2710
2711#define WAITING_SCB_TAILS 0x100
2712
3550#define WAITING_TID_HEAD 0x120 2713#define WAITING_TID_HEAD 0x120
3551 2714
3552#define WAITING_TID_TAIL 0x122 2715#define WAITING_TID_TAIL 0x122
@@ -3575,8 +2738,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3575#define PRELOADEN 0x80 2738#define PRELOADEN 0x80
3576#define WIDEODD 0x40 2739#define WIDEODD 0x40
3577#define SCSIEN 0x20 2740#define SCSIEN 0x20
3578#define SDMAEN 0x10
3579#define SDMAENACK 0x10 2741#define SDMAENACK 0x10
2742#define SDMAEN 0x10
3580#define HDMAEN 0x08 2743#define HDMAEN 0x08
3581#define HDMAENACK 0x08 2744#define HDMAENACK 0x08
3582#define DIRECTION 0x04 2745#define DIRECTION 0x04
@@ -3674,12 +2837,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3674 2837
3675#define MK_MESSAGE_SCSIID 0x162 2838#define MK_MESSAGE_SCSIID 0x162
3676 2839
3677#define SCB_BASE 0x180
3678
3679#define SCB_RESIDUAL_DATACNT 0x180 2840#define SCB_RESIDUAL_DATACNT 0x180
3680#define SCB_CDB_STORE 0x180 2841#define SCB_CDB_STORE 0x180
3681#define SCB_HOST_CDB_PTR 0x180 2842#define SCB_HOST_CDB_PTR 0x180
3682 2843
2844#define SCB_BASE 0x180
2845
3683#define SCB_RESIDUAL_SGPTR 0x184 2846#define SCB_RESIDUAL_SGPTR 0x184
3684#define SG_ADDR_MASK 0xf8 2847#define SG_ADDR_MASK 0xf8
3685#define SG_OVERRUN_RESID 0x02 2848#define SG_OVERRUN_RESID 0x02
@@ -3747,6 +2910,17 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3747#define SCB_DISCONNECTED_LISTS 0x1b8 2910#define SCB_DISCONNECTED_LISTS 0x1b8
3748 2911
3749 2912
2913#define CMD_GROUP_CODE_SHIFT 0x05
2914#define STIMESEL_MIN 0x18
2915#define STIMESEL_SHIFT 0x03
2916#define INVALID_ADDR 0x80
2917#define AHD_PRECOMP_MASK 0x07
2918#define TARGET_DATA_IN 0x01
2919#define CCSCBADDR_MAX 0x80
2920#define NUMDSPS 0x14
2921#define SEEOP_EWEN_ADDR 0xc0
2922#define AHD_ANNEXCOL_PER_DEV0 0x04
2923#define DST_MODE_SHIFT 0x04
3750#define AHD_TIMER_MAX_US 0x18ffe7 2924#define AHD_TIMER_MAX_US 0x18ffe7
3751#define AHD_TIMER_MAX_TICKS 0xffff 2925#define AHD_TIMER_MAX_TICKS 0xffff
3752#define AHD_SENSE_BUFSIZE 0x100 2926#define AHD_SENSE_BUFSIZE 0x100
@@ -3781,43 +2955,32 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3781#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 2955#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
3782#define NVRAM_SCB_OFFSET 0x2c 2956#define NVRAM_SCB_OFFSET 0x2c
3783#define STATUS_PKT_SENSE 0xff 2957#define STATUS_PKT_SENSE 0xff
3784#define CMD_GROUP_CODE_SHIFT 0x05
3785#define MAX_OFFSET_PACED_BUG 0x7f 2958#define MAX_OFFSET_PACED_BUG 0x7f
3786#define STIMESEL_BUG_ADJ 0x08 2959#define STIMESEL_BUG_ADJ 0x08
3787#define STIMESEL_MIN 0x18
3788#define STIMESEL_SHIFT 0x03
3789#define CCSGRAM_MAXSEGS 0x10 2960#define CCSGRAM_MAXSEGS 0x10
3790#define INVALID_ADDR 0x80
3791#define SEEOP_ERAL_ADDR 0x80 2961#define SEEOP_ERAL_ADDR 0x80
3792#define AHD_SLEWRATE_DEF_REVB 0x08 2962#define AHD_SLEWRATE_DEF_REVB 0x08
3793#define AHD_PRECOMP_CUTBACK_17 0x04 2963#define AHD_PRECOMP_CUTBACK_17 0x04
3794#define AHD_PRECOMP_MASK 0x07
3795#define SRC_MODE_SHIFT 0x00 2964#define SRC_MODE_SHIFT 0x00
3796#define PKT_OVERRUN_BUFSIZE 0x200 2965#define PKT_OVERRUN_BUFSIZE 0x200
3797#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 2966#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
3798#define TARGET_DATA_IN 0x01
3799#define HOST_MSG 0xff 2967#define HOST_MSG 0xff
3800#define MAX_OFFSET 0xfe 2968#define MAX_OFFSET 0xfe
3801#define BUS_16_BIT 0x01 2969#define BUS_16_BIT 0x01
3802#define CCSCBADDR_MAX 0x80
3803#define NUMDSPS 0x14
3804#define SEEOP_EWEN_ADDR 0xc0
3805#define AHD_ANNEXCOL_PER_DEV0 0x04
3806#define DST_MODE_SHIFT 0x04
3807 2970
3808 2971
3809/* Downloaded Constant Definitions */ 2972/* Downloaded Constant Definitions */
2973#define SG_SIZEOF 0x04
2974#define SG_PREFETCH_ALIGN_MASK 0x02
2975#define SG_PREFETCH_CNT_LIMIT 0x01
3810#define CACHELINE_MASK 0x07 2976#define CACHELINE_MASK 0x07
3811#define SCB_TRANSFER_SIZE 0x06 2977#define SCB_TRANSFER_SIZE 0x06
3812#define PKT_OVERRUN_BUFOFFSET 0x05 2978#define PKT_OVERRUN_BUFOFFSET 0x05
3813#define SG_SIZEOF 0x04
3814#define SG_PREFETCH_ADDR_MASK 0x03 2979#define SG_PREFETCH_ADDR_MASK 0x03
3815#define SG_PREFETCH_ALIGN_MASK 0x02
3816#define SG_PREFETCH_CNT_LIMIT 0x01
3817#define SG_PREFETCH_CNT 0x00 2980#define SG_PREFETCH_CNT 0x00
3818#define DOWNLOAD_CONST_COUNT 0x08 2981#define DOWNLOAD_CONST_COUNT 0x08
3819 2982
3820 2983
3821/* Exported Labels */ 2984/* Exported Labels */
3822#define LABEL_seq_isr 0x28f
3823#define LABEL_timer_isr 0x28b 2985#define LABEL_timer_isr 0x28b
2986#define LABEL_seq_isr 0x28f
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
index db38a61a8cb4..c4c8a96bf5a3 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
@@ -8,7 +8,7 @@
8 8
9#include "aic79xx_osm.h" 9#include "aic79xx_osm.h"
10 10
11static ahd_reg_parse_entry_t MODE_PTR_parse_table[] = { 11static const ahd_reg_parse_entry_t MODE_PTR_parse_table[] = {
12 { "SRC_MODE", 0x07, 0x07 }, 12 { "SRC_MODE", 0x07, 0x07 },
13 { "DST_MODE", 0x70, 0x70 } 13 { "DST_MODE", 0x70, 0x70 }
14}; 14};
@@ -20,7 +20,7 @@ ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
20 0x00, regvalue, cur_col, wrap)); 20 0x00, regvalue, cur_col, wrap));
21} 21}
22 22
23static ahd_reg_parse_entry_t INTSTAT_parse_table[] = { 23static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
24 { "SPLTINT", 0x01, 0x01 }, 24 { "SPLTINT", 0x01, 0x01 },
25 { "CMDCMPLT", 0x02, 0x02 }, 25 { "CMDCMPLT", 0x02, 0x02 },
26 { "SEQINT", 0x04, 0x04 }, 26 { "SEQINT", 0x04, 0x04 },
@@ -39,7 +39,7 @@ ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
39 0x01, regvalue, cur_col, wrap)); 39 0x01, regvalue, cur_col, wrap));
40} 40}
41 41
42static ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = { 42static const ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = {
43 { "NO_SEQINT", 0x00, 0xff }, 43 { "NO_SEQINT", 0x00, 0xff },
44 { "BAD_PHASE", 0x01, 0xff }, 44 { "BAD_PHASE", 0x01, 0xff },
45 { "SEND_REJECT", 0x02, 0xff }, 45 { "SEND_REJECT", 0x02, 0xff },
@@ -76,7 +76,7 @@ ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap)
76 0x02, regvalue, cur_col, wrap)); 76 0x02, regvalue, cur_col, wrap));
77} 77}
78 78
79static ahd_reg_parse_entry_t CLRINT_parse_table[] = { 79static const ahd_reg_parse_entry_t CLRINT_parse_table[] = {
80 { "CLRSPLTINT", 0x01, 0x01 }, 80 { "CLRSPLTINT", 0x01, 0x01 },
81 { "CLRCMDINT", 0x02, 0x02 }, 81 { "CLRCMDINT", 0x02, 0x02 },
82 { "CLRSEQINT", 0x04, 0x04 }, 82 { "CLRSEQINT", 0x04, 0x04 },
@@ -94,7 +94,7 @@ ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
94 0x03, regvalue, cur_col, wrap)); 94 0x03, regvalue, cur_col, wrap));
95} 95}
96 96
97static ahd_reg_parse_entry_t ERROR_parse_table[] = { 97static const ahd_reg_parse_entry_t ERROR_parse_table[] = {
98 { "DSCTMOUT", 0x02, 0x02 }, 98 { "DSCTMOUT", 0x02, 0x02 },
99 { "ILLOPCODE", 0x04, 0x04 }, 99 { "ILLOPCODE", 0x04, 0x04 },
100 { "SQPARERR", 0x08, 0x08 }, 100 { "SQPARERR", 0x08, 0x08 },
@@ -111,24 +111,7 @@ ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
111 0x04, regvalue, cur_col, wrap)); 111 0x04, regvalue, cur_col, wrap));
112} 112}
113 113
114static ahd_reg_parse_entry_t CLRERR_parse_table[] = { 114static const ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
115 { "CLRDSCTMOUT", 0x02, 0x02 },
116 { "CLRILLOPCODE", 0x04, 0x04 },
117 { "CLRSQPARERR", 0x08, 0x08 },
118 { "CLRDPARERR", 0x10, 0x10 },
119 { "CLRMPARERR", 0x20, 0x20 },
120 { "CLRCIOACCESFAIL", 0x40, 0x40 },
121 { "CLRCIOPARERR", 0x80, 0x80 }
122};
123
124int
125ahd_clrerr_print(u_int regvalue, u_int *cur_col, u_int wrap)
126{
127 return (ahd_print_register(CLRERR_parse_table, 7, "CLRERR",
128 0x04, regvalue, cur_col, wrap));
129}
130
131static ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
132 { "CHIPRST", 0x01, 0x01 }, 115 { "CHIPRST", 0x01, 0x01 },
133 { "CHIPRSTACK", 0x01, 0x01 }, 116 { "CHIPRSTACK", 0x01, 0x01 },
134 { "INTEN", 0x02, 0x02 }, 117 { "INTEN", 0x02, 0x02 },
@@ -160,7 +143,7 @@ ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
160 0x08, regvalue, cur_col, wrap)); 143 0x08, regvalue, cur_col, wrap));
161} 144}
162 145
163static ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 146static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
164 { "ENINT_COALESCE", 0x40, 0x40 }, 147 { "ENINT_COALESCE", 0x40, 0x40 },
165 { "HOST_TQINPOS", 0x80, 0x80 } 148 { "HOST_TQINPOS", 0x80, 0x80 }
166}; 149};
@@ -172,7 +155,7 @@ ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
172 0x0b, regvalue, cur_col, wrap)); 155 0x0b, regvalue, cur_col, wrap));
173} 156}
174 157
175static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = { 158static const ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
176 { "SEQ_SPLTINT", 0x01, 0x01 }, 159 { "SEQ_SPLTINT", 0x01, 0x01 },
177 { "SEQ_PCIINT", 0x02, 0x02 }, 160 { "SEQ_PCIINT", 0x02, 0x02 },
178 { "SEQ_SCSIINT", 0x04, 0x04 }, 161 { "SEQ_SCSIINT", 0x04, 0x04 },
@@ -187,7 +170,7 @@ ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
187 0x0c, regvalue, cur_col, wrap)); 170 0x0c, regvalue, cur_col, wrap));
188} 171}
189 172
190static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = { 173static const ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
191 { "CLRSEQ_SPLTINT", 0x01, 0x01 }, 174 { "CLRSEQ_SPLTINT", 0x01, 0x01 },
192 { "CLRSEQ_PCIINT", 0x02, 0x02 }, 175 { "CLRSEQ_PCIINT", 0x02, 0x02 },
193 { "CLRSEQ_SCSIINT", 0x04, 0x04 }, 176 { "CLRSEQ_SCSIINT", 0x04, 0x04 },
@@ -230,7 +213,7 @@ ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
230 0x14, regvalue, cur_col, wrap)); 213 0x14, regvalue, cur_col, wrap));
231} 214}
232 215
233static ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 216static const ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
234 { "SCB_QSIZE_4", 0x00, 0x0f }, 217 { "SCB_QSIZE_4", 0x00, 0x0f },
235 { "SCB_QSIZE_8", 0x01, 0x0f }, 218 { "SCB_QSIZE_8", 0x01, 0x0f },
236 { "SCB_QSIZE_16", 0x02, 0x0f }, 219 { "SCB_QSIZE_16", 0x02, 0x0f },
@@ -258,7 +241,7 @@ ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
258 0x16, regvalue, cur_col, wrap)); 241 0x16, regvalue, cur_col, wrap));
259} 242}
260 243
261static ahd_reg_parse_entry_t INTCTL_parse_table[] = { 244static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
262 { "SPLTINTEN", 0x01, 0x01 }, 245 { "SPLTINTEN", 0x01, 0x01 },
263 { "SEQINTEN", 0x02, 0x02 }, 246 { "SEQINTEN", 0x02, 0x02 },
264 { "SCSIINTEN", 0x04, 0x04 }, 247 { "SCSIINTEN", 0x04, 0x04 },
@@ -276,7 +259,7 @@ ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
276 0x18, regvalue, cur_col, wrap)); 259 0x18, regvalue, cur_col, wrap));
277} 260}
278 261
279static ahd_reg_parse_entry_t DFCNTRL_parse_table[] = { 262static const ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
280 { "DIRECTIONEN", 0x01, 0x01 }, 263 { "DIRECTIONEN", 0x01, 0x01 },
281 { "FIFOFLUSH", 0x02, 0x02 }, 264 { "FIFOFLUSH", 0x02, 0x02 },
282 { "FIFOFLUSHACK", 0x02, 0x02 }, 265 { "FIFOFLUSHACK", 0x02, 0x02 },
@@ -297,7 +280,7 @@ ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
297 0x19, regvalue, cur_col, wrap)); 280 0x19, regvalue, cur_col, wrap));
298} 281}
299 282
300static ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = { 283static const ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
301 { "CIOPARCKEN", 0x01, 0x01 }, 284 { "CIOPARCKEN", 0x01, 0x01 },
302 { "DISABLE_TWATE", 0x02, 0x02 }, 285 { "DISABLE_TWATE", 0x02, 0x02 },
303 { "EXTREQLCK", 0x10, 0x10 }, 286 { "EXTREQLCK", 0x10, 0x10 },
@@ -313,7 +296,7 @@ ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
313 0x19, regvalue, cur_col, wrap)); 296 0x19, regvalue, cur_col, wrap));
314} 297}
315 298
316static ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { 299static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
317 { "FIFOEMP", 0x01, 0x01 }, 300 { "FIFOEMP", 0x01, 0x01 },
318 { "FIFOFULL", 0x02, 0x02 }, 301 { "FIFOFULL", 0x02, 0x02 },
319 { "DFTHRESH", 0x04, 0x04 }, 302 { "DFTHRESH", 0x04, 0x04 },
@@ -330,7 +313,7 @@ ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
330 0x1a, regvalue, cur_col, wrap)); 313 0x1a, regvalue, cur_col, wrap));
331} 314}
332 315
333static ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 316static const ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
334 { "LAST_SEG_DONE", 0x01, 0x01 }, 317 { "LAST_SEG_DONE", 0x01, 0x01 },
335 { "LAST_SEG", 0x02, 0x02 }, 318 { "LAST_SEG", 0x02, 0x02 },
336 { "ODD_SEG", 0x04, 0x04 }, 319 { "ODD_SEG", 0x04, 0x04 },
@@ -344,20 +327,7 @@ ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
344 0x1b, regvalue, cur_col, wrap)); 327 0x1b, regvalue, cur_col, wrap));
345} 328}
346 329
347static ahd_reg_parse_entry_t ARBCTL_parse_table[] = { 330static const ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
348 { "USE_TIME", 0x07, 0x07 },
349 { "RETRY_SWEN", 0x08, 0x08 },
350 { "RESET_HARB", 0x80, 0x80 }
351};
352
353int
354ahd_arbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
355{
356 return (ahd_print_register(ARBCTL_parse_table, 3, "ARBCTL",
357 0x1b, regvalue, cur_col, wrap));
358}
359
360static ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
361 { "LAST_SEG", 0x02, 0x02 }, 331 { "LAST_SEG", 0x02, 0x02 },
362 { "ODD_SEG", 0x04, 0x04 }, 332 { "ODD_SEG", 0x04, 0x04 },
363 { "SG_ADDR_MASK", 0xf8, 0xf8 } 333 { "SG_ADDR_MASK", 0xf8, 0xf8 }
@@ -378,20 +348,6 @@ ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap)
378} 348}
379 349
380int 350int
381ahd_typeptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
382{
383 return (ahd_print_register(NULL, 0, "TYPEPTR",
384 0x20, regvalue, cur_col, wrap));
385}
386
387int
388ahd_tagptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
389{
390 return (ahd_print_register(NULL, 0, "TAGPTR",
391 0x21, regvalue, cur_col, wrap));
392}
393
394int
395ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 351ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
396{ 352{
397 return (ahd_print_register(NULL, 0, "LUNPTR", 353 return (ahd_print_register(NULL, 0, "LUNPTR",
@@ -399,20 +355,6 @@ ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
399} 355}
400 356
401int 357int
402ahd_datalenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
403{
404 return (ahd_print_register(NULL, 0, "DATALENPTR",
405 0x23, regvalue, cur_col, wrap));
406}
407
408int
409ahd_statlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
410{
411 return (ahd_print_register(NULL, 0, "STATLENPTR",
412 0x24, regvalue, cur_col, wrap));
413}
414
415int
416ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 358ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
417{ 359{
418 return (ahd_print_register(NULL, 0, "CMDLENPTR", 360 return (ahd_print_register(NULL, 0, "CMDLENPTR",
@@ -448,13 +390,6 @@ ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
448} 390}
449 391
450int 392int
451ahd_idptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
452{
453 return (ahd_print_register(NULL, 0, "IDPTR",
454 0x2a, regvalue, cur_col, wrap));
455}
456
457int
458ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 393ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
459{ 394{
460 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR", 395 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR",
@@ -468,28 +403,7 @@ ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
468 0x2c, regvalue, cur_col, wrap)); 403 0x2c, regvalue, cur_col, wrap));
469} 404}
470 405
471int 406static const ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
472ahd_maxcmdbytes_print(u_int regvalue, u_int *cur_col, u_int wrap)
473{
474 return (ahd_print_register(NULL, 0, "MAXCMDBYTES",
475 0x2d, regvalue, cur_col, wrap));
476}
477
478int
479ahd_maxcmd2rcv_print(u_int regvalue, u_int *cur_col, u_int wrap)
480{
481 return (ahd_print_register(NULL, 0, "MAXCMD2RCV",
482 0x2e, regvalue, cur_col, wrap));
483}
484
485int
486ahd_shortthresh_print(u_int regvalue, u_int *cur_col, u_int wrap)
487{
488 return (ahd_print_register(NULL, 0, "SHORTTHRESH",
489 0x2f, regvalue, cur_col, wrap));
490}
491
492static ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
493 { "ILUNLEN", 0x0f, 0x0f }, 407 { "ILUNLEN", 0x0f, 0x0f },
494 { "TLUNLEN", 0xf0, 0xf0 } 408 { "TLUNLEN", 0xf0, 0xf0 }
495}; 409};
@@ -522,49 +436,7 @@ ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
522 0x33, regvalue, cur_col, wrap)); 436 0x33, regvalue, cur_col, wrap));
523} 437}
524 438
525int 439static const ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
526ahd_lqrsvd01_print(u_int regvalue, u_int *cur_col, u_int wrap)
527{
528 return (ahd_print_register(NULL, 0, "LQRSVD01",
529 0x34, regvalue, cur_col, wrap));
530}
531
532int
533ahd_lqrsvd16_print(u_int regvalue, u_int *cur_col, u_int wrap)
534{
535 return (ahd_print_register(NULL, 0, "LQRSVD16",
536 0x35, regvalue, cur_col, wrap));
537}
538
539int
540ahd_lqrsvd17_print(u_int regvalue, u_int *cur_col, u_int wrap)
541{
542 return (ahd_print_register(NULL, 0, "LQRSVD17",
543 0x36, regvalue, cur_col, wrap));
544}
545
546int
547ahd_cmdrsvd0_print(u_int regvalue, u_int *cur_col, u_int wrap)
548{
549 return (ahd_print_register(NULL, 0, "CMDRSVD0",
550 0x37, regvalue, cur_col, wrap));
551}
552
553static ahd_reg_parse_entry_t LQCTL0_parse_table[] = {
554 { "LQ0INITGCLT", 0x03, 0x03 },
555 { "LQ0TARGCLT", 0x0c, 0x0c },
556 { "LQIINITGCLT", 0x30, 0x30 },
557 { "LQITARGCLT", 0xc0, 0xc0 }
558};
559
560int
561ahd_lqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
562{
563 return (ahd_print_register(LQCTL0_parse_table, 4, "LQCTL0",
564 0x38, regvalue, cur_col, wrap));
565}
566
567static ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
568 { "ABORTPENDING", 0x01, 0x01 }, 440 { "ABORTPENDING", 0x01, 0x01 },
569 { "SINGLECMD", 0x02, 0x02 }, 441 { "SINGLECMD", 0x02, 0x02 },
570 { "PCI2PCI", 0x04, 0x04 } 442 { "PCI2PCI", 0x04, 0x04 }
@@ -577,23 +449,7 @@ ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
577 0x38, regvalue, cur_col, wrap)); 449 0x38, regvalue, cur_col, wrap));
578} 450}
579 451
580static ahd_reg_parse_entry_t SCSBIST0_parse_table[] = { 452static const ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
581 { "OSBISTRUN", 0x01, 0x01 },
582 { "OSBISTDONE", 0x02, 0x02 },
583 { "OSBISTERR", 0x04, 0x04 },
584 { "GSBISTRUN", 0x10, 0x10 },
585 { "GSBISTDONE", 0x20, 0x20 },
586 { "GSBISTERR", 0x40, 0x40 }
587};
588
589int
590ahd_scsbist0_print(u_int regvalue, u_int *cur_col, u_int wrap)
591{
592 return (ahd_print_register(SCSBIST0_parse_table, 6, "SCSBIST0",
593 0x39, regvalue, cur_col, wrap));
594}
595
596static ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
597 { "LQOPAUSE", 0x01, 0x01 }, 453 { "LQOPAUSE", 0x01, 0x01 },
598 { "LQOTOIDLE", 0x02, 0x02 }, 454 { "LQOTOIDLE", 0x02, 0x02 },
599 { "LQOCONTINUE", 0x04, 0x04 }, 455 { "LQOCONTINUE", 0x04, 0x04 },
@@ -611,20 +467,7 @@ ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
611 0x39, regvalue, cur_col, wrap)); 467 0x39, regvalue, cur_col, wrap));
612} 468}
613 469
614static ahd_reg_parse_entry_t SCSBIST1_parse_table[] = { 470static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
615 { "NTBISTRUN", 0x01, 0x01 },
616 { "NTBISTDONE", 0x02, 0x02 },
617 { "NTBISTERR", 0x04, 0x04 }
618};
619
620int
621ahd_scsbist1_print(u_int regvalue, u_int *cur_col, u_int wrap)
622{
623 return (ahd_print_register(SCSBIST1_parse_table, 3, "SCSBIST1",
624 0x3a, regvalue, cur_col, wrap));
625}
626
627static ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
628 { "SCSIRSTO", 0x01, 0x01 }, 471 { "SCSIRSTO", 0x01, 0x01 },
629 { "FORCEBUSFREE", 0x10, 0x10 }, 472 { "FORCEBUSFREE", 0x10, 0x10 },
630 { "ENARBO", 0x20, 0x20 }, 473 { "ENARBO", 0x20, 0x20 },
@@ -639,7 +482,7 @@ ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
639 0x3a, regvalue, cur_col, wrap)); 482 0x3a, regvalue, cur_col, wrap));
640} 483}
641 484
642static ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = { 485static const ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
643 { "ALTSTIM", 0x01, 0x01 }, 486 { "ALTSTIM", 0x01, 0x01 },
644 { "ENAUTOATNP", 0x02, 0x02 }, 487 { "ENAUTOATNP", 0x02, 0x02 },
645 { "MANUALP", 0x0c, 0x0c }, 488 { "MANUALP", 0x0c, 0x0c },
@@ -655,7 +498,7 @@ ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
655 0x3b, regvalue, cur_col, wrap)); 498 0x3b, regvalue, cur_col, wrap));
656} 499}
657 500
658static ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = { 501static const ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = {
659 { "SPIOEN", 0x08, 0x08 }, 502 { "SPIOEN", 0x08, 0x08 },
660 { "BIOSCANCELEN", 0x10, 0x10 }, 503 { "BIOSCANCELEN", 0x10, 0x10 },
661 { "DFPEXP", 0x40, 0x40 }, 504 { "DFPEXP", 0x40, 0x40 },
@@ -669,21 +512,7 @@ ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
669 0x3c, regvalue, cur_col, wrap)); 512 0x3c, regvalue, cur_col, wrap));
670} 513}
671 514
672int 515static const ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
673ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
674{
675 return (ahd_print_register(NULL, 0, "DLCOUNT",
676 0x3c, regvalue, cur_col, wrap));
677}
678
679int
680ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
681{
682 return (ahd_print_register(NULL, 0, "BUSINITID",
683 0x3c, regvalue, cur_col, wrap));
684}
685
686static ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
687 { "STPWEN", 0x01, 0x01 }, 516 { "STPWEN", 0x01, 0x01 },
688 { "ACTNEGEN", 0x02, 0x02 }, 517 { "ACTNEGEN", 0x02, 0x02 },
689 { "ENSTIMER", 0x04, 0x04 }, 518 { "ENSTIMER", 0x04, 0x04 },
@@ -700,27 +529,7 @@ ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
700 0x3d, regvalue, cur_col, wrap)); 529 0x3d, regvalue, cur_col, wrap));
701} 530}
702 531
703int 532static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
704ahd_bustargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
705{
706 return (ahd_print_register(NULL, 0, "BUSTARGID",
707 0x3e, regvalue, cur_col, wrap));
708}
709
710static ahd_reg_parse_entry_t SXFRCTL2_parse_table[] = {
711 { "ASU", 0x07, 0x07 },
712 { "CMDDMAEN", 0x08, 0x08 },
713 { "AUTORSTDIS", 0x10, 0x10 }
714};
715
716int
717ahd_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
718{
719 return (ahd_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
720 0x3e, regvalue, cur_col, wrap));
721}
722
723static ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
724 { "CURRFIFO_0", 0x00, 0x03 }, 533 { "CURRFIFO_0", 0x00, 0x03 },
725 { "CURRFIFO_1", 0x01, 0x03 }, 534 { "CURRFIFO_1", 0x01, 0x03 },
726 { "CURRFIFO_NONE", 0x03, 0x03 }, 535 { "CURRFIFO_NONE", 0x03, 0x03 },
@@ -736,7 +545,14 @@ ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
736 0x3f, regvalue, cur_col, wrap)); 545 0x3f, regvalue, cur_col, wrap));
737} 546}
738 547
739static ahd_reg_parse_entry_t SCSISIGO_parse_table[] = { 548int
549ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
550{
551 return (ahd_print_register(NULL, 0, "MULTARGID",
552 0x40, regvalue, cur_col, wrap));
553}
554
555static const ahd_reg_parse_entry_t SCSISIGO_parse_table[] = {
740 { "P_DATAOUT", 0x00, 0xe0 }, 556 { "P_DATAOUT", 0x00, 0xe0 },
741 { "P_DATAOUT_DT", 0x20, 0xe0 }, 557 { "P_DATAOUT_DT", 0x20, 0xe0 },
742 { "P_DATAIN", 0x40, 0xe0 }, 558 { "P_DATAIN", 0x40, 0xe0 },
@@ -763,14 +579,7 @@ ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
763 0x40, regvalue, cur_col, wrap)); 579 0x40, regvalue, cur_col, wrap));
764} 580}
765 581
766int 582static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
767ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
768{
769 return (ahd_print_register(NULL, 0, "MULTARGID",
770 0x40, regvalue, cur_col, wrap));
771}
772
773static ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
774 { "P_DATAOUT", 0x00, 0xe0 }, 583 { "P_DATAOUT", 0x00, 0xe0 },
775 { "P_DATAOUT_DT", 0x20, 0xe0 }, 584 { "P_DATAOUT_DT", 0x20, 0xe0 },
776 { "P_DATAIN", 0x40, 0xe0 }, 585 { "P_DATAIN", 0x40, 0xe0 },
@@ -797,7 +606,7 @@ ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
797 0x41, regvalue, cur_col, wrap)); 606 0x41, regvalue, cur_col, wrap));
798} 607}
799 608
800static ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = { 609static const ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
801 { "DATA_OUT_PHASE", 0x01, 0x03 }, 610 { "DATA_OUT_PHASE", 0x01, 0x03 },
802 { "DATA_IN_PHASE", 0x02, 0x03 }, 611 { "DATA_IN_PHASE", 0x02, 0x03 },
803 { "DATA_PHASE_MASK", 0x03, 0x03 }, 612 { "DATA_PHASE_MASK", 0x03, 0x03 },
@@ -815,13 +624,6 @@ ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
815} 624}
816 625
817int 626int
818ahd_scsidat0_img_print(u_int regvalue, u_int *cur_col, u_int wrap)
819{
820 return (ahd_print_register(NULL, 0, "SCSIDAT0_IMG",
821 0x43, regvalue, cur_col, wrap));
822}
823
824int
825ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap) 627ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap)
826{ 628{
827 return (ahd_print_register(NULL, 0, "SCSIDAT", 629 return (ahd_print_register(NULL, 0, "SCSIDAT",
@@ -835,7 +637,7 @@ ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
835 0x46, regvalue, cur_col, wrap)); 637 0x46, regvalue, cur_col, wrap));
836} 638}
837 639
838static ahd_reg_parse_entry_t TARGIDIN_parse_table[] = { 640static const ahd_reg_parse_entry_t TARGIDIN_parse_table[] = {
839 { "TARGID", 0x0f, 0x0f }, 641 { "TARGID", 0x0f, 0x0f },
840 { "CLKOUT", 0x80, 0x80 } 642 { "CLKOUT", 0x80, 0x80 }
841}; 643};
@@ -847,7 +649,7 @@ ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap)
847 0x48, regvalue, cur_col, wrap)); 649 0x48, regvalue, cur_col, wrap));
848} 650}
849 651
850static ahd_reg_parse_entry_t SELID_parse_table[] = { 652static const ahd_reg_parse_entry_t SELID_parse_table[] = {
851 { "ONEBIT", 0x08, 0x08 }, 653 { "ONEBIT", 0x08, 0x08 },
852 { "SELID_MASK", 0xf0, 0xf0 } 654 { "SELID_MASK", 0xf0, 0xf0 }
853}; 655};
@@ -859,7 +661,7 @@ ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
859 0x49, regvalue, cur_col, wrap)); 661 0x49, regvalue, cur_col, wrap));
860} 662}
861 663
862static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = { 664static const ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
863 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 665 { "AUTO_MSGOUT_DE", 0x02, 0x02 },
864 { "ENDGFORMCHK", 0x04, 0x04 }, 666 { "ENDGFORMCHK", 0x04, 0x04 },
865 { "BUSFREEREV", 0x10, 0x10 }, 667 { "BUSFREEREV", 0x10, 0x10 },
@@ -876,7 +678,7 @@ ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
876 0x4a, regvalue, cur_col, wrap)); 678 0x4a, regvalue, cur_col, wrap));
877} 679}
878 680
879static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = { 681static const ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
880 { "SELWIDE", 0x02, 0x02 }, 682 { "SELWIDE", 0x02, 0x02 },
881 { "ENAB20", 0x04, 0x04 }, 683 { "ENAB20", 0x04, 0x04 },
882 { "ENAB40", 0x08, 0x08 }, 684 { "ENAB40", 0x08, 0x08 },
@@ -891,24 +693,7 @@ ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
891 0x4a, regvalue, cur_col, wrap)); 693 0x4a, regvalue, cur_col, wrap));
892} 694}
893 695
894static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = { 696static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
895 { "CLRARBDO", 0x01, 0x01 },
896 { "CLRSPIORDY", 0x02, 0x02 },
897 { "CLROVERRUN", 0x04, 0x04 },
898 { "CLRIOERR", 0x08, 0x08 },
899 { "CLRSELINGO", 0x10, 0x10 },
900 { "CLRSELDI", 0x20, 0x20 },
901 { "CLRSELDO", 0x40, 0x40 }
902};
903
904int
905ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
906{
907 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
908 0x4b, regvalue, cur_col, wrap));
909}
910
911static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
912 { "ARBDO", 0x01, 0x01 }, 697 { "ARBDO", 0x01, 0x01 },
913 { "SPIORDY", 0x02, 0x02 }, 698 { "SPIORDY", 0x02, 0x02 },
914 { "OVERRUN", 0x04, 0x04 }, 699 { "OVERRUN", 0x04, 0x04 },
@@ -926,7 +711,7 @@ ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
926 0x4b, regvalue, cur_col, wrap)); 711 0x4b, regvalue, cur_col, wrap));
927} 712}
928 713
929static ahd_reg_parse_entry_t SIMODE0_parse_table[] = { 714static const ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
930 { "ENARBDO", 0x01, 0x01 }, 715 { "ENARBDO", 0x01, 0x01 },
931 { "ENSPIORDY", 0x02, 0x02 }, 716 { "ENSPIORDY", 0x02, 0x02 },
932 { "ENOVERRUN", 0x04, 0x04 }, 717 { "ENOVERRUN", 0x04, 0x04 },
@@ -943,24 +728,24 @@ ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
943 0x4b, regvalue, cur_col, wrap)); 728 0x4b, regvalue, cur_col, wrap));
944} 729}
945 730
946static ahd_reg_parse_entry_t CLRSINT1_parse_table[] = { 731static const ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
947 { "CLRREQINIT", 0x01, 0x01 }, 732 { "CLRARBDO", 0x01, 0x01 },
948 { "CLRSTRB2FAST", 0x02, 0x02 }, 733 { "CLRSPIORDY", 0x02, 0x02 },
949 { "CLRSCSIPERR", 0x04, 0x04 }, 734 { "CLROVERRUN", 0x04, 0x04 },
950 { "CLRBUSFREE", 0x08, 0x08 }, 735 { "CLRIOERR", 0x08, 0x08 },
951 { "CLRSCSIRSTI", 0x20, 0x20 }, 736 { "CLRSELINGO", 0x10, 0x10 },
952 { "CLRATNO", 0x40, 0x40 }, 737 { "CLRSELDI", 0x20, 0x20 },
953 { "CLRSELTIMEO", 0x80, 0x80 } 738 { "CLRSELDO", 0x40, 0x40 }
954}; 739};
955 740
956int 741int
957ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 742ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
958{ 743{
959 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", 744 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
960 0x4c, regvalue, cur_col, wrap)); 745 0x4b, regvalue, cur_col, wrap));
961} 746}
962 747
963static ahd_reg_parse_entry_t SSTAT1_parse_table[] = { 748static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
964 { "REQINIT", 0x01, 0x01 }, 749 { "REQINIT", 0x01, 0x01 },
965 { "STRB2FAST", 0x02, 0x02 }, 750 { "STRB2FAST", 0x02, 0x02 },
966 { "SCSIPERR", 0x04, 0x04 }, 751 { "SCSIPERR", 0x04, 0x04 },
@@ -978,7 +763,24 @@ ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
978 0x4c, regvalue, cur_col, wrap)); 763 0x4c, regvalue, cur_col, wrap));
979} 764}
980 765
981static ahd_reg_parse_entry_t SSTAT2_parse_table[] = { 766static const ahd_reg_parse_entry_t CLRSINT1_parse_table[] = {
767 { "CLRREQINIT", 0x01, 0x01 },
768 { "CLRSTRB2FAST", 0x02, 0x02 },
769 { "CLRSCSIPERR", 0x04, 0x04 },
770 { "CLRBUSFREE", 0x08, 0x08 },
771 { "CLRSCSIRSTI", 0x20, 0x20 },
772 { "CLRATNO", 0x40, 0x40 },
773 { "CLRSELTIMEO", 0x80, 0x80 }
774};
775
776int
777ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
778{
779 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
780 0x4c, regvalue, cur_col, wrap));
781}
782
783static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
982 { "BUSFREE_LQO", 0x40, 0xc0 }, 784 { "BUSFREE_LQO", 0x40, 0xc0 },
983 { "BUSFREE_DFF0", 0x80, 0xc0 }, 785 { "BUSFREE_DFF0", 0x80, 0xc0 },
984 { "BUSFREE_DFF1", 0xc0, 0xc0 }, 786 { "BUSFREE_DFF1", 0xc0, 0xc0 },
@@ -998,20 +800,7 @@ ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
998 0x4d, regvalue, cur_col, wrap)); 800 0x4d, regvalue, cur_col, wrap));
999} 801}
1000 802
1001static ahd_reg_parse_entry_t SIMODE2_parse_table[] = { 803static const ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
1002 { "ENDMADONE", 0x01, 0x01 },
1003 { "ENSDONE", 0x02, 0x02 },
1004 { "ENWIDE_RES", 0x04, 0x04 }
1005};
1006
1007int
1008ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1009{
1010 return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
1011 0x4d, regvalue, cur_col, wrap));
1012}
1013
1014static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
1015 { "CLRDMADONE", 0x01, 0x01 }, 804 { "CLRDMADONE", 0x01, 0x01 },
1016 { "CLRSDONE", 0x02, 0x02 }, 805 { "CLRSDONE", 0x02, 0x02 },
1017 { "CLRWIDE_RES", 0x04, 0x04 }, 806 { "CLRWIDE_RES", 0x04, 0x04 },
@@ -1025,7 +814,7 @@ ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1025 0x4d, regvalue, cur_col, wrap)); 814 0x4d, regvalue, cur_col, wrap));
1026} 815}
1027 816
1028static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { 817static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
1029 { "DTERR", 0x01, 0x01 }, 818 { "DTERR", 0x01, 0x01 },
1030 { "DGFORMERR", 0x02, 0x02 }, 819 { "DGFORMERR", 0x02, 0x02 },
1031 { "CRCERR", 0x04, 0x04 }, 820 { "CRCERR", 0x04, 0x04 },
@@ -1064,7 +853,7 @@ ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap)
1064 0x4f, regvalue, cur_col, wrap)); 853 0x4f, regvalue, cur_col, wrap));
1065} 854}
1066 855
1067static ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { 856static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
1068 { "LQIATNCMD", 0x01, 0x01 }, 857 { "LQIATNCMD", 0x01, 0x01 },
1069 { "LQIATNLQ", 0x02, 0x02 }, 858 { "LQIATNLQ", 0x02, 0x02 },
1070 { "LQIBADLQT", 0x04, 0x04 }, 859 { "LQIBADLQT", 0x04, 0x04 },
@@ -1080,23 +869,7 @@ ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1080 0x50, regvalue, cur_col, wrap)); 869 0x50, regvalue, cur_col, wrap));
1081} 870}
1082 871
1083static ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = { 872static const ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
1084 { "CLRLQIATNCMD", 0x01, 0x01 },
1085 { "CLRLQIATNLQ", 0x02, 0x02 },
1086 { "CLRLQIBADLQT", 0x04, 0x04 },
1087 { "CLRLQICRCT2", 0x08, 0x08 },
1088 { "CLRLQICRCT1", 0x10, 0x10 },
1089 { "CLRLQIATNQAS", 0x20, 0x20 }
1090};
1091
1092int
1093ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1094{
1095 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
1096 0x50, regvalue, cur_col, wrap));
1097}
1098
1099static ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
1100 { "ENLQIATNCMD", 0x01, 0x01 }, 873 { "ENLQIATNCMD", 0x01, 0x01 },
1101 { "ENLQIATNLQ", 0x02, 0x02 }, 874 { "ENLQIATNLQ", 0x02, 0x02 },
1102 { "ENLQIBADLQT", 0x04, 0x04 }, 875 { "ENLQIBADLQT", 0x04, 0x04 },
@@ -1112,7 +885,23 @@ ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1112 0x50, regvalue, cur_col, wrap)); 885 0x50, regvalue, cur_col, wrap));
1113} 886}
1114 887
1115static ahd_reg_parse_entry_t LQIMODE1_parse_table[] = { 888static const ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = {
889 { "CLRLQIATNCMD", 0x01, 0x01 },
890 { "CLRLQIATNLQ", 0x02, 0x02 },
891 { "CLRLQIBADLQT", 0x04, 0x04 },
892 { "CLRLQICRCT2", 0x08, 0x08 },
893 { "CLRLQICRCT1", 0x10, 0x10 },
894 { "CLRLQIATNQAS", 0x20, 0x20 }
895};
896
897int
898ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
899{
900 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
901 0x50, regvalue, cur_col, wrap));
902}
903
904static const ahd_reg_parse_entry_t LQIMODE1_parse_table[] = {
1116 { "ENLQIOVERI_NLQ", 0x01, 0x01 }, 905 { "ENLQIOVERI_NLQ", 0x01, 0x01 },
1117 { "ENLQIOVERI_LQ", 0x02, 0x02 }, 906 { "ENLQIOVERI_LQ", 0x02, 0x02 },
1118 { "ENLQIBADLQI", 0x04, 0x04 }, 907 { "ENLQIBADLQI", 0x04, 0x04 },
@@ -1130,7 +919,7 @@ ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1130 0x51, regvalue, cur_col, wrap)); 919 0x51, regvalue, cur_col, wrap));
1131} 920}
1132 921
1133static ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { 922static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
1134 { "LQIOVERI_NLQ", 0x01, 0x01 }, 923 { "LQIOVERI_NLQ", 0x01, 0x01 },
1135 { "LQIOVERI_LQ", 0x02, 0x02 }, 924 { "LQIOVERI_LQ", 0x02, 0x02 },
1136 { "LQIBADLQI", 0x04, 0x04 }, 925 { "LQIBADLQI", 0x04, 0x04 },
@@ -1148,7 +937,7 @@ ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1148 0x51, regvalue, cur_col, wrap)); 937 0x51, regvalue, cur_col, wrap));
1149} 938}
1150 939
1151static ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = { 940static const ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = {
1152 { "CLRLQIOVERI_NLQ", 0x01, 0x01 }, 941 { "CLRLQIOVERI_NLQ", 0x01, 0x01 },
1153 { "CLRLQIOVERI_LQ", 0x02, 0x02 }, 942 { "CLRLQIOVERI_LQ", 0x02, 0x02 },
1154 { "CLRLQIBADLQI", 0x04, 0x04 }, 943 { "CLRLQIBADLQI", 0x04, 0x04 },
@@ -1166,7 +955,7 @@ ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1166 0x51, regvalue, cur_col, wrap)); 955 0x51, regvalue, cur_col, wrap));
1167} 956}
1168 957
1169static ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { 958static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
1170 { "LQIGSAVAIL", 0x01, 0x01 }, 959 { "LQIGSAVAIL", 0x01, 0x01 },
1171 { "LQISTOPCMD", 0x02, 0x02 }, 960 { "LQISTOPCMD", 0x02, 0x02 },
1172 { "LQISTOPLQ", 0x04, 0x04 }, 961 { "LQISTOPLQ", 0x04, 0x04 },
@@ -1184,7 +973,7 @@ ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1184 0x52, regvalue, cur_col, wrap)); 973 0x52, regvalue, cur_col, wrap));
1185} 974}
1186 975
1187static ahd_reg_parse_entry_t SSTAT3_parse_table[] = { 976static const ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
1188 { "OSRAMPERR", 0x01, 0x01 }, 977 { "OSRAMPERR", 0x01, 0x01 },
1189 { "NTRAMPERR", 0x02, 0x02 } 978 { "NTRAMPERR", 0x02, 0x02 }
1190}; 979};
@@ -1196,7 +985,7 @@ ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1196 0x53, regvalue, cur_col, wrap)); 985 0x53, regvalue, cur_col, wrap));
1197} 986}
1198 987
1199static ahd_reg_parse_entry_t SIMODE3_parse_table[] = { 988static const ahd_reg_parse_entry_t SIMODE3_parse_table[] = {
1200 { "ENOSRAMPERR", 0x01, 0x01 }, 989 { "ENOSRAMPERR", 0x01, 0x01 },
1201 { "ENNTRAMPERR", 0x02, 0x02 } 990 { "ENNTRAMPERR", 0x02, 0x02 }
1202}; 991};
@@ -1208,7 +997,7 @@ ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1208 0x53, regvalue, cur_col, wrap)); 997 0x53, regvalue, cur_col, wrap));
1209} 998}
1210 999
1211static ahd_reg_parse_entry_t CLRSINT3_parse_table[] = { 1000static const ahd_reg_parse_entry_t CLRSINT3_parse_table[] = {
1212 { "CLROSRAMPERR", 0x01, 0x01 }, 1001 { "CLROSRAMPERR", 0x01, 0x01 },
1213 { "CLRNTRAMPERR", 0x02, 0x02 } 1002 { "CLRNTRAMPERR", 0x02, 0x02 }
1214}; 1003};
@@ -1220,7 +1009,7 @@ ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1220 0x53, regvalue, cur_col, wrap)); 1009 0x53, regvalue, cur_col, wrap));
1221} 1010}
1222 1011
1223static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { 1012static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
1224 { "LQOTCRC", 0x01, 0x01 }, 1013 { "LQOTCRC", 0x01, 0x01 },
1225 { "LQOATNPKT", 0x02, 0x02 }, 1014 { "LQOATNPKT", 0x02, 0x02 },
1226 { "LQOATNLQ", 0x04, 0x04 }, 1015 { "LQOATNLQ", 0x04, 0x04 },
@@ -1235,7 +1024,7 @@ ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1235 0x54, regvalue, cur_col, wrap)); 1024 0x54, regvalue, cur_col, wrap));
1236} 1025}
1237 1026
1238static ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = { 1027static const ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = {
1239 { "CLRLQOTCRC", 0x01, 0x01 }, 1028 { "CLRLQOTCRC", 0x01, 0x01 },
1240 { "CLRLQOATNPKT", 0x02, 0x02 }, 1029 { "CLRLQOATNPKT", 0x02, 0x02 },
1241 { "CLRLQOATNLQ", 0x04, 0x04 }, 1030 { "CLRLQOATNLQ", 0x04, 0x04 },
@@ -1250,7 +1039,7 @@ ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1250 0x54, regvalue, cur_col, wrap)); 1039 0x54, regvalue, cur_col, wrap));
1251} 1040}
1252 1041
1253static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = { 1042static const ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
1254 { "ENLQOTCRC", 0x01, 0x01 }, 1043 { "ENLQOTCRC", 0x01, 0x01 },
1255 { "ENLQOATNPKT", 0x02, 0x02 }, 1044 { "ENLQOATNPKT", 0x02, 0x02 },
1256 { "ENLQOATNLQ", 0x04, 0x04 }, 1045 { "ENLQOATNLQ", 0x04, 0x04 },
@@ -1265,7 +1054,7 @@ ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1265 0x54, regvalue, cur_col, wrap)); 1054 0x54, regvalue, cur_col, wrap));
1266} 1055}
1267 1056
1268static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = { 1057static const ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
1269 { "ENLQOPHACHGINPKT", 0x01, 0x01 }, 1058 { "ENLQOPHACHGINPKT", 0x01, 0x01 },
1270 { "ENLQOBUSFREE", 0x02, 0x02 }, 1059 { "ENLQOBUSFREE", 0x02, 0x02 },
1271 { "ENLQOBADQAS", 0x04, 0x04 }, 1060 { "ENLQOBADQAS", 0x04, 0x04 },
@@ -1280,7 +1069,7 @@ ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1280 0x55, regvalue, cur_col, wrap)); 1069 0x55, regvalue, cur_col, wrap));
1281} 1070}
1282 1071
1283static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { 1072static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
1284 { "LQOPHACHGINPKT", 0x01, 0x01 }, 1073 { "LQOPHACHGINPKT", 0x01, 0x01 },
1285 { "LQOBUSFREE", 0x02, 0x02 }, 1074 { "LQOBUSFREE", 0x02, 0x02 },
1286 { "LQOBADQAS", 0x04, 0x04 }, 1075 { "LQOBADQAS", 0x04, 0x04 },
@@ -1295,7 +1084,7 @@ ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1295 0x55, regvalue, cur_col, wrap)); 1084 0x55, regvalue, cur_col, wrap));
1296} 1085}
1297 1086
1298static ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = { 1087static const ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = {
1299 { "CLRLQOPHACHGINPKT", 0x01, 0x01 }, 1088 { "CLRLQOPHACHGINPKT", 0x01, 0x01 },
1300 { "CLRLQOBUSFREE", 0x02, 0x02 }, 1089 { "CLRLQOBUSFREE", 0x02, 0x02 },
1301 { "CLRLQOBADQAS", 0x04, 0x04 }, 1090 { "CLRLQOBADQAS", 0x04, 0x04 },
@@ -1310,7 +1099,7 @@ ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1310 0x55, regvalue, cur_col, wrap)); 1099 0x55, regvalue, cur_col, wrap));
1311} 1100}
1312 1101
1313static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { 1102static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
1314 { "LQOSTOP0", 0x01, 0x01 }, 1103 { "LQOSTOP0", 0x01, 0x01 },
1315 { "LQOPHACHGOUTPKT", 0x02, 0x02 }, 1104 { "LQOPHACHGOUTPKT", 0x02, 0x02 },
1316 { "LQOWAITFIFO", 0x10, 0x10 }, 1105 { "LQOWAITFIFO", 0x10, 0x10 },
@@ -1331,7 +1120,7 @@ ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1331 0x56, regvalue, cur_col, wrap)); 1120 0x56, regvalue, cur_col, wrap));
1332} 1121}
1333 1122
1334static ahd_reg_parse_entry_t SIMODE1_parse_table[] = { 1123static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
1335 { "ENREQINIT", 0x01, 0x01 }, 1124 { "ENREQINIT", 0x01, 0x01 },
1336 { "ENSTRB2FAST", 0x02, 0x02 }, 1125 { "ENSTRB2FAST", 0x02, 0x02 },
1337 { "ENSCSIPERR", 0x04, 0x04 }, 1126 { "ENSCSIPERR", 0x04, 0x04 },
@@ -1356,7 +1145,7 @@ ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1356 0x58, regvalue, cur_col, wrap)); 1145 0x58, regvalue, cur_col, wrap));
1357} 1146}
1358 1147
1359static ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { 1148static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
1360 { "RSTCHN", 0x01, 0x01 }, 1149 { "RSTCHN", 0x01, 0x01 },
1361 { "CLRCHN", 0x02, 0x02 }, 1150 { "CLRCHN", 0x02, 0x02 },
1362 { "CLRSHCNT", 0x04, 0x04 }, 1151 { "CLRSHCNT", 0x04, 0x04 },
@@ -1370,15 +1159,17 @@ ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1370 0x5a, regvalue, cur_col, wrap)); 1159 0x5a, regvalue, cur_col, wrap));
1371} 1160}
1372 1161
1373static ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = { 1162static const ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = {
1374 { "LQONOCHKOVER", 0x01, 0x01 }, 1163 { "LQONOCHKOVER", 0x01, 0x01 },
1164 { "LQONOHOLDLACK", 0x02, 0x02 },
1165 { "LQOBUSETDLY", 0x40, 0x40 },
1375 { "LQOH2A_VERSION", 0x80, 0x80 } 1166 { "LQOH2A_VERSION", 0x80, 0x80 }
1376}; 1167};
1377 1168
1378int 1169int
1379ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1170ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1380{ 1171{
1381 return (ahd_print_register(LQOSCSCTL_parse_table, 2, "LQOSCSCTL", 1172 return (ahd_print_register(LQOSCSCTL_parse_table, 4, "LQOSCSCTL",
1382 0x5a, regvalue, cur_col, wrap)); 1173 0x5a, regvalue, cur_col, wrap));
1383} 1174}
1384 1175
@@ -1389,7 +1180,7 @@ ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1389 0x5a, regvalue, cur_col, wrap)); 1180 0x5a, regvalue, cur_col, wrap));
1390} 1181}
1391 1182
1392static ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = { 1183static const ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = {
1393 { "CLRCFG4TCMD", 0x01, 0x01 }, 1184 { "CLRCFG4TCMD", 0x01, 0x01 },
1394 { "CLRCFG4ICMD", 0x02, 0x02 }, 1185 { "CLRCFG4ICMD", 0x02, 0x02 },
1395 { "CLRCFG4TSTAT", 0x04, 0x04 }, 1186 { "CLRCFG4TSTAT", 0x04, 0x04 },
@@ -1406,7 +1197,7 @@ ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
1406 0x5b, regvalue, cur_col, wrap)); 1197 0x5b, regvalue, cur_col, wrap));
1407} 1198}
1408 1199
1409static ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { 1200static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
1410 { "CFG4TCMD", 0x01, 0x01 }, 1201 { "CFG4TCMD", 0x01, 0x01 },
1411 { "CFG4ICMD", 0x02, 0x02 }, 1202 { "CFG4ICMD", 0x02, 0x02 },
1412 { "CFG4TSTAT", 0x04, 0x04 }, 1203 { "CFG4TSTAT", 0x04, 0x04 },
@@ -1423,14 +1214,7 @@ ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
1423 0x5b, regvalue, cur_col, wrap)); 1214 0x5b, regvalue, cur_col, wrap));
1424} 1215}
1425 1216
1426int 1217static const ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
1427ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1428{
1429 return (ahd_print_register(NULL, 0, "CURRSCB",
1430 0x5c, regvalue, cur_col, wrap));
1431}
1432
1433static ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
1434 { "ENCFG4TCMD", 0x01, 0x01 }, 1218 { "ENCFG4TCMD", 0x01, 0x01 },
1435 { "ENCFG4ICMD", 0x02, 0x02 }, 1219 { "ENCFG4ICMD", 0x02, 0x02 },
1436 { "ENCFG4TSTAT", 0x04, 0x04 }, 1220 { "ENCFG4TSTAT", 0x04, 0x04 },
@@ -1447,7 +1231,14 @@ ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
1447 0x5c, regvalue, cur_col, wrap)); 1231 0x5c, regvalue, cur_col, wrap));
1448} 1232}
1449 1233
1450static ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { 1234int
1235ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1236{
1237 return (ahd_print_register(NULL, 0, "CURRSCB",
1238 0x5c, regvalue, cur_col, wrap));
1239}
1240
1241static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
1451 { "FIFOFREE", 0x01, 0x01 }, 1242 { "FIFOFREE", 0x01, 0x01 },
1452 { "DATAINFIFO", 0x02, 0x02 }, 1243 { "DATAINFIFO", 0x02, 0x02 },
1453 { "DLZERO", 0x04, 0x04 }, 1244 { "DLZERO", 0x04, 0x04 },
@@ -1464,24 +1255,6 @@ ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1464 0x5d, regvalue, cur_col, wrap)); 1255 0x5d, regvalue, cur_col, wrap));
1465} 1256}
1466 1257
1467static ahd_reg_parse_entry_t CRCCONTROL_parse_table[] = {
1468 { "CRCVALCHKEN", 0x40, 0x40 }
1469};
1470
1471int
1472ahd_crccontrol_print(u_int regvalue, u_int *cur_col, u_int wrap)
1473{
1474 return (ahd_print_register(CRCCONTROL_parse_table, 1, "CRCCONTROL",
1475 0x5d, regvalue, cur_col, wrap));
1476}
1477
1478int
1479ahd_dfftag_print(u_int regvalue, u_int *cur_col, u_int wrap)
1480{
1481 return (ahd_print_register(NULL, 0, "DFFTAG",
1482 0x5e, regvalue, cur_col, wrap));
1483}
1484
1485int 1258int
1486ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1259ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1487{ 1260{
@@ -1489,31 +1262,6 @@ ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1489 0x5e, regvalue, cur_col, wrap)); 1262 0x5e, regvalue, cur_col, wrap));
1490} 1263}
1491 1264
1492static ahd_reg_parse_entry_t SCSITEST_parse_table[] = {
1493 { "SEL_TXPLL_DEBUG", 0x04, 0x04 },
1494 { "CNTRTEST", 0x08, 0x08 }
1495};
1496
1497int
1498ahd_scsitest_print(u_int regvalue, u_int *cur_col, u_int wrap)
1499{
1500 return (ahd_print_register(SCSITEST_parse_table, 2, "SCSITEST",
1501 0x5e, regvalue, cur_col, wrap));
1502}
1503
1504static ahd_reg_parse_entry_t IOPDNCTL_parse_table[] = {
1505 { "PDN_DIFFSENSE", 0x01, 0x01 },
1506 { "PDN_IDIST", 0x04, 0x04 },
1507 { "DISABLE_OE", 0x80, 0x80 }
1508};
1509
1510int
1511ahd_iopdnctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1512{
1513 return (ahd_print_register(IOPDNCTL_parse_table, 3, "IOPDNCTL",
1514 0x5f, regvalue, cur_col, wrap));
1515}
1516
1517int 1265int
1518ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1266ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1519{ 1267{
@@ -1529,13 +1277,6 @@ ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1529} 1277}
1530 1278
1531int 1279int
1532ahd_dgrpcrci_print(u_int regvalue, u_int *cur_col, u_int wrap)
1533{
1534 return (ahd_print_register(NULL, 0, "DGRPCRCI",
1535 0x60, regvalue, cur_col, wrap));
1536}
1537
1538int
1539ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap) 1280ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
1540{ 1281{
1541 return (ahd_print_register(NULL, 0, "NEGPERIOD", 1282 return (ahd_print_register(NULL, 0, "NEGPERIOD",
@@ -1543,20 +1284,13 @@ ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
1543} 1284}
1544 1285
1545int 1286int
1546ahd_packcrci_print(u_int regvalue, u_int *cur_col, u_int wrap)
1547{
1548 return (ahd_print_register(NULL, 0, "PACKCRCI",
1549 0x62, regvalue, cur_col, wrap));
1550}
1551
1552int
1553ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap) 1287ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
1554{ 1288{
1555 return (ahd_print_register(NULL, 0, "NEGOFFSET", 1289 return (ahd_print_register(NULL, 0, "NEGOFFSET",
1556 0x62, regvalue, cur_col, wrap)); 1290 0x62, regvalue, cur_col, wrap));
1557} 1291}
1558 1292
1559static ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = { 1293static const ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = {
1560 { "PPROPT_IUT", 0x01, 0x01 }, 1294 { "PPROPT_IUT", 0x01, 0x01 },
1561 { "PPROPT_DT", 0x02, 0x02 }, 1295 { "PPROPT_DT", 0x02, 0x02 },
1562 { "PPROPT_QAS", 0x04, 0x04 }, 1296 { "PPROPT_QAS", 0x04, 0x04 },
@@ -1570,7 +1304,7 @@ ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap)
1570 0x63, regvalue, cur_col, wrap)); 1304 0x63, regvalue, cur_col, wrap));
1571} 1305}
1572 1306
1573static ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = { 1307static const ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = {
1574 { "WIDEXFER", 0x01, 0x01 }, 1308 { "WIDEXFER", 0x01, 0x01 },
1575 { "ENAUTOATNO", 0x02, 0x02 }, 1309 { "ENAUTOATNO", 0x02, 0x02 },
1576 { "ENAUTOATNI", 0x04, 0x04 }, 1310 { "ENAUTOATNI", 0x04, 0x04 },
@@ -1601,20 +1335,21 @@ ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1601 0x66, regvalue, cur_col, wrap)); 1335 0x66, regvalue, cur_col, wrap));
1602} 1336}
1603 1337
1604static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = { 1338static const ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
1605 { "LSTSGCLRDIS", 0x01, 0x01 }, 1339 { "LSTSGCLRDIS", 0x01, 0x01 },
1606 { "SHVALIDSTDIS", 0x02, 0x02 }, 1340 { "SHVALIDSTDIS", 0x02, 0x02 },
1607 { "DFFACTCLR", 0x04, 0x04 }, 1341 { "DFFACTCLR", 0x04, 0x04 },
1608 { "SDONEMSKDIS", 0x08, 0x08 }, 1342 { "SDONEMSKDIS", 0x08, 0x08 },
1609 { "WIDERESEN", 0x10, 0x10 }, 1343 { "WIDERESEN", 0x10, 0x10 },
1610 { "CURRFIFODEF", 0x20, 0x20 }, 1344 { "CURRFIFODEF", 0x20, 0x20 },
1611 { "STSELSKIDDIS", 0x40, 0x40 } 1345 { "STSELSKIDDIS", 0x40, 0x40 },
1346 { "BIDICHKDIS", 0x80, 0x80 }
1612}; 1347};
1613 1348
1614int 1349int
1615ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap) 1350ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
1616{ 1351{
1617 return (ahd_print_register(SCSCHKN_parse_table, 7, "SCSCHKN", 1352 return (ahd_print_register(SCSCHKN_parse_table, 8, "SCSCHKN",
1618 0x66, regvalue, cur_col, wrap)); 1353 0x66, regvalue, cur_col, wrap));
1619} 1354}
1620 1355
@@ -1625,23 +1360,6 @@ ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1625 0x67, regvalue, cur_col, wrap)); 1360 0x67, regvalue, cur_col, wrap));
1626} 1361}
1627 1362
1628static ahd_reg_parse_entry_t PLL960CTL0_parse_table[] = {
1629 { "PLL_ENFBM", 0x01, 0x01 },
1630 { "PLL_DLPF", 0x02, 0x02 },
1631 { "PLL_ENLPF", 0x04, 0x04 },
1632 { "PLL_ENLUD", 0x08, 0x08 },
1633 { "PLL_NS", 0x30, 0x30 },
1634 { "PLL_PWDN", 0x40, 0x40 },
1635 { "PLL_VCOSEL", 0x80, 0x80 }
1636};
1637
1638int
1639ahd_pll960ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1640{
1641 return (ahd_print_register(PLL960CTL0_parse_table, 7, "PLL960CTL0",
1642 0x68, regvalue, cur_col, wrap));
1643}
1644
1645int 1363int
1646ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1364ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1647{ 1365{
@@ -1656,33 +1374,6 @@ ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1656 0x69, regvalue, cur_col, wrap)); 1374 0x69, regvalue, cur_col, wrap));
1657} 1375}
1658 1376
1659static ahd_reg_parse_entry_t PLL960CTL1_parse_table[] = {
1660 { "PLL_RST", 0x01, 0x01 },
1661 { "PLL_CNTCLR", 0x40, 0x40 },
1662 { "PLL_CNTEN", 0x80, 0x80 }
1663};
1664
1665int
1666ahd_pll960ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1667{
1668 return (ahd_print_register(PLL960CTL1_parse_table, 3, "PLL960CTL1",
1669 0x69, regvalue, cur_col, wrap));
1670}
1671
1672int
1673ahd_pll960cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1674{
1675 return (ahd_print_register(NULL, 0, "PLL960CNT0",
1676 0x6a, regvalue, cur_col, wrap));
1677}
1678
1679int
1680ahd_xsig_print(u_int regvalue, u_int *cur_col, u_int wrap)
1681{
1682 return (ahd_print_register(NULL, 0, "XSIG",
1683 0x6a, regvalue, cur_col, wrap));
1684}
1685
1686int 1377int
1687ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1378ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1688{ 1379{
@@ -1690,57 +1381,6 @@ ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1690 0x6b, regvalue, cur_col, wrap)); 1381 0x6b, regvalue, cur_col, wrap));
1691} 1382}
1692 1383
1693static ahd_reg_parse_entry_t PLL400CTL0_parse_table[] = {
1694 { "PLL_ENFBM", 0x01, 0x01 },
1695 { "PLL_DLPF", 0x02, 0x02 },
1696 { "PLL_ENLPF", 0x04, 0x04 },
1697 { "PLL_ENLUD", 0x08, 0x08 },
1698 { "PLL_NS", 0x30, 0x30 },
1699 { "PLL_PWDN", 0x40, 0x40 },
1700 { "PLL_VCOSEL", 0x80, 0x80 }
1701};
1702
1703int
1704ahd_pll400ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1705{
1706 return (ahd_print_register(PLL400CTL0_parse_table, 7, "PLL400CTL0",
1707 0x6c, regvalue, cur_col, wrap));
1708}
1709
1710int
1711ahd_fairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
1712{
1713 return (ahd_print_register(NULL, 0, "FAIRNESS",
1714 0x6c, regvalue, cur_col, wrap));
1715}
1716
1717static ahd_reg_parse_entry_t PLL400CTL1_parse_table[] = {
1718 { "PLL_RST", 0x01, 0x01 },
1719 { "PLL_CNTCLR", 0x40, 0x40 },
1720 { "PLL_CNTEN", 0x80, 0x80 }
1721};
1722
1723int
1724ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1725{
1726 return (ahd_print_register(PLL400CTL1_parse_table, 3, "PLL400CTL1",
1727 0x6d, regvalue, cur_col, wrap));
1728}
1729
1730int
1731ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
1732{
1733 return (ahd_print_register(NULL, 0, "UNFAIRNESS",
1734 0x6e, regvalue, cur_col, wrap));
1735}
1736
1737int
1738ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1739{
1740 return (ahd_print_register(NULL, 0, "PLL400CNT0",
1741 0x6e, regvalue, cur_col, wrap));
1742}
1743
1744int 1384int
1745ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1385ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1746{ 1386{
@@ -1748,31 +1388,6 @@ ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1748 0x70, regvalue, cur_col, wrap)); 1388 0x70, regvalue, cur_col, wrap));
1749} 1389}
1750 1390
1751static ahd_reg_parse_entry_t PLLDELAY_parse_table[] = {
1752 { "SPLIT_DROP_REQ", 0x80, 0x80 }
1753};
1754
1755int
1756ahd_plldelay_print(u_int regvalue, u_int *cur_col, u_int wrap)
1757{
1758 return (ahd_print_register(PLLDELAY_parse_table, 1, "PLLDELAY",
1759 0x70, regvalue, cur_col, wrap));
1760}
1761
1762int
1763ahd_hodmaadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1764{
1765 return (ahd_print_register(NULL, 0, "HODMAADR",
1766 0x70, regvalue, cur_col, wrap));
1767}
1768
1769int
1770ahd_hodmacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1771{
1772 return (ahd_print_register(NULL, 0, "HODMACNT",
1773 0x78, regvalue, cur_col, wrap));
1774}
1775
1776int 1391int
1777ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1392ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1778{ 1393{
@@ -1781,10 +1396,10 @@ ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1781} 1396}
1782 1397
1783int 1398int
1784ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap) 1399ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1785{ 1400{
1786 return (ahd_print_register(NULL, 0, "HODMAEN", 1401 return (ahd_print_register(NULL, 0, "SGHADDR",
1787 0x7a, regvalue, cur_col, wrap)); 1402 0x7c, regvalue, cur_col, wrap));
1788} 1403}
1789 1404
1790int 1405int
@@ -1795,10 +1410,10 @@ ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1795} 1410}
1796 1411
1797int 1412int
1798ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1413ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1799{ 1414{
1800 return (ahd_print_register(NULL, 0, "SGHADDR", 1415 return (ahd_print_register(NULL, 0, "SGHCNT",
1801 0x7c, regvalue, cur_col, wrap)); 1416 0x84, regvalue, cur_col, wrap));
1802} 1417}
1803 1418
1804int 1419int
@@ -1808,14 +1423,7 @@ ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1808 0x84, regvalue, cur_col, wrap)); 1423 0x84, regvalue, cur_col, wrap));
1809} 1424}
1810 1425
1811int 1426static const ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1812ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1813{
1814 return (ahd_print_register(NULL, 0, "SGHCNT",
1815 0x84, regvalue, cur_col, wrap));
1816}
1817
1818static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1819 { "WR_DFTHRSH_MIN", 0x00, 0x70 }, 1427 { "WR_DFTHRSH_MIN", 0x00, 0x70 },
1820 { "RD_DFTHRSH_MIN", 0x00, 0x07 }, 1428 { "RD_DFTHRSH_MIN", 0x00, 0x07 },
1821 { "RD_DFTHRSH_25", 0x01, 0x07 }, 1429 { "RD_DFTHRSH_25", 0x01, 0x07 },
@@ -1843,209 +1451,7 @@ ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1843 0x88, regvalue, cur_col, wrap)); 1451 0x88, regvalue, cur_col, wrap));
1844} 1452}
1845 1453
1846int 1454static const ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
1847ahd_romaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1848{
1849 return (ahd_print_register(NULL, 0, "ROMADDR",
1850 0x8a, regvalue, cur_col, wrap));
1851}
1852
1853static ahd_reg_parse_entry_t ROMCNTRL_parse_table[] = {
1854 { "RDY", 0x01, 0x01 },
1855 { "REPEAT", 0x02, 0x02 },
1856 { "ROMSPD", 0x18, 0x18 },
1857 { "ROMOP", 0xe0, 0xe0 }
1858};
1859
1860int
1861ahd_romcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1862{
1863 return (ahd_print_register(ROMCNTRL_parse_table, 4, "ROMCNTRL",
1864 0x8d, regvalue, cur_col, wrap));
1865}
1866
1867int
1868ahd_romdata_print(u_int regvalue, u_int *cur_col, u_int wrap)
1869{
1870 return (ahd_print_register(NULL, 0, "ROMDATA",
1871 0x8e, regvalue, cur_col, wrap));
1872}
1873
1874static ahd_reg_parse_entry_t CMCRXMSG0_parse_table[] = {
1875 { "CFNUM", 0x07, 0x07 },
1876 { "CDNUM", 0xf8, 0xf8 }
1877};
1878
1879int
1880ahd_cmcrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1881{
1882 return (ahd_print_register(CMCRXMSG0_parse_table, 2, "CMCRXMSG0",
1883 0x90, regvalue, cur_col, wrap));
1884}
1885
1886static ahd_reg_parse_entry_t ROENABLE_parse_table[] = {
1887 { "DCH0ROEN", 0x01, 0x01 },
1888 { "DCH1ROEN", 0x02, 0x02 },
1889 { "SGROEN", 0x04, 0x04 },
1890 { "CMCROEN", 0x08, 0x08 },
1891 { "OVLYROEN", 0x10, 0x10 },
1892 { "MSIROEN", 0x20, 0x20 }
1893};
1894
1895int
1896ahd_roenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
1897{
1898 return (ahd_print_register(ROENABLE_parse_table, 6, "ROENABLE",
1899 0x90, regvalue, cur_col, wrap));
1900}
1901
1902static ahd_reg_parse_entry_t OVLYRXMSG0_parse_table[] = {
1903 { "CFNUM", 0x07, 0x07 },
1904 { "CDNUM", 0xf8, 0xf8 }
1905};
1906
1907int
1908ahd_ovlyrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1909{
1910 return (ahd_print_register(OVLYRXMSG0_parse_table, 2, "OVLYRXMSG0",
1911 0x90, regvalue, cur_col, wrap));
1912}
1913
1914static ahd_reg_parse_entry_t DCHRXMSG0_parse_table[] = {
1915 { "CFNUM", 0x07, 0x07 },
1916 { "CDNUM", 0xf8, 0xf8 }
1917};
1918
1919int
1920ahd_dchrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1921{
1922 return (ahd_print_register(DCHRXMSG0_parse_table, 2, "DCHRXMSG0",
1923 0x90, regvalue, cur_col, wrap));
1924}
1925
1926static ahd_reg_parse_entry_t OVLYRXMSG1_parse_table[] = {
1927 { "CBNUM", 0xff, 0xff }
1928};
1929
1930int
1931ahd_ovlyrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1932{
1933 return (ahd_print_register(OVLYRXMSG1_parse_table, 1, "OVLYRXMSG1",
1934 0x91, regvalue, cur_col, wrap));
1935}
1936
1937static ahd_reg_parse_entry_t NSENABLE_parse_table[] = {
1938 { "DCH0NSEN", 0x01, 0x01 },
1939 { "DCH1NSEN", 0x02, 0x02 },
1940 { "SGNSEN", 0x04, 0x04 },
1941 { "CMCNSEN", 0x08, 0x08 },
1942 { "OVLYNSEN", 0x10, 0x10 },
1943 { "MSINSEN", 0x20, 0x20 }
1944};
1945
1946int
1947ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
1948{
1949 return (ahd_print_register(NSENABLE_parse_table, 6, "NSENABLE",
1950 0x91, regvalue, cur_col, wrap));
1951}
1952
1953static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = {
1954 { "CBNUM", 0xff, 0xff }
1955};
1956
1957int
1958ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1959{
1960 return (ahd_print_register(CMCRXMSG1_parse_table, 1, "CMCRXMSG1",
1961 0x91, regvalue, cur_col, wrap));
1962}
1963
1964static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
1965 { "CBNUM", 0xff, 0xff }
1966};
1967
1968int
1969ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1970{
1971 return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
1972 0x91, regvalue, cur_col, wrap));
1973}
1974
1975static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = {
1976 { "MINDEX", 0xff, 0xff }
1977};
1978
1979int
1980ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1981{
1982 return (ahd_print_register(DCHRXMSG2_parse_table, 1, "DCHRXMSG2",
1983 0x92, regvalue, cur_col, wrap));
1984}
1985
1986static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = {
1987 { "MINDEX", 0xff, 0xff }
1988};
1989
1990int
1991ahd_cmcrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1992{
1993 return (ahd_print_register(CMCRXMSG2_parse_table, 1, "CMCRXMSG2",
1994 0x92, regvalue, cur_col, wrap));
1995}
1996
1997int
1998ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap)
1999{
2000 return (ahd_print_register(NULL, 0, "OST",
2001 0x92, regvalue, cur_col, wrap));
2002}
2003
2004static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
2005 { "MINDEX", 0xff, 0xff }
2006};
2007
2008int
2009ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2010{
2011 return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
2012 0x92, regvalue, cur_col, wrap));
2013}
2014
2015static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = {
2016 { "MCLASS", 0x0f, 0x0f }
2017};
2018
2019int
2020ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2021{
2022 return (ahd_print_register(DCHRXMSG3_parse_table, 1, "DCHRXMSG3",
2023 0x93, regvalue, cur_col, wrap));
2024}
2025
2026static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
2027 { "MCLASS", 0x0f, 0x0f }
2028};
2029
2030int
2031ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2032{
2033 return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
2034 0x93, regvalue, cur_col, wrap));
2035}
2036
2037static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = {
2038 { "MCLASS", 0x0f, 0x0f }
2039};
2040
2041int
2042ahd_cmcrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2043{
2044 return (ahd_print_register(CMCRXMSG3_parse_table, 1, "CMCRXMSG3",
2045 0x93, regvalue, cur_col, wrap));
2046}
2047
2048static ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
2049 { "CMPABCDIS", 0x01, 0x01 }, 1455 { "CMPABCDIS", 0x01, 0x01 },
2050 { "TSCSERREN", 0x02, 0x02 }, 1456 { "TSCSERREN", 0x02, 0x02 },
2051 { "SRSPDPEEN", 0x04, 0x04 }, 1457 { "SRSPDPEEN", 0x04, 0x04 },
@@ -2062,46 +1468,7 @@ ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2062 0x93, regvalue, cur_col, wrap)); 1468 0x93, regvalue, cur_col, wrap));
2063} 1469}
2064 1470
2065int 1471static const ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
2066ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2067{
2068 return (ahd_print_register(NULL, 0, "OVLYSEQBCNT",
2069 0x94, regvalue, cur_col, wrap));
2070}
2071
2072int
2073ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2074{
2075 return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
2076 0x94, regvalue, cur_col, wrap));
2077}
2078
2079int
2080ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2081{
2082 return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
2083 0x94, regvalue, cur_col, wrap));
2084}
2085
2086static ahd_reg_parse_entry_t CMCSPLTSTAT0_parse_table[] = {
2087 { "RXSPLTRSP", 0x01, 0x01 },
2088 { "RXSCEMSG", 0x02, 0x02 },
2089 { "RXOVRUN", 0x04, 0x04 },
2090 { "CNTNOTCMPLT", 0x08, 0x08 },
2091 { "SCDATBUCKET", 0x10, 0x10 },
2092 { "SCADERR", 0x20, 0x20 },
2093 { "SCBCERR", 0x40, 0x40 },
2094 { "STAETERM", 0x80, 0x80 }
2095};
2096
2097int
2098ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2099{
2100 return (ahd_print_register(CMCSPLTSTAT0_parse_table, 8, "CMCSPLTSTAT0",
2101 0x96, regvalue, cur_col, wrap));
2102}
2103
2104static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
2105 { "RXSPLTRSP", 0x01, 0x01 }, 1472 { "RXSPLTRSP", 0x01, 0x01 },
2106 { "RXSCEMSG", 0x02, 0x02 }, 1473 { "RXSCEMSG", 0x02, 0x02 },
2107 { "RXOVRUN", 0x04, 0x04 }, 1474 { "RXOVRUN", 0x04, 0x04 },
@@ -2119,47 +1486,7 @@ ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2119 0x96, regvalue, cur_col, wrap)); 1486 0x96, regvalue, cur_col, wrap));
2120} 1487}
2121 1488
2122static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = { 1489static const ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
2123 { "RXSPLTRSP", 0x01, 0x01 },
2124 { "RXSCEMSG", 0x02, 0x02 },
2125 { "RXOVRUN", 0x04, 0x04 },
2126 { "CNTNOTCMPLT", 0x08, 0x08 },
2127 { "SCDATBUCKET", 0x10, 0x10 },
2128 { "SCADERR", 0x20, 0x20 },
2129 { "SCBCERR", 0x40, 0x40 },
2130 { "STAETERM", 0x80, 0x80 }
2131};
2132
2133int
2134ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2135{
2136 return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
2137 0x96, regvalue, cur_col, wrap));
2138}
2139
2140static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = {
2141 { "RXDATABUCKET", 0x01, 0x01 }
2142};
2143
2144int
2145ahd_cmcspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2146{
2147 return (ahd_print_register(CMCSPLTSTAT1_parse_table, 1, "CMCSPLTSTAT1",
2148 0x97, regvalue, cur_col, wrap));
2149}
2150
2151static ahd_reg_parse_entry_t OVLYSPLTSTAT1_parse_table[] = {
2152 { "RXDATABUCKET", 0x01, 0x01 }
2153};
2154
2155int
2156ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2157{
2158 return (ahd_print_register(OVLYSPLTSTAT1_parse_table, 1, "OVLYSPLTSTAT1",
2159 0x97, regvalue, cur_col, wrap));
2160}
2161
2162static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
2163 { "RXDATABUCKET", 0x01, 0x01 } 1490 { "RXDATABUCKET", 0x01, 0x01 }
2164}; 1491};
2165 1492
@@ -2170,139 +1497,7 @@ ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2170 0x97, regvalue, cur_col, wrap)); 1497 0x97, regvalue, cur_col, wrap));
2171} 1498}
2172 1499
2173static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = { 1500static const ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
2174 { "CFNUM", 0x07, 0x07 },
2175 { "CDNUM", 0xf8, 0xf8 }
2176};
2177
2178int
2179ahd_sgrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2180{
2181 return (ahd_print_register(SGRXMSG0_parse_table, 2, "SGRXMSG0",
2182 0x98, regvalue, cur_col, wrap));
2183}
2184
2185static ahd_reg_parse_entry_t SLVSPLTOUTADR0_parse_table[] = {
2186 { "LOWER_ADDR", 0x7f, 0x7f }
2187};
2188
2189int
2190ahd_slvspltoutadr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2191{
2192 return (ahd_print_register(SLVSPLTOUTADR0_parse_table, 1, "SLVSPLTOUTADR0",
2193 0x98, regvalue, cur_col, wrap));
2194}
2195
2196static ahd_reg_parse_entry_t SGRXMSG1_parse_table[] = {
2197 { "CBNUM", 0xff, 0xff }
2198};
2199
2200int
2201ahd_sgrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2202{
2203 return (ahd_print_register(SGRXMSG1_parse_table, 1, "SGRXMSG1",
2204 0x99, regvalue, cur_col, wrap));
2205}
2206
2207static ahd_reg_parse_entry_t SLVSPLTOUTADR1_parse_table[] = {
2208 { "REQ_FNUM", 0x07, 0x07 },
2209 { "REQ_DNUM", 0xf8, 0xf8 }
2210};
2211
2212int
2213ahd_slvspltoutadr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2214{
2215 return (ahd_print_register(SLVSPLTOUTADR1_parse_table, 2, "SLVSPLTOUTADR1",
2216 0x99, regvalue, cur_col, wrap));
2217}
2218
2219static ahd_reg_parse_entry_t SGRXMSG2_parse_table[] = {
2220 { "MINDEX", 0xff, 0xff }
2221};
2222
2223int
2224ahd_sgrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2225{
2226 return (ahd_print_register(SGRXMSG2_parse_table, 1, "SGRXMSG2",
2227 0x9a, regvalue, cur_col, wrap));
2228}
2229
2230static ahd_reg_parse_entry_t SLVSPLTOUTADR2_parse_table[] = {
2231 { "REQ_BNUM", 0xff, 0xff }
2232};
2233
2234int
2235ahd_slvspltoutadr2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2236{
2237 return (ahd_print_register(SLVSPLTOUTADR2_parse_table, 1, "SLVSPLTOUTADR2",
2238 0x9a, regvalue, cur_col, wrap));
2239}
2240
2241static ahd_reg_parse_entry_t SGRXMSG3_parse_table[] = {
2242 { "MCLASS", 0x0f, 0x0f }
2243};
2244
2245int
2246ahd_sgrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2247{
2248 return (ahd_print_register(SGRXMSG3_parse_table, 1, "SGRXMSG3",
2249 0x9b, regvalue, cur_col, wrap));
2250}
2251
2252static ahd_reg_parse_entry_t SLVSPLTOUTADR3_parse_table[] = {
2253 { "RLXORD", 0x10, 0x10 },
2254 { "TAG_NUM", 0x1f, 0x1f }
2255};
2256
2257int
2258ahd_slvspltoutadr3_print(u_int regvalue, u_int *cur_col, u_int wrap)
2259{
2260 return (ahd_print_register(SLVSPLTOUTADR3_parse_table, 2, "SLVSPLTOUTADR3",
2261 0x9b, regvalue, cur_col, wrap));
2262}
2263
2264int
2265ahd_sgseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2266{
2267 return (ahd_print_register(NULL, 0, "SGSEQBCNT",
2268 0x9c, regvalue, cur_col, wrap));
2269}
2270
2271static ahd_reg_parse_entry_t SLVSPLTOUTATTR0_parse_table[] = {
2272 { "LOWER_BCNT", 0xff, 0xff }
2273};
2274
2275int
2276ahd_slvspltoutattr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2277{
2278 return (ahd_print_register(SLVSPLTOUTATTR0_parse_table, 1, "SLVSPLTOUTATTR0",
2279 0x9c, regvalue, cur_col, wrap));
2280}
2281
2282static ahd_reg_parse_entry_t SLVSPLTOUTATTR1_parse_table[] = {
2283 { "CMPLT_FNUM", 0x07, 0x07 },
2284 { "CMPLT_DNUM", 0xf8, 0xf8 }
2285};
2286
2287int
2288ahd_slvspltoutattr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2289{
2290 return (ahd_print_register(SLVSPLTOUTATTR1_parse_table, 2, "SLVSPLTOUTATTR1",
2291 0x9d, regvalue, cur_col, wrap));
2292}
2293
2294static ahd_reg_parse_entry_t SLVSPLTOUTATTR2_parse_table[] = {
2295 { "CMPLT_BNUM", 0xff, 0xff }
2296};
2297
2298int
2299ahd_slvspltoutattr2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2300{
2301 return (ahd_print_register(SLVSPLTOUTATTR2_parse_table, 1, "SLVSPLTOUTATTR2",
2302 0x9e, regvalue, cur_col, wrap));
2303}
2304
2305static ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
2306 { "RXSPLTRSP", 0x01, 0x01 }, 1501 { "RXSPLTRSP", 0x01, 0x01 },
2307 { "RXSCEMSG", 0x02, 0x02 }, 1502 { "RXSCEMSG", 0x02, 0x02 },
2308 { "RXOVRUN", 0x04, 0x04 }, 1503 { "RXOVRUN", 0x04, 0x04 },
@@ -2320,7 +1515,7 @@ ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2320 0x9e, regvalue, cur_col, wrap)); 1515 0x9e, regvalue, cur_col, wrap));
2321} 1516}
2322 1517
2323static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = { 1518static const ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
2324 { "RXDATABUCKET", 0x01, 0x01 } 1519 { "RXDATABUCKET", 0x01, 0x01 }
2325}; 1520};
2326 1521
@@ -2331,19 +1526,7 @@ ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2331 0x9f, regvalue, cur_col, wrap)); 1526 0x9f, regvalue, cur_col, wrap));
2332} 1527}
2333 1528
2334static ahd_reg_parse_entry_t SFUNCT_parse_table[] = { 1529static const ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
2335 { "TEST_NUM", 0x0f, 0x0f },
2336 { "TEST_GROUP", 0xf0, 0xf0 }
2337};
2338
2339int
2340ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
2341{
2342 return (ahd_print_register(SFUNCT_parse_table, 2, "SFUNCT",
2343 0x9f, regvalue, cur_col, wrap));
2344}
2345
2346static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
2347 { "DPR", 0x01, 0x01 }, 1530 { "DPR", 0x01, 0x01 },
2348 { "TWATERR", 0x02, 0x02 }, 1531 { "TWATERR", 0x02, 0x02 },
2349 { "RDPERR", 0x04, 0x04 }, 1532 { "RDPERR", 0x04, 0x04 },
@@ -2368,83 +1551,6 @@ ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2368 0xa0, regvalue, cur_col, wrap)); 1551 0xa0, regvalue, cur_col, wrap));
2369} 1552}
2370 1553
2371static ahd_reg_parse_entry_t DF1PCISTAT_parse_table[] = {
2372 { "DPR", 0x01, 0x01 },
2373 { "TWATERR", 0x02, 0x02 },
2374 { "RDPERR", 0x04, 0x04 },
2375 { "SCAAPERR", 0x08, 0x08 },
2376 { "RTA", 0x10, 0x10 },
2377 { "RMA", 0x20, 0x20 },
2378 { "SSE", 0x40, 0x40 },
2379 { "DPE", 0x80, 0x80 }
2380};
2381
2382int
2383ahd_df1pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2384{
2385 return (ahd_print_register(DF1PCISTAT_parse_table, 8, "DF1PCISTAT",
2386 0xa1, regvalue, cur_col, wrap));
2387}
2388
2389static ahd_reg_parse_entry_t SGPCISTAT_parse_table[] = {
2390 { "DPR", 0x01, 0x01 },
2391 { "RDPERR", 0x04, 0x04 },
2392 { "SCAAPERR", 0x08, 0x08 },
2393 { "RTA", 0x10, 0x10 },
2394 { "RMA", 0x20, 0x20 },
2395 { "SSE", 0x40, 0x40 },
2396 { "DPE", 0x80, 0x80 }
2397};
2398
2399int
2400ahd_sgpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2401{
2402 return (ahd_print_register(SGPCISTAT_parse_table, 7, "SGPCISTAT",
2403 0xa2, regvalue, cur_col, wrap));
2404}
2405
2406int
2407ahd_reg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2408{
2409 return (ahd_print_register(NULL, 0, "REG1",
2410 0xa2, regvalue, cur_col, wrap));
2411}
2412
2413static ahd_reg_parse_entry_t CMCPCISTAT_parse_table[] = {
2414 { "DPR", 0x01, 0x01 },
2415 { "TWATERR", 0x02, 0x02 },
2416 { "RDPERR", 0x04, 0x04 },
2417 { "SCAAPERR", 0x08, 0x08 },
2418 { "RTA", 0x10, 0x10 },
2419 { "RMA", 0x20, 0x20 },
2420 { "SSE", 0x40, 0x40 },
2421 { "DPE", 0x80, 0x80 }
2422};
2423
2424int
2425ahd_cmcpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2426{
2427 return (ahd_print_register(CMCPCISTAT_parse_table, 8, "CMCPCISTAT",
2428 0xa3, regvalue, cur_col, wrap));
2429}
2430
2431static ahd_reg_parse_entry_t OVLYPCISTAT_parse_table[] = {
2432 { "DPR", 0x01, 0x01 },
2433 { "RDPERR", 0x04, 0x04 },
2434 { "SCAAPERR", 0x08, 0x08 },
2435 { "RTA", 0x10, 0x10 },
2436 { "RMA", 0x20, 0x20 },
2437 { "SSE", 0x40, 0x40 },
2438 { "DPE", 0x80, 0x80 }
2439};
2440
2441int
2442ahd_ovlypcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2443{
2444 return (ahd_print_register(OVLYPCISTAT_parse_table, 7, "OVLYPCISTAT",
2445 0xa4, regvalue, cur_col, wrap));
2446}
2447
2448int 1554int
2449ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1555ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2450{ 1556{
@@ -2452,7 +1558,7 @@ ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2452 0xa4, regvalue, cur_col, wrap)); 1558 0xa4, regvalue, cur_col, wrap));
2453} 1559}
2454 1560
2455static ahd_reg_parse_entry_t SG_STATE_parse_table[] = { 1561static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
2456 { "SEGS_AVAIL", 0x01, 0x01 }, 1562 { "SEGS_AVAIL", 0x01, 0x01 },
2457 { "LOADING_NEEDED", 0x02, 0x02 }, 1563 { "LOADING_NEEDED", 0x02, 0x02 },
2458 { "FETCH_INPROG", 0x04, 0x04 } 1564 { "FETCH_INPROG", 0x04, 0x04 }
@@ -2465,23 +1571,7 @@ ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
2465 0xa6, regvalue, cur_col, wrap)); 1571 0xa6, regvalue, cur_col, wrap));
2466} 1572}
2467 1573
2468static ahd_reg_parse_entry_t MSIPCISTAT_parse_table[] = { 1574static const ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
2469 { "DPR", 0x01, 0x01 },
2470 { "TWATERR", 0x02, 0x02 },
2471 { "CLRPENDMSI", 0x08, 0x08 },
2472 { "RTA", 0x10, 0x10 },
2473 { "RMA", 0x20, 0x20 },
2474 { "SSE", 0x40, 0x40 }
2475};
2476
2477int
2478ahd_msipcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2479{
2480 return (ahd_print_register(MSIPCISTAT_parse_table, 6, "MSIPCISTAT",
2481 0xa6, regvalue, cur_col, wrap));
2482}
2483
2484static ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
2485 { "TWATERR", 0x02, 0x02 }, 1575 { "TWATERR", 0x02, 0x02 },
2486 { "STA", 0x08, 0x08 }, 1576 { "STA", 0x08, 0x08 },
2487 { "SSE", 0x40, 0x40 }, 1577 { "SSE", 0x40, 0x40 },
@@ -2496,27 +1586,13 @@ ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2496} 1586}
2497 1587
2498int 1588int
2499ahd_data_count_odd_print(u_int regvalue, u_int *cur_col, u_int wrap)
2500{
2501 return (ahd_print_register(NULL, 0, "DATA_COUNT_ODD",
2502 0xa7, regvalue, cur_col, wrap));
2503}
2504
2505int
2506ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1589ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2507{ 1590{
2508 return (ahd_print_register(NULL, 0, "SCBPTR", 1591 return (ahd_print_register(NULL, 0, "SCBPTR",
2509 0xa8, regvalue, cur_col, wrap)); 1592 0xa8, regvalue, cur_col, wrap));
2510} 1593}
2511 1594
2512int 1595static const ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
2513ahd_ccscbacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2514{
2515 return (ahd_print_register(NULL, 0, "CCSCBACNT",
2516 0xab, regvalue, cur_col, wrap));
2517}
2518
2519static ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
2520 { "SCBPTR_OFF", 0x07, 0x07 }, 1596 { "SCBPTR_OFF", 0x07, 0x07 },
2521 { "SCBPTR_ADDR", 0x38, 0x38 }, 1597 { "SCBPTR_ADDR", 0x38, 0x38 },
2522 { "AUSCBPTR_EN", 0x80, 0x80 } 1598 { "AUSCBPTR_EN", 0x80, 0x80 }
@@ -2537,36 +1613,13 @@ ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2537} 1613}
2538 1614
2539int 1615int
2540ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
2541{
2542 return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
2543 0xac, regvalue, cur_col, wrap));
2544}
2545
2546int
2547ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1616ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2548{ 1617{
2549 return (ahd_print_register(NULL, 0, "CCSCBADDR", 1618 return (ahd_print_register(NULL, 0, "CCSCBADDR",
2550 0xac, regvalue, cur_col, wrap)); 1619 0xac, regvalue, cur_col, wrap));
2551} 1620}
2552 1621
2553static ahd_reg_parse_entry_t CMC_RAMBIST_parse_table[] = { 1622static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
2554 { "CMC_BUFFER_BIST_EN", 0x01, 0x01 },
2555 { "CMC_BUFFER_BIST_FAIL",0x02, 0x02 },
2556 { "SG_BIST_EN", 0x10, 0x10 },
2557 { "SG_BIST_FAIL", 0x20, 0x20 },
2558 { "SCBRAMBIST_FAIL", 0x40, 0x40 },
2559 { "SG_ELEMENT_SIZE", 0x80, 0x80 }
2560};
2561
2562int
2563ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap)
2564{
2565 return (ahd_print_register(CMC_RAMBIST_parse_table, 6, "CMC_RAMBIST",
2566 0xad, regvalue, cur_col, wrap));
2567}
2568
2569static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
2570 { "CCSCBRESET", 0x01, 0x01 }, 1623 { "CCSCBRESET", 0x01, 0x01 },
2571 { "CCSCBDIR", 0x04, 0x04 }, 1624 { "CCSCBDIR", 0x04, 0x04 },
2572 { "CCSCBEN", 0x08, 0x08 }, 1625 { "CCSCBEN", 0x08, 0x08 },
@@ -2582,7 +1635,7 @@ ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2582 0xad, regvalue, cur_col, wrap)); 1635 0xad, regvalue, cur_col, wrap));
2583} 1636}
2584 1637
2585static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = { 1638static const ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
2586 { "CCSGRESET", 0x01, 0x01 }, 1639 { "CCSGRESET", 0x01, 0x01 },
2587 { "SG_FETCH_REQ", 0x02, 0x02 }, 1640 { "SG_FETCH_REQ", 0x02, 0x02 },
2588 { "CCSGENACK", 0x08, 0x08 }, 1641 { "CCSGENACK", 0x08, 0x08 },
@@ -2606,13 +1659,6 @@ ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
2606} 1659}
2607 1660
2608int 1661int
2609ahd_flexadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2610{
2611 return (ahd_print_register(NULL, 0, "FLEXADR",
2612 0xb0, regvalue, cur_col, wrap));
2613}
2614
2615int
2616ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) 1662ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
2617{ 1663{
2618 return (ahd_print_register(NULL, 0, "CCSCBRAM", 1664 return (ahd_print_register(NULL, 0, "CCSCBRAM",
@@ -2620,39 +1666,13 @@ ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
2620} 1666}
2621 1667
2622int 1668int
2623ahd_flexcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2624{
2625 return (ahd_print_register(NULL, 0, "FLEXCNT",
2626 0xb3, regvalue, cur_col, wrap));
2627}
2628
2629static ahd_reg_parse_entry_t FLEXDMASTAT_parse_table[] = {
2630 { "FLEXDMADONE", 0x01, 0x01 },
2631 { "FLEXDMAERR", 0x02, 0x02 }
2632};
2633
2634int
2635ahd_flexdmastat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2636{
2637 return (ahd_print_register(FLEXDMASTAT_parse_table, 2, "FLEXDMASTAT",
2638 0xb5, regvalue, cur_col, wrap));
2639}
2640
2641int
2642ahd_flexdata_print(u_int regvalue, u_int *cur_col, u_int wrap)
2643{
2644 return (ahd_print_register(NULL, 0, "FLEXDATA",
2645 0xb6, regvalue, cur_col, wrap));
2646}
2647
2648int
2649ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1669ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2650{ 1670{
2651 return (ahd_print_register(NULL, 0, "BRDDAT", 1671 return (ahd_print_register(NULL, 0, "BRDDAT",
2652 0xb8, regvalue, cur_col, wrap)); 1672 0xb8, regvalue, cur_col, wrap));
2653} 1673}
2654 1674
2655static ahd_reg_parse_entry_t BRDCTL_parse_table[] = { 1675static const ahd_reg_parse_entry_t BRDCTL_parse_table[] = {
2656 { "BRDSTB", 0x01, 0x01 }, 1676 { "BRDSTB", 0x01, 0x01 },
2657 { "BRDRW", 0x02, 0x02 }, 1677 { "BRDRW", 0x02, 0x02 },
2658 { "BRDEN", 0x04, 0x04 }, 1678 { "BRDEN", 0x04, 0x04 },
@@ -2682,7 +1702,7 @@ ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2682 0xbc, regvalue, cur_col, wrap)); 1702 0xbc, regvalue, cur_col, wrap));
2683} 1703}
2684 1704
2685static ahd_reg_parse_entry_t SEECTL_parse_table[] = { 1705static const ahd_reg_parse_entry_t SEECTL_parse_table[] = {
2686 { "SEEOP_ERAL", 0x40, 0x70 }, 1706 { "SEEOP_ERAL", 0x40, 0x70 },
2687 { "SEEOP_WRITE", 0x50, 0x70 }, 1707 { "SEEOP_WRITE", 0x50, 0x70 },
2688 { "SEEOP_READ", 0x60, 0x70 }, 1708 { "SEEOP_READ", 0x60, 0x70 },
@@ -2702,7 +1722,7 @@ ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2702 0xbe, regvalue, cur_col, wrap)); 1722 0xbe, regvalue, cur_col, wrap));
2703} 1723}
2704 1724
2705static ahd_reg_parse_entry_t SEESTAT_parse_table[] = { 1725static const ahd_reg_parse_entry_t SEESTAT_parse_table[] = {
2706 { "SEESTART", 0x01, 0x01 }, 1726 { "SEESTART", 0x01, 0x01 },
2707 { "SEEBUSY", 0x02, 0x02 }, 1727 { "SEEBUSY", 0x02, 0x02 },
2708 { "SEEARBACK", 0x04, 0x04 }, 1728 { "SEEARBACK", 0x04, 0x04 },
@@ -2718,34 +1738,7 @@ ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2718 0xbe, regvalue, cur_col, wrap)); 1738 0xbe, regvalue, cur_col, wrap));
2719} 1739}
2720 1740
2721int 1741static const ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
2722ahd_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2723{
2724 return (ahd_print_register(NULL, 0, "SCBCNT",
2725 0xbf, regvalue, cur_col, wrap));
2726}
2727
2728int
2729ahd_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2730{
2731 return (ahd_print_register(NULL, 0, "DFWADDR",
2732 0xc0, regvalue, cur_col, wrap));
2733}
2734
2735static ahd_reg_parse_entry_t DSPFLTRCTL_parse_table[] = {
2736 { "DSPFCNTSEL", 0x0f, 0x0f },
2737 { "EDGESENSE", 0x10, 0x10 },
2738 { "FLTRDISABLE", 0x20, 0x20 }
2739};
2740
2741int
2742ahd_dspfltrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2743{
2744 return (ahd_print_register(DSPFLTRCTL_parse_table, 3, "DSPFLTRCTL",
2745 0xc0, regvalue, cur_col, wrap));
2746}
2747
2748static ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
2749 { "XMITOFFSTDIS", 0x02, 0x02 }, 1742 { "XMITOFFSTDIS", 0x02, 0x02 },
2750 { "RCVROFFSTDIS", 0x04, 0x04 }, 1743 { "RCVROFFSTDIS", 0x04, 0x04 },
2751 { "DESQDIS", 0x10, 0x10 }, 1744 { "DESQDIS", 0x10, 0x10 },
@@ -2760,44 +1753,13 @@ ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2760} 1753}
2761 1754
2762int 1755int
2763ahd_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2764{
2765 return (ahd_print_register(NULL, 0, "DFRADDR",
2766 0xc2, regvalue, cur_col, wrap));
2767}
2768
2769static ahd_reg_parse_entry_t DSPREQCTL_parse_table[] = {
2770 { "MANREQDLY", 0x3f, 0x3f },
2771 { "MANREQCTL", 0xc0, 0xc0 }
2772};
2773
2774int
2775ahd_dspreqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2776{
2777 return (ahd_print_register(DSPREQCTL_parse_table, 2, "DSPREQCTL",
2778 0xc2, regvalue, cur_col, wrap));
2779}
2780
2781static ahd_reg_parse_entry_t DSPACKCTL_parse_table[] = {
2782 { "MANACKDLY", 0x3f, 0x3f },
2783 { "MANACKCTL", 0xc0, 0xc0 }
2784};
2785
2786int
2787ahd_dspackctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2788{
2789 return (ahd_print_register(DSPACKCTL_parse_table, 2, "DSPACKCTL",
2790 0xc3, regvalue, cur_col, wrap));
2791}
2792
2793int
2794ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1756ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
2795{ 1757{
2796 return (ahd_print_register(NULL, 0, "DFDAT", 1758 return (ahd_print_register(NULL, 0, "DFDAT",
2797 0xc4, regvalue, cur_col, wrap)); 1759 0xc4, regvalue, cur_col, wrap));
2798} 1760}
2799 1761
2800static ahd_reg_parse_entry_t DSPSELECT_parse_table[] = { 1762static const ahd_reg_parse_entry_t DSPSELECT_parse_table[] = {
2801 { "DSPSEL", 0x1f, 0x1f }, 1763 { "DSPSEL", 0x1f, 0x1f },
2802 { "AUTOINCEN", 0x80, 0x80 } 1764 { "AUTOINCEN", 0x80, 0x80 }
2803}; 1765};
@@ -2809,7 +1771,7 @@ ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap)
2809 0xc4, regvalue, cur_col, wrap)); 1771 0xc4, regvalue, cur_col, wrap));
2810} 1772}
2811 1773
2812static ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = { 1774static const ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = {
2813 { "XMITMANVAL", 0x3f, 0x3f }, 1775 { "XMITMANVAL", 0x3f, 0x3f },
2814 { "AUTOXBCDIS", 0x80, 0x80 } 1776 { "AUTOXBCDIS", 0x80, 0x80 }
2815}; 1777};
@@ -2821,91 +1783,7 @@ ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2821 0xc5, regvalue, cur_col, wrap)); 1783 0xc5, regvalue, cur_col, wrap));
2822} 1784}
2823 1785
2824static ahd_reg_parse_entry_t RCVRBIOSCTL_parse_table[] = { 1786static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
2825 { "RCVRMANVAL", 0x3f, 0x3f },
2826 { "AUTORBCDIS", 0x80, 0x80 }
2827};
2828
2829int
2830ahd_rcvrbiosctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2831{
2832 return (ahd_print_register(RCVRBIOSCTL_parse_table, 2, "RCVRBIOSCTL",
2833 0xc6, regvalue, cur_col, wrap));
2834}
2835
2836int
2837ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
2838{
2839 return (ahd_print_register(NULL, 0, "WRTBIASCALC",
2840 0xc7, regvalue, cur_col, wrap));
2841}
2842
2843int
2844ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
2845{
2846 return (ahd_print_register(NULL, 0, "RCVRBIASCALC",
2847 0xc8, regvalue, cur_col, wrap));
2848}
2849
2850int
2851ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
2852{
2853 return (ahd_print_register(NULL, 0, "DFPTRS",
2854 0xc8, regvalue, cur_col, wrap));
2855}
2856
2857int
2858ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
2859{
2860 return (ahd_print_register(NULL, 0, "SKEWCALC",
2861 0xc9, regvalue, cur_col, wrap));
2862}
2863
2864int
2865ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2866{
2867 return (ahd_print_register(NULL, 0, "DFBKPTR",
2868 0xc9, regvalue, cur_col, wrap));
2869}
2870
2871static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = {
2872 { "DFF_RAMBIST_EN", 0x01, 0x01 },
2873 { "DFF_RAMBIST_DONE", 0x02, 0x02 },
2874 { "DFF_RAMBIST_FAIL", 0x04, 0x04 },
2875 { "DFF_DIR_ERR", 0x08, 0x08 },
2876 { "DFF_CIO_RD_RDY", 0x10, 0x10 },
2877 { "DFF_CIO_WR_RDY", 0x20, 0x20 }
2878};
2879
2880int
2881ahd_dfdbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
2882{
2883 return (ahd_print_register(DFDBCTL_parse_table, 6, "DFDBCTL",
2884 0xcb, regvalue, cur_col, wrap));
2885}
2886
2887int
2888ahd_dfscnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2889{
2890 return (ahd_print_register(NULL, 0, "DFSCNT",
2891 0xcc, regvalue, cur_col, wrap));
2892}
2893
2894int
2895ahd_dfbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2896{
2897 return (ahd_print_register(NULL, 0, "DFBCNT",
2898 0xce, regvalue, cur_col, wrap));
2899}
2900
2901int
2902ahd_ovlyaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2903{
2904 return (ahd_print_register(NULL, 0, "OVLYADDR",
2905 0xd4, regvalue, cur_col, wrap));
2906}
2907
2908static ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
2909 { "LOADRAM", 0x01, 0x01 }, 1787 { "LOADRAM", 0x01, 0x01 },
2910 { "SEQRESET", 0x02, 0x02 }, 1788 { "SEQRESET", 0x02, 0x02 },
2911 { "STEP", 0x04, 0x04 }, 1789 { "STEP", 0x04, 0x04 },
@@ -2923,21 +1801,7 @@ ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
2923 0xd6, regvalue, cur_col, wrap)); 1801 0xd6, regvalue, cur_col, wrap));
2924} 1802}
2925 1803
2926static ahd_reg_parse_entry_t SEQCTL1_parse_table[] = { 1804static const ahd_reg_parse_entry_t FLAGS_parse_table[] = {
2927 { "RAMBIST_EN", 0x01, 0x01 },
2928 { "RAMBIST_FAIL", 0x02, 0x02 },
2929 { "RAMBIST_DONE", 0x04, 0x04 },
2930 { "OVRLAY_DATA_CHK", 0x08, 0x08 }
2931};
2932
2933int
2934ahd_seqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2935{
2936 return (ahd_print_register(SEQCTL1_parse_table, 4, "SEQCTL1",
2937 0xd7, regvalue, cur_col, wrap));
2938}
2939
2940static ahd_reg_parse_entry_t FLAGS_parse_table[] = {
2941 { "CARRY", 0x01, 0x01 }, 1805 { "CARRY", 0x01, 0x01 },
2942 { "ZERO", 0x02, 0x02 } 1806 { "ZERO", 0x02, 0x02 }
2943}; 1807};
@@ -2949,7 +1813,7 @@ ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
2949 0xd8, regvalue, cur_col, wrap)); 1813 0xd8, regvalue, cur_col, wrap));
2950} 1814}
2951 1815
2952static ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { 1816static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
2953 { "IRET", 0x01, 0x01 }, 1817 { "IRET", 0x01, 0x01 },
2954 { "INTMASK1", 0x02, 0x02 }, 1818 { "INTMASK1", 0x02, 0x02 },
2955 { "INTMASK2", 0x04, 0x04 }, 1819 { "INTMASK2", 0x04, 0x04 },
@@ -3002,24 +1866,6 @@ ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
3002} 1866}
3003 1867
3004int 1868int
3005ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
3006{
3007 return (ahd_print_register(NULL, 0, "BRKADDR0",
3008 0xe6, regvalue, cur_col, wrap));
3009}
3010
3011static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = {
3012 { "BRKDIS", 0x80, 0x80 }
3013};
3014
3015int
3016ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
3017{
3018 return (ahd_print_register(BRKADDR1_parse_table, 1, "BRKADDR1",
3019 0xe6, regvalue, cur_col, wrap));
3020}
3021
3022int
3023ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) 1869ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
3024{ 1870{
3025 return (ahd_print_register(NULL, 0, "ALLONES", 1871 return (ahd_print_register(NULL, 0, "ALLONES",
@@ -3055,13 +1901,6 @@ ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
3055} 1901}
3056 1902
3057int 1903int
3058ahd_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
3059{
3060 return (ahd_print_register(NULL, 0, "FUNCTION1",
3061 0xf0, regvalue, cur_col, wrap));
3062}
3063
3064int
3065ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 1904ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
3066{ 1905{
3067 return (ahd_print_register(NULL, 0, "STACK", 1906 return (ahd_print_register(NULL, 0, "STACK",
@@ -3083,13 +1922,6 @@ ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3083} 1922}
3084 1923
3085int 1924int
3086ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3087{
3088 return (ahd_print_register(NULL, 0, "LASTADDR",
3089 0xf6, regvalue, cur_col, wrap));
3090}
3091
3092int
3093ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1925ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3094{ 1926{
3095 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR", 1927 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
@@ -3111,23 +1943,16 @@ ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap)
3111} 1943}
3112 1944
3113int 1945int
3114ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap) 1946ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
3115{
3116 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
3117 0x100, regvalue, cur_col, wrap));
3118}
3119
3120int
3121ahd_ahd_pci_config_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
3122{ 1947{
3123 return (ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 1948 return (ahd_print_register(NULL, 0, "SRAM_BASE",
3124 0x100, regvalue, cur_col, wrap)); 1949 0x100, regvalue, cur_col, wrap));
3125} 1950}
3126 1951
3127int 1952int
3128ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 1953ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap)
3129{ 1954{
3130 return (ahd_print_register(NULL, 0, "SRAM_BASE", 1955 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
3131 0x100, regvalue, cur_col, wrap)); 1956 0x100, regvalue, cur_col, wrap));
3132} 1957}
3133 1958
@@ -3215,7 +2040,7 @@ ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
3215 0x137, regvalue, cur_col, wrap)); 2040 0x137, regvalue, cur_col, wrap));
3216} 2041}
3217 2042
3218static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = { 2043static const ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
3219 { "FIFORESET", 0x01, 0x01 }, 2044 { "FIFORESET", 0x01, 0x01 },
3220 { "FIFOFLUSH", 0x02, 0x02 }, 2045 { "FIFOFLUSH", 0x02, 0x02 },
3221 { "DIRECTION", 0x04, 0x04 }, 2046 { "DIRECTION", 0x04, 0x04 },
@@ -3235,7 +2060,7 @@ ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
3235 0x138, regvalue, cur_col, wrap)); 2060 0x138, regvalue, cur_col, wrap));
3236} 2061}
3237 2062
3238static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 2063static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
3239 { "NO_DISCONNECT", 0x01, 0x01 }, 2064 { "NO_DISCONNECT", 0x01, 0x01 },
3240 { "SPHASE_PENDING", 0x02, 0x02 }, 2065 { "SPHASE_PENDING", 0x02, 0x02 },
3241 { "DPHASE_PENDING", 0x04, 0x04 }, 2066 { "DPHASE_PENDING", 0x04, 0x04 },
@@ -3268,7 +2093,7 @@ ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
3268 0x13b, regvalue, cur_col, wrap)); 2093 0x13b, regvalue, cur_col, wrap));
3269} 2094}
3270 2095
3271static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { 2096static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
3272 { "P_DATAOUT", 0x00, 0xe0 }, 2097 { "P_DATAOUT", 0x00, 0xe0 },
3273 { "P_DATAOUT_DT", 0x20, 0xe0 }, 2098 { "P_DATAOUT_DT", 0x20, 0xe0 },
3274 { "P_DATAIN", 0x40, 0xe0 }, 2099 { "P_DATAIN", 0x40, 0xe0 },
@@ -3326,7 +2151,7 @@ ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3326 0x144, regvalue, cur_col, wrap)); 2151 0x144, regvalue, cur_col, wrap));
3327} 2152}
3328 2153
3329static ahd_reg_parse_entry_t ARG_1_parse_table[] = { 2154static const ahd_reg_parse_entry_t ARG_1_parse_table[] = {
3330 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 }, 2155 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 },
3331 { "CONT_MSG_LOOP_READ", 0x03, 0x03 }, 2156 { "CONT_MSG_LOOP_READ", 0x03, 0x03 },
3332 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 }, 2157 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 },
@@ -3358,7 +2183,7 @@ ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
3358 0x14a, regvalue, cur_col, wrap)); 2183 0x14a, regvalue, cur_col, wrap));
3359} 2184}
3360 2185
3361static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 2186static const ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
3362 { "ALTSTIM", 0x01, 0x01 }, 2187 { "ALTSTIM", 0x01, 0x01 },
3363 { "ENAUTOATNP", 0x02, 0x02 }, 2188 { "ENAUTOATNP", 0x02, 0x02 },
3364 { "MANUALP", 0x0c, 0x0c }, 2189 { "MANUALP", 0x0c, 0x0c },
@@ -3381,7 +2206,7 @@ ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
3381 0x14c, regvalue, cur_col, wrap)); 2206 0x14c, regvalue, cur_col, wrap));
3382} 2207}
3383 2208
3384static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 2209static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
3385 { "PENDING_MK_MESSAGE", 0x01, 0x01 }, 2210 { "PENDING_MK_MESSAGE", 0x01, 0x01 },
3386 { "TARGET_MSG_PENDING", 0x02, 0x02 }, 2211 { "TARGET_MSG_PENDING", 0x02, 0x02 },
3387 { "SELECTOUT_QFROZEN", 0x04, 0x04 } 2212 { "SELECTOUT_QFROZEN", 0x04, 0x04 }
@@ -3465,20 +2290,20 @@ ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
3465} 2290}
3466 2291
3467int 2292int
3468ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 2293ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
3469{ 2294{
3470 return (ahd_print_register(NULL, 0, "SCB_BASE", 2295 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT",
3471 0x180, regvalue, cur_col, wrap)); 2296 0x180, regvalue, cur_col, wrap));
3472} 2297}
3473 2298
3474int 2299int
3475ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2300ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
3476{ 2301{
3477 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 2302 return (ahd_print_register(NULL, 0, "SCB_BASE",
3478 0x180, regvalue, cur_col, wrap)); 2303 0x180, regvalue, cur_col, wrap));
3479} 2304}
3480 2305
3481static ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = { 2306static const ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = {
3482 { "SG_LIST_NULL", 0x01, 0x01 }, 2307 { "SG_LIST_NULL", 0x01, 0x01 },
3483 { "SG_OVERRUN_RESID", 0x02, 0x02 }, 2308 { "SG_OVERRUN_RESID", 0x02, 0x02 },
3484 { "SG_ADDR_MASK", 0xf8, 0xf8 } 2309 { "SG_ADDR_MASK", 0xf8, 0xf8 }
@@ -3499,27 +2324,6 @@ ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
3499} 2324}
3500 2325
3501int 2326int
3502ahd_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
3503{
3504 return (ahd_print_register(NULL, 0, "SCB_TARGET_PHASES",
3505 0x189, regvalue, cur_col, wrap));
3506}
3507
3508int
3509ahd_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
3510{
3511 return (ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
3512 0x18a, regvalue, cur_col, wrap));
3513}
3514
3515int
3516ahd_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
3517{
3518 return (ahd_print_register(NULL, 0, "SCB_TARGET_ITAG",
3519 0x18b, regvalue, cur_col, wrap));
3520}
3521
3522int
3523ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2327ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3524{ 2328{
3525 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 2329 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR",
@@ -3533,7 +2337,7 @@ ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
3533 0x190, regvalue, cur_col, wrap)); 2337 0x190, regvalue, cur_col, wrap));
3534} 2338}
3535 2339
3536static ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 2340static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
3537 { "SCB_TAG_TYPE", 0x03, 0x03 }, 2341 { "SCB_TAG_TYPE", 0x03, 0x03 },
3538 { "DISCONNECTED", 0x04, 0x04 }, 2342 { "DISCONNECTED", 0x04, 0x04 },
3539 { "STATUS_RCVD", 0x08, 0x08 }, 2343 { "STATUS_RCVD", 0x08, 0x08 },
@@ -3550,7 +2354,7 @@ ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
3550 0x192, regvalue, cur_col, wrap)); 2354 0x192, regvalue, cur_col, wrap));
3551} 2355}
3552 2356
3553static ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 2357static const ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
3554 { "OID", 0x0f, 0x0f }, 2358 { "OID", 0x0f, 0x0f },
3555 { "TID", 0xf0, 0xf0 } 2359 { "TID", 0xf0, 0xf0 }
3556}; 2360};
@@ -3562,7 +2366,7 @@ ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
3562 0x193, regvalue, cur_col, wrap)); 2366 0x193, regvalue, cur_col, wrap));
3563} 2367}
3564 2368
3565static ahd_reg_parse_entry_t SCB_LUN_parse_table[] = { 2369static const ahd_reg_parse_entry_t SCB_LUN_parse_table[] = {
3566 { "LID", 0xff, 0xff } 2370 { "LID", 0xff, 0xff }
3567}; 2371};
3568 2372
@@ -3573,7 +2377,7 @@ ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
3573 0x194, regvalue, cur_col, wrap)); 2377 0x194, regvalue, cur_col, wrap));
3574} 2378}
3575 2379
3576static ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = { 2380static const ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = {
3577 { "SCB_XFERLEN_ODD", 0x01, 0x01 } 2381 { "SCB_XFERLEN_ODD", 0x01, 0x01 }
3578}; 2382};
3579 2383
@@ -3584,7 +2388,7 @@ ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap)
3584 0x195, regvalue, cur_col, wrap)); 2388 0x195, regvalue, cur_col, wrap));
3585} 2389}
3586 2390
3587static ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = { 2391static const ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = {
3588 { "SCB_CDB_LEN_PTR", 0x80, 0x80 } 2392 { "SCB_CDB_LEN_PTR", 0x80, 0x80 }
3589}; 2393};
3590 2394
@@ -3609,7 +2413,7 @@ ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
3609 0x198, regvalue, cur_col, wrap)); 2413 0x198, regvalue, cur_col, wrap));
3610} 2414}
3611 2415
3612static ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 2416static const ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
3613 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }, 2417 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f },
3614 { "SG_LAST_SEG", 0x80, 0x80 } 2418 { "SG_LAST_SEG", 0x80, 0x80 }
3615}; 2419};
@@ -3621,7 +2425,7 @@ ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
3621 0x1a0, regvalue, cur_col, wrap)); 2425 0x1a0, regvalue, cur_col, wrap));
3622} 2426}
3623 2427
3624static ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 2428static const ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
3625 { "SG_LIST_NULL", 0x01, 0x01 }, 2429 { "SG_LIST_NULL", 0x01, 0x01 },
3626 { "SG_FULL_RESID", 0x02, 0x02 }, 2430 { "SG_FULL_RESID", 0x02, 0x02 },
3627 { "SG_STATUS_VALID", 0x04, 0x04 } 2431 { "SG_STATUS_VALID", 0x04, 0x04 }
@@ -3656,13 +2460,6 @@ ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap)
3656} 2460}
3657 2461
3658int 2462int
3659ahd_scb_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
3660{
3661 return (ahd_print_register(NULL, 0, "SCB_SPARE",
3662 0x1b0, regvalue, cur_col, wrap));
3663}
3664
3665int
3666ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap) 2463ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap)
3667{ 2464{
3668 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 2465 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS",
diff --git a/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped b/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped
index 11bed07e90b7..4b51e232392f 100644
--- a/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_seq.h_shipped
@@ -5,7 +5,7 @@
5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $ 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
7 */ 7 */
8static uint8_t seqprog[] = { 8static const uint8_t seqprog[] = {
9 0xff, 0x02, 0x06, 0x78, 9 0xff, 0x02, 0x06, 0x78,
10 0x00, 0xea, 0x6e, 0x59, 10 0x00, 0xea, 0x6e, 0x59,
11 0x01, 0xea, 0x04, 0x30, 11 0x01, 0xea, 0x04, 0x30,
@@ -1027,7 +1027,7 @@ ahd_patch0_func(struct ahd_softc *ahd)
1027 return (0); 1027 return (0);
1028} 1028}
1029 1029
1030static struct patch { 1030static const struct patch {
1031 ahd_patch_func_t *patch_func; 1031 ahd_patch_func_t *patch_func;
1032 uint32_t begin :10, 1032 uint32_t begin :10,
1033 skip_instr :10, 1033 skip_instr :10,
@@ -1166,7 +1166,7 @@ static struct patch {
1166 { ahd_patch23_func, 815, 11, 1 } 1166 { ahd_patch23_func, 815, 11, 1 }
1167}; 1167};
1168 1168
1169static struct cs { 1169static const struct cs {
1170 uint16_t begin; 1170 uint16_t begin;
1171 uint16_t end; 1171 uint16_t end;
1172} critical_sections[] = { 1172} critical_sections[] = {
diff --git a/drivers/scsi/aic7xxx/aic7xxx.h b/drivers/scsi/aic7xxx/aic7xxx.h
index c0344e617651..e4e651cca3e4 100644
--- a/drivers/scsi/aic7xxx/aic7xxx.h
+++ b/drivers/scsi/aic7xxx/aic7xxx.h
@@ -736,7 +736,7 @@ struct ahc_syncrate {
736#define ST_SXFR 0x010 /* Rate Single Transition Only */ 736#define ST_SXFR 0x010 /* Rate Single Transition Only */
737#define DT_SXFR 0x040 /* Rate Double Transition Only */ 737#define DT_SXFR 0x040 /* Rate Double Transition Only */
738 uint8_t period; /* Period to send to SCSI target */ 738 uint8_t period; /* Period to send to SCSI target */
739 char *rate; 739 const char *rate;
740}; 740};
741 741
742/* Safe and valid period for async negotiations. */ 742/* Safe and valid period for async negotiations. */
@@ -1114,7 +1114,7 @@ typedef int (ahc_device_setup_t)(struct ahc_softc *);
1114struct ahc_pci_identity { 1114struct ahc_pci_identity {
1115 uint64_t full_id; 1115 uint64_t full_id;
1116 uint64_t id_mask; 1116 uint64_t id_mask;
1117 char *name; 1117 const char *name;
1118 ahc_device_setup_t *setup; 1118 ahc_device_setup_t *setup;
1119}; 1119};
1120 1120
@@ -1133,15 +1133,11 @@ extern const int ahc_num_aic7770_devs;
1133 1133
1134/*************************** Function Declarations ****************************/ 1134/*************************** Function Declarations ****************************/
1135/******************************************************************************/ 1135/******************************************************************************/
1136u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
1137void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
1138void ahc_busy_tcl(struct ahc_softc *ahc,
1139 u_int tcl, u_int busyid);
1140 1136
1141/***************************** PCI Front End *********************************/ 1137/***************************** PCI Front End *********************************/
1142struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1138const struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t);
1143int ahc_pci_config(struct ahc_softc *, 1139int ahc_pci_config(struct ahc_softc *,
1144 struct ahc_pci_identity *); 1140 const struct ahc_pci_identity *);
1145int ahc_pci_test_register_access(struct ahc_softc *); 1141int ahc_pci_test_register_access(struct ahc_softc *);
1146#ifdef CONFIG_PM 1142#ifdef CONFIG_PM
1147void ahc_pci_resume(struct ahc_softc *ahc); 1143void ahc_pci_resume(struct ahc_softc *ahc);
@@ -1155,9 +1151,6 @@ int aic7770_config(struct ahc_softc *ahc,
1155 1151
1156/************************** SCB and SCB queue management **********************/ 1152/************************** SCB and SCB queue management **********************/
1157int ahc_probe_scbs(struct ahc_softc *); 1153int ahc_probe_scbs(struct ahc_softc *);
1158void ahc_run_untagged_queues(struct ahc_softc *ahc);
1159void ahc_run_untagged_queue(struct ahc_softc *ahc,
1160 struct scb_tailq *queue);
1161void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1154void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1162 struct scb *scb); 1155 struct scb *scb);
1163int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1156int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
@@ -1178,22 +1171,8 @@ int ahc_resume(struct ahc_softc *ahc);
1178#endif 1171#endif
1179void ahc_set_unit(struct ahc_softc *, int); 1172void ahc_set_unit(struct ahc_softc *, int);
1180void ahc_set_name(struct ahc_softc *, char *); 1173void ahc_set_name(struct ahc_softc *, char *);
1181void ahc_alloc_scbs(struct ahc_softc *ahc);
1182void ahc_free(struct ahc_softc *ahc); 1174void ahc_free(struct ahc_softc *ahc);
1183int ahc_reset(struct ahc_softc *ahc, int reinit); 1175int ahc_reset(struct ahc_softc *ahc, int reinit);
1184void ahc_shutdown(void *arg);
1185
1186/*************************** Interrupt Services *******************************/
1187void ahc_clear_intstat(struct ahc_softc *ahc);
1188void ahc_run_qoutfifo(struct ahc_softc *ahc);
1189#ifdef AHC_TARGET_MODE
1190void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
1191#endif
1192void ahc_handle_brkadrint(struct ahc_softc *ahc);
1193void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
1194void ahc_handle_scsiint(struct ahc_softc *ahc,
1195 u_int intstat);
1196void ahc_clear_critical_section(struct ahc_softc *ahc);
1197 1176
1198/***************************** Error Recovery *********************************/ 1177/***************************** Error Recovery *********************************/
1199typedef enum { 1178typedef enum {
@@ -1214,36 +1193,19 @@ int ahc_search_disc_list(struct ahc_softc *ahc, int target,
1214 char channel, int lun, u_int tag, 1193 char channel, int lun, u_int tag,
1215 int stop_on_first, int remove, 1194 int stop_on_first, int remove,
1216 int save_state); 1195 int save_state);
1217void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
1218int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1196int ahc_reset_channel(struct ahc_softc *ahc, char channel,
1219 int initiate_reset); 1197 int initiate_reset);
1220int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1198
1221 char channel, int lun, u_int tag,
1222 role_t role, uint32_t status);
1223void ahc_restart(struct ahc_softc *ahc);
1224void ahc_calc_residual(struct ahc_softc *ahc,
1225 struct scb *scb);
1226/*************************** Utility Functions ********************************/ 1199/*************************** Utility Functions ********************************/
1227struct ahc_phase_table_entry*
1228 ahc_lookup_phase_entry(int phase);
1229void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1200void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1230 u_int our_id, u_int target, 1201 u_int our_id, u_int target,
1231 u_int lun, char channel, 1202 u_int lun, char channel,
1232 role_t role); 1203 role_t role);
1233/************************** Transfer Negotiation ******************************/ 1204/************************** Transfer Negotiation ******************************/
1234struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1205const struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1235 u_int *ppr_options, u_int maxsync); 1206 u_int *ppr_options, u_int maxsync);
1236u_int ahc_find_period(struct ahc_softc *ahc, 1207u_int ahc_find_period(struct ahc_softc *ahc,
1237 u_int scsirate, u_int maxsync); 1208 u_int scsirate, u_int maxsync);
1238void ahc_validate_offset(struct ahc_softc *ahc,
1239 struct ahc_initiator_tinfo *tinfo,
1240 struct ahc_syncrate *syncrate,
1241 u_int *offset, int wide,
1242 role_t role);
1243void ahc_validate_width(struct ahc_softc *ahc,
1244 struct ahc_initiator_tinfo *tinfo,
1245 u_int *bus_width,
1246 role_t role);
1247/* 1209/*
1248 * Negotiation types. These are used to qualify if we should renegotiate 1210 * Negotiation types. These are used to qualify if we should renegotiate
1249 * even if our goal and current transport parameters are identical. 1211 * even if our goal and current transport parameters are identical.
@@ -1263,7 +1225,7 @@ void ahc_set_width(struct ahc_softc *ahc,
1263 u_int width, u_int type, int paused); 1225 u_int width, u_int type, int paused);
1264void ahc_set_syncrate(struct ahc_softc *ahc, 1226void ahc_set_syncrate(struct ahc_softc *ahc,
1265 struct ahc_devinfo *devinfo, 1227 struct ahc_devinfo *devinfo,
1266 struct ahc_syncrate *syncrate, 1228 const struct ahc_syncrate *syncrate,
1267 u_int period, u_int offset, 1229 u_int period, u_int offset,
1268 u_int ppr_options, 1230 u_int ppr_options,
1269 u_int type, int paused); 1231 u_int type, int paused);
@@ -1305,11 +1267,10 @@ extern uint32_t ahc_debug;
1305#define AHC_SHOW_MASKED_ERRORS 0x1000 1267#define AHC_SHOW_MASKED_ERRORS 0x1000
1306#define AHC_DEBUG_SEQUENCER 0x2000 1268#define AHC_DEBUG_SEQUENCER 0x2000
1307#endif 1269#endif
1308void ahc_print_scb(struct scb *scb);
1309void ahc_print_devinfo(struct ahc_softc *ahc, 1270void ahc_print_devinfo(struct ahc_softc *ahc,
1310 struct ahc_devinfo *dev); 1271 struct ahc_devinfo *dev);
1311void ahc_dump_card_state(struct ahc_softc *ahc); 1272void ahc_dump_card_state(struct ahc_softc *ahc);
1312int ahc_print_register(ahc_reg_parse_entry_t *table, 1273int ahc_print_register(const ahc_reg_parse_entry_t *table,
1313 u_int num_entries, 1274 u_int num_entries,
1314 const char *name, 1275 const char *name,
1315 u_int address, 1276 u_int address,
diff --git a/drivers/scsi/aic7xxx/aic7xxx.reg b/drivers/scsi/aic7xxx/aic7xxx.reg
index e196d83b93c7..0d2f763c3427 100644
--- a/drivers/scsi/aic7xxx/aic7xxx.reg
+++ b/drivers/scsi/aic7xxx/aic7xxx.reg
@@ -238,6 +238,7 @@ register SXFRCTL2 {
238register OPTIONMODE { 238register OPTIONMODE {
239 address 0x008 239 address 0x008
240 access_mode RW 240 access_mode RW
241 count 2
241 field AUTORATEEN 0x80 242 field AUTORATEEN 0x80
242 field AUTOACKEN 0x40 243 field AUTOACKEN 0x40
243 field ATNMGMNTEN 0x20 244 field ATNMGMNTEN 0x20
@@ -254,6 +255,7 @@ register TARGCRCCNT {
254 address 0x00a 255 address 0x00a
255 size 2 256 size 2
256 access_mode RW 257 access_mode RW
258 count 2
257} 259}
258 260
259/* 261/*
@@ -344,6 +346,7 @@ register SSTAT2 {
344register SSTAT3 { 346register SSTAT3 {
345 address 0x00e 347 address 0x00e
346 access_mode RO 348 access_mode RO
349 count 2
347 mask SCSICNT 0xf0 350 mask SCSICNT 0xf0
348 mask OFFCNT 0x0f 351 mask OFFCNT 0x0f
349 mask U2OFFCNT 0x7f 352 mask U2OFFCNT 0x7f
@@ -367,6 +370,7 @@ register SCSIID_ULTRA2 {
367register SIMODE0 { 370register SIMODE0 {
368 address 0x010 371 address 0x010
369 access_mode RW 372 access_mode RW
373 count 2
370 field ENSELDO 0x40 374 field ENSELDO 0x40
371 field ENSELDI 0x20 375 field ENSELDI 0x20
372 field ENSELINGO 0x10 376 field ENSELINGO 0x10
@@ -429,6 +433,7 @@ register SHADDR {
429register SELTIMER { 433register SELTIMER {
430 address 0x018 434 address 0x018
431 access_mode RW 435 access_mode RW
436 count 1
432 field STAGE6 0x20 437 field STAGE6 0x20
433 field STAGE5 0x10 438 field STAGE5 0x10
434 field STAGE4 0x08 439 field STAGE4 0x08
@@ -467,6 +472,7 @@ register TARGID {
467 address 0x01b 472 address 0x01b
468 size 2 473 size 2
469 access_mode RW 474 access_mode RW
475 count 14
470} 476}
471 477
472/* 478/*
@@ -480,6 +486,7 @@ register TARGID {
480register SPIOCAP { 486register SPIOCAP {
481 address 0x01b 487 address 0x01b
482 access_mode RW 488 access_mode RW
489 count 10
483 field SOFT1 0x80 490 field SOFT1 0x80
484 field SOFT0 0x40 491 field SOFT0 0x40
485 field SOFTCMDEN 0x20 492 field SOFTCMDEN 0x20
@@ -492,6 +499,7 @@ register SPIOCAP {
492 499
493register BRDCTL { 500register BRDCTL {
494 address 0x01d 501 address 0x01d
502 count 11
495 field BRDDAT7 0x80 503 field BRDDAT7 0x80
496 field BRDDAT6 0x40 504 field BRDDAT6 0x40
497 field BRDDAT5 0x20 505 field BRDDAT5 0x20
@@ -534,6 +542,7 @@ register BRDCTL {
534 */ 542 */
535register SEECTL { 543register SEECTL {
536 address 0x01e 544 address 0x01e
545 count 11
537 field EXTARBACK 0x80 546 field EXTARBACK 0x80
538 field EXTARBREQ 0x40 547 field EXTARBREQ 0x40
539 field SEEMS 0x20 548 field SEEMS 0x20
@@ -570,6 +579,7 @@ register SBLKCTL {
570register SEQCTL { 579register SEQCTL {
571 address 0x060 580 address 0x060
572 access_mode RW 581 access_mode RW
582 count 15
573 field PERRORDIS 0x80 583 field PERRORDIS 0x80
574 field PAUSEDIS 0x40 584 field PAUSEDIS 0x40
575 field FAILDIS 0x20 585 field FAILDIS 0x20
@@ -590,6 +600,7 @@ register SEQCTL {
590register SEQRAM { 600register SEQRAM {
591 address 0x061 601 address 0x061
592 access_mode RW 602 access_mode RW
603 count 2
593} 604}
594 605
595/* 606/*
@@ -604,6 +615,7 @@ register SEQADDR0 {
604register SEQADDR1 { 615register SEQADDR1 {
605 address 0x063 616 address 0x063
606 access_mode RW 617 access_mode RW
618 count 8
607 mask SEQADDR1_MASK 0x01 619 mask SEQADDR1_MASK 0x01
608} 620}
609 621
@@ -649,6 +661,7 @@ register NONE {
649register FLAGS { 661register FLAGS {
650 address 0x06b 662 address 0x06b
651 access_mode RO 663 access_mode RO
664 count 18
652 field ZERO 0x02 665 field ZERO 0x02
653 field CARRY 0x01 666 field CARRY 0x01
654} 667}
@@ -671,6 +684,7 @@ register FUNCTION1 {
671register STACK { 684register STACK {
672 address 0x06f 685 address 0x06f
673 access_mode RO 686 access_mode RO
687 count 5
674} 688}
675 689
676const STACK_SIZE 4 690const STACK_SIZE 4
@@ -692,6 +706,7 @@ register BCTL {
692register DSCOMMAND0 { 706register DSCOMMAND0 {
693 address 0x084 707 address 0x084
694 access_mode RW 708 access_mode RW
709 count 7
695 field CACHETHEN 0x80 /* Cache Threshold enable */ 710 field CACHETHEN 0x80 /* Cache Threshold enable */
696 field DPARCKEN 0x40 /* Data Parity Check Enable */ 711 field DPARCKEN 0x40 /* Data Parity Check Enable */
697 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 712 field MPARCKEN 0x20 /* Memory Parity Check Enable */
@@ -717,6 +732,7 @@ register DSCOMMAND1 {
717register BUSTIME { 732register BUSTIME {
718 address 0x085 733 address 0x085
719 access_mode RW 734 access_mode RW
735 count 2
720 mask BOFF 0xf0 736 mask BOFF 0xf0
721 mask BON 0x0f 737 mask BON 0x0f
722} 738}
@@ -727,6 +743,7 @@ register BUSTIME {
727register BUSSPD { 743register BUSSPD {
728 address 0x086 744 address 0x086
729 access_mode RW 745 access_mode RW
746 count 2
730 mask DFTHRSH 0xc0 747 mask DFTHRSH 0xc0
731 mask STBOFF 0x38 748 mask STBOFF 0x38
732 mask STBON 0x07 749 mask STBON 0x07
@@ -737,6 +754,7 @@ register BUSSPD {
737/* aic7850/55/60/70/80/95 only */ 754/* aic7850/55/60/70/80/95 only */
738register DSPCISTATUS { 755register DSPCISTATUS {
739 address 0x086 756 address 0x086
757 count 4
740 mask DFTHRSH_100 0xc0 758 mask DFTHRSH_100 0xc0
741} 759}
742 760
@@ -758,6 +776,7 @@ const SEQ_MAILBOX_SHIFT 0
758register HCNTRL { 776register HCNTRL {
759 address 0x087 777 address 0x087
760 access_mode RW 778 access_mode RW
779 count 14
761 field POWRDN 0x40 780 field POWRDN 0x40
762 field SWINT 0x10 781 field SWINT 0x10
763 field IRQMS 0x08 782 field IRQMS 0x08
@@ -869,6 +888,7 @@ register INTSTAT {
869register ERROR { 888register ERROR {
870 address 0x092 889 address 0x092
871 access_mode RO 890 access_mode RO
891 count 26
872 field CIOPARERR 0x80 /* Ultra2 only */ 892 field CIOPARERR 0x80 /* Ultra2 only */
873 field PCIERRSTAT 0x40 /* PCI only */ 893 field PCIERRSTAT 0x40 /* PCI only */
874 field MPARERR 0x20 /* PCI only */ 894 field MPARERR 0x20 /* PCI only */
@@ -885,6 +905,7 @@ register ERROR {
885register CLRINT { 905register CLRINT {
886 address 0x092 906 address 0x092
887 access_mode WO 907 access_mode WO
908 count 24
888 field CLRPARERR 0x10 /* PCI only */ 909 field CLRPARERR 0x10 /* PCI only */
889 field CLRBRKADRINT 0x08 910 field CLRBRKADRINT 0x08
890 field CLRSCSIINT 0x04 911 field CLRSCSIINT 0x04
@@ -943,6 +964,7 @@ register DFDAT {
943register SCBCNT { 964register SCBCNT {
944 address 0x09a 965 address 0x09a
945 access_mode RW 966 access_mode RW
967 count 1
946 field SCBAUTO 0x80 968 field SCBAUTO 0x80
947 mask SCBCNT_MASK 0x1f 969 mask SCBCNT_MASK 0x1f
948} 970}
@@ -954,6 +976,7 @@ register SCBCNT {
954register QINFIFO { 976register QINFIFO {
955 address 0x09b 977 address 0x09b
956 access_mode RW 978 access_mode RW
979 count 12
957} 980}
958 981
959/* 982/*
@@ -972,11 +995,13 @@ register QINCNT {
972register QOUTFIFO { 995register QOUTFIFO {
973 address 0x09d 996 address 0x09d
974 access_mode WO 997 access_mode WO
998 count 7
975} 999}
976 1000
977register CRCCONTROL1 { 1001register CRCCONTROL1 {
978 address 0x09d 1002 address 0x09d
979 access_mode RW 1003 access_mode RW
1004 count 3
980 field CRCONSEEN 0x80 1005 field CRCONSEEN 0x80
981 field CRCVALCHKEN 0x40 1006 field CRCVALCHKEN 0x40
982 field CRCENDCHKEN 0x20 1007 field CRCENDCHKEN 0x20
@@ -1013,6 +1038,7 @@ register SCSIPHASE {
1013register SFUNCT { 1038register SFUNCT {
1014 address 0x09f 1039 address 0x09f
1015 access_mode RW 1040 access_mode RW
1041 count 4
1016 field ALT_MODE 0x80 1042 field ALT_MODE 0x80
1017} 1043}
1018 1044
@@ -1095,6 +1121,7 @@ scb {
1095 } 1121 }
1096 SCB_SCSIOFFSET { 1122 SCB_SCSIOFFSET {
1097 size 1 1123 size 1
1124 count 1
1098 } 1125 }
1099 SCB_NEXT { 1126 SCB_NEXT {
1100 size 1 1127 size 1
@@ -1118,6 +1145,7 @@ const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
1118register SEECTL_2840 { 1145register SEECTL_2840 {
1119 address 0x0c0 1146 address 0x0c0
1120 access_mode RW 1147 access_mode RW
1148 count 2
1121 field CS_2840 0x04 1149 field CS_2840 0x04
1122 field CK_2840 0x02 1150 field CK_2840 0x02
1123 field DO_2840 0x01 1151 field DO_2840 0x01
@@ -1126,6 +1154,7 @@ register SEECTL_2840 {
1126register STATUS_2840 { 1154register STATUS_2840 {
1127 address 0x0c1 1155 address 0x0c1
1128 access_mode RW 1156 access_mode RW
1157 count 4
1129 field EEPROM_TF 0x80 1158 field EEPROM_TF 0x80
1130 mask BIOS_SEL 0x60 1159 mask BIOS_SEL 0x60
1131 mask ADSEL 0x1e 1160 mask ADSEL 0x1e
@@ -1161,6 +1190,7 @@ register CCSGCTL {
1161 1190
1162register CCSCBCNT { 1191register CCSCBCNT {
1163 address 0xEF 1192 address 0xEF
1193 count 1
1164} 1194}
1165 1195
1166register CCSCBCTL { 1196register CCSCBCTL {
@@ -1187,6 +1217,7 @@ register CCSCBRAM {
1187register SCBBADDR { 1217register SCBBADDR {
1188 address 0x0F0 1218 address 0x0F0
1189 access_mode RW 1219 access_mode RW
1220 count 3
1190} 1221}
1191 1222
1192register CCSCBPTR { 1223register CCSCBPTR {
@@ -1195,6 +1226,7 @@ register CCSCBPTR {
1195 1226
1196register HNSCB_QOFF { 1227register HNSCB_QOFF {
1197 address 0x0F4 1228 address 0x0F4
1229 count 4
1198} 1230}
1199 1231
1200register SNSCB_QOFF { 1232register SNSCB_QOFF {
@@ -1234,6 +1266,7 @@ register DFF_THRSH {
1234 mask WR_DFTHRSH_85 0x50 1266 mask WR_DFTHRSH_85 0x50
1235 mask WR_DFTHRSH_90 0x60 1267 mask WR_DFTHRSH_90 0x60
1236 mask WR_DFTHRSH_MAX 0x70 1268 mask WR_DFTHRSH_MAX 0x70
1269 count 4
1237} 1270}
1238 1271
1239register SG_CACHE_PRE { 1272register SG_CACHE_PRE {
@@ -1287,6 +1320,7 @@ scratch_ram {
1287 ULTRA_ENB { 1320 ULTRA_ENB {
1288 alias CMDSIZE_TABLE 1321 alias CMDSIZE_TABLE
1289 size 2 1322 size 2
1323 count 2
1290 } 1324 }
1291 /* 1325 /*
1292 * Bit vector of targets that have disconnection disabled as set by 1326 * Bit vector of targets that have disconnection disabled as set by
@@ -1296,6 +1330,7 @@ scratch_ram {
1296 */ 1330 */
1297 DISC_DSB { 1331 DISC_DSB {
1298 size 2 1332 size 2
1333 count 6
1299 } 1334 }
1300 CMDSIZE_TABLE_TAIL { 1335 CMDSIZE_TABLE_TAIL {
1301 size 4 1336 size 4
@@ -1323,6 +1358,7 @@ scratch_ram {
1323 /* Parameters for DMA Logic */ 1358 /* Parameters for DMA Logic */
1324 DMAPARAMS { 1359 DMAPARAMS {
1325 size 1 1360 size 1
1361 count 12
1326 field PRELOADEN 0x80 1362 field PRELOADEN 0x80
1327 field WIDEODD 0x40 1363 field WIDEODD 0x40
1328 field SCSIEN 0x20 1364 field SCSIEN 0x20
@@ -1436,11 +1472,12 @@ scratch_ram {
1436 KERNEL_TQINPOS { 1472 KERNEL_TQINPOS {
1437 size 1 1473 size 1
1438 } 1474 }
1439 TQINPOS { 1475 TQINPOS {
1440 size 1 1476 size 1
1441 } 1477 }
1442 ARG_1 { 1478 ARG_1 {
1443 size 1 1479 size 1
1480 count 1
1444 mask SEND_MSG 0x80 1481 mask SEND_MSG 0x80
1445 mask SEND_SENSE 0x40 1482 mask SEND_SENSE 0x40
1446 mask SEND_REJ 0x20 1483 mask SEND_REJ 0x20
@@ -1495,6 +1532,7 @@ scratch_ram {
1495 size 1 1532 size 1
1496 field HA_274_EXTENDED_TRANS 0x01 1533 field HA_274_EXTENDED_TRANS 0x01
1497 alias INITIATOR_TAG 1534 alias INITIATOR_TAG
1535 count 1
1498 } 1536 }
1499 1537
1500 SEQ_FLAGS2 { 1538 SEQ_FLAGS2 {
@@ -1518,6 +1556,7 @@ scratch_ram {
1518 */ 1556 */
1519 SCSICONF { 1557 SCSICONF {
1520 size 1 1558 size 1
1559 count 12
1521 field TERM_ENB 0x80 1560 field TERM_ENB 0x80
1522 field RESET_SCSI 0x40 1561 field RESET_SCSI 0x40
1523 field ENSPCHK 0x20 1562 field ENSPCHK 0x20
@@ -1527,16 +1566,19 @@ scratch_ram {
1527 INTDEF { 1566 INTDEF {
1528 address 0x05c 1567 address 0x05c
1529 size 1 1568 size 1
1569 count 1
1530 field EDGE_TRIG 0x80 1570 field EDGE_TRIG 0x80
1531 mask VECTOR 0x0f 1571 mask VECTOR 0x0f
1532 } 1572 }
1533 HOSTCONF { 1573 HOSTCONF {
1534 address 0x05d 1574 address 0x05d
1535 size 1 1575 size 1
1576 count 1
1536 } 1577 }
1537 HA_274_BIOSCTRL { 1578 HA_274_BIOSCTRL {
1538 address 0x05f 1579 address 0x05f
1539 size 1 1580 size 1
1581 count 1
1540 mask BIOSMODE 0x30 1582 mask BIOSMODE 0x30
1541 mask BIOSDISABLED 0x30 1583 mask BIOSDISABLED 0x30
1542 field CHANNEL_B_PRIMARY 0x08 1584 field CHANNEL_B_PRIMARY 0x08
@@ -1552,6 +1594,7 @@ scratch_ram {
1552 */ 1594 */
1553 TARG_OFFSET { 1595 TARG_OFFSET {
1554 size 16 1596 size 16
1597 count 1
1555 } 1598 }
1556} 1599}
1557 1600
diff --git a/drivers/scsi/aic7xxx/aic7xxx_93cx6.c b/drivers/scsi/aic7xxx/aic7xxx_93cx6.c
index 3cb07e114e89..dd11999b77b6 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_93cx6.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_93cx6.c
@@ -84,16 +84,16 @@ struct seeprom_cmd {
84}; 84};
85 85
86/* Short opcodes for the c46 */ 86/* Short opcodes for the c46 */
87static struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}}; 87static const struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
88static struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}}; 88static const struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
89 89
90/* Long opcodes for the C56/C66 */ 90/* Long opcodes for the C56/C66 */
91static struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}}; 91static const struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
92static struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}}; 92static const struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
93 93
94/* Common opcodes */ 94/* Common opcodes */
95static struct seeprom_cmd seeprom_write = {3, {1, 0, 1}}; 95static const struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
96static struct seeprom_cmd seeprom_read = {3, {1, 1, 0}}; 96static const struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
97 97
98/* 98/*
99 * Wait for the SEERDY to go high; about 800 ns. 99 * Wait for the SEERDY to go high; about 800 ns.
@@ -108,7 +108,7 @@ static struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
108 * Send a START condition and the given command 108 * Send a START condition and the given command
109 */ 109 */
110static void 110static void
111send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd) 111send_seeprom_cmd(struct seeprom_descriptor *sd, const struct seeprom_cmd *cmd)
112{ 112{
113 uint8_t temp; 113 uint8_t temp;
114 int i = 0; 114 int i = 0;
@@ -227,7 +227,7 @@ int
227ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, 227ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
228 u_int start_addr, u_int count) 228 u_int start_addr, u_int count)
229{ 229{
230 struct seeprom_cmd *ewen, *ewds; 230 const struct seeprom_cmd *ewen, *ewds;
231 uint16_t v; 231 uint16_t v;
232 uint8_t temp; 232 uint8_t temp;
233 int i, k; 233 int i, k;
diff --git a/drivers/scsi/aic7xxx/aic7xxx_core.c b/drivers/scsi/aic7xxx/aic7xxx_core.c
index 64e62ce59c15..0ae2b4605d09 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_core.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_core.c
@@ -51,8 +51,7 @@
51#endif 51#endif
52 52
53/***************************** Lookup Tables **********************************/ 53/***************************** Lookup Tables **********************************/
54char *ahc_chip_names[] = 54static const char *const ahc_chip_names[] = {
55{
56 "NONE", 55 "NONE",
57 "aic7770", 56 "aic7770",
58 "aic7850", 57 "aic7850",
@@ -75,10 +74,10 @@ static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names);
75 */ 74 */
76struct ahc_hard_error_entry { 75struct ahc_hard_error_entry {
77 uint8_t errno; 76 uint8_t errno;
78 char *errmesg; 77 const char *errmesg;
79}; 78};
80 79
81static struct ahc_hard_error_entry ahc_hard_errors[] = { 80static const struct ahc_hard_error_entry ahc_hard_errors[] = {
82 { ILLHADDR, "Illegal Host Access" }, 81 { ILLHADDR, "Illegal Host Access" },
83 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 82 { ILLSADDR, "Illegal Sequencer Address referrenced" },
84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 83 { ILLOPCODE, "Illegal Opcode in sequencer program" },
@@ -90,7 +89,7 @@ static struct ahc_hard_error_entry ahc_hard_errors[] = {
90}; 89};
91static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors); 90static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
92 91
93static struct ahc_phase_table_entry ahc_phase_table[] = 92static const struct ahc_phase_table_entry ahc_phase_table[] =
94{ 93{
95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 94 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 95 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
@@ -115,7 +114,7 @@ static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
115 * Provides a mapping of tranfer periods in ns to the proper value to 114 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg. 115 * stick in the scsixfer reg.
117 */ 116 */
118static struct ahc_syncrate ahc_syncrates[] = 117static const struct ahc_syncrate ahc_syncrates[] =
119{ 118{
120 /* ultra2 fast/ultra period rate */ 119 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" }, 120 { 0x42, 0x000, 9, "80.0" },
@@ -148,7 +147,7 @@ static struct ahc_tmode_tstate*
148static void ahc_free_tstate(struct ahc_softc *ahc, 147static void ahc_free_tstate(struct ahc_softc *ahc,
149 u_int scsi_id, char channel, int force); 148 u_int scsi_id, char channel, int force);
150#endif 149#endif
151static struct ahc_syncrate* 150static const struct ahc_syncrate*
152 ahc_devlimited_syncrate(struct ahc_softc *ahc, 151 ahc_devlimited_syncrate(struct ahc_softc *ahc,
153 struct ahc_initiator_tinfo *, 152 struct ahc_initiator_tinfo *,
154 u_int *period, 153 u_int *period,
@@ -204,9 +203,9 @@ static void ahc_setup_target_msgin(struct ahc_softc *ahc,
204#endif 203#endif
205 204
206static bus_dmamap_callback_t ahc_dmamap_cb; 205static bus_dmamap_callback_t ahc_dmamap_cb;
207static void ahc_build_free_scb_list(struct ahc_softc *ahc); 206static void ahc_build_free_scb_list(struct ahc_softc *ahc);
208static int ahc_init_scbdata(struct ahc_softc *ahc); 207static int ahc_init_scbdata(struct ahc_softc *ahc);
209static void ahc_fini_scbdata(struct ahc_softc *ahc); 208static void ahc_fini_scbdata(struct ahc_softc *ahc);
210static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 209static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
211 struct scb *prev_scb, 210 struct scb *prev_scb,
212 struct scb *scb); 211 struct scb *scb);
@@ -222,7 +221,7 @@ static void ahc_dumpseq(struct ahc_softc *ahc);
222#endif 221#endif
223static int ahc_loadseq(struct ahc_softc *ahc); 222static int ahc_loadseq(struct ahc_softc *ahc);
224static int ahc_check_patch(struct ahc_softc *ahc, 223static int ahc_check_patch(struct ahc_softc *ahc,
225 struct patch **start_patch, 224 const struct patch **start_patch,
226 u_int start_instr, u_int *skip_addr); 225 u_int start_instr, u_int *skip_addr);
227static void ahc_download_instr(struct ahc_softc *ahc, 226static void ahc_download_instr(struct ahc_softc *ahc,
228 u_int instrptr, uint8_t *dconsts); 227 u_int instrptr, uint8_t *dconsts);
@@ -237,11 +236,582 @@ static void ahc_update_scsiid(struct ahc_softc *ahc,
237static int ahc_handle_target_cmd(struct ahc_softc *ahc, 236static int ahc_handle_target_cmd(struct ahc_softc *ahc,
238 struct target_cmd *cmd); 237 struct target_cmd *cmd);
239#endif 238#endif
239
240static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
241static void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
242static void ahc_busy_tcl(struct ahc_softc *ahc,
243 u_int tcl, u_int busyid);
244
245/************************** SCB and SCB queue management **********************/
246static void ahc_run_untagged_queues(struct ahc_softc *ahc);
247static void ahc_run_untagged_queue(struct ahc_softc *ahc,
248 struct scb_tailq *queue);
249
250/****************************** Initialization ********************************/
251static void ahc_alloc_scbs(struct ahc_softc *ahc);
252static void ahc_shutdown(void *arg);
253
254/*************************** Interrupt Services *******************************/
255static void ahc_clear_intstat(struct ahc_softc *ahc);
256static void ahc_run_qoutfifo(struct ahc_softc *ahc);
257#ifdef AHC_TARGET_MODE
258static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
259#endif
260static void ahc_handle_brkadrint(struct ahc_softc *ahc);
261static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
262static void ahc_handle_scsiint(struct ahc_softc *ahc,
263 u_int intstat);
264static void ahc_clear_critical_section(struct ahc_softc *ahc);
265
266/***************************** Error Recovery *********************************/
267static void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
268static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
269 char channel, int lun, u_int tag,
270 role_t role, uint32_t status);
271static void ahc_calc_residual(struct ahc_softc *ahc,
272 struct scb *scb);
273
274/*********************** Untagged Transaction Routines ************************/
275static inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
276static inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
277
278/*
279 * Block our completion routine from starting the next untagged
280 * transaction for this target or target lun.
281 */
282static inline void
283ahc_freeze_untagged_queues(struct ahc_softc *ahc)
284{
285 if ((ahc->flags & AHC_SCB_BTT) == 0)
286 ahc->untagged_queue_lock++;
287}
288
289/*
290 * Allow the next untagged transaction for this target or target lun
291 * to be executed. We use a counting semaphore to allow the lock
292 * to be acquired recursively. Once the count drops to zero, the
293 * transaction queues will be run.
294 */
295static inline void
296ahc_release_untagged_queues(struct ahc_softc *ahc)
297{
298 if ((ahc->flags & AHC_SCB_BTT) == 0) {
299 ahc->untagged_queue_lock--;
300 if (ahc->untagged_queue_lock == 0)
301 ahc_run_untagged_queues(ahc);
302 }
303}
304
240/************************* Sequencer Execution Control ************************/ 305/************************* Sequencer Execution Control ************************/
241/* 306/*
242 * Restart the sequencer program from address zero 307 * Work around any chip bugs related to halting sequencer execution.
308 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
309 * reading a register that will set this signal and deassert it.
310 * Without this workaround, if the chip is paused, by an interrupt or
311 * manual pause while accessing scb ram, accesses to certain registers
312 * will hang the system (infinite pci retries).
313 */
314static void
315ahc_pause_bug_fix(struct ahc_softc *ahc)
316{
317 if ((ahc->features & AHC_ULTRA2) != 0)
318 (void)ahc_inb(ahc, CCSCBCTL);
319}
320
321/*
322 * Determine whether the sequencer has halted code execution.
323 * Returns non-zero status if the sequencer is stopped.
324 */
325int
326ahc_is_paused(struct ahc_softc *ahc)
327{
328 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
329}
330
331/*
332 * Request that the sequencer stop and wait, indefinitely, for it
333 * to stop. The sequencer will only acknowledge that it is paused
334 * once it has reached an instruction boundary and PAUSEDIS is
335 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
336 * for critical sections.
337 */
338void
339ahc_pause(struct ahc_softc *ahc)
340{
341 ahc_outb(ahc, HCNTRL, ahc->pause);
342
343 /*
344 * Since the sequencer can disable pausing in a critical section, we
345 * must loop until it actually stops.
346 */
347 while (ahc_is_paused(ahc) == 0)
348 ;
349
350 ahc_pause_bug_fix(ahc);
351}
352
353/*
354 * Allow the sequencer to continue program execution.
355 * We check here to ensure that no additional interrupt
356 * sources that would cause the sequencer to halt have been
357 * asserted. If, for example, a SCSI bus reset is detected
358 * while we are fielding a different, pausing, interrupt type,
359 * we don't want to release the sequencer before going back
360 * into our interrupt handler and dealing with this new
361 * condition.
362 */
363void
364ahc_unpause(struct ahc_softc *ahc)
365{
366 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
367 ahc_outb(ahc, HCNTRL, ahc->unpause);
368}
369
370/************************** Memory mapping routines ***************************/
371static struct ahc_dma_seg *
372ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
373{
374 int sg_index;
375
376 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
377 /* sg_list_phys points to entry 1, not 0 */
378 sg_index++;
379
380 return (&scb->sg_list[sg_index]);
381}
382
383static uint32_t
384ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
385{
386 int sg_index;
387
388 /* sg_list_phys points to entry 1, not 0 */
389 sg_index = sg - &scb->sg_list[1];
390
391 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
392}
393
394static uint32_t
395ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
396{
397 return (ahc->scb_data->hscb_busaddr
398 + (sizeof(struct hardware_scb) * index));
399}
400
401static void
402ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
403{
404 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
405 ahc->scb_data->hscb_dmamap,
406 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
407 /*len*/sizeof(*scb->hscb), op);
408}
409
410void
411ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
412{
413 if (scb->sg_count == 0)
414 return;
415
416 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
417 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
418 * sizeof(struct ahc_dma_seg),
419 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
420}
421
422#ifdef AHC_TARGET_MODE
423static uint32_t
424ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
425{
426 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
427}
428#endif
429
430/*********************** Miscelaneous Support Functions ***********************/
431/*
432 * Determine whether the sequencer reported a residual
433 * for this SCB/transaction.
434 */
435static void
436ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
437{
438 uint32_t sgptr;
439
440 sgptr = ahc_le32toh(scb->hscb->sgptr);
441 if ((sgptr & SG_RESID_VALID) != 0)
442 ahc_calc_residual(ahc, scb);
443}
444
445/*
446 * Return pointers to the transfer negotiation information
447 * for the specified our_id/remote_id pair.
448 */
449struct ahc_initiator_tinfo *
450ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
451 u_int remote_id, struct ahc_tmode_tstate **tstate)
452{
453 /*
454 * Transfer data structures are stored from the perspective
455 * of the target role. Since the parameters for a connection
456 * in the initiator role to a given target are the same as
457 * when the roles are reversed, we pretend we are the target.
458 */
459 if (channel == 'B')
460 our_id += 8;
461 *tstate = ahc->enabled_targets[our_id];
462 return (&(*tstate)->transinfo[remote_id]);
463}
464
465uint16_t
466ahc_inw(struct ahc_softc *ahc, u_int port)
467{
468 uint16_t r = ahc_inb(ahc, port+1) << 8;
469 return r | ahc_inb(ahc, port);
470}
471
472void
473ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
474{
475 ahc_outb(ahc, port, value & 0xFF);
476 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
477}
478
479uint32_t
480ahc_inl(struct ahc_softc *ahc, u_int port)
481{
482 return ((ahc_inb(ahc, port))
483 | (ahc_inb(ahc, port+1) << 8)
484 | (ahc_inb(ahc, port+2) << 16)
485 | (ahc_inb(ahc, port+3) << 24));
486}
487
488void
489ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
490{
491 ahc_outb(ahc, port, (value) & 0xFF);
492 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
493 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
494 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
495}
496
497uint64_t
498ahc_inq(struct ahc_softc *ahc, u_int port)
499{
500 return ((ahc_inb(ahc, port))
501 | (ahc_inb(ahc, port+1) << 8)
502 | (ahc_inb(ahc, port+2) << 16)
503 | (ahc_inb(ahc, port+3) << 24)
504 | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
505 | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
506 | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
507 | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
508}
509
510void
511ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
512{
513 ahc_outb(ahc, port, value & 0xFF);
514 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
515 ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
516 ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
517 ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
518 ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
519 ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
520 ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
521}
522
523/*
524 * Get a free scb. If there are none, see if we can allocate a new SCB.
525 */
526struct scb *
527ahc_get_scb(struct ahc_softc *ahc)
528{
529 struct scb *scb;
530
531 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
532 ahc_alloc_scbs(ahc);
533 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
534 if (scb == NULL)
535 return (NULL);
536 }
537 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
538 return (scb);
539}
540
541/*
542 * Return an SCB resource to the free list.
543 */
544void
545ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
546{
547 struct hardware_scb *hscb;
548
549 hscb = scb->hscb;
550 /* Clean up for the next user */
551 ahc->scb_data->scbindex[hscb->tag] = NULL;
552 scb->flags = SCB_FREE;
553 hscb->control = 0;
554
555 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
556
557 /* Notify the OSM that a resource is now available. */
558 ahc_platform_scb_free(ahc, scb);
559}
560
561struct scb *
562ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
563{
564 struct scb* scb;
565
566 scb = ahc->scb_data->scbindex[tag];
567 if (scb != NULL)
568 ahc_sync_scb(ahc, scb,
569 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
570 return (scb);
571}
572
573static void
574ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
575{
576 struct hardware_scb *q_hscb;
577 u_int saved_tag;
578
579 /*
580 * Our queuing method is a bit tricky. The card
581 * knows in advance which HSCB to download, and we
582 * can't disappoint it. To achieve this, the next
583 * SCB to download is saved off in ahc->next_queued_scb.
584 * When we are called to queue "an arbitrary scb",
585 * we copy the contents of the incoming HSCB to the one
586 * the sequencer knows about, swap HSCB pointers and
587 * finally assign the SCB to the tag indexed location
588 * in the scb_array. This makes sure that we can still
589 * locate the correct SCB by SCB_TAG.
590 */
591 q_hscb = ahc->next_queued_scb->hscb;
592 saved_tag = q_hscb->tag;
593 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
594 if ((scb->flags & SCB_CDB32_PTR) != 0) {
595 q_hscb->shared_data.cdb_ptr =
596 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
597 + offsetof(struct hardware_scb, cdb32));
598 }
599 q_hscb->tag = saved_tag;
600 q_hscb->next = scb->hscb->tag;
601
602 /* Now swap HSCB pointers. */
603 ahc->next_queued_scb->hscb = scb->hscb;
604 scb->hscb = q_hscb;
605
606 /* Now define the mapping from tag to SCB in the scbindex */
607 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
608}
609
610/*
611 * Tell the sequencer about a new transaction to execute.
243 */ 612 */
244void 613void
614ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
615{
616 ahc_swap_with_next_hscb(ahc, scb);
617
618 if (scb->hscb->tag == SCB_LIST_NULL
619 || scb->hscb->next == SCB_LIST_NULL)
620 panic("Attempt to queue invalid SCB tag %x:%x\n",
621 scb->hscb->tag, scb->hscb->next);
622
623 /*
624 * Setup data "oddness".
625 */
626 scb->hscb->lun &= LID;
627 if (ahc_get_transfer_length(scb) & 0x1)
628 scb->hscb->lun |= SCB_XFERLEN_ODD;
629
630 /*
631 * Keep a history of SCBs we've downloaded in the qinfifo.
632 */
633 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
634
635 /*
636 * Make sure our data is consistent from the
637 * perspective of the adapter.
638 */
639 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
640
641 /* Tell the adapter about the newly queued SCB */
642 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
643 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
644 } else {
645 if ((ahc->features & AHC_AUTOPAUSE) == 0)
646 ahc_pause(ahc);
647 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
648 if ((ahc->features & AHC_AUTOPAUSE) == 0)
649 ahc_unpause(ahc);
650 }
651}
652
653struct scsi_sense_data *
654ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
655{
656 int offset;
657
658 offset = scb - ahc->scb_data->scbarray;
659 return (&ahc->scb_data->sense[offset]);
660}
661
662static uint32_t
663ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
664{
665 int offset;
666
667 offset = scb - ahc->scb_data->scbarray;
668 return (ahc->scb_data->sense_busaddr
669 + (offset * sizeof(struct scsi_sense_data)));
670}
671
672/************************** Interrupt Processing ******************************/
673static void
674ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
675{
676 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
677 /*offset*/0, /*len*/256, op);
678}
679
680static void
681ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
682{
683#ifdef AHC_TARGET_MODE
684 if ((ahc->flags & AHC_TARGETROLE) != 0) {
685 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
686 ahc->shared_data_dmamap,
687 ahc_targetcmd_offset(ahc, 0),
688 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
689 op);
690 }
691#endif
692}
693
694/*
695 * See if the firmware has posted any completed commands
696 * into our in-core command complete fifos.
697 */
698#define AHC_RUN_QOUTFIFO 0x1
699#define AHC_RUN_TQINFIFO 0x2
700static u_int
701ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
702{
703 u_int retval;
704
705 retval = 0;
706 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
707 /*offset*/ahc->qoutfifonext, /*len*/1,
708 BUS_DMASYNC_POSTREAD);
709 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
710 retval |= AHC_RUN_QOUTFIFO;
711#ifdef AHC_TARGET_MODE
712 if ((ahc->flags & AHC_TARGETROLE) != 0
713 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
714 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
715 ahc->shared_data_dmamap,
716 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
717 /*len*/sizeof(struct target_cmd),
718 BUS_DMASYNC_POSTREAD);
719 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
720 retval |= AHC_RUN_TQINFIFO;
721 }
722#endif
723 return (retval);
724}
725
726/*
727 * Catch an interrupt from the adapter
728 */
729int
730ahc_intr(struct ahc_softc *ahc)
731{
732 u_int intstat;
733
734 if ((ahc->pause & INTEN) == 0) {
735 /*
736 * Our interrupt is not enabled on the chip
737 * and may be disabled for re-entrancy reasons,
738 * so just return. This is likely just a shared
739 * interrupt.
740 */
741 return (0);
742 }
743 /*
744 * Instead of directly reading the interrupt status register,
745 * infer the cause of the interrupt by checking our in-core
746 * completion queues. This avoids a costly PCI bus read in
747 * most cases.
748 */
749 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
750 && (ahc_check_cmdcmpltqueues(ahc) != 0))
751 intstat = CMDCMPLT;
752 else {
753 intstat = ahc_inb(ahc, INTSTAT);
754 }
755
756 if ((intstat & INT_PEND) == 0) {
757#if AHC_PCI_CONFIG > 0
758 if (ahc->unsolicited_ints > 500) {
759 ahc->unsolicited_ints = 0;
760 if ((ahc->chip & AHC_PCI) != 0
761 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
762 ahc->bus_intr(ahc);
763 }
764#endif
765 ahc->unsolicited_ints++;
766 return (0);
767 }
768 ahc->unsolicited_ints = 0;
769
770 if (intstat & CMDCMPLT) {
771 ahc_outb(ahc, CLRINT, CLRCMDINT);
772
773 /*
774 * Ensure that the chip sees that we've cleared
775 * this interrupt before we walk the output fifo.
776 * Otherwise, we may, due to posted bus writes,
777 * clear the interrupt after we finish the scan,
778 * and after the sequencer has added new entries
779 * and asserted the interrupt again.
780 */
781 ahc_flush_device_writes(ahc);
782 ahc_run_qoutfifo(ahc);
783#ifdef AHC_TARGET_MODE
784 if ((ahc->flags & AHC_TARGETROLE) != 0)
785 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
786#endif
787 }
788
789 /*
790 * Handle statuses that may invalidate our cached
791 * copy of INTSTAT separately.
792 */
793 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
794 /* Hot eject. Do nothing */
795 } else if (intstat & BRKADRINT) {
796 ahc_handle_brkadrint(ahc);
797 } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
798
799 ahc_pause_bug_fix(ahc);
800
801 if ((intstat & SEQINT) != 0)
802 ahc_handle_seqint(ahc, intstat);
803
804 if ((intstat & SCSIINT) != 0)
805 ahc_handle_scsiint(ahc, intstat);
806 }
807 return (1);
808}
809
810/************************* Sequencer Execution Control ************************/
811/*
812 * Restart the sequencer program from address zero
813 */
814static void
245ahc_restart(struct ahc_softc *ahc) 815ahc_restart(struct ahc_softc *ahc)
246{ 816{
247 817
@@ -302,7 +872,7 @@ ahc_restart(struct ahc_softc *ahc)
302} 872}
303 873
304/************************* Input/Output Queues ********************************/ 874/************************* Input/Output Queues ********************************/
305void 875static void
306ahc_run_qoutfifo(struct ahc_softc *ahc) 876ahc_run_qoutfifo(struct ahc_softc *ahc)
307{ 877{
308 struct scb *scb; 878 struct scb *scb;
@@ -349,7 +919,7 @@ ahc_run_qoutfifo(struct ahc_softc *ahc)
349 } 919 }
350} 920}
351 921
352void 922static void
353ahc_run_untagged_queues(struct ahc_softc *ahc) 923ahc_run_untagged_queues(struct ahc_softc *ahc)
354{ 924{
355 int i; 925 int i;
@@ -358,7 +928,7 @@ ahc_run_untagged_queues(struct ahc_softc *ahc)
358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 928 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
359} 929}
360 930
361void 931static void
362ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 932ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
363{ 933{
364 struct scb *scb; 934 struct scb *scb;
@@ -374,7 +944,7 @@ ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
374} 944}
375 945
376/************************* Interrupt Handling *********************************/ 946/************************* Interrupt Handling *********************************/
377void 947static void
378ahc_handle_brkadrint(struct ahc_softc *ahc) 948ahc_handle_brkadrint(struct ahc_softc *ahc)
379{ 949{
380 /* 950 /*
@@ -403,7 +973,7 @@ ahc_handle_brkadrint(struct ahc_softc *ahc)
403 ahc_shutdown(ahc); 973 ahc_shutdown(ahc);
404} 974}
405 975
406void 976static void
407ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 977ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
408{ 978{
409 struct scb *scb; 979 struct scb *scb;
@@ -954,7 +1524,7 @@ unpause:
954 ahc_unpause(ahc); 1524 ahc_unpause(ahc);
955} 1525}
956 1526
957void 1527static void
958ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 1528ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
959{ 1529{
960 u_int scb_index; 1530 u_int scb_index;
@@ -1407,7 +1977,7 @@ ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1407} 1977}
1408 1978
1409#define AHC_MAX_STEPS 2000 1979#define AHC_MAX_STEPS 2000
1410void 1980static void
1411ahc_clear_critical_section(struct ahc_softc *ahc) 1981ahc_clear_critical_section(struct ahc_softc *ahc)
1412{ 1982{
1413 int stepping; 1983 int stepping;
@@ -1500,7 +2070,7 @@ ahc_clear_critical_section(struct ahc_softc *ahc)
1500/* 2070/*
1501 * Clear any pending interrupt status. 2071 * Clear any pending interrupt status.
1502 */ 2072 */
1503void 2073static void
1504ahc_clear_intstat(struct ahc_softc *ahc) 2074ahc_clear_intstat(struct ahc_softc *ahc)
1505{ 2075{
1506 /* Clear any interrupt conditions this may have caused */ 2076 /* Clear any interrupt conditions this may have caused */
@@ -1519,7 +2089,8 @@ ahc_clear_intstat(struct ahc_softc *ahc)
1519uint32_t ahc_debug = AHC_DEBUG_OPTS; 2089uint32_t ahc_debug = AHC_DEBUG_OPTS;
1520#endif 2090#endif
1521 2091
1522void 2092#if 0 /* unused */
2093static void
1523ahc_print_scb(struct scb *scb) 2094ahc_print_scb(struct scb *scb)
1524{ 2095{
1525 int i; 2096 int i;
@@ -1551,6 +2122,7 @@ ahc_print_scb(struct scb *scb)
1551 } 2122 }
1552 } 2123 }
1553} 2124}
2125#endif
1554 2126
1555/************************* Transfer Negotiation *******************************/ 2127/************************* Transfer Negotiation *******************************/
1556/* 2128/*
@@ -1634,7 +2206,7 @@ ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1634 * by the capabilities of the bus connectivity of and sync settings for 2206 * by the capabilities of the bus connectivity of and sync settings for
1635 * the target. 2207 * the target.
1636 */ 2208 */
1637struct ahc_syncrate * 2209const struct ahc_syncrate *
1638ahc_devlimited_syncrate(struct ahc_softc *ahc, 2210ahc_devlimited_syncrate(struct ahc_softc *ahc,
1639 struct ahc_initiator_tinfo *tinfo, 2211 struct ahc_initiator_tinfo *tinfo,
1640 u_int *period, u_int *ppr_options, role_t role) 2212 u_int *period, u_int *ppr_options, role_t role)
@@ -1689,11 +2261,11 @@ ahc_devlimited_syncrate(struct ahc_softc *ahc,
1689 * Return the period and offset that should be sent to the target 2261 * Return the period and offset that should be sent to the target
1690 * if this was the beginning of an SDTR. 2262 * if this was the beginning of an SDTR.
1691 */ 2263 */
1692struct ahc_syncrate * 2264const struct ahc_syncrate *
1693ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 2265ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1694 u_int *ppr_options, u_int maxsync) 2266 u_int *ppr_options, u_int maxsync)
1695{ 2267{
1696 struct ahc_syncrate *syncrate; 2268 const struct ahc_syncrate *syncrate;
1697 2269
1698 if ((ahc->features & AHC_DT) == 0) 2270 if ((ahc->features & AHC_DT) == 0)
1699 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2271 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
@@ -1768,7 +2340,7 @@ ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1768u_int 2340u_int
1769ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 2341ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1770{ 2342{
1771 struct ahc_syncrate *syncrate; 2343 const struct ahc_syncrate *syncrate;
1772 2344
1773 if ((ahc->features & AHC_ULTRA2) != 0) 2345 if ((ahc->features & AHC_ULTRA2) != 0)
1774 scsirate &= SXFR_ULTRA2; 2346 scsirate &= SXFR_ULTRA2;
@@ -1806,10 +2378,10 @@ ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1806 * Truncate the given synchronous offset to a value the 2378 * Truncate the given synchronous offset to a value the
1807 * current adapter type and syncrate are capable of. 2379 * current adapter type and syncrate are capable of.
1808 */ 2380 */
1809void 2381static void
1810ahc_validate_offset(struct ahc_softc *ahc, 2382ahc_validate_offset(struct ahc_softc *ahc,
1811 struct ahc_initiator_tinfo *tinfo, 2383 struct ahc_initiator_tinfo *tinfo,
1812 struct ahc_syncrate *syncrate, 2384 const struct ahc_syncrate *syncrate,
1813 u_int *offset, int wide, role_t role) 2385 u_int *offset, int wide, role_t role)
1814{ 2386{
1815 u_int maxoffset; 2387 u_int maxoffset;
@@ -1838,7 +2410,7 @@ ahc_validate_offset(struct ahc_softc *ahc,
1838 * Truncate the given transfer width parameter to a value the 2410 * Truncate the given transfer width parameter to a value the
1839 * current adapter type is capable of. 2411 * current adapter type is capable of.
1840 */ 2412 */
1841void 2413static void
1842ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 2414ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1843 u_int *bus_width, role_t role) 2415 u_int *bus_width, role_t role)
1844{ 2416{
@@ -1913,7 +2485,7 @@ ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1913 */ 2485 */
1914void 2486void
1915ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2487ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1916 struct ahc_syncrate *syncrate, u_int period, 2488 const struct ahc_syncrate *syncrate, u_int period,
1917 u_int offset, u_int ppr_options, u_int type, int paused) 2489 u_int offset, u_int ppr_options, u_int type, int paused)
1918{ 2490{
1919 struct ahc_initiator_tinfo *tinfo; 2491 struct ahc_initiator_tinfo *tinfo;
@@ -2220,11 +2792,11 @@ ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2220 role); 2792 role);
2221} 2793}
2222 2794
2223struct ahc_phase_table_entry* 2795static const struct ahc_phase_table_entry*
2224ahc_lookup_phase_entry(int phase) 2796ahc_lookup_phase_entry(int phase)
2225{ 2797{
2226 struct ahc_phase_table_entry *entry; 2798 const struct ahc_phase_table_entry *entry;
2227 struct ahc_phase_table_entry *last_entry; 2799 const struct ahc_phase_table_entry *last_entry;
2228 2800
2229 /* 2801 /*
2230 * num_phases doesn't include the default entry which 2802 * num_phases doesn't include the default entry which
@@ -2390,7 +2962,7 @@ ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2390 */ 2962 */
2391 struct ahc_initiator_tinfo *tinfo; 2963 struct ahc_initiator_tinfo *tinfo;
2392 struct ahc_tmode_tstate *tstate; 2964 struct ahc_tmode_tstate *tstate;
2393 struct ahc_syncrate *rate; 2965 const struct ahc_syncrate *rate;
2394 int dowide; 2966 int dowide;
2395 int dosync; 2967 int dosync;
2396 int doppr; 2968 int doppr;
@@ -2655,7 +3227,7 @@ proto_violation_reset:
2655 */ 3227 */
2656static void 3228static void
2657ahc_handle_message_phase(struct ahc_softc *ahc) 3229ahc_handle_message_phase(struct ahc_softc *ahc)
2658{ 3230{
2659 struct ahc_devinfo devinfo; 3231 struct ahc_devinfo devinfo;
2660 u_int bus_phase; 3232 u_int bus_phase;
2661 int end_session; 3233 int end_session;
@@ -3056,7 +3628,7 @@ ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3056 switch (ahc->msgin_buf[2]) { 3628 switch (ahc->msgin_buf[2]) {
3057 case MSG_EXT_SDTR: 3629 case MSG_EXT_SDTR:
3058 { 3630 {
3059 struct ahc_syncrate *syncrate; 3631 const struct ahc_syncrate *syncrate;
3060 u_int period; 3632 u_int period;
3061 u_int ppr_options; 3633 u_int ppr_options;
3062 u_int offset; 3634 u_int offset;
@@ -3231,7 +3803,7 @@ ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3231 } 3803 }
3232 case MSG_EXT_PPR: 3804 case MSG_EXT_PPR:
3233 { 3805 {
3234 struct ahc_syncrate *syncrate; 3806 const struct ahc_syncrate *syncrate;
3235 u_int period; 3807 u_int period;
3236 u_int offset; 3808 u_int offset;
3237 u_int bus_width; 3809 u_int bus_width;
@@ -3984,7 +4556,7 @@ ahc_free(struct ahc_softc *ahc)
3984 return; 4556 return;
3985} 4557}
3986 4558
3987void 4559static void
3988ahc_shutdown(void *arg) 4560ahc_shutdown(void *arg)
3989{ 4561{
3990 struct ahc_softc *ahc; 4562 struct ahc_softc *ahc;
@@ -4388,7 +4960,7 @@ ahc_fini_scbdata(struct ahc_softc *ahc)
4388 free(scb_data->scbarray, M_DEVBUF); 4960 free(scb_data->scbarray, M_DEVBUF);
4389} 4961}
4390 4962
4391void 4963static void
4392ahc_alloc_scbs(struct ahc_softc *ahc) 4964ahc_alloc_scbs(struct ahc_softc *ahc)
4393{ 4965{
4394 struct scb_data *scb_data; 4966 struct scb_data *scb_data;
@@ -5121,7 +5693,7 @@ ahc_resume(struct ahc_softc *ahc)
5121 * Return the untagged transaction id for a given target/channel lun. 5693 * Return the untagged transaction id for a given target/channel lun.
5122 * Optionally, clear the entry. 5694 * Optionally, clear the entry.
5123 */ 5695 */
5124u_int 5696static u_int
5125ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5697ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5126{ 5698{
5127 u_int scbid; 5699 u_int scbid;
@@ -5142,7 +5714,7 @@ ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5142 return (scbid); 5714 return (scbid);
5143} 5715}
5144 5716
5145void 5717static void
5146ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5718ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5147{ 5719{
5148 u_int target_offset; 5720 u_int target_offset;
@@ -5160,7 +5732,7 @@ ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5160 } 5732 }
5161} 5733}
5162 5734
5163void 5735static void
5164ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5736ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5165{ 5737{
5166 u_int target_offset; 5738 u_int target_offset;
@@ -5215,7 +5787,7 @@ ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5215 return match; 5787 return match;
5216} 5788}
5217 5789
5218void 5790static void
5219ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5791ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5220{ 5792{
5221 int target; 5793 int target;
@@ -5707,7 +6279,7 @@ ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5707 */ 6279 */
5708static u_int 6280static u_int
5709ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 6281ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5710{ 6282{
5711 u_int curscb, next; 6283 u_int curscb, next;
5712 6284
5713 /* 6285 /*
@@ -5756,7 +6328,7 @@ ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5756 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 6328 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5757 * is paused before it is called. 6329 * is paused before it is called.
5758 */ 6330 */
5759int 6331static int
5760ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 6332ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5761 int lun, u_int tag, role_t role, uint32_t status) 6333 int lun, u_int tag, role_t role, uint32_t status)
5762{ 6334{
@@ -6078,7 +6650,7 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6078/* 6650/*
6079 * Calculate the residual for a just completed SCB. 6651 * Calculate the residual for a just completed SCB.
6080 */ 6652 */
6081void 6653static void
6082ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6654ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6083{ 6655{
6084 struct hardware_scb *hscb; 6656 struct hardware_scb *hscb;
@@ -6279,7 +6851,7 @@ ahc_loadseq(struct ahc_softc *ahc)
6279 struct cs cs_table[num_critical_sections]; 6851 struct cs cs_table[num_critical_sections];
6280 u_int begin_set[num_critical_sections]; 6852 u_int begin_set[num_critical_sections];
6281 u_int end_set[num_critical_sections]; 6853 u_int end_set[num_critical_sections];
6282 struct patch *cur_patch; 6854 const struct patch *cur_patch;
6283 u_int cs_count; 6855 u_int cs_count;
6284 u_int cur_cs; 6856 u_int cur_cs;
6285 u_int i; 6857 u_int i;
@@ -6384,11 +6956,11 @@ ahc_loadseq(struct ahc_softc *ahc)
6384} 6956}
6385 6957
6386static int 6958static int
6387ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6959ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
6388 u_int start_instr, u_int *skip_addr) 6960 u_int start_instr, u_int *skip_addr)
6389{ 6961{
6390 struct patch *cur_patch; 6962 const struct patch *cur_patch;
6391 struct patch *last_patch; 6963 const struct patch *last_patch;
6392 u_int num_patches; 6964 u_int num_patches;
6393 6965
6394 num_patches = ARRAY_SIZE(patches); 6966 num_patches = ARRAY_SIZE(patches);
@@ -6447,7 +7019,7 @@ ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6447 case AIC_OP_JE: 7019 case AIC_OP_JE:
6448 case AIC_OP_JZ: 7020 case AIC_OP_JZ:
6449 { 7021 {
6450 struct patch *cur_patch; 7022 const struct patch *cur_patch;
6451 int address_offset; 7023 int address_offset;
6452 u_int address; 7024 u_int address;
6453 u_int skip_addr; 7025 u_int skip_addr;
@@ -6545,7 +7117,7 @@ ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6545} 7117}
6546 7118
6547int 7119int
6548ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 7120ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries,
6549 const char *name, u_int address, u_int value, 7121 const char *name, u_int address, u_int value,
6550 u_int *cur_column, u_int wrap_point) 7122 u_int *cur_column, u_int wrap_point)
6551{ 7123{
@@ -7229,7 +7801,7 @@ ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7229 ahc_outb(ahc, SCSIID, scsiid); 7801 ahc_outb(ahc, SCSIID, scsiid);
7230} 7802}
7231 7803
7232void 7804static void
7233ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7805ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7234{ 7806{
7235 struct target_cmd *cmd; 7807 struct target_cmd *cmd;
diff --git a/drivers/scsi/aic7xxx/aic7xxx_inline.h b/drivers/scsi/aic7xxx/aic7xxx_inline.h
index cba2f23bbe79..09bf2f4d78d5 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_inline.h
+++ b/drivers/scsi/aic7xxx/aic7xxx_inline.h
@@ -46,179 +46,13 @@
46#define _AIC7XXX_INLINE_H_ 46#define _AIC7XXX_INLINE_H_
47 47
48/************************* Sequencer Execution Control ************************/ 48/************************* Sequencer Execution Control ************************/
49static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); 49int ahc_is_paused(struct ahc_softc *ahc);
50static __inline int ahc_is_paused(struct ahc_softc *ahc); 50void ahc_pause(struct ahc_softc *ahc);
51static __inline void ahc_pause(struct ahc_softc *ahc); 51void ahc_unpause(struct ahc_softc *ahc);
52static __inline void ahc_unpause(struct ahc_softc *ahc);
53
54/*
55 * Work around any chip bugs related to halting sequencer execution.
56 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
57 * reading a register that will set this signal and deassert it.
58 * Without this workaround, if the chip is paused, by an interrupt or
59 * manual pause while accessing scb ram, accesses to certain registers
60 * will hang the system (infinite pci retries).
61 */
62static __inline void
63ahc_pause_bug_fix(struct ahc_softc *ahc)
64{
65 if ((ahc->features & AHC_ULTRA2) != 0)
66 (void)ahc_inb(ahc, CCSCBCTL);
67}
68
69/*
70 * Determine whether the sequencer has halted code execution.
71 * Returns non-zero status if the sequencer is stopped.
72 */
73static __inline int
74ahc_is_paused(struct ahc_softc *ahc)
75{
76 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
77}
78
79/*
80 * Request that the sequencer stop and wait, indefinitely, for it
81 * to stop. The sequencer will only acknowledge that it is paused
82 * once it has reached an instruction boundary and PAUSEDIS is
83 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
84 * for critical sections.
85 */
86static __inline void
87ahc_pause(struct ahc_softc *ahc)
88{
89 ahc_outb(ahc, HCNTRL, ahc->pause);
90
91 /*
92 * Since the sequencer can disable pausing in a critical section, we
93 * must loop until it actually stops.
94 */
95 while (ahc_is_paused(ahc) == 0)
96 ;
97
98 ahc_pause_bug_fix(ahc);
99}
100
101/*
102 * Allow the sequencer to continue program execution.
103 * We check here to ensure that no additional interrupt
104 * sources that would cause the sequencer to halt have been
105 * asserted. If, for example, a SCSI bus reset is detected
106 * while we are fielding a different, pausing, interrupt type,
107 * we don't want to release the sequencer before going back
108 * into our interrupt handler and dealing with this new
109 * condition.
110 */
111static __inline void
112ahc_unpause(struct ahc_softc *ahc)
113{
114 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
115 ahc_outb(ahc, HCNTRL, ahc->unpause);
116}
117
118/*********************** Untagged Transaction Routines ************************/
119static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
120static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
121
122/*
123 * Block our completion routine from starting the next untagged
124 * transaction for this target or target lun.
125 */
126static __inline void
127ahc_freeze_untagged_queues(struct ahc_softc *ahc)
128{
129 if ((ahc->flags & AHC_SCB_BTT) == 0)
130 ahc->untagged_queue_lock++;
131}
132
133/*
134 * Allow the next untagged transaction for this target or target lun
135 * to be executed. We use a counting semaphore to allow the lock
136 * to be acquired recursively. Once the count drops to zero, the
137 * transaction queues will be run.
138 */
139static __inline void
140ahc_release_untagged_queues(struct ahc_softc *ahc)
141{
142 if ((ahc->flags & AHC_SCB_BTT) == 0) {
143 ahc->untagged_queue_lock--;
144 if (ahc->untagged_queue_lock == 0)
145 ahc_run_untagged_queues(ahc);
146 }
147}
148 52
149/************************** Memory mapping routines ***************************/ 53/************************** Memory mapping routines ***************************/
150static __inline struct ahc_dma_seg * 54void ahc_sync_sglist(struct ahc_softc *ahc,
151 ahc_sg_bus_to_virt(struct scb *scb, 55 struct scb *scb, int op);
152 uint32_t sg_busaddr);
153static __inline uint32_t
154 ahc_sg_virt_to_bus(struct scb *scb,
155 struct ahc_dma_seg *sg);
156static __inline uint32_t
157 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
158static __inline void ahc_sync_scb(struct ahc_softc *ahc,
159 struct scb *scb, int op);
160static __inline void ahc_sync_sglist(struct ahc_softc *ahc,
161 struct scb *scb, int op);
162static __inline uint32_t
163 ahc_targetcmd_offset(struct ahc_softc *ahc,
164 u_int index);
165
166static __inline struct ahc_dma_seg *
167ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
168{
169 int sg_index;
170
171 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
172 /* sg_list_phys points to entry 1, not 0 */
173 sg_index++;
174
175 return (&scb->sg_list[sg_index]);
176}
177
178static __inline uint32_t
179ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
180{
181 int sg_index;
182
183 /* sg_list_phys points to entry 1, not 0 */
184 sg_index = sg - &scb->sg_list[1];
185
186 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
187}
188
189static __inline uint32_t
190ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
191{
192 return (ahc->scb_data->hscb_busaddr
193 + (sizeof(struct hardware_scb) * index));
194}
195
196static __inline void
197ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
198{
199 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
200 ahc->scb_data->hscb_dmamap,
201 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
202 /*len*/sizeof(*scb->hscb), op);
203}
204
205static __inline void
206ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
207{
208 if (scb->sg_count == 0)
209 return;
210
211 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
212 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
213 * sizeof(struct ahc_dma_seg),
214 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
215}
216
217static __inline uint32_t
218ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
219{
220 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
221}
222 56
223/******************************** Debugging ***********************************/ 57/******************************** Debugging ***********************************/
224static __inline char *ahc_name(struct ahc_softc *ahc); 58static __inline char *ahc_name(struct ahc_softc *ahc);
@@ -231,420 +65,34 @@ ahc_name(struct ahc_softc *ahc)
231 65
232/*********************** Miscellaneous Support Functions ***********************/ 66/*********************** Miscellaneous Support Functions ***********************/
233 67
234static __inline void ahc_update_residual(struct ahc_softc *ahc, 68struct ahc_initiator_tinfo *
235 struct scb *scb); 69 ahc_fetch_transinfo(struct ahc_softc *ahc,
236static __inline struct ahc_initiator_tinfo * 70 char channel, u_int our_id,
237 ahc_fetch_transinfo(struct ahc_softc *ahc, 71 u_int remote_id,
238 char channel, u_int our_id, 72 struct ahc_tmode_tstate **tstate);
239 u_int remote_id, 73uint16_t
240 struct ahc_tmode_tstate **tstate); 74 ahc_inw(struct ahc_softc *ahc, u_int port);
241static __inline uint16_t 75void ahc_outw(struct ahc_softc *ahc, u_int port,
242 ahc_inw(struct ahc_softc *ahc, u_int port); 76 u_int value);
243static __inline void ahc_outw(struct ahc_softc *ahc, u_int port, 77uint32_t
244 u_int value); 78 ahc_inl(struct ahc_softc *ahc, u_int port);
245static __inline uint32_t 79void ahc_outl(struct ahc_softc *ahc, u_int port,
246 ahc_inl(struct ahc_softc *ahc, u_int port); 80 uint32_t value);
247static __inline void ahc_outl(struct ahc_softc *ahc, u_int port, 81uint64_t
248 uint32_t value); 82 ahc_inq(struct ahc_softc *ahc, u_int port);
249static __inline uint64_t 83void ahc_outq(struct ahc_softc *ahc, u_int port,
250 ahc_inq(struct ahc_softc *ahc, u_int port); 84 uint64_t value);
251static __inline void ahc_outq(struct ahc_softc *ahc, u_int port, 85struct scb*
252 uint64_t value); 86 ahc_get_scb(struct ahc_softc *ahc);
253static __inline struct scb* 87void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
254 ahc_get_scb(struct ahc_softc *ahc); 88struct scb *
255static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 89 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag);
256static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc, 90void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
257 struct scb *scb); 91struct scsi_sense_data *
258static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb); 92 ahc_get_sense_buf(struct ahc_softc *ahc,
259static __inline struct scsi_sense_data * 93 struct scb *scb);
260 ahc_get_sense_buf(struct ahc_softc *ahc,
261 struct scb *scb);
262static __inline uint32_t
263 ahc_get_sense_bufaddr(struct ahc_softc *ahc,
264 struct scb *scb);
265
266/*
267 * Determine whether the sequencer reported a residual
268 * for this SCB/transaction.
269 */
270static __inline void
271ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
272{
273 uint32_t sgptr;
274
275 sgptr = ahc_le32toh(scb->hscb->sgptr);
276 if ((sgptr & SG_RESID_VALID) != 0)
277 ahc_calc_residual(ahc, scb);
278}
279
280/*
281 * Return pointers to the transfer negotiation information
282 * for the specified our_id/remote_id pair.
283 */
284static __inline struct ahc_initiator_tinfo *
285ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
286 u_int remote_id, struct ahc_tmode_tstate **tstate)
287{
288 /*
289 * Transfer data structures are stored from the perspective
290 * of the target role. Since the parameters for a connection
291 * in the initiator role to a given target are the same as
292 * when the roles are reversed, we pretend we are the target.
293 */
294 if (channel == 'B')
295 our_id += 8;
296 *tstate = ahc->enabled_targets[our_id];
297 return (&(*tstate)->transinfo[remote_id]);
298}
299
300static __inline uint16_t
301ahc_inw(struct ahc_softc *ahc, u_int port)
302{
303 uint16_t r = ahc_inb(ahc, port+1) << 8;
304 return r | ahc_inb(ahc, port);
305}
306
307static __inline void
308ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
309{
310 ahc_outb(ahc, port, value & 0xFF);
311 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
312}
313
314static __inline uint32_t
315ahc_inl(struct ahc_softc *ahc, u_int port)
316{
317 return ((ahc_inb(ahc, port))
318 | (ahc_inb(ahc, port+1) << 8)
319 | (ahc_inb(ahc, port+2) << 16)
320 | (ahc_inb(ahc, port+3) << 24));
321}
322
323static __inline void
324ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
325{
326 ahc_outb(ahc, port, (value) & 0xFF);
327 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
328 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
329 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
330}
331
332static __inline uint64_t
333ahc_inq(struct ahc_softc *ahc, u_int port)
334{
335 return ((ahc_inb(ahc, port))
336 | (ahc_inb(ahc, port+1) << 8)
337 | (ahc_inb(ahc, port+2) << 16)
338 | (ahc_inb(ahc, port+3) << 24)
339 | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
340 | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
341 | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
342 | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
343}
344
345static __inline void
346ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
347{
348 ahc_outb(ahc, port, value & 0xFF);
349 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
350 ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
351 ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
352 ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
353 ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
354 ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
355 ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
356}
357
358/*
359 * Get a free scb. If there are none, see if we can allocate a new SCB.
360 */
361static __inline struct scb *
362ahc_get_scb(struct ahc_softc *ahc)
363{
364 struct scb *scb;
365
366 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
367 ahc_alloc_scbs(ahc);
368 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
369 if (scb == NULL)
370 return (NULL);
371 }
372 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
373 return (scb);
374}
375
376/*
377 * Return an SCB resource to the free list.
378 */
379static __inline void
380ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
381{
382 struct hardware_scb *hscb;
383
384 hscb = scb->hscb;
385 /* Clean up for the next user */
386 ahc->scb_data->scbindex[hscb->tag] = NULL;
387 scb->flags = SCB_FREE;
388 hscb->control = 0;
389
390 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
391
392 /* Notify the OSM that a resource is now available. */
393 ahc_platform_scb_free(ahc, scb);
394}
395
396static __inline struct scb *
397ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
398{
399 struct scb* scb;
400
401 scb = ahc->scb_data->scbindex[tag];
402 if (scb != NULL)
403 ahc_sync_scb(ahc, scb,
404 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
405 return (scb);
406}
407
408static __inline void
409ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
410{
411 struct hardware_scb *q_hscb;
412 u_int saved_tag;
413
414 /*
415 * Our queuing method is a bit tricky. The card
416 * knows in advance which HSCB to download, and we
417 * can't disappoint it. To achieve this, the next
418 * SCB to download is saved off in ahc->next_queued_scb.
419 * When we are called to queue "an arbitrary scb",
420 * we copy the contents of the incoming HSCB to the one
421 * the sequencer knows about, swap HSCB pointers and
422 * finally assign the SCB to the tag indexed location
423 * in the scb_array. This makes sure that we can still
424 * locate the correct SCB by SCB_TAG.
425 */
426 q_hscb = ahc->next_queued_scb->hscb;
427 saved_tag = q_hscb->tag;
428 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
429 if ((scb->flags & SCB_CDB32_PTR) != 0) {
430 q_hscb->shared_data.cdb_ptr =
431 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
432 + offsetof(struct hardware_scb, cdb32));
433 }
434 q_hscb->tag = saved_tag;
435 q_hscb->next = scb->hscb->tag;
436
437 /* Now swap HSCB pointers. */
438 ahc->next_queued_scb->hscb = scb->hscb;
439 scb->hscb = q_hscb;
440
441 /* Now define the mapping from tag to SCB in the scbindex */
442 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
443}
444
445/*
446 * Tell the sequencer about a new transaction to execute.
447 */
448static __inline void
449ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
450{
451 ahc_swap_with_next_hscb(ahc, scb);
452
453 if (scb->hscb->tag == SCB_LIST_NULL
454 || scb->hscb->next == SCB_LIST_NULL)
455 panic("Attempt to queue invalid SCB tag %x:%x\n",
456 scb->hscb->tag, scb->hscb->next);
457
458 /*
459 * Setup data "oddness".
460 */
461 scb->hscb->lun &= LID;
462 if (ahc_get_transfer_length(scb) & 0x1)
463 scb->hscb->lun |= SCB_XFERLEN_ODD;
464
465 /*
466 * Keep a history of SCBs we've downloaded in the qinfifo.
467 */
468 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
469
470 /*
471 * Make sure our data is consistent from the
472 * perspective of the adapter.
473 */
474 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
475
476 /* Tell the adapter about the newly queued SCB */
477 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
478 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
479 } else {
480 if ((ahc->features & AHC_AUTOPAUSE) == 0)
481 ahc_pause(ahc);
482 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
483 if ((ahc->features & AHC_AUTOPAUSE) == 0)
484 ahc_unpause(ahc);
485 }
486}
487
488static __inline struct scsi_sense_data *
489ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
490{
491 int offset;
492
493 offset = scb - ahc->scb_data->scbarray;
494 return (&ahc->scb_data->sense[offset]);
495}
496
497static __inline uint32_t
498ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
499{
500 int offset;
501
502 offset = scb - ahc->scb_data->scbarray;
503 return (ahc->scb_data->sense_busaddr
504 + (offset * sizeof(struct scsi_sense_data)));
505}
506 94
507/************************** Interrupt Processing ******************************/ 95/************************** Interrupt Processing ******************************/
508static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op); 96int ahc_intr(struct ahc_softc *ahc);
509static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op);
510static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc);
511static __inline int ahc_intr(struct ahc_softc *ahc);
512
513static __inline void
514ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
515{
516 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
517 /*offset*/0, /*len*/256, op);
518}
519
520static __inline void
521ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
522{
523#ifdef AHC_TARGET_MODE
524 if ((ahc->flags & AHC_TARGETROLE) != 0) {
525 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
526 ahc->shared_data_dmamap,
527 ahc_targetcmd_offset(ahc, 0),
528 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
529 op);
530 }
531#endif
532}
533
534/*
535 * See if the firmware has posted any completed commands
536 * into our in-core command complete fifos.
537 */
538#define AHC_RUN_QOUTFIFO 0x1
539#define AHC_RUN_TQINFIFO 0x2
540static __inline u_int
541ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
542{
543 u_int retval;
544
545 retval = 0;
546 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
547 /*offset*/ahc->qoutfifonext, /*len*/1,
548 BUS_DMASYNC_POSTREAD);
549 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
550 retval |= AHC_RUN_QOUTFIFO;
551#ifdef AHC_TARGET_MODE
552 if ((ahc->flags & AHC_TARGETROLE) != 0
553 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
554 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
555 ahc->shared_data_dmamap,
556 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
557 /*len*/sizeof(struct target_cmd),
558 BUS_DMASYNC_POSTREAD);
559 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
560 retval |= AHC_RUN_TQINFIFO;
561 }
562#endif
563 return (retval);
564}
565
566/*
567 * Catch an interrupt from the adapter
568 */
569static __inline int
570ahc_intr(struct ahc_softc *ahc)
571{
572 u_int intstat;
573
574 if ((ahc->pause & INTEN) == 0) {
575 /*
576 * Our interrupt is not enabled on the chip
577 * and may be disabled for re-entrancy reasons,
578 * so just return. This is likely just a shared
579 * interrupt.
580 */
581 return (0);
582 }
583 /*
584 * Instead of directly reading the interrupt status register,
585 * infer the cause of the interrupt by checking our in-core
586 * completion queues. This avoids a costly PCI bus read in
587 * most cases.
588 */
589 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
590 && (ahc_check_cmdcmpltqueues(ahc) != 0))
591 intstat = CMDCMPLT;
592 else {
593 intstat = ahc_inb(ahc, INTSTAT);
594 }
595
596 if ((intstat & INT_PEND) == 0) {
597#if AHC_PCI_CONFIG > 0
598 if (ahc->unsolicited_ints > 500) {
599 ahc->unsolicited_ints = 0;
600 if ((ahc->chip & AHC_PCI) != 0
601 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
602 ahc->bus_intr(ahc);
603 }
604#endif
605 ahc->unsolicited_ints++;
606 return (0);
607 }
608 ahc->unsolicited_ints = 0;
609
610 if (intstat & CMDCMPLT) {
611 ahc_outb(ahc, CLRINT, CLRCMDINT);
612
613 /*
614 * Ensure that the chip sees that we've cleared
615 * this interrupt before we walk the output fifo.
616 * Otherwise, we may, due to posted bus writes,
617 * clear the interrupt after we finish the scan,
618 * and after the sequencer has added new entries
619 * and asserted the interrupt again.
620 */
621 ahc_flush_device_writes(ahc);
622 ahc_run_qoutfifo(ahc);
623#ifdef AHC_TARGET_MODE
624 if ((ahc->flags & AHC_TARGETROLE) != 0)
625 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
626#endif
627 }
628
629 /*
630 * Handle statuses that may invalidate our cached
631 * copy of INTSTAT separately.
632 */
633 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
634 /* Hot eject. Do nothing */
635 } else if (intstat & BRKADRINT) {
636 ahc_handle_brkadrint(ahc);
637 } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
638
639 ahc_pause_bug_fix(ahc);
640
641 if ((intstat & SEQINT) != 0)
642 ahc_handle_seqint(ahc, intstat);
643
644 if ((intstat & SCSIINT) != 0)
645 ahc_handle_scsiint(ahc, intstat);
646 }
647 return (1);
648}
649 97
650#endif /* _AIC7XXX_INLINE_H_ */ 98#endif /* _AIC7XXX_INLINE_H_ */
diff --git a/drivers/scsi/aic7xxx/aic7xxx_osm.c b/drivers/scsi/aic7xxx/aic7xxx_osm.c
index 42ad48e09f02..fd2b9785ff4f 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_osm.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_osm.c
@@ -388,14 +388,83 @@ static int aic7xxx_setup(char *s);
388static int ahc_linux_unit; 388static int ahc_linux_unit;
389 389
390 390
391/************************** OS Utility Wrappers *******************************/
392void
393ahc_delay(long usec)
394{
395 /*
396 * udelay on Linux can have problems for
397 * multi-millisecond waits. Wait at most
398 * 1024us per call.
399 */
400 while (usec > 0) {
401 udelay(usec % 1024);
402 usec -= 1024;
403 }
404}
405
406/***************************** Low Level I/O **********************************/
407uint8_t
408ahc_inb(struct ahc_softc * ahc, long port)
409{
410 uint8_t x;
411
412 if (ahc->tag == BUS_SPACE_MEMIO) {
413 x = readb(ahc->bsh.maddr + port);
414 } else {
415 x = inb(ahc->bsh.ioport + port);
416 }
417 mb();
418 return (x);
419}
420
421void
422ahc_outb(struct ahc_softc * ahc, long port, uint8_t val)
423{
424 if (ahc->tag == BUS_SPACE_MEMIO) {
425 writeb(val, ahc->bsh.maddr + port);
426 } else {
427 outb(val, ahc->bsh.ioport + port);
428 }
429 mb();
430}
431
432void
433ahc_outsb(struct ahc_softc * ahc, long port, uint8_t *array, int count)
434{
435 int i;
436
437 /*
438 * There is probably a more efficient way to do this on Linux
439 * but we don't use this for anything speed critical and this
440 * should work.
441 */
442 for (i = 0; i < count; i++)
443 ahc_outb(ahc, port, *array++);
444}
445
446void
447ahc_insb(struct ahc_softc * ahc, long port, uint8_t *array, int count)
448{
449 int i;
450
451 /*
452 * There is probably a more efficient way to do this on Linux
453 * but we don't use this for anything speed critical and this
454 * should work.
455 */
456 for (i = 0; i < count; i++)
457 *array++ = ahc_inb(ahc, port);
458}
459
391/********************************* Inlines ************************************/ 460/********************************* Inlines ************************************/
392static __inline void ahc_linux_unmap_scb(struct ahc_softc*, struct scb*); 461static void ahc_linux_unmap_scb(struct ahc_softc*, struct scb*);
393 462
394static __inline int ahc_linux_map_seg(struct ahc_softc *ahc, struct scb *scb, 463static int ahc_linux_map_seg(struct ahc_softc *ahc, struct scb *scb,
395 struct ahc_dma_seg *sg, 464 struct ahc_dma_seg *sg,
396 dma_addr_t addr, bus_size_t len); 465 dma_addr_t addr, bus_size_t len);
397 466
398static __inline void 467static void
399ahc_linux_unmap_scb(struct ahc_softc *ahc, struct scb *scb) 468ahc_linux_unmap_scb(struct ahc_softc *ahc, struct scb *scb)
400{ 469{
401 struct scsi_cmnd *cmd; 470 struct scsi_cmnd *cmd;
@@ -406,7 +475,7 @@ ahc_linux_unmap_scb(struct ahc_softc *ahc, struct scb *scb)
406 scsi_dma_unmap(cmd); 475 scsi_dma_unmap(cmd);
407} 476}
408 477
409static __inline int 478static int
410ahc_linux_map_seg(struct ahc_softc *ahc, struct scb *scb, 479ahc_linux_map_seg(struct ahc_softc *ahc, struct scb *scb,
411 struct ahc_dma_seg *sg, dma_addr_t addr, bus_size_t len) 480 struct ahc_dma_seg *sg, dma_addr_t addr, bus_size_t len)
412{ 481{
@@ -442,13 +511,11 @@ ahc_linux_info(struct Scsi_Host *host)
442 bp = &buffer[0]; 511 bp = &buffer[0];
443 ahc = *(struct ahc_softc **)host->hostdata; 512 ahc = *(struct ahc_softc **)host->hostdata;
444 memset(bp, 0, sizeof(buffer)); 513 memset(bp, 0, sizeof(buffer));
445 strcpy(bp, "Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev "); 514 strcpy(bp, "Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev " AIC7XXX_DRIVER_VERSION "\n"
446 strcat(bp, AIC7XXX_DRIVER_VERSION); 515 " <");
447 strcat(bp, "\n");
448 strcat(bp, " <");
449 strcat(bp, ahc->description); 516 strcat(bp, ahc->description);
450 strcat(bp, ">\n"); 517 strcat(bp, ">\n"
451 strcat(bp, " "); 518 " ");
452 ahc_controller_info(ahc, ahc_info); 519 ahc_controller_info(ahc, ahc_info);
453 strcat(bp, ahc_info); 520 strcat(bp, ahc_info);
454 strcat(bp, "\n"); 521 strcat(bp, "\n");
@@ -964,7 +1031,7 @@ aic7xxx_setup(char *s)
964 char *p; 1031 char *p;
965 char *end; 1032 char *end;
966 1033
967 static struct { 1034 static const struct {
968 const char *name; 1035 const char *name;
969 uint32_t *flag; 1036 uint32_t *flag;
970 } options[] = { 1037 } options[] = {
@@ -2317,7 +2384,7 @@ static void ahc_linux_set_period(struct scsi_target *starget, int period)
2317 unsigned int ppr_options = tinfo->goal.ppr_options; 2384 unsigned int ppr_options = tinfo->goal.ppr_options;
2318 unsigned long flags; 2385 unsigned long flags;
2319 unsigned long offset = tinfo->goal.offset; 2386 unsigned long offset = tinfo->goal.offset;
2320 struct ahc_syncrate *syncrate; 2387 const struct ahc_syncrate *syncrate;
2321 2388
2322 if (offset == 0) 2389 if (offset == 0)
2323 offset = MAX_OFFSET; 2390 offset = MAX_OFFSET;
@@ -2361,7 +2428,7 @@ static void ahc_linux_set_offset(struct scsi_target *starget, int offset)
2361 unsigned int ppr_options = 0; 2428 unsigned int ppr_options = 0;
2362 unsigned int period = 0; 2429 unsigned int period = 0;
2363 unsigned long flags; 2430 unsigned long flags;
2364 struct ahc_syncrate *syncrate = NULL; 2431 const struct ahc_syncrate *syncrate = NULL;
2365 2432
2366 ahc_compile_devinfo(&devinfo, shost->this_id, starget->id, 0, 2433 ahc_compile_devinfo(&devinfo, shost->this_id, starget->id, 0,
2367 starget->channel + 'A', ROLE_INITIATOR); 2434 starget->channel + 'A', ROLE_INITIATOR);
@@ -2391,7 +2458,7 @@ static void ahc_linux_set_dt(struct scsi_target *starget, int dt)
2391 unsigned int period = tinfo->goal.period; 2458 unsigned int period = tinfo->goal.period;
2392 unsigned int width = tinfo->goal.width; 2459 unsigned int width = tinfo->goal.width;
2393 unsigned long flags; 2460 unsigned long flags;
2394 struct ahc_syncrate *syncrate; 2461 const struct ahc_syncrate *syncrate;
2395 2462
2396 if (dt && spi_max_width(starget)) { 2463 if (dt && spi_max_width(starget)) {
2397 ppr_options |= MSG_EXT_PPR_DT_REQ; 2464 ppr_options |= MSG_EXT_PPR_DT_REQ;
diff --git a/drivers/scsi/aic7xxx/aic7xxx_osm.h b/drivers/scsi/aic7xxx/aic7xxx_osm.h
index b48dab447bde..3f7238db35e5 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_osm.h
+++ b/drivers/scsi/aic7xxx/aic7xxx_osm.h
@@ -365,7 +365,7 @@ struct ahc_platform_data {
365#define AHC_LINUX_NOIRQ ((uint32_t)~0) 365#define AHC_LINUX_NOIRQ ((uint32_t)~0)
366 uint32_t irq; /* IRQ for this adapter */ 366 uint32_t irq; /* IRQ for this adapter */
367 uint32_t bios_address; 367 uint32_t bios_address;
368 uint32_t mem_busaddr; /* Mem Base Addr */ 368 resource_size_t mem_busaddr; /* Mem Base Addr */
369}; 369};
370 370
371/************************** OS Utility Wrappers *******************************/ 371/************************** OS Utility Wrappers *******************************/
@@ -375,82 +375,16 @@ struct ahc_platform_data {
375#define malloc(size, type, flags) kmalloc(size, flags) 375#define malloc(size, type, flags) kmalloc(size, flags)
376#define free(ptr, type) kfree(ptr) 376#define free(ptr, type) kfree(ptr)
377 377
378static __inline void ahc_delay(long); 378void ahc_delay(long);
379static __inline void
380ahc_delay(long usec)
381{
382 /*
383 * udelay on Linux can have problems for
384 * multi-millisecond waits. Wait at most
385 * 1024us per call.
386 */
387 while (usec > 0) {
388 udelay(usec % 1024);
389 usec -= 1024;
390 }
391}
392 379
393 380
394/***************************** Low Level I/O **********************************/ 381/***************************** Low Level I/O **********************************/
395static __inline uint8_t ahc_inb(struct ahc_softc * ahc, long port); 382uint8_t ahc_inb(struct ahc_softc * ahc, long port);
396static __inline void ahc_outb(struct ahc_softc * ahc, long port, uint8_t val); 383void ahc_outb(struct ahc_softc * ahc, long port, uint8_t val);
397static __inline void ahc_outsb(struct ahc_softc * ahc, long port, 384void ahc_outsb(struct ahc_softc * ahc, long port,
398 uint8_t *, int count); 385 uint8_t *, int count);
399static __inline void ahc_insb(struct ahc_softc * ahc, long port, 386void ahc_insb(struct ahc_softc * ahc, long port,
400 uint8_t *, int count); 387 uint8_t *, int count);
401
402static __inline uint8_t
403ahc_inb(struct ahc_softc * ahc, long port)
404{
405 uint8_t x;
406
407 if (ahc->tag == BUS_SPACE_MEMIO) {
408 x = readb(ahc->bsh.maddr + port);
409 } else {
410 x = inb(ahc->bsh.ioport + port);
411 }
412 mb();
413 return (x);
414}
415
416static __inline void
417ahc_outb(struct ahc_softc * ahc, long port, uint8_t val)
418{
419 if (ahc->tag == BUS_SPACE_MEMIO) {
420 writeb(val, ahc->bsh.maddr + port);
421 } else {
422 outb(val, ahc->bsh.ioport + port);
423 }
424 mb();
425}
426
427static __inline void
428ahc_outsb(struct ahc_softc * ahc, long port, uint8_t *array, int count)
429{
430 int i;
431
432 /*
433 * There is probably a more efficient way to do this on Linux
434 * but we don't use this for anything speed critical and this
435 * should work.
436 */
437 for (i = 0; i < count; i++)
438 ahc_outb(ahc, port, *array++);
439}
440
441static __inline void
442ahc_insb(struct ahc_softc * ahc, long port, uint8_t *array, int count)
443{
444 int i;
445
446 /*
447 * There is probably a more efficient way to do this on Linux
448 * but we don't use this for anything speed critical and this
449 * should work.
450 */
451 for (i = 0; i < count; i++)
452 *array++ = ahc_inb(ahc, port);
453}
454 388
455/**************************** Initialization **********************************/ 389/**************************** Initialization **********************************/
456int ahc_linux_register_host(struct ahc_softc *, 390int ahc_linux_register_host(struct ahc_softc *,
@@ -464,9 +398,6 @@ struct info_str {
464 int pos; 398 int pos;
465}; 399};
466 400
467void ahc_format_transinfo(struct info_str *info,
468 struct ahc_transinfo *tinfo);
469
470/******************************** Locking *************************************/ 401/******************************** Locking *************************************/
471/* Lock protecting internal data structures */ 402/* Lock protecting internal data structures */
472 403
@@ -555,61 +486,12 @@ void ahc_linux_pci_exit(void);
555int ahc_pci_map_registers(struct ahc_softc *ahc); 486int ahc_pci_map_registers(struct ahc_softc *ahc);
556int ahc_pci_map_int(struct ahc_softc *ahc); 487int ahc_pci_map_int(struct ahc_softc *ahc);
557 488
558static __inline uint32_t ahc_pci_read_config(ahc_dev_softc_t pci, 489uint32_t ahc_pci_read_config(ahc_dev_softc_t pci,
559 int reg, int width); 490 int reg, int width);
560 491
561static __inline uint32_t 492void ahc_pci_write_config(ahc_dev_softc_t pci,
562ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width) 493 int reg, uint32_t value,
563{ 494 int width);
564 switch (width) {
565 case 1:
566 {
567 uint8_t retval;
568
569 pci_read_config_byte(pci, reg, &retval);
570 return (retval);
571 }
572 case 2:
573 {
574 uint16_t retval;
575 pci_read_config_word(pci, reg, &retval);
576 return (retval);
577 }
578 case 4:
579 {
580 uint32_t retval;
581 pci_read_config_dword(pci, reg, &retval);
582 return (retval);
583 }
584 default:
585 panic("ahc_pci_read_config: Read size too big");
586 /* NOTREACHED */
587 return (0);
588 }
589}
590
591static __inline void ahc_pci_write_config(ahc_dev_softc_t pci,
592 int reg, uint32_t value,
593 int width);
594
595static __inline void
596ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
597{
598 switch (width) {
599 case 1:
600 pci_write_config_byte(pci, reg, value);
601 break;
602 case 2:
603 pci_write_config_word(pci, reg, value);
604 break;
605 case 4:
606 pci_write_config_dword(pci, reg, value);
607 break;
608 default:
609 panic("ahc_pci_write_config: Write size too big");
610 /* NOTREACHED */
611 }
612}
613 495
614static __inline int ahc_get_pci_function(ahc_dev_softc_t); 496static __inline int ahc_get_pci_function(ahc_dev_softc_t);
615static __inline int 497static __inline int
diff --git a/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c b/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c
index 3d3eaef65fb3..0d7628f1f1ef 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c
@@ -46,7 +46,7 @@
46*/ 46*/
47#define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI) 47#define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI)
48 48
49static struct pci_device_id ahc_linux_pci_id_table[] = { 49static const struct pci_device_id ahc_linux_pci_id_table[] = {
50 /* aic7850 based controllers */ 50 /* aic7850 based controllers */
51 ID(ID_AHA_2902_04_10_15_20C_30C), 51 ID(ID_AHA_2902_04_10_15_20C_30C),
52 /* aic7860 based controllers */ 52 /* aic7860 based controllers */
@@ -206,7 +206,7 @@ ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
206 const uint64_t mask_39bit = 0x7FFFFFFFFFULL; 206 const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
207 struct ahc_softc *ahc; 207 struct ahc_softc *ahc;
208 ahc_dev_softc_t pci; 208 ahc_dev_softc_t pci;
209 struct ahc_pci_identity *entry; 209 const struct ahc_pci_identity *entry;
210 char *name; 210 char *name;
211 int error; 211 int error;
212 struct device *dev = &pdev->dev; 212 struct device *dev = &pdev->dev;
@@ -269,6 +269,57 @@ ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
269 return (0); 269 return (0);
270} 270}
271 271
272/******************************* PCI Routines *********************************/
273uint32_t
274ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)
275{
276 switch (width) {
277 case 1:
278 {
279 uint8_t retval;
280
281 pci_read_config_byte(pci, reg, &retval);
282 return (retval);
283 }
284 case 2:
285 {
286 uint16_t retval;
287 pci_read_config_word(pci, reg, &retval);
288 return (retval);
289 }
290 case 4:
291 {
292 uint32_t retval;
293 pci_read_config_dword(pci, reg, &retval);
294 return (retval);
295 }
296 default:
297 panic("ahc_pci_read_config: Read size too big");
298 /* NOTREACHED */
299 return (0);
300 }
301}
302
303void
304ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
305{
306 switch (width) {
307 case 1:
308 pci_write_config_byte(pci, reg, value);
309 break;
310 case 2:
311 pci_write_config_word(pci, reg, value);
312 break;
313 case 4:
314 pci_write_config_dword(pci, reg, value);
315 break;
316 default:
317 panic("ahc_pci_write_config: Write size too big");
318 /* NOTREACHED */
319 }
320}
321
322
272static struct pci_driver aic7xxx_pci_driver = { 323static struct pci_driver aic7xxx_pci_driver = {
273 .name = "aic7xxx", 324 .name = "aic7xxx",
274 .probe = ahc_linux_pci_dev_probe, 325 .probe = ahc_linux_pci_dev_probe,
@@ -293,7 +344,7 @@ ahc_linux_pci_exit(void)
293} 344}
294 345
295static int 346static int
296ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, u_long *base) 347ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base)
297{ 348{
298 if (aic7xxx_allow_memio == 0) 349 if (aic7xxx_allow_memio == 0)
299 return (ENOMEM); 350 return (ENOMEM);
@@ -308,10 +359,10 @@ ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, u_long *base)
308 359
309static int 360static int
310ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc, 361ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
311 u_long *bus_addr, 362 resource_size_t *bus_addr,
312 uint8_t __iomem **maddr) 363 uint8_t __iomem **maddr)
313{ 364{
314 u_long start; 365 resource_size_t start;
315 int error; 366 int error;
316 367
317 error = 0; 368 error = 0;
@@ -336,7 +387,7 @@ int
336ahc_pci_map_registers(struct ahc_softc *ahc) 387ahc_pci_map_registers(struct ahc_softc *ahc)
337{ 388{
338 uint32_t command; 389 uint32_t command;
339 u_long base; 390 resource_size_t base;
340 uint8_t __iomem *maddr; 391 uint8_t __iomem *maddr;
341 int error; 392 int error;
342 393
@@ -374,12 +425,12 @@ ahc_pci_map_registers(struct ahc_softc *ahc)
374 } else 425 } else
375 command |= PCIM_CMD_MEMEN; 426 command |= PCIM_CMD_MEMEN;
376 } else { 427 } else {
377 printf("aic7xxx: PCI%d:%d:%d MEM region 0x%lx " 428 printf("aic7xxx: PCI%d:%d:%d MEM region 0x%llx "
378 "unavailable. Cannot memory map device.\n", 429 "unavailable. Cannot memory map device.\n",
379 ahc_get_pci_bus(ahc->dev_softc), 430 ahc_get_pci_bus(ahc->dev_softc),
380 ahc_get_pci_slot(ahc->dev_softc), 431 ahc_get_pci_slot(ahc->dev_softc),
381 ahc_get_pci_function(ahc->dev_softc), 432 ahc_get_pci_function(ahc->dev_softc),
382 base); 433 (unsigned long long)base);
383 } 434 }
384 435
385 /* 436 /*
@@ -390,15 +441,15 @@ ahc_pci_map_registers(struct ahc_softc *ahc)
390 error = ahc_linux_pci_reserve_io_region(ahc, &base); 441 error = ahc_linux_pci_reserve_io_region(ahc, &base);
391 if (error == 0) { 442 if (error == 0) {
392 ahc->tag = BUS_SPACE_PIO; 443 ahc->tag = BUS_SPACE_PIO;
393 ahc->bsh.ioport = base; 444 ahc->bsh.ioport = (u_long)base;
394 command |= PCIM_CMD_PORTEN; 445 command |= PCIM_CMD_PORTEN;
395 } else { 446 } else {
396 printf("aic7xxx: PCI%d:%d:%d IO region 0x%lx[0..255] " 447 printf("aic7xxx: PCI%d:%d:%d IO region 0x%llx[0..255] "
397 "unavailable. Cannot map device.\n", 448 "unavailable. Cannot map device.\n",
398 ahc_get_pci_bus(ahc->dev_softc), 449 ahc_get_pci_bus(ahc->dev_softc),
399 ahc_get_pci_slot(ahc->dev_softc), 450 ahc_get_pci_slot(ahc->dev_softc),
400 ahc_get_pci_function(ahc->dev_softc), 451 ahc_get_pci_function(ahc->dev_softc),
401 base); 452 (unsigned long long)base);
402 } 453 }
403 } 454 }
404 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4); 455 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
diff --git a/drivers/scsi/aic7xxx/aic7xxx_pci.c b/drivers/scsi/aic7xxx/aic7xxx_pci.c
index 56848f41e4f9..c07cb6eebb02 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_pci.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_pci.c
@@ -168,8 +168,7 @@ static ahc_device_setup_t ahc_aha394XX_setup;
168static ahc_device_setup_t ahc_aha494XX_setup; 168static ahc_device_setup_t ahc_aha494XX_setup;
169static ahc_device_setup_t ahc_aha398XX_setup; 169static ahc_device_setup_t ahc_aha398XX_setup;
170 170
171static struct ahc_pci_identity ahc_pci_ident_table [] = 171static const struct ahc_pci_identity ahc_pci_ident_table[] = {
172{
173 /* aic7850 based controllers */ 172 /* aic7850 based controllers */
174 { 173 {
175 ID_AHA_2902_04_10_15_20C_30C, 174 ID_AHA_2902_04_10_15_20C_30C,
@@ -668,7 +667,7 @@ ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
668 return (result); 667 return (result);
669} 668}
670 669
671struct ahc_pci_identity * 670const struct ahc_pci_identity *
672ahc_find_pci_device(ahc_dev_softc_t pci) 671ahc_find_pci_device(ahc_dev_softc_t pci)
673{ 672{
674 uint64_t full_id; 673 uint64_t full_id;
@@ -676,7 +675,7 @@ ahc_find_pci_device(ahc_dev_softc_t pci)
676 uint16_t vendor; 675 uint16_t vendor;
677 uint16_t subdevice; 676 uint16_t subdevice;
678 uint16_t subvendor; 677 uint16_t subvendor;
679 struct ahc_pci_identity *entry; 678 const struct ahc_pci_identity *entry;
680 u_int i; 679 u_int i;
681 680
682 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 681 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
@@ -710,7 +709,7 @@ ahc_find_pci_device(ahc_dev_softc_t pci)
710} 709}
711 710
712int 711int
713ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 712ahc_pci_config(struct ahc_softc *ahc, const struct ahc_pci_identity *entry)
714{ 713{
715 u_int command; 714 u_int command;
716 u_int our_id; 715 u_int our_id;
diff --git a/drivers/scsi/aic7xxx/aic7xxx_proc.c b/drivers/scsi/aic7xxx/aic7xxx_proc.c
index 99e5443e7535..e92991a7c485 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_proc.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_proc.c
@@ -58,7 +58,7 @@ static int ahc_proc_write_seeprom(struct ahc_softc *ahc,
58 * Table of syncrates that don't follow the "divisible by 4" 58 * Table of syncrates that don't follow the "divisible by 4"
59 * rule. This table will be expanded in future SCSI specs. 59 * rule. This table will be expanded in future SCSI specs.
60 */ 60 */
61static struct { 61static const struct {
62 u_int period_factor; 62 u_int period_factor;
63 u_int period; /* in 100ths of ns */ 63 u_int period; /* in 100ths of ns */
64} scsi_syncrates[] = { 64} scsi_syncrates[] = {
@@ -137,7 +137,7 @@ copy_info(struct info_str *info, char *fmt, ...)
137 return (len); 137 return (len);
138} 138}
139 139
140void 140static void
141ahc_format_transinfo(struct info_str *info, struct ahc_transinfo *tinfo) 141ahc_format_transinfo(struct info_str *info, struct ahc_transinfo *tinfo)
142{ 142{
143 u_int speed; 143 u_int speed;
diff --git a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
index 88bfd767c51c..309a562b009e 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
+++ b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
@@ -8,7 +8,7 @@
8 8
9#include "aic7xxx_osm.h" 9#include "aic7xxx_osm.h"
10 10
11static ahc_reg_parse_entry_t SCSISEQ_parse_table[] = { 11static const ahc_reg_parse_entry_t SCSISEQ_parse_table[] = {
12 { "SCSIRSTO", 0x01, 0x01 }, 12 { "SCSIRSTO", 0x01, 0x01 },
13 { "ENAUTOATNP", 0x02, 0x02 }, 13 { "ENAUTOATNP", 0x02, 0x02 },
14 { "ENAUTOATNI", 0x04, 0x04 }, 14 { "ENAUTOATNI", 0x04, 0x04 },
@@ -26,7 +26,7 @@ ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap)
26 0x00, regvalue, cur_col, wrap)); 26 0x00, regvalue, cur_col, wrap));
27} 27}
28 28
29static ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = { 29static const ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = {
30 { "CLRCHN", 0x02, 0x02 }, 30 { "CLRCHN", 0x02, 0x02 },
31 { "SCAMEN", 0x04, 0x04 }, 31 { "SCAMEN", 0x04, 0x04 },
32 { "SPIOEN", 0x08, 0x08 }, 32 { "SPIOEN", 0x08, 0x08 },
@@ -43,7 +43,7 @@ ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
43 0x01, regvalue, cur_col, wrap)); 43 0x01, regvalue, cur_col, wrap));
44} 44}
45 45
46static ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = { 46static const ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = {
47 { "STPWEN", 0x01, 0x01 }, 47 { "STPWEN", 0x01, 0x01 },
48 { "ACTNEGEN", 0x02, 0x02 }, 48 { "ACTNEGEN", 0x02, 0x02 },
49 { "ENSTIMER", 0x04, 0x04 }, 49 { "ENSTIMER", 0x04, 0x04 },
@@ -60,7 +60,7 @@ ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
60 0x02, regvalue, cur_col, wrap)); 60 0x02, regvalue, cur_col, wrap));
61} 61}
62 62
63static ahc_reg_parse_entry_t SCSISIGO_parse_table[] = { 63static const ahc_reg_parse_entry_t SCSISIGO_parse_table[] = {
64 { "ACKO", 0x01, 0x01 }, 64 { "ACKO", 0x01, 0x01 },
65 { "REQO", 0x02, 0x02 }, 65 { "REQO", 0x02, 0x02 },
66 { "BSYO", 0x04, 0x04 }, 66 { "BSYO", 0x04, 0x04 },
@@ -85,7 +85,7 @@ ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
85 0x03, regvalue, cur_col, wrap)); 85 0x03, regvalue, cur_col, wrap));
86} 86}
87 87
88static ahc_reg_parse_entry_t SCSISIGI_parse_table[] = { 88static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
89 { "ACKI", 0x01, 0x01 }, 89 { "ACKI", 0x01, 0x01 },
90 { "REQI", 0x02, 0x02 }, 90 { "REQI", 0x02, 0x02 },
91 { "BSYI", 0x04, 0x04 }, 91 { "BSYI", 0x04, 0x04 },
@@ -112,7 +112,7 @@ ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
112 0x03, regvalue, cur_col, wrap)); 112 0x03, regvalue, cur_col, wrap));
113} 113}
114 114
115static ahc_reg_parse_entry_t SCSIRATE_parse_table[] = { 115static const ahc_reg_parse_entry_t SCSIRATE_parse_table[] = {
116 { "SINGLE_EDGE", 0x10, 0x10 }, 116 { "SINGLE_EDGE", 0x10, 0x10 },
117 { "ENABLE_CRC", 0x40, 0x40 }, 117 { "ENABLE_CRC", 0x40, 0x40 },
118 { "WIDEXFER", 0x80, 0x80 }, 118 { "WIDEXFER", 0x80, 0x80 },
@@ -128,7 +128,7 @@ ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
128 0x04, regvalue, cur_col, wrap)); 128 0x04, regvalue, cur_col, wrap));
129} 129}
130 130
131static ahc_reg_parse_entry_t SCSIID_parse_table[] = { 131static const ahc_reg_parse_entry_t SCSIID_parse_table[] = {
132 { "TWIN_CHNLB", 0x80, 0x80 }, 132 { "TWIN_CHNLB", 0x80, 0x80 },
133 { "OID", 0x0f, 0x0f }, 133 { "OID", 0x0f, 0x0f },
134 { "TWIN_TID", 0x70, 0x70 }, 134 { "TWIN_TID", 0x70, 0x70 },
@@ -151,20 +151,13 @@ ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap)
151} 151}
152 152
153int 153int
154ahc_scsidath_print(u_int regvalue, u_int *cur_col, u_int wrap)
155{
156 return (ahc_print_register(NULL, 0, "SCSIDATH",
157 0x07, regvalue, cur_col, wrap));
158}
159
160int
161ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 154ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
162{ 155{
163 return (ahc_print_register(NULL, 0, "STCNT", 156 return (ahc_print_register(NULL, 0, "STCNT",
164 0x08, regvalue, cur_col, wrap)); 157 0x08, regvalue, cur_col, wrap));
165} 158}
166 159
167static ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = { 160static const ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = {
168 { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 }, 161 { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 },
169 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 162 { "AUTO_MSGOUT_DE", 0x02, 0x02 },
170 { "SCSIDATL_IMGEN", 0x04, 0x04 }, 163 { "SCSIDATL_IMGEN", 0x04, 0x04 },
@@ -190,7 +183,7 @@ ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
190 0x0a, regvalue, cur_col, wrap)); 183 0x0a, regvalue, cur_col, wrap));
191} 184}
192 185
193static ahc_reg_parse_entry_t CLRSINT0_parse_table[] = { 186static const ahc_reg_parse_entry_t CLRSINT0_parse_table[] = {
194 { "CLRSPIORDY", 0x02, 0x02 }, 187 { "CLRSPIORDY", 0x02, 0x02 },
195 { "CLRSWRAP", 0x08, 0x08 }, 188 { "CLRSWRAP", 0x08, 0x08 },
196 { "CLRIOERR", 0x08, 0x08 }, 189 { "CLRIOERR", 0x08, 0x08 },
@@ -206,7 +199,7 @@ ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
206 0x0b, regvalue, cur_col, wrap)); 199 0x0b, regvalue, cur_col, wrap));
207} 200}
208 201
209static ahc_reg_parse_entry_t SSTAT0_parse_table[] = { 202static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
210 { "DMADONE", 0x01, 0x01 }, 203 { "DMADONE", 0x01, 0x01 },
211 { "SPIORDY", 0x02, 0x02 }, 204 { "SPIORDY", 0x02, 0x02 },
212 { "SDONE", 0x04, 0x04 }, 205 { "SDONE", 0x04, 0x04 },
@@ -225,7 +218,7 @@ ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
225 0x0b, regvalue, cur_col, wrap)); 218 0x0b, regvalue, cur_col, wrap));
226} 219}
227 220
228static ahc_reg_parse_entry_t CLRSINT1_parse_table[] = { 221static const ahc_reg_parse_entry_t CLRSINT1_parse_table[] = {
229 { "CLRREQINIT", 0x01, 0x01 }, 222 { "CLRREQINIT", 0x01, 0x01 },
230 { "CLRPHASECHG", 0x02, 0x02 }, 223 { "CLRPHASECHG", 0x02, 0x02 },
231 { "CLRSCSIPERR", 0x04, 0x04 }, 224 { "CLRSCSIPERR", 0x04, 0x04 },
@@ -242,7 +235,7 @@ ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
242 0x0c, regvalue, cur_col, wrap)); 235 0x0c, regvalue, cur_col, wrap));
243} 236}
244 237
245static ahc_reg_parse_entry_t SSTAT1_parse_table[] = { 238static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
246 { "REQINIT", 0x01, 0x01 }, 239 { "REQINIT", 0x01, 0x01 },
247 { "PHASECHG", 0x02, 0x02 }, 240 { "PHASECHG", 0x02, 0x02 },
248 { "SCSIPERR", 0x04, 0x04 }, 241 { "SCSIPERR", 0x04, 0x04 },
@@ -260,7 +253,7 @@ ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
260 0x0c, regvalue, cur_col, wrap)); 253 0x0c, regvalue, cur_col, wrap));
261} 254}
262 255
263static ahc_reg_parse_entry_t SSTAT2_parse_table[] = { 256static const ahc_reg_parse_entry_t SSTAT2_parse_table[] = {
264 { "DUAL_EDGE_ERR", 0x01, 0x01 }, 257 { "DUAL_EDGE_ERR", 0x01, 0x01 },
265 { "CRCREQERR", 0x02, 0x02 }, 258 { "CRCREQERR", 0x02, 0x02 },
266 { "CRCENDERR", 0x04, 0x04 }, 259 { "CRCENDERR", 0x04, 0x04 },
@@ -278,7 +271,7 @@ ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
278 0x0d, regvalue, cur_col, wrap)); 271 0x0d, regvalue, cur_col, wrap));
279} 272}
280 273
281static ahc_reg_parse_entry_t SSTAT3_parse_table[] = { 274static const ahc_reg_parse_entry_t SSTAT3_parse_table[] = {
282 { "OFFCNT", 0x0f, 0x0f }, 275 { "OFFCNT", 0x0f, 0x0f },
283 { "U2OFFCNT", 0x7f, 0x7f }, 276 { "U2OFFCNT", 0x7f, 0x7f },
284 { "SCSICNT", 0xf0, 0xf0 } 277 { "SCSICNT", 0xf0, 0xf0 }
@@ -291,7 +284,7 @@ ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
291 0x0e, regvalue, cur_col, wrap)); 284 0x0e, regvalue, cur_col, wrap));
292} 285}
293 286
294static ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = { 287static const ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = {
295 { "OID", 0x0f, 0x0f }, 288 { "OID", 0x0f, 0x0f },
296 { "TID", 0xf0, 0xf0 } 289 { "TID", 0xf0, 0xf0 }
297}; 290};
@@ -303,7 +296,7 @@ ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap)
303 0x0f, regvalue, cur_col, wrap)); 296 0x0f, regvalue, cur_col, wrap));
304} 297}
305 298
306static ahc_reg_parse_entry_t SIMODE0_parse_table[] = { 299static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
307 { "ENDMADONE", 0x01, 0x01 }, 300 { "ENDMADONE", 0x01, 0x01 },
308 { "ENSPIORDY", 0x02, 0x02 }, 301 { "ENSPIORDY", 0x02, 0x02 },
309 { "ENSDONE", 0x04, 0x04 }, 302 { "ENSDONE", 0x04, 0x04 },
@@ -321,7 +314,7 @@ ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
321 0x10, regvalue, cur_col, wrap)); 314 0x10, regvalue, cur_col, wrap));
322} 315}
323 316
324static ahc_reg_parse_entry_t SIMODE1_parse_table[] = { 317static const ahc_reg_parse_entry_t SIMODE1_parse_table[] = {
325 { "ENREQINIT", 0x01, 0x01 }, 318 { "ENREQINIT", 0x01, 0x01 },
326 { "ENPHASECHG", 0x02, 0x02 }, 319 { "ENPHASECHG", 0x02, 0x02 },
327 { "ENSCSIPERR", 0x04, 0x04 }, 320 { "ENSCSIPERR", 0x04, 0x04 },
@@ -347,33 +340,13 @@ ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
347} 340}
348 341
349int 342int
350ahc_scsibush_print(u_int regvalue, u_int *cur_col, u_int wrap)
351{
352 return (ahc_print_register(NULL, 0, "SCSIBUSH",
353 0x13, regvalue, cur_col, wrap));
354}
355
356static ahc_reg_parse_entry_t SXFRCTL2_parse_table[] = {
357 { "CMDDMAEN", 0x08, 0x08 },
358 { "AUTORSTDIS", 0x10, 0x10 },
359 { "ASYNC_SETUP", 0x07, 0x07 }
360};
361
362int
363ahc_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
364{
365 return (ahc_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
366 0x13, regvalue, cur_col, wrap));
367}
368
369int
370ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 343ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
371{ 344{
372 return (ahc_print_register(NULL, 0, "SHADDR", 345 return (ahc_print_register(NULL, 0, "SHADDR",
373 0x14, regvalue, cur_col, wrap)); 346 0x14, regvalue, cur_col, wrap));
374} 347}
375 348
376static ahc_reg_parse_entry_t SELTIMER_parse_table[] = { 349static const ahc_reg_parse_entry_t SELTIMER_parse_table[] = {
377 { "STAGE1", 0x01, 0x01 }, 350 { "STAGE1", 0x01, 0x01 },
378 { "STAGE2", 0x02, 0x02 }, 351 { "STAGE2", 0x02, 0x02 },
379 { "STAGE3", 0x04, 0x04 }, 352 { "STAGE3", 0x04, 0x04 },
@@ -389,7 +362,7 @@ ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
389 0x18, regvalue, cur_col, wrap)); 362 0x18, regvalue, cur_col, wrap));
390} 363}
391 364
392static ahc_reg_parse_entry_t SELID_parse_table[] = { 365static const ahc_reg_parse_entry_t SELID_parse_table[] = {
393 { "ONEBIT", 0x08, 0x08 }, 366 { "ONEBIT", 0x08, 0x08 },
394 { "SELID_MASK", 0xf0, 0xf0 } 367 { "SELID_MASK", 0xf0, 0xf0 }
395}; 368};
@@ -401,21 +374,6 @@ ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
401 0x19, regvalue, cur_col, wrap)); 374 0x19, regvalue, cur_col, wrap));
402} 375}
403 376
404static ahc_reg_parse_entry_t SCAMCTL_parse_table[] = {
405 { "DFLTTID", 0x10, 0x10 },
406 { "ALTSTIM", 0x20, 0x20 },
407 { "CLRSCAMSELID", 0x40, 0x40 },
408 { "ENSCAMSELO", 0x80, 0x80 },
409 { "SCAMLVL", 0x03, 0x03 }
410};
411
412int
413ahc_scamctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
414{
415 return (ahc_print_register(SCAMCTL_parse_table, 5, "SCAMCTL",
416 0x1a, regvalue, cur_col, wrap));
417}
418
419int 377int
420ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap) 378ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
421{ 379{
@@ -423,7 +381,7 @@ ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
423 0x1b, regvalue, cur_col, wrap)); 381 0x1b, regvalue, cur_col, wrap));
424} 382}
425 383
426static ahc_reg_parse_entry_t SPIOCAP_parse_table[] = { 384static const ahc_reg_parse_entry_t SPIOCAP_parse_table[] = {
427 { "SSPIOCPS", 0x01, 0x01 }, 385 { "SSPIOCPS", 0x01, 0x01 },
428 { "ROM", 0x02, 0x02 }, 386 { "ROM", 0x02, 0x02 },
429 { "EEPROM", 0x04, 0x04 }, 387 { "EEPROM", 0x04, 0x04 },
@@ -441,7 +399,7 @@ ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap)
441 0x1b, regvalue, cur_col, wrap)); 399 0x1b, regvalue, cur_col, wrap));
442} 400}
443 401
444static ahc_reg_parse_entry_t BRDCTL_parse_table[] = { 402static const ahc_reg_parse_entry_t BRDCTL_parse_table[] = {
445 { "BRDCTL0", 0x01, 0x01 }, 403 { "BRDCTL0", 0x01, 0x01 },
446 { "BRDSTB_ULTRA2", 0x01, 0x01 }, 404 { "BRDSTB_ULTRA2", 0x01, 0x01 },
447 { "BRDCTL1", 0x02, 0x02 }, 405 { "BRDCTL1", 0x02, 0x02 },
@@ -464,7 +422,7 @@ ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
464 0x1d, regvalue, cur_col, wrap)); 422 0x1d, regvalue, cur_col, wrap));
465} 423}
466 424
467static ahc_reg_parse_entry_t SEECTL_parse_table[] = { 425static const ahc_reg_parse_entry_t SEECTL_parse_table[] = {
468 { "SEEDI", 0x01, 0x01 }, 426 { "SEEDI", 0x01, 0x01 },
469 { "SEEDO", 0x02, 0x02 }, 427 { "SEEDO", 0x02, 0x02 },
470 { "SEECK", 0x04, 0x04 }, 428 { "SEECK", 0x04, 0x04 },
@@ -482,7 +440,7 @@ ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
482 0x1e, regvalue, cur_col, wrap)); 440 0x1e, regvalue, cur_col, wrap));
483} 441}
484 442
485static ahc_reg_parse_entry_t SBLKCTL_parse_table[] = { 443static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
486 { "XCVR", 0x01, 0x01 }, 444 { "XCVR", 0x01, 0x01 },
487 { "SELWIDE", 0x02, 0x02 }, 445 { "SELWIDE", 0x02, 0x02 },
488 { "ENAB20", 0x04, 0x04 }, 446 { "ENAB20", 0x04, 0x04 },
@@ -522,13 +480,6 @@ ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap)
522} 480}
523 481
524int 482int
525ahc_cmdsize_table_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
526{
527 return (ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL",
528 0x34, regvalue, cur_col, wrap));
529}
530
531int
532ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap) 483ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap)
533{ 484{
534 return (ahc_print_register(NULL, 0, "MWI_RESIDUAL", 485 return (ahc_print_register(NULL, 0, "MWI_RESIDUAL",
@@ -549,7 +500,7 @@ ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
549 0x3a, regvalue, cur_col, wrap)); 500 0x3a, regvalue, cur_col, wrap));
550} 501}
551 502
552static ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = { 503static const ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = {
553 { "FIFORESET", 0x01, 0x01 }, 504 { "FIFORESET", 0x01, 0x01 },
554 { "FIFOFLUSH", 0x02, 0x02 }, 505 { "FIFOFLUSH", 0x02, 0x02 },
555 { "DIRECTION", 0x04, 0x04 }, 506 { "DIRECTION", 0x04, 0x04 },
@@ -569,7 +520,7 @@ ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
569 0x3b, regvalue, cur_col, wrap)); 520 0x3b, regvalue, cur_col, wrap));
570} 521}
571 522
572static ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 523static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
573 { "NO_DISCONNECT", 0x01, 0x01 }, 524 { "NO_DISCONNECT", 0x01, 0x01 },
574 { "SPHASE_PENDING", 0x02, 0x02 }, 525 { "SPHASE_PENDING", 0x02, 0x02 },
575 { "DPHASE_PENDING", 0x04, 0x04 }, 526 { "DPHASE_PENDING", 0x04, 0x04 },
@@ -602,7 +553,7 @@ ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
602 0x3e, regvalue, cur_col, wrap)); 553 0x3e, regvalue, cur_col, wrap));
603} 554}
604 555
605static ahc_reg_parse_entry_t LASTPHASE_parse_table[] = { 556static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
606 { "MSGI", 0x20, 0x20 }, 557 { "MSGI", 0x20, 0x20 },
607 { "IOI", 0x40, 0x40 }, 558 { "IOI", 0x40, 0x40 },
608 { "CDI", 0x80, 0x80 }, 559 { "CDI", 0x80, 0x80 },
@@ -645,13 +596,6 @@ ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
645} 596}
646 597
647int 598int
648ahc_complete_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
649{
650 return (ahc_print_register(NULL, 0, "COMPLETE_SCBH",
651 0x43, regvalue, cur_col, wrap));
652}
653
654int
655ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 599ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
656{ 600{
657 return (ahc_print_register(NULL, 0, "HSCB_ADDR", 601 return (ahc_print_register(NULL, 0, "HSCB_ADDR",
@@ -700,7 +644,7 @@ ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
700 0x50, regvalue, cur_col, wrap)); 644 0x50, regvalue, cur_col, wrap));
701} 645}
702 646
703static ahc_reg_parse_entry_t ARG_1_parse_table[] = { 647static const ahc_reg_parse_entry_t ARG_1_parse_table[] = {
704 { "CONT_TARG_SESSION", 0x02, 0x02 }, 648 { "CONT_TARG_SESSION", 0x02, 0x02 },
705 { "CONT_MSG_LOOP", 0x04, 0x04 }, 649 { "CONT_MSG_LOOP", 0x04, 0x04 },
706 { "EXIT_MSG_LOOP", 0x08, 0x08 }, 650 { "EXIT_MSG_LOOP", 0x08, 0x08 },
@@ -731,7 +675,7 @@ ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
731 0x53, regvalue, cur_col, wrap)); 675 0x53, regvalue, cur_col, wrap));
732} 676}
733 677
734static ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 678static const ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
735 { "ENAUTOATNP", 0x02, 0x02 }, 679 { "ENAUTOATNP", 0x02, 0x02 },
736 { "ENAUTOATNI", 0x04, 0x04 }, 680 { "ENAUTOATNI", 0x04, 0x04 },
737 { "ENAUTOATNO", 0x08, 0x08 }, 681 { "ENAUTOATNO", 0x08, 0x08 },
@@ -747,7 +691,7 @@ ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
747 0x54, regvalue, cur_col, wrap)); 691 0x54, regvalue, cur_col, wrap));
748} 692}
749 693
750static ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = { 694static const ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = {
751 { "HA_274_EXTENDED_TRANS",0x01, 0x01 } 695 { "HA_274_EXTENDED_TRANS",0x01, 0x01 }
752}; 696};
753 697
@@ -758,7 +702,7 @@ ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap)
758 0x56, regvalue, cur_col, wrap)); 702 0x56, regvalue, cur_col, wrap));
759} 703}
760 704
761static ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 705static const ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
762 { "SCB_DMA", 0x01, 0x01 }, 706 { "SCB_DMA", 0x01, 0x01 },
763 { "TARGET_MSG_PENDING", 0x02, 0x02 } 707 { "TARGET_MSG_PENDING", 0x02, 0x02 }
764}; 708};
@@ -770,7 +714,7 @@ ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
770 0x57, regvalue, cur_col, wrap)); 714 0x57, regvalue, cur_col, wrap));
771} 715}
772 716
773static ahc_reg_parse_entry_t SCSICONF_parse_table[] = { 717static const ahc_reg_parse_entry_t SCSICONF_parse_table[] = {
774 { "ENSPCHK", 0x20, 0x20 }, 718 { "ENSPCHK", 0x20, 0x20 },
775 { "RESET_SCSI", 0x40, 0x40 }, 719 { "RESET_SCSI", 0x40, 0x40 },
776 { "TERM_ENB", 0x80, 0x80 }, 720 { "TERM_ENB", 0x80, 0x80 },
@@ -785,7 +729,7 @@ ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
785 0x5a, regvalue, cur_col, wrap)); 729 0x5a, regvalue, cur_col, wrap));
786} 730}
787 731
788static ahc_reg_parse_entry_t INTDEF_parse_table[] = { 732static const ahc_reg_parse_entry_t INTDEF_parse_table[] = {
789 { "EDGE_TRIG", 0x80, 0x80 }, 733 { "EDGE_TRIG", 0x80, 0x80 },
790 { "VECTOR", 0x0f, 0x0f } 734 { "VECTOR", 0x0f, 0x0f }
791}; 735};
@@ -804,7 +748,7 @@ ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
804 0x5d, regvalue, cur_col, wrap)); 748 0x5d, regvalue, cur_col, wrap));
805} 749}
806 750
807static ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = { 751static const ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = {
808 { "CHANNEL_B_PRIMARY", 0x08, 0x08 }, 752 { "CHANNEL_B_PRIMARY", 0x08, 0x08 },
809 { "BIOSMODE", 0x30, 0x30 }, 753 { "BIOSMODE", 0x30, 0x30 },
810 { "BIOSDISABLED", 0x30, 0x30 } 754 { "BIOSDISABLED", 0x30, 0x30 }
@@ -817,7 +761,7 @@ ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
817 0x5f, regvalue, cur_col, wrap)); 761 0x5f, regvalue, cur_col, wrap));
818} 762}
819 763
820static ahc_reg_parse_entry_t SEQCTL_parse_table[] = { 764static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
821 { "LOADRAM", 0x01, 0x01 }, 765 { "LOADRAM", 0x01, 0x01 },
822 { "SEQRESET", 0x02, 0x02 }, 766 { "SEQRESET", 0x02, 0x02 },
823 { "STEP", 0x04, 0x04 }, 767 { "STEP", 0x04, 0x04 },
@@ -849,7 +793,7 @@ ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
849 0x62, regvalue, cur_col, wrap)); 793 0x62, regvalue, cur_col, wrap));
850} 794}
851 795
852static ahc_reg_parse_entry_t SEQADDR1_parse_table[] = { 796static const ahc_reg_parse_entry_t SEQADDR1_parse_table[] = {
853 { "SEQADDR1_MASK", 0x01, 0x01 } 797 { "SEQADDR1_MASK", 0x01, 0x01 }
854}; 798};
855 799
@@ -902,7 +846,7 @@ ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
902 0x6a, regvalue, cur_col, wrap)); 846 0x6a, regvalue, cur_col, wrap));
903} 847}
904 848
905static ahc_reg_parse_entry_t FLAGS_parse_table[] = { 849static const ahc_reg_parse_entry_t FLAGS_parse_table[] = {
906 { "CARRY", 0x01, 0x01 }, 850 { "CARRY", 0x01, 0x01 },
907 { "ZERO", 0x02, 0x02 } 851 { "ZERO", 0x02, 0x02 }
908}; 852};
@@ -929,13 +873,6 @@ ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
929} 873}
930 874
931int 875int
932ahc_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
933{
934 return (ahc_print_register(NULL, 0, "FUNCTION1",
935 0x6e, regvalue, cur_col, wrap));
936}
937
938int
939ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 876ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
940{ 877{
941 return (ahc_print_register(NULL, 0, "STACK", 878 return (ahc_print_register(NULL, 0, "STACK",
@@ -956,19 +893,7 @@ ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
956 0x70, regvalue, cur_col, wrap)); 893 0x70, regvalue, cur_col, wrap));
957} 894}
958 895
959static ahc_reg_parse_entry_t BCTL_parse_table[] = { 896static const ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
960 { "ENABLE", 0x01, 0x01 },
961 { "ACE", 0x08, 0x08 }
962};
963
964int
965ahc_bctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
966{
967 return (ahc_print_register(BCTL_parse_table, 2, "BCTL",
968 0x84, regvalue, cur_col, wrap));
969}
970
971static ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
972 { "CIOPARCKEN", 0x01, 0x01 }, 897 { "CIOPARCKEN", 0x01, 0x01 },
973 { "USCBSIZE32", 0x02, 0x02 }, 898 { "USCBSIZE32", 0x02, 0x02 },
974 { "RAMPS", 0x04, 0x04 }, 899 { "RAMPS", 0x04, 0x04 },
@@ -986,7 +911,7 @@ ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
986 0x84, regvalue, cur_col, wrap)); 911 0x84, regvalue, cur_col, wrap));
987} 912}
988 913
989static ahc_reg_parse_entry_t BUSTIME_parse_table[] = { 914static const ahc_reg_parse_entry_t BUSTIME_parse_table[] = {
990 { "BON", 0x0f, 0x0f }, 915 { "BON", 0x0f, 0x0f },
991 { "BOFF", 0xf0, 0xf0 } 916 { "BOFF", 0xf0, 0xf0 }
992}; 917};
@@ -998,7 +923,7 @@ ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap)
998 0x85, regvalue, cur_col, wrap)); 923 0x85, regvalue, cur_col, wrap));
999} 924}
1000 925
1001static ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = { 926static const ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = {
1002 { "HADDLDSEL0", 0x01, 0x01 }, 927 { "HADDLDSEL0", 0x01, 0x01 },
1003 { "HADDLDSEL1", 0x02, 0x02 }, 928 { "HADDLDSEL1", 0x02, 0x02 },
1004 { "DSLATT", 0xfc, 0xfc } 929 { "DSLATT", 0xfc, 0xfc }
@@ -1011,7 +936,7 @@ ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1011 0x85, regvalue, cur_col, wrap)); 936 0x85, regvalue, cur_col, wrap));
1012} 937}
1013 938
1014static ahc_reg_parse_entry_t BUSSPD_parse_table[] = { 939static const ahc_reg_parse_entry_t BUSSPD_parse_table[] = {
1015 { "STBON", 0x07, 0x07 }, 940 { "STBON", 0x07, 0x07 },
1016 { "STBOFF", 0x38, 0x38 }, 941 { "STBOFF", 0x38, 0x38 },
1017 { "DFTHRSH_75", 0x80, 0x80 }, 942 { "DFTHRSH_75", 0x80, 0x80 },
@@ -1026,7 +951,7 @@ ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap)
1026 0x86, regvalue, cur_col, wrap)); 951 0x86, regvalue, cur_col, wrap));
1027} 952}
1028 953
1029static ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 954static const ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
1030 { "SEQ_MAILBOX", 0x0f, 0x0f }, 955 { "SEQ_MAILBOX", 0x0f, 0x0f },
1031 { "HOST_TQINPOS", 0x80, 0x80 }, 956 { "HOST_TQINPOS", 0x80, 0x80 },
1032 { "HOST_MAILBOX", 0xf0, 0xf0 } 957 { "HOST_MAILBOX", 0xf0, 0xf0 }
@@ -1039,7 +964,7 @@ ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
1039 0x86, regvalue, cur_col, wrap)); 964 0x86, regvalue, cur_col, wrap));
1040} 965}
1041 966
1042static ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = { 967static const ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = {
1043 { "DFTHRSH_100", 0xc0, 0xc0 } 968 { "DFTHRSH_100", 0xc0, 0xc0 }
1044}; 969};
1045 970
@@ -1050,7 +975,7 @@ ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
1050 0x86, regvalue, cur_col, wrap)); 975 0x86, regvalue, cur_col, wrap));
1051} 976}
1052 977
1053static ahc_reg_parse_entry_t HCNTRL_parse_table[] = { 978static const ahc_reg_parse_entry_t HCNTRL_parse_table[] = {
1054 { "CHIPRST", 0x01, 0x01 }, 979 { "CHIPRST", 0x01, 0x01 },
1055 { "CHIPRSTACK", 0x01, 0x01 }, 980 { "CHIPRSTACK", 0x01, 0x01 },
1056 { "INTEN", 0x02, 0x02 }, 981 { "INTEN", 0x02, 0x02 },
@@ -1088,7 +1013,7 @@ ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1088 0x90, regvalue, cur_col, wrap)); 1013 0x90, regvalue, cur_col, wrap));
1089} 1014}
1090 1015
1091static ahc_reg_parse_entry_t INTSTAT_parse_table[] = { 1016static const ahc_reg_parse_entry_t INTSTAT_parse_table[] = {
1092 { "SEQINT", 0x01, 0x01 }, 1017 { "SEQINT", 0x01, 0x01 },
1093 { "CMDCMPLT", 0x02, 0x02 }, 1018 { "CMDCMPLT", 0x02, 0x02 },
1094 { "SCSIINT", 0x04, 0x04 }, 1019 { "SCSIINT", 0x04, 0x04 },
@@ -1119,7 +1044,7 @@ ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1119 0x91, regvalue, cur_col, wrap)); 1044 0x91, regvalue, cur_col, wrap));
1120} 1045}
1121 1046
1122static ahc_reg_parse_entry_t CLRINT_parse_table[] = { 1047static const ahc_reg_parse_entry_t CLRINT_parse_table[] = {
1123 { "CLRSEQINT", 0x01, 0x01 }, 1048 { "CLRSEQINT", 0x01, 0x01 },
1124 { "CLRCMDINT", 0x02, 0x02 }, 1049 { "CLRCMDINT", 0x02, 0x02 },
1125 { "CLRSCSIINT", 0x04, 0x04 }, 1050 { "CLRSCSIINT", 0x04, 0x04 },
@@ -1134,7 +1059,7 @@ ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
1134 0x92, regvalue, cur_col, wrap)); 1059 0x92, regvalue, cur_col, wrap));
1135} 1060}
1136 1061
1137static ahc_reg_parse_entry_t ERROR_parse_table[] = { 1062static const ahc_reg_parse_entry_t ERROR_parse_table[] = {
1138 { "ILLHADDR", 0x01, 0x01 }, 1063 { "ILLHADDR", 0x01, 0x01 },
1139 { "ILLSADDR", 0x02, 0x02 }, 1064 { "ILLSADDR", 0x02, 0x02 },
1140 { "ILLOPCODE", 0x04, 0x04 }, 1065 { "ILLOPCODE", 0x04, 0x04 },
@@ -1152,7 +1077,7 @@ ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
1152 0x92, regvalue, cur_col, wrap)); 1077 0x92, regvalue, cur_col, wrap));
1153} 1078}
1154 1079
1155static ahc_reg_parse_entry_t DFCNTRL_parse_table[] = { 1080static const ahc_reg_parse_entry_t DFCNTRL_parse_table[] = {
1156 { "FIFORESET", 0x01, 0x01 }, 1081 { "FIFORESET", 0x01, 0x01 },
1157 { "FIFOFLUSH", 0x02, 0x02 }, 1082 { "FIFOFLUSH", 0x02, 0x02 },
1158 { "DIRECTION", 0x04, 0x04 }, 1083 { "DIRECTION", 0x04, 0x04 },
@@ -1172,7 +1097,7 @@ ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1172 0x93, regvalue, cur_col, wrap)); 1097 0x93, regvalue, cur_col, wrap));
1173} 1098}
1174 1099
1175static ahc_reg_parse_entry_t DFSTATUS_parse_table[] = { 1100static const ahc_reg_parse_entry_t DFSTATUS_parse_table[] = {
1176 { "FIFOEMP", 0x01, 0x01 }, 1101 { "FIFOEMP", 0x01, 0x01 },
1177 { "FIFOFULL", 0x02, 0x02 }, 1102 { "FIFOFULL", 0x02, 0x02 },
1178 { "DFTHRESH", 0x04, 0x04 }, 1103 { "DFTHRESH", 0x04, 0x04 },
@@ -1198,20 +1123,13 @@ ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1198} 1123}
1199 1124
1200int 1125int
1201ahc_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1202{
1203 return (ahc_print_register(NULL, 0, "DFRADDR",
1204 0x97, regvalue, cur_col, wrap));
1205}
1206
1207int
1208ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1126ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1209{ 1127{
1210 return (ahc_print_register(NULL, 0, "DFDAT", 1128 return (ahc_print_register(NULL, 0, "DFDAT",
1211 0x99, regvalue, cur_col, wrap)); 1129 0x99, regvalue, cur_col, wrap));
1212} 1130}
1213 1131
1214static ahc_reg_parse_entry_t SCBCNT_parse_table[] = { 1132static const ahc_reg_parse_entry_t SCBCNT_parse_table[] = {
1215 { "SCBAUTO", 0x80, 0x80 }, 1133 { "SCBAUTO", 0x80, 0x80 },
1216 { "SCBCNT_MASK", 0x1f, 0x1f } 1134 { "SCBCNT_MASK", 0x1f, 0x1f }
1217}; 1135};
@@ -1231,20 +1149,13 @@ ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1231} 1149}
1232 1150
1233int 1151int
1234ahc_qincnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1235{
1236 return (ahc_print_register(NULL, 0, "QINCNT",
1237 0x9c, regvalue, cur_col, wrap));
1238}
1239
1240int
1241ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) 1152ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1242{ 1153{
1243 return (ahc_print_register(NULL, 0, "QOUTFIFO", 1154 return (ahc_print_register(NULL, 0, "QOUTFIFO",
1244 0x9d, regvalue, cur_col, wrap)); 1155 0x9d, regvalue, cur_col, wrap));
1245} 1156}
1246 1157
1247static ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = { 1158static const ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = {
1248 { "TARGCRCCNTEN", 0x04, 0x04 }, 1159 { "TARGCRCCNTEN", 0x04, 0x04 },
1249 { "TARGCRCENDEN", 0x08, 0x08 }, 1160 { "TARGCRCENDEN", 0x08, 0x08 },
1250 { "CRCREQCHKEN", 0x10, 0x10 }, 1161 { "CRCREQCHKEN", 0x10, 0x10 },
@@ -1260,14 +1171,7 @@ ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1260 0x9d, regvalue, cur_col, wrap)); 1171 0x9d, regvalue, cur_col, wrap));
1261} 1172}
1262 1173
1263int 1174static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
1264ahc_qoutcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1265{
1266 return (ahc_print_register(NULL, 0, "QOUTCNT",
1267 0x9e, regvalue, cur_col, wrap));
1268}
1269
1270static ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
1271 { "DATA_OUT_PHASE", 0x01, 0x01 }, 1175 { "DATA_OUT_PHASE", 0x01, 0x01 },
1272 { "DATA_IN_PHASE", 0x02, 0x02 }, 1176 { "DATA_IN_PHASE", 0x02, 0x02 },
1273 { "MSG_OUT_PHASE", 0x04, 0x04 }, 1177 { "MSG_OUT_PHASE", 0x04, 0x04 },
@@ -1284,7 +1188,7 @@ ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
1284 0x9e, regvalue, cur_col, wrap)); 1188 0x9e, regvalue, cur_col, wrap));
1285} 1189}
1286 1190
1287static ahc_reg_parse_entry_t SFUNCT_parse_table[] = { 1191static const ahc_reg_parse_entry_t SFUNCT_parse_table[] = {
1288 { "ALT_MODE", 0x80, 0x80 } 1192 { "ALT_MODE", 0x80, 0x80 }
1289}; 1193};
1290 1194
@@ -1351,7 +1255,7 @@ ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1351 0xac, regvalue, cur_col, wrap)); 1255 0xac, regvalue, cur_col, wrap));
1352} 1256}
1353 1257
1354static ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 1258static const ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
1355 { "SG_LAST_SEG", 0x80, 0x80 }, 1259 { "SG_LAST_SEG", 0x80, 0x80 },
1356 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f } 1260 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }
1357}; 1261};
@@ -1363,7 +1267,7 @@ ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1363 0xb0, regvalue, cur_col, wrap)); 1267 0xb0, regvalue, cur_col, wrap));
1364} 1268}
1365 1269
1366static ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 1270static const ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
1367 { "SG_LIST_NULL", 0x01, 0x01 }, 1271 { "SG_LIST_NULL", 0x01, 0x01 },
1368 { "SG_FULL_RESID", 0x02, 0x02 }, 1272 { "SG_FULL_RESID", 0x02, 0x02 },
1369 { "SG_RESID_VALID", 0x04, 0x04 } 1273 { "SG_RESID_VALID", 0x04, 0x04 }
@@ -1376,7 +1280,7 @@ ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1376 0xb4, regvalue, cur_col, wrap)); 1280 0xb4, regvalue, cur_col, wrap));
1377} 1281}
1378 1282
1379static ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 1283static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
1380 { "DISCONNECTED", 0x04, 0x04 }, 1284 { "DISCONNECTED", 0x04, 0x04 },
1381 { "ULTRAENB", 0x08, 0x08 }, 1285 { "ULTRAENB", 0x08, 0x08 },
1382 { "MK_MESSAGE", 0x10, 0x10 }, 1286 { "MK_MESSAGE", 0x10, 0x10 },
@@ -1394,7 +1298,7 @@ ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
1394 0xb8, regvalue, cur_col, wrap)); 1298 0xb8, regvalue, cur_col, wrap));
1395} 1299}
1396 1300
1397static ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 1301static const ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
1398 { "TWIN_CHNLB", 0x80, 0x80 }, 1302 { "TWIN_CHNLB", 0x80, 0x80 },
1399 { "OID", 0x0f, 0x0f }, 1303 { "OID", 0x0f, 0x0f },
1400 { "TWIN_TID", 0x70, 0x70 }, 1304 { "TWIN_TID", 0x70, 0x70 },
@@ -1408,7 +1312,7 @@ ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1408 0xb9, regvalue, cur_col, wrap)); 1312 0xb9, regvalue, cur_col, wrap));
1409} 1313}
1410 1314
1411static ahc_reg_parse_entry_t SCB_LUN_parse_table[] = { 1315static const ahc_reg_parse_entry_t SCB_LUN_parse_table[] = {
1412 { "SCB_XFERLEN_ODD", 0x80, 0x80 }, 1316 { "SCB_XFERLEN_ODD", 0x80, 0x80 },
1413 { "LID", 0x3f, 0x3f } 1317 { "LID", 0x3f, 0x3f }
1414}; 1318};
@@ -1455,14 +1359,7 @@ ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
1455 0xbf, regvalue, cur_col, wrap)); 1359 0xbf, regvalue, cur_col, wrap));
1456} 1360}
1457 1361
1458int 1362static const ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
1459ahc_scb_64_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
1460{
1461 return (ahc_print_register(NULL, 0, "SCB_64_SPARE",
1462 0xc0, regvalue, cur_col, wrap));
1463}
1464
1465static ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
1466 { "DO_2840", 0x01, 0x01 }, 1363 { "DO_2840", 0x01, 0x01 },
1467 { "CK_2840", 0x02, 0x02 }, 1364 { "CK_2840", 0x02, 0x02 },
1468 { "CS_2840", 0x04, 0x04 } 1365 { "CS_2840", 0x04, 0x04 }
@@ -1475,7 +1372,7 @@ ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
1475 0xc0, regvalue, cur_col, wrap)); 1372 0xc0, regvalue, cur_col, wrap));
1476} 1373}
1477 1374
1478static ahc_reg_parse_entry_t STATUS_2840_parse_table[] = { 1375static const ahc_reg_parse_entry_t STATUS_2840_parse_table[] = {
1479 { "DI_2840", 0x01, 0x01 }, 1376 { "DI_2840", 0x01, 0x01 },
1480 { "EEPROM_TF", 0x80, 0x80 }, 1377 { "EEPROM_TF", 0x80, 0x80 },
1481 { "ADSEL", 0x1e, 0x1e }, 1378 { "ADSEL", 0x1e, 0x1e },
@@ -1524,7 +1421,7 @@ ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1524 0xea, regvalue, cur_col, wrap)); 1421 0xea, regvalue, cur_col, wrap));
1525} 1422}
1526 1423
1527static ahc_reg_parse_entry_t CCSGCTL_parse_table[] = { 1424static const ahc_reg_parse_entry_t CCSGCTL_parse_table[] = {
1528 { "CCSGRESET", 0x01, 0x01 }, 1425 { "CCSGRESET", 0x01, 0x01 },
1529 { "SG_FETCH_NEEDED", 0x02, 0x02 }, 1426 { "SG_FETCH_NEEDED", 0x02, 0x02 },
1530 { "CCSGEN", 0x08, 0x08 }, 1427 { "CCSGEN", 0x08, 0x08 },
@@ -1552,7 +1449,7 @@ ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1552 0xed, regvalue, cur_col, wrap)); 1449 0xed, regvalue, cur_col, wrap));
1553} 1450}
1554 1451
1555static ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = { 1452static const ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = {
1556 { "CCSCBRESET", 0x01, 0x01 }, 1453 { "CCSCBRESET", 0x01, 0x01 },
1557 { "CCSCBDIR", 0x04, 0x04 }, 1454 { "CCSCBDIR", 0x04, 0x04 },
1558 { "CCSCBEN", 0x08, 0x08 }, 1455 { "CCSCBEN", 0x08, 0x08 },
@@ -1610,7 +1507,7 @@ ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1610 0xf8, regvalue, cur_col, wrap)); 1507 0xf8, regvalue, cur_col, wrap));
1611} 1508}
1612 1509
1613static ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 1510static const ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
1614 { "SDSCB_ROLLOVER", 0x10, 0x10 }, 1511 { "SDSCB_ROLLOVER", 0x10, 0x10 },
1615 { "SNSCB_ROLLOVER", 0x20, 0x20 }, 1512 { "SNSCB_ROLLOVER", 0x20, 0x20 },
1616 { "SCB_AVAIL", 0x40, 0x40 }, 1513 { "SCB_AVAIL", 0x40, 0x40 },
@@ -1625,7 +1522,7 @@ ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
1625 0xfa, regvalue, cur_col, wrap)); 1522 0xfa, regvalue, cur_col, wrap));
1626} 1523}
1627 1524
1628static ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = { 1525static const ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1629 { "RD_DFTHRSH_MIN", 0x00, 0x00 }, 1526 { "RD_DFTHRSH_MIN", 0x00, 0x00 },
1630 { "WR_DFTHRSH_MIN", 0x00, 0x00 }, 1527 { "WR_DFTHRSH_MIN", 0x00, 0x00 },
1631 { "RD_DFTHRSH_25", 0x01, 0x01 }, 1528 { "RD_DFTHRSH_25", 0x01, 0x01 },
@@ -1653,7 +1550,7 @@ ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1653 0xfb, regvalue, cur_col, wrap)); 1550 0xfb, regvalue, cur_col, wrap));
1654} 1551}
1655 1552
1656static ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 1553static const ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
1657 { "LAST_SEG_DONE", 0x01, 0x01 }, 1554 { "LAST_SEG_DONE", 0x01, 0x01 },
1658 { "LAST_SEG", 0x02, 0x02 }, 1555 { "LAST_SEG", 0x02, 0x02 },
1659 { "SG_ADDR_MASK", 0xf8, 0xf8 } 1556 { "SG_ADDR_MASK", 0xf8, 0xf8 }
@@ -1666,7 +1563,7 @@ ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
1666 0xfc, regvalue, cur_col, wrap)); 1563 0xfc, regvalue, cur_col, wrap));
1667} 1564}
1668 1565
1669static ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { 1566static const ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
1670 { "LAST_SEG_DONE", 0x01, 0x01 }, 1567 { "LAST_SEG_DONE", 0x01, 0x01 },
1671 { "LAST_SEG", 0x02, 0x02 }, 1568 { "LAST_SEG", 0x02, 0x02 },
1672 { "SG_ADDR_MASK", 0xf8, 0xf8 } 1569 { "SG_ADDR_MASK", 0xf8, 0xf8 }
diff --git a/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped b/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped
index 4cee08521e75..07e93fbae706 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped
+++ b/drivers/scsi/aic7xxx/aic7xxx_seq.h_shipped
@@ -5,7 +5,7 @@
5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $ 5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
7 */ 7 */
8static uint8_t seqprog[] = { 8static const uint8_t seqprog[] = {
9 0xb2, 0x00, 0x00, 0x08, 9 0xb2, 0x00, 0x00, 0x08,
10 0xf7, 0x11, 0x22, 0x08, 10 0xf7, 0x11, 0x22, 0x08,
11 0x00, 0x65, 0xee, 0x59, 11 0x00, 0x65, 0xee, 0x59,
@@ -1081,7 +1081,7 @@ ahc_patch0_func(struct ahc_softc *ahc)
1081 return (0); 1081 return (0);
1082} 1082}
1083 1083
1084static struct patch { 1084static const struct patch {
1085 ahc_patch_func_t *patch_func; 1085 ahc_patch_func_t *patch_func;
1086 uint32_t begin :10, 1086 uint32_t begin :10,
1087 skip_instr :10, 1087 skip_instr :10,
@@ -1291,7 +1291,7 @@ static struct patch {
1291 { ahc_patch4_func, 865, 12, 1 } 1291 { ahc_patch4_func, 865, 12, 1 }
1292}; 1292};
1293 1293
1294static struct cs { 1294static const struct cs {
1295 uint16_t begin; 1295 uint16_t begin;
1296 uint16_t end; 1296 uint16_t end;
1297} critical_sections[] = { 1297} critical_sections[] = {
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm.c b/drivers/scsi/aic7xxx/aicasm/aicasm.c
index 924102720b14..e4a778720301 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm.c
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm.c
@@ -362,7 +362,7 @@ output_code()
362" *\n" 362" *\n"
363"%s */\n", versions); 363"%s */\n", versions);
364 364
365 fprintf(ofile, "static uint8_t seqprog[] = {\n"); 365 fprintf(ofile, "static const uint8_t seqprog[] = {\n");
366 for (cur_instr = STAILQ_FIRST(&seq_program); 366 for (cur_instr = STAILQ_FIRST(&seq_program);
367 cur_instr != NULL; 367 cur_instr != NULL;
368 cur_instr = STAILQ_NEXT(cur_instr, links)) { 368 cur_instr = STAILQ_NEXT(cur_instr, links)) {
@@ -415,7 +415,7 @@ output_code()
415 } 415 }
416 416
417 fprintf(ofile, 417 fprintf(ofile,
418"static struct patch {\n" 418"static const struct patch {\n"
419" %spatch_func_t *patch_func;\n" 419" %spatch_func_t *patch_func;\n"
420" uint32_t begin :10,\n" 420" uint32_t begin :10,\n"
421" skip_instr :10,\n" 421" skip_instr :10,\n"
@@ -435,7 +435,7 @@ output_code()
435 fprintf(ofile, "\n};\n\n"); 435 fprintf(ofile, "\n};\n\n");
436 436
437 fprintf(ofile, 437 fprintf(ofile,
438"static struct cs {\n" 438"static const struct cs {\n"
439" uint16_t begin;\n" 439" uint16_t begin;\n"
440" uint16_t end;\n" 440" uint16_t end;\n"
441"} critical_sections[] = {\n"); 441"} critical_sections[] = {\n");
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y b/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y
index 702e2dbd11fb..81be6a261cc8 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y
@@ -101,11 +101,12 @@ static void format_3_instr(int opcode, symbol_ref_t *src,
101 expression_t *immed, symbol_ref_t *address); 101 expression_t *immed, symbol_ref_t *address);
102static void test_readable_symbol(symbol_t *symbol); 102static void test_readable_symbol(symbol_t *symbol);
103static void test_writable_symbol(symbol_t *symbol); 103static void test_writable_symbol(symbol_t *symbol);
104static void type_check(symbol_t *symbol, expression_t *expression, int and_op); 104static void type_check(symbol_ref_t *sym, expression_t *expression, int and_op);
105static void make_expression(expression_t *immed, int value); 105static void make_expression(expression_t *immed, int value);
106static void add_conditional(symbol_t *symbol); 106static void add_conditional(symbol_t *symbol);
107static void add_version(const char *verstring); 107static void add_version(const char *verstring);
108static int is_download_const(expression_t *immed); 108static int is_download_const(expression_t *immed);
109static int is_location_address(symbol_t *symbol);
109void yyerror(const char *string); 110void yyerror(const char *string);
110 111
111#define SRAM_SYMNAME "SRAM_BASE" 112#define SRAM_SYMNAME "SRAM_BASE"
@@ -142,6 +143,8 @@ void yyerror(const char *string);
142 143
143%token <value> T_ADDRESS 144%token <value> T_ADDRESS
144 145
146%token T_COUNT
147
145%token T_ACCESS_MODE 148%token T_ACCESS_MODE
146 149
147%token T_MODES 150%token T_MODES
@@ -192,10 +195,10 @@ void yyerror(const char *string);
192 195
193%token <value> T_OR 196%token <value> T_OR
194 197
195/* 16 bit extensions */ 198/* 16 bit extensions, not implemented
196%token <value> T_OR16 T_AND16 T_XOR16 T_ADD16 199 * %token <value> T_OR16 T_AND16 T_XOR16 T_ADD16
197%token <value> T_ADC16 T_MVI16 T_TEST16 T_CMP16 T_CMPXCHG 200 * %token <value> T_ADC16 T_MVI16 T_TEST16 T_CMP16 T_CMPXCHG
198 201 */
199%token T_RET 202%token T_RET
200 203
201%token T_NOP 204%token T_NOP
@@ -214,7 +217,7 @@ void yyerror(const char *string);
214 217
215%type <expression> expression immediate immediate_or_a 218%type <expression> expression immediate immediate_or_a
216 219
217%type <value> export ret f1_opcode f2_opcode f4_opcode jmp_jc_jnc_call jz_jnz je_jne 220%type <value> export ret f1_opcode f2_opcode jmp_jc_jnc_call jz_jnz je_jne
218 221
219%type <value> mode_value mode_list macro_arglist 222%type <value> mode_value mode_list macro_arglist
220 223
@@ -313,13 +316,13 @@ reg_definition:
313 stop("Register multiply defined", EX_DATAERR); 316 stop("Register multiply defined", EX_DATAERR);
314 /* NOTREACHED */ 317 /* NOTREACHED */
315 } 318 }
316 cur_symbol = $1; 319 cur_symbol = $1;
317 cur_symbol->type = cur_symtype; 320 cur_symbol->type = cur_symtype;
318 initialize_symbol(cur_symbol); 321 initialize_symbol(cur_symbol);
319 } 322 }
320 reg_attribute_list 323 reg_attribute_list
321 '}' 324 '}'
322 { 325 {
323 /* 326 /*
324 * Default to allowing everything in for registers 327 * Default to allowing everything in for registers
325 * with no bit or mask definitions. 328 * with no bit or mask definitions.
@@ -349,9 +352,10 @@ reg_attribute_list:
349| reg_attribute_list reg_attribute 352| reg_attribute_list reg_attribute
350; 353;
351 354
352reg_attribute: 355reg_attribute:
353 reg_address 356 reg_address
354| size 357| size
358| count
355| access_mode 359| access_mode
356| modes 360| modes
357| field_defn 361| field_defn
@@ -392,6 +396,13 @@ size:
392 } 396 }
393; 397;
394 398
399count:
400 T_COUNT T_NUMBER
401 {
402 cur_symbol->count += $2;
403 }
404;
405
395access_mode: 406access_mode:
396 T_ACCESS_MODE T_MODE 407 T_ACCESS_MODE T_MODE
397 { 408 {
@@ -641,14 +652,14 @@ expression:
641 &($1.referenced_syms), 652 &($1.referenced_syms),
642 &($3.referenced_syms)); 653 &($3.referenced_syms));
643 } 654 }
644| expression T_EXPR_LSHIFT expression 655| expression T_EXPR_LSHIFT expression
645 { 656 {
646 $$.value = $1.value << $3.value; 657 $$.value = $1.value << $3.value;
647 symlist_merge(&$$.referenced_syms, 658 symlist_merge(&$$.referenced_syms,
648 &$1.referenced_syms, 659 &$1.referenced_syms,
649 &$3.referenced_syms); 660 &$3.referenced_syms);
650 } 661 }
651| expression T_EXPR_RSHIFT expression 662| expression T_EXPR_RSHIFT expression
652 { 663 {
653 $$.value = $1.value >> $3.value; 664 $$.value = $1.value >> $3.value;
654 symlist_merge(&$$.referenced_syms, 665 symlist_merge(&$$.referenced_syms,
@@ -714,7 +725,7 @@ expression:
714; 725;
715 726
716constant: 727constant:
717 T_CONST T_SYMBOL expression 728 T_CONST T_SYMBOL expression
718 { 729 {
719 if ($2->type != UNINITIALIZED) { 730 if ($2->type != UNINITIALIZED) {
720 stop("Re-definition of symbol as a constant", 731 stop("Re-definition of symbol as a constant",
@@ -800,6 +811,7 @@ scratch_ram:
800 cur_symtype = SRAMLOC; 811 cur_symtype = SRAMLOC;
801 cur_symbol->type = SRAMLOC; 812 cur_symbol->type = SRAMLOC;
802 initialize_symbol(cur_symbol); 813 initialize_symbol(cur_symbol);
814 cur_symbol->count += 1;
803 } 815 }
804 reg_address 816 reg_address
805 { 817 {
@@ -831,6 +843,7 @@ scb:
831 initialize_symbol(cur_symbol); 843 initialize_symbol(cur_symbol);
832 /* 64 bytes of SCB space */ 844 /* 64 bytes of SCB space */
833 cur_symbol->info.rinfo->size = 64; 845 cur_symbol->info.rinfo->size = 64;
846 cur_symbol->count += 1;
834 } 847 }
835 reg_address 848 reg_address
836 { 849 {
@@ -1311,14 +1324,18 @@ f2_opcode:
1311| T_ROR { $$ = AIC_OP_ROR; } 1324| T_ROR { $$ = AIC_OP_ROR; }
1312; 1325;
1313 1326
1314f4_opcode: 1327/*
1315 T_OR16 { $$ = AIC_OP_OR16; } 1328 * 16bit opcodes, not used
1316| T_AND16 { $$ = AIC_OP_AND16; } 1329 *
1317| T_XOR16 { $$ = AIC_OP_XOR16; } 1330 *f4_opcode:
1318| T_ADD16 { $$ = AIC_OP_ADD16; } 1331 * T_OR16 { $$ = AIC_OP_OR16; }
1319| T_ADC16 { $$ = AIC_OP_ADC16; } 1332 *| T_AND16 { $$ = AIC_OP_AND16; }
1320| T_MVI16 { $$ = AIC_OP_MVI16; } 1333 *| T_XOR16 { $$ = AIC_OP_XOR16; }
1321; 1334 *| T_ADD16 { $$ = AIC_OP_ADD16; }
1335 *| T_ADC16 { $$ = AIC_OP_ADC16; }
1336 *| T_MVI16 { $$ = AIC_OP_MVI16; }
1337 *;
1338 */
1322 1339
1323code: 1340code:
1324 f2_opcode destination ',' expression opt_source ret ';' 1341 f2_opcode destination ',' expression opt_source ret ';'
@@ -1357,6 +1374,7 @@ code:
1357code: 1374code:
1358 T_OR reg_symbol ',' immediate jmp_jc_jnc_call address ';' 1375 T_OR reg_symbol ',' immediate jmp_jc_jnc_call address ';'
1359 { 1376 {
1377 type_check(&$2, &$4, AIC_OP_OR);
1360 format_3_instr($5, &$2, &$4, &$6); 1378 format_3_instr($5, &$2, &$4, &$6);
1361 } 1379 }
1362; 1380;
@@ -1528,7 +1546,7 @@ initialize_symbol(symbol_t *symbol)
1528 sizeof(struct cond_info)); 1546 sizeof(struct cond_info));
1529 break; 1547 break;
1530 case MACRO: 1548 case MACRO:
1531 symbol->info.macroinfo = 1549 symbol->info.macroinfo =
1532 (struct macro_info *)malloc(sizeof(struct macro_info)); 1550 (struct macro_info *)malloc(sizeof(struct macro_info));
1533 if (symbol->info.macroinfo == NULL) { 1551 if (symbol->info.macroinfo == NULL) {
1534 stop("Can't create macro info", EX_SOFTWARE); 1552 stop("Can't create macro info", EX_SOFTWARE);
@@ -1552,7 +1570,6 @@ add_macro_arg(const char *argtext, int argnum)
1552 struct macro_arg *marg; 1570 struct macro_arg *marg;
1553 int i; 1571 int i;
1554 int retval; 1572 int retval;
1555
1556 1573
1557 if (cur_symbol == NULL || cur_symbol->type != MACRO) { 1574 if (cur_symbol == NULL || cur_symbol->type != MACRO) {
1558 stop("Invalid current symbol for adding macro arg", 1575 stop("Invalid current symbol for adding macro arg",
@@ -1633,8 +1650,10 @@ format_1_instr(int opcode, symbol_ref_t *dest, expression_t *immed,
1633 test_writable_symbol(dest->symbol); 1650 test_writable_symbol(dest->symbol);
1634 test_readable_symbol(src->symbol); 1651 test_readable_symbol(src->symbol);
1635 1652
1636 /* Ensure that immediate makes sense for this destination */ 1653 if (!is_location_address(dest->symbol)) {
1637 type_check(dest->symbol, immed, opcode); 1654 /* Ensure that immediate makes sense for this destination */
1655 type_check(dest, immed, opcode);
1656 }
1638 1657
1639 /* Allocate sequencer space for the instruction and fill it out */ 1658 /* Allocate sequencer space for the instruction and fill it out */
1640 instr = seq_alloc(); 1659 instr = seq_alloc();
@@ -1766,9 +1785,6 @@ format_3_instr(int opcode, symbol_ref_t *src,
1766 /* Test register permissions */ 1785 /* Test register permissions */
1767 test_readable_symbol(src->symbol); 1786 test_readable_symbol(src->symbol);
1768 1787
1769 /* Ensure that immediate makes sense for this source */
1770 type_check(src->symbol, immed, opcode);
1771
1772 /* Allocate sequencer space for the instruction and fill it out */ 1788 /* Allocate sequencer space for the instruction and fill it out */
1773 instr = seq_alloc(); 1789 instr = seq_alloc();
1774 f3_instr = &instr->format.format3; 1790 f3_instr = &instr->format.format3;
@@ -1797,7 +1813,6 @@ format_3_instr(int opcode, symbol_ref_t *src,
1797static void 1813static void
1798test_readable_symbol(symbol_t *symbol) 1814test_readable_symbol(symbol_t *symbol)
1799{ 1815{
1800
1801 if ((symbol->info.rinfo->modes & (0x1 << src_mode)) == 0) { 1816 if ((symbol->info.rinfo->modes & (0x1 << src_mode)) == 0) {
1802 snprintf(errbuf, sizeof(errbuf), 1817 snprintf(errbuf, sizeof(errbuf),
1803 "Register %s unavailable in source reg mode %d", 1818 "Register %s unavailable in source reg mode %d",
@@ -1815,7 +1830,6 @@ test_readable_symbol(symbol_t *symbol)
1815static void 1830static void
1816test_writable_symbol(symbol_t *symbol) 1831test_writable_symbol(symbol_t *symbol)
1817{ 1832{
1818
1819 if ((symbol->info.rinfo->modes & (0x1 << dst_mode)) == 0) { 1833 if ((symbol->info.rinfo->modes & (0x1 << dst_mode)) == 0) {
1820 snprintf(errbuf, sizeof(errbuf), 1834 snprintf(errbuf, sizeof(errbuf),
1821 "Register %s unavailable in destination reg mode %d", 1835 "Register %s unavailable in destination reg mode %d",
@@ -1831,25 +1845,34 @@ test_writable_symbol(symbol_t *symbol)
1831} 1845}
1832 1846
1833static void 1847static void
1834type_check(symbol_t *symbol, expression_t *expression, int opcode) 1848type_check(symbol_ref_t *sym, expression_t *expression, int opcode)
1835{ 1849{
1850 symbol_t *symbol = sym->symbol;
1836 symbol_node_t *node; 1851 symbol_node_t *node;
1837 int and_op; 1852 int and_op;
1853 int8_t value, mask;
1838 1854
1839 and_op = FALSE; 1855 and_op = FALSE;
1840 if (opcode == AIC_OP_AND || opcode == AIC_OP_JNZ || opcode == AIC_OP_JZ)
1841 and_op = TRUE;
1842
1843 /* 1856 /*
1844 * Make sure that we aren't attempting to write something 1857 * Make sure that we aren't attempting to write something
1845 * that hasn't been defined. If this is an and operation, 1858 * that hasn't been defined. If this is an and operation,
1846 * this is a mask, so "undefined" bits are okay. 1859 * this is a mask, so "undefined" bits are okay.
1847 */ 1860 */
1848 if (and_op == FALSE 1861 if (opcode == AIC_OP_AND || opcode == AIC_OP_JNZ ||
1849 && (expression->value & ~symbol->info.rinfo->valid_bitmask) != 0) { 1862 opcode == AIC_OP_JZ || opcode == AIC_OP_JNE ||
1863 opcode == AIC_OP_BMOV)
1864 and_op = TRUE;
1865
1866 /*
1867 * Defaulting to 8 bit logic
1868 */
1869 mask = (int8_t)~symbol->info.rinfo->valid_bitmask;
1870 value = (int8_t)expression->value;
1871
1872 if (and_op == FALSE && (mask & value) != 0 ) {
1850 snprintf(errbuf, sizeof(errbuf), 1873 snprintf(errbuf, sizeof(errbuf),
1851 "Invalid bit(s) 0x%x in immediate written to %s", 1874 "Invalid bit(s) 0x%x in immediate written to %s",
1852 expression->value & ~symbol->info.rinfo->valid_bitmask, 1875 (mask & value),
1853 symbol->name); 1876 symbol->name);
1854 stop(errbuf, EX_DATAERR); 1877 stop(errbuf, EX_DATAERR);
1855 /* NOTREACHED */ 1878 /* NOTREACHED */
@@ -1959,3 +1982,13 @@ is_download_const(expression_t *immed)
1959 1982
1960 return (FALSE); 1983 return (FALSE);
1961} 1984}
1985
1986static int
1987is_location_address(symbol_t *sym)
1988{
1989 if (sym->type == SCBLOC ||
1990 sym->type == SRAMLOC)
1991 return (TRUE);
1992 return (FALSE);
1993}
1994
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l b/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l
index 7c3983f868a9..2c7f02daf88d 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l
@@ -162,6 +162,7 @@ register { return T_REGISTER; }
162const { yylval.value = FALSE; return T_CONST; } 162const { yylval.value = FALSE; return T_CONST; }
163download { return T_DOWNLOAD; } 163download { return T_DOWNLOAD; }
164address { return T_ADDRESS; } 164address { return T_ADDRESS; }
165count { return T_COUNT; }
165access_mode { return T_ACCESS_MODE; } 166access_mode { return T_ACCESS_MODE; }
166modes { return T_MODES; } 167modes { return T_MODES; }
167RW|RO|WO { 168RW|RO|WO {
@@ -228,15 +229,15 @@ ret { return T_RET; }
228nop { return T_NOP; } 229nop { return T_NOP; }
229 230
230 /* ARP2 16bit extensions */ 231 /* ARP2 16bit extensions */
231or16 { return T_OR16; } 232 /* or16 { return T_OR16; } */
232and16 { return T_AND16; } 233 /* and16 { return T_AND16; }*/
233xor16 { return T_XOR16; } 234 /* xor16 { return T_XOR16; }*/
234add16 { return T_ADD16; } 235 /* add16 { return T_ADD16; }*/
235adc16 { return T_ADC16; } 236 /* adc16 { return T_ADC16; }*/
236mvi16 { return T_MVI16; } 237 /* mvi16 { return T_MVI16; }*/
237test16 { return T_TEST16; } 238 /* test16 { return T_TEST16; }*/
238cmp16 { return T_CMP16; } 239 /* cmp16 { return T_CMP16; }*/
239cmpxchg { return T_CMPXCHG; } 240 /* cmpxchg { return T_CMPXCHG; }*/
240 241
241 /* Allowed Symbols */ 242 /* Allowed Symbols */
242\<\< { return T_EXPR_LSHIFT; } 243\<\< { return T_EXPR_LSHIFT; }
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c
index f1f448dff569..fcd357872b43 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c
@@ -77,6 +77,7 @@ symbol_create(char *name)
77 if (new_symbol->name == NULL) 77 if (new_symbol->name == NULL)
78 stop("Unable to strdup symbol name", EX_SOFTWARE); 78 stop("Unable to strdup symbol name", EX_SOFTWARE);
79 new_symbol->type = UNINITIALIZED; 79 new_symbol->type = UNINITIALIZED;
80 new_symbol->count = 1;
80 return (new_symbol); 81 return (new_symbol);
81} 82}
82 83
@@ -198,6 +199,12 @@ symtable_get(char *name)
198 } 199 }
199 } 200 }
200 memcpy(&stored_ptr, data.data, sizeof(stored_ptr)); 201 memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
202 stored_ptr->count++;
203 data.data = &stored_ptr;
204 if (symtable->put(symtable, &key, &data, /*flags*/0) !=0) {
205 perror("Symtable put failed");
206 exit(EX_SOFTWARE);
207 }
201 return (stored_ptr); 208 return (stored_ptr);
202} 209}
203 210
@@ -256,7 +263,7 @@ symlist_add(symlist_t *symlist, symbol_t *symbol, int how)
256 && (curnode->symbol->info.finfo->value > 263 && (curnode->symbol->info.finfo->value >
257 newnode->symbol->info.finfo->value)))) 264 newnode->symbol->info.finfo->value))))
258 || (!field && (curnode->symbol->info.rinfo->address > 265 || (!field && (curnode->symbol->info.rinfo->address >
259 newnode->symbol->info.rinfo->address))) { 266 newnode->symbol->info.rinfo->address))) {
260 SLIST_INSERT_HEAD(symlist, newnode, links); 267 SLIST_INSERT_HEAD(symlist, newnode, links);
261 return; 268 return;
262 } 269 }
@@ -271,7 +278,7 @@ symlist_add(symlist_t *symlist, symbol_t *symbol, int how)
271 278
272 cursymbol = SLIST_NEXT(curnode, links)->symbol; 279 cursymbol = SLIST_NEXT(curnode, links)->symbol;
273 if ((field 280 if ((field
274 && (cursymbol->type > symbol->type 281 && (cursymbol->type > symbol->type
275 || (cursymbol->type == symbol->type 282 || (cursymbol->type == symbol->type
276 && (cursymbol->info.finfo->value > 283 && (cursymbol->info.finfo->value >
277 symbol->info.finfo->value)))) 284 symbol->info.finfo->value))))
@@ -351,7 +358,7 @@ aic_print_reg_dump_types(FILE *ofile)
351{ 358{
352 if (ofile == NULL) 359 if (ofile == NULL)
353 return; 360 return;
354 361
355 fprintf(ofile, 362 fprintf(ofile,
356"typedef int (%sreg_print_t)(u_int, u_int *, u_int);\n" 363"typedef int (%sreg_print_t)(u_int, u_int *, u_int);\n"
357"typedef struct %sreg_parse_entry {\n" 364"typedef struct %sreg_parse_entry {\n"
@@ -370,7 +377,7 @@ aic_print_reg_dump_start(FILE *dfile, symbol_node_t *regnode)
370 return; 377 return;
371 378
372 fprintf(dfile, 379 fprintf(dfile,
373"static %sreg_parse_entry_t %s_parse_table[] = {\n", 380"static const %sreg_parse_entry_t %s_parse_table[] = {\n",
374 prefix, 381 prefix,
375 regnode->symbol->name); 382 regnode->symbol->name);
376} 383}
@@ -385,7 +392,7 @@ aic_print_reg_dump_end(FILE *ofile, FILE *dfile,
385 lower_name = strdup(regnode->symbol->name); 392 lower_name = strdup(regnode->symbol->name);
386 if (lower_name == NULL) 393 if (lower_name == NULL)
387 stop("Unable to strdup symbol name", EX_SOFTWARE); 394 stop("Unable to strdup symbol name", EX_SOFTWARE);
388 395
389 for (letter = lower_name; *letter != '\0'; letter++) 396 for (letter = lower_name; *letter != '\0'; letter++)
390 *letter = tolower(*letter); 397 *letter = tolower(*letter);
391 398
@@ -472,6 +479,7 @@ symtable_dump(FILE *ofile, FILE *dfile)
472 DBT key; 479 DBT key;
473 DBT data; 480 DBT data;
474 int flag; 481 int flag;
482 int reg_count = 0, reg_used = 0;
475 u_int i; 483 u_int i;
476 484
477 if (symtable == NULL) 485 if (symtable == NULL)
@@ -541,6 +549,9 @@ symtable_dump(FILE *ofile, FILE *dfile)
541 int num_entries; 549 int num_entries;
542 550
543 num_entries = 0; 551 num_entries = 0;
552 reg_count++;
553 if (curnode->symbol->count == 1)
554 break;
544 fields = &curnode->symbol->info.rinfo->fields; 555 fields = &curnode->symbol->info.rinfo->fields;
545 SLIST_FOREACH(fieldnode, fields, links) { 556 SLIST_FOREACH(fieldnode, fields, links) {
546 if (num_entries == 0) 557 if (num_entries == 0)
@@ -553,11 +564,14 @@ symtable_dump(FILE *ofile, FILE *dfile)
553 } 564 }
554 aic_print_reg_dump_end(ofile, dfile, 565 aic_print_reg_dump_end(ofile, dfile,
555 curnode, num_entries); 566 curnode, num_entries);
567 reg_used++;
556 } 568 }
557 default: 569 default:
558 break; 570 break;
559 } 571 }
560 } 572 }
573 fprintf(stderr, "%s: %d of %d register definitions used\n", appname,
574 reg_used, reg_count);
561 575
562 /* Fold in the masks and bits */ 576 /* Fold in the masks and bits */
563 while (SLIST_FIRST(&masks) != NULL) { 577 while (SLIST_FIRST(&masks) != NULL) {
@@ -646,7 +660,6 @@ symtable_dump(FILE *ofile, FILE *dfile)
646 free(curnode); 660 free(curnode);
647 } 661 }
648 662
649
650 fprintf(ofile, "\n\n/* Downloaded Constant Definitions */\n"); 663 fprintf(ofile, "\n\n/* Downloaded Constant Definitions */\n");
651 664
652 for (i = 0; SLIST_FIRST(&download_constants) != NULL; i++) { 665 for (i = 0; SLIST_FIRST(&download_constants) != NULL; i++) {
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h
index afc22e8b4903..05190c1a2fb7 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h
@@ -128,6 +128,7 @@ typedef struct expression_info {
128typedef struct symbol { 128typedef struct symbol {
129 char *name; 129 char *name;
130 symtype type; 130 symtype type;
131 int count;
131 union { 132 union {
132 struct reg_info *rinfo; 133 struct reg_info *rinfo;
133 struct field_info *finfo; 134 struct field_info *finfo;
diff --git a/drivers/scsi/eata.c b/drivers/scsi/eata.c
index 8be3d76656fa..a73a6bbb1b2b 100644
--- a/drivers/scsi/eata.c
+++ b/drivers/scsi/eata.c
@@ -2286,17 +2286,14 @@ static void flush_dev(struct scsi_device *dev, unsigned long cursec,
2286 } 2286 }
2287} 2287}
2288 2288
2289static irqreturn_t ihdlr(int irq, struct Scsi_Host *shost) 2289static irqreturn_t ihdlr(struct Scsi_Host *shost)
2290{ 2290{
2291 struct scsi_cmnd *SCpnt; 2291 struct scsi_cmnd *SCpnt;
2292 unsigned int i, k, c, status, tstatus, reg; 2292 unsigned int i, k, c, status, tstatus, reg;
2293 struct mssp *spp; 2293 struct mssp *spp;
2294 struct mscp *cpp; 2294 struct mscp *cpp;
2295 struct hostdata *ha = (struct hostdata *)shost->hostdata; 2295 struct hostdata *ha = (struct hostdata *)shost->hostdata;
2296 2296 int irq = shost->irq;
2297 if (shost->irq != irq)
2298 panic("%s: ihdlr, irq %d, shost->irq %d.\n", ha->board_name, irq,
2299 shost->irq);
2300 2297
2301 /* Check if this board need to be serviced */ 2298 /* Check if this board need to be serviced */
2302 if (!(inb(shost->io_port + REG_AUX_STATUS) & IRQ_ASSERTED)) 2299 if (!(inb(shost->io_port + REG_AUX_STATUS) & IRQ_ASSERTED))
@@ -2535,7 +2532,7 @@ static irqreturn_t ihdlr(int irq, struct Scsi_Host *shost)
2535 return IRQ_NONE; 2532 return IRQ_NONE;
2536} 2533}
2537 2534
2538static irqreturn_t do_interrupt_handler(int irq, void *shap) 2535static irqreturn_t do_interrupt_handler(int dummy, void *shap)
2539{ 2536{
2540 struct Scsi_Host *shost; 2537 struct Scsi_Host *shost;
2541 unsigned int j; 2538 unsigned int j;
@@ -2548,7 +2545,7 @@ static irqreturn_t do_interrupt_handler(int irq, void *shap)
2548 shost = sh[j]; 2545 shost = sh[j];
2549 2546
2550 spin_lock_irqsave(shost->host_lock, spin_flags); 2547 spin_lock_irqsave(shost->host_lock, spin_flags);
2551 ret = ihdlr(irq, shost); 2548 ret = ihdlr(shost);
2552 spin_unlock_irqrestore(shost->host_lock, spin_flags); 2549 spin_unlock_irqrestore(shost->host_lock, spin_flags);
2553 return ret; 2550 return ret;
2554} 2551}
diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
index bfdee5968892..a0b6d414953d 100644
--- a/drivers/scsi/esp_scsi.c
+++ b/drivers/scsi/esp_scsi.c
@@ -978,7 +978,7 @@ static int esp_check_spur_intr(struct esp *esp)
978 */ 978 */
979 if (!esp->ops->dma_error(esp)) { 979 if (!esp->ops->dma_error(esp)) {
980 printk(KERN_ERR PFX "esp%d: Spurious irq, " 980 printk(KERN_ERR PFX "esp%d: Spurious irq, "
981 "sreg=%x.\n", 981 "sreg=%02x.\n",
982 esp->host->unique_id, esp->sreg); 982 esp->host->unique_id, esp->sreg);
983 return -1; 983 return -1;
984 } 984 }
@@ -1447,6 +1447,9 @@ static void esp_msgin_sdtr(struct esp *esp, struct esp_target_data *tp)
1447 if (offset > 15) 1447 if (offset > 15)
1448 goto do_reject; 1448 goto do_reject;
1449 1449
1450 if (esp->flags & ESP_FLAG_DISABLE_SYNC)
1451 offset = 0;
1452
1450 if (offset) { 1453 if (offset) {
1451 int rounded_up, one_clock; 1454 int rounded_up, one_clock;
1452 1455
@@ -1697,7 +1700,12 @@ again:
1697 else 1700 else
1698 ent->flags &= ~ESP_CMD_FLAG_WRITE; 1701 ent->flags &= ~ESP_CMD_FLAG_WRITE;
1699 1702
1700 dma_len = esp_dma_length_limit(esp, dma_addr, dma_len); 1703 if (esp->ops->dma_length_limit)
1704 dma_len = esp->ops->dma_length_limit(esp, dma_addr,
1705 dma_len);
1706 else
1707 dma_len = esp_dma_length_limit(esp, dma_addr, dma_len);
1708
1701 esp->data_dma_len = dma_len; 1709 esp->data_dma_len = dma_len;
1702 1710
1703 if (!dma_len) { 1711 if (!dma_len) {
@@ -1761,7 +1769,6 @@ again:
1761 esp_advance_dma(esp, ent, cmd, bytes_sent); 1769 esp_advance_dma(esp, ent, cmd, bytes_sent);
1762 esp_event(esp, ESP_EVENT_CHECK_PHASE); 1770 esp_event(esp, ESP_EVENT_CHECK_PHASE);
1763 goto again; 1771 goto again;
1764 break;
1765 } 1772 }
1766 1773
1767 case ESP_EVENT_STATUS: { 1774 case ESP_EVENT_STATUS: {
@@ -2235,7 +2242,7 @@ static void esp_bootup_reset(struct esp *esp)
2235 2242
2236static void esp_set_clock_params(struct esp *esp) 2243static void esp_set_clock_params(struct esp *esp)
2237{ 2244{
2238 int fmhz; 2245 int fhz;
2239 u8 ccf; 2246 u8 ccf;
2240 2247
2241 /* This is getting messy but it has to be done correctly or else 2248 /* This is getting messy but it has to be done correctly or else
@@ -2270,9 +2277,9 @@ static void esp_set_clock_params(struct esp *esp)
2270 * This entails the smallest and largest sync period we could ever 2277 * This entails the smallest and largest sync period we could ever
2271 * handle on this ESP. 2278 * handle on this ESP.
2272 */ 2279 */
2273 fmhz = esp->cfreq; 2280 fhz = esp->cfreq;
2274 2281
2275 ccf = ((fmhz / 1000000) + 4) / 5; 2282 ccf = ((fhz / 1000000) + 4) / 5;
2276 if (ccf == 1) 2283 if (ccf == 1)
2277 ccf = 2; 2284 ccf = 2;
2278 2285
@@ -2281,16 +2288,16 @@ static void esp_set_clock_params(struct esp *esp)
2281 * been unable to find the clock-frequency PROM property. All 2288 * been unable to find the clock-frequency PROM property. All
2282 * other machines provide useful values it seems. 2289 * other machines provide useful values it seems.
2283 */ 2290 */
2284 if (fmhz <= 5000000 || ccf < 1 || ccf > 8) { 2291 if (fhz <= 5000000 || ccf < 1 || ccf > 8) {
2285 fmhz = 20000000; 2292 fhz = 20000000;
2286 ccf = 4; 2293 ccf = 4;
2287 } 2294 }
2288 2295
2289 esp->cfact = (ccf == 8 ? 0 : ccf); 2296 esp->cfact = (ccf == 8 ? 0 : ccf);
2290 esp->cfreq = fmhz; 2297 esp->cfreq = fhz;
2291 esp->ccycle = ESP_MHZ_TO_CYCLE(fmhz); 2298 esp->ccycle = ESP_HZ_TO_CYCLE(fhz);
2292 esp->ctick = ESP_TICK(ccf, esp->ccycle); 2299 esp->ctick = ESP_TICK(ccf, esp->ccycle);
2293 esp->neg_defp = ESP_NEG_DEFP(fmhz, ccf); 2300 esp->neg_defp = ESP_NEG_DEFP(fhz, ccf);
2294 esp->sync_defp = SYNC_DEFP_SLOW; 2301 esp->sync_defp = SYNC_DEFP_SLOW;
2295} 2302}
2296 2303
@@ -2382,6 +2389,12 @@ static int esp_slave_configure(struct scsi_device *dev)
2382 struct esp_target_data *tp = &esp->target[dev->id]; 2389 struct esp_target_data *tp = &esp->target[dev->id];
2383 int goal_tags, queue_depth; 2390 int goal_tags, queue_depth;
2384 2391
2392 if (esp->flags & ESP_FLAG_DISABLE_SYNC) {
2393 /* Bypass async domain validation */
2394 dev->ppr = 0;
2395 dev->sdtr = 0;
2396 }
2397
2385 goal_tags = 0; 2398 goal_tags = 0;
2386 2399
2387 if (dev->tagged_supported) { 2400 if (dev->tagged_supported) {
diff --git a/drivers/scsi/esp_scsi.h b/drivers/scsi/esp_scsi.h
index d5576d54ce76..bb43a1388188 100644
--- a/drivers/scsi/esp_scsi.h
+++ b/drivers/scsi/esp_scsi.h
@@ -224,7 +224,7 @@
224#define ESP_TIMEO_CONST 8192 224#define ESP_TIMEO_CONST 8192
225#define ESP_NEG_DEFP(mhz, cfact) \ 225#define ESP_NEG_DEFP(mhz, cfact) \
226 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) 226 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
227#define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000)) 227#define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000))
228#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) 228#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
229 229
230/* For slow to medium speed input clock rates we shoot for 5mb/s, but for high 230/* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
@@ -240,9 +240,9 @@ struct esp_cmd_priv {
240 int num_sg; 240 int num_sg;
241 } u; 241 } u;
242 242
243 unsigned int cur_residue; 243 int cur_residue;
244 struct scatterlist *cur_sg; 244 struct scatterlist *cur_sg;
245 unsigned int tot_residue; 245 int tot_residue;
246}; 246};
247#define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp)) 247#define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp))
248 248
@@ -368,6 +368,12 @@ struct esp_driver_ops {
368 */ 368 */
369 int (*irq_pending)(struct esp *esp); 369 int (*irq_pending)(struct esp *esp);
370 370
371 /* Return the maximum allowable size of a DMA transfer for a
372 * given buffer.
373 */
374 u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr,
375 u32 dma_len);
376
371 /* Reset the DMA engine entirely. On return, ESP interrupts 377 /* Reset the DMA engine entirely. On return, ESP interrupts
372 * should be enabled. Often the interrupt enabling is 378 * should be enabled. Often the interrupt enabling is
373 * controlled in the DMA engine. 379 * controlled in the DMA engine.
@@ -471,6 +477,7 @@ struct esp {
471#define ESP_FLAG_DOING_SLOWCMD 0x00000004 477#define ESP_FLAG_DOING_SLOWCMD 0x00000004
472#define ESP_FLAG_WIDE_CAPABLE 0x00000008 478#define ESP_FLAG_WIDE_CAPABLE 0x00000008
473#define ESP_FLAG_QUICKIRQ_CHECK 0x00000010 479#define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
480#define ESP_FLAG_DISABLE_SYNC 0x00000020
474 481
475 u8 select_state; 482 u8 select_state;
476#define ESP_SELECT_NONE 0x00 /* Not selecting */ 483#define ESP_SELECT_NONE 0x00 /* Not selecting */
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c
index c264a8c5f01e..3690360d7a79 100644
--- a/drivers/scsi/hosts.c
+++ b/drivers/scsi/hosts.c
@@ -199,9 +199,13 @@ int scsi_add_host(struct Scsi_Host *shost, struct device *dev)
199 if (!shost->can_queue) { 199 if (!shost->can_queue) {
200 printk(KERN_ERR "%s: can_queue = 0 no longer supported\n", 200 printk(KERN_ERR "%s: can_queue = 0 no longer supported\n",
201 sht->name); 201 sht->name);
202 goto out; 202 goto fail;
203 } 203 }
204 204
205 error = scsi_setup_command_freelist(shost);
206 if (error)
207 goto fail;
208
205 if (!shost->shost_gendev.parent) 209 if (!shost->shost_gendev.parent)
206 shost->shost_gendev.parent = dev ? dev : &platform_bus; 210 shost->shost_gendev.parent = dev ? dev : &platform_bus;
207 211
@@ -255,6 +259,8 @@ int scsi_add_host(struct Scsi_Host *shost, struct device *dev)
255 out_del_gendev: 259 out_del_gendev:
256 device_del(&shost->shost_gendev); 260 device_del(&shost->shost_gendev);
257 out: 261 out:
262 scsi_destroy_command_freelist(shost);
263 fail:
258 return error; 264 return error;
259} 265}
260EXPORT_SYMBOL(scsi_add_host); 266EXPORT_SYMBOL(scsi_add_host);
@@ -284,6 +290,11 @@ static void scsi_host_dev_release(struct device *dev)
284 kfree(shost); 290 kfree(shost);
285} 291}
286 292
293struct device_type scsi_host_type = {
294 .name = "scsi_host",
295 .release = scsi_host_dev_release,
296};
297
287/** 298/**
288 * scsi_host_alloc - register a scsi host adapter instance. 299 * scsi_host_alloc - register a scsi host adapter instance.
289 * @sht: pointer to scsi host template 300 * @sht: pointer to scsi host template
@@ -376,33 +387,31 @@ struct Scsi_Host *scsi_host_alloc(struct scsi_host_template *sht, int privsize)
376 else 387 else
377 shost->dma_boundary = 0xffffffff; 388 shost->dma_boundary = 0xffffffff;
378 389
379 rval = scsi_setup_command_freelist(shost);
380 if (rval)
381 goto fail_kfree;
382
383 device_initialize(&shost->shost_gendev); 390 device_initialize(&shost->shost_gendev);
384 snprintf(shost->shost_gendev.bus_id, BUS_ID_SIZE, "host%d", 391 snprintf(shost->shost_gendev.bus_id, BUS_ID_SIZE, "host%d",
385 shost->host_no); 392 shost->host_no);
386 shost->shost_gendev.release = scsi_host_dev_release; 393#ifndef CONFIG_SYSFS_DEPRECATED
394 shost->shost_gendev.bus = &scsi_bus_type;
395#endif
396 shost->shost_gendev.type = &scsi_host_type;
387 397
388 device_initialize(&shost->shost_dev); 398 device_initialize(&shost->shost_dev);
389 shost->shost_dev.parent = &shost->shost_gendev; 399 shost->shost_dev.parent = &shost->shost_gendev;
390 shost->shost_dev.class = &shost_class; 400 shost->shost_dev.class = &shost_class;
391 snprintf(shost->shost_dev.bus_id, BUS_ID_SIZE, "host%d", 401 snprintf(shost->shost_dev.bus_id, BUS_ID_SIZE, "host%d",
392 shost->host_no); 402 shost->host_no);
403 shost->shost_dev.groups = scsi_sysfs_shost_attr_groups;
393 404
394 shost->ehandler = kthread_run(scsi_error_handler, shost, 405 shost->ehandler = kthread_run(scsi_error_handler, shost,
395 "scsi_eh_%d", shost->host_no); 406 "scsi_eh_%d", shost->host_no);
396 if (IS_ERR(shost->ehandler)) { 407 if (IS_ERR(shost->ehandler)) {
397 rval = PTR_ERR(shost->ehandler); 408 rval = PTR_ERR(shost->ehandler);
398 goto fail_destroy_freelist; 409 goto fail_kfree;
399 } 410 }
400 411
401 scsi_proc_hostdir_add(shost->hostt); 412 scsi_proc_hostdir_add(shost->hostt);
402 return shost; 413 return shost;
403 414
404 fail_destroy_freelist:
405 scsi_destroy_command_freelist(shost);
406 fail_kfree: 415 fail_kfree:
407 kfree(shost); 416 kfree(shost);
408 return NULL; 417 return NULL;
@@ -496,7 +505,7 @@ void scsi_exit_hosts(void)
496 505
497int scsi_is_host_device(const struct device *dev) 506int scsi_is_host_device(const struct device *dev)
498{ 507{
499 return dev->release == scsi_host_dev_release; 508 return dev->type == &scsi_host_type;
500} 509}
501EXPORT_SYMBOL(scsi_is_host_device); 510EXPORT_SYMBOL(scsi_is_host_device);
502 511
diff --git a/drivers/scsi/jazz_esp.c b/drivers/scsi/jazz_esp.c
index 5d231015bb20..b2d481dd3750 100644
--- a/drivers/scsi/jazz_esp.c
+++ b/drivers/scsi/jazz_esp.c
@@ -217,11 +217,15 @@ static int __devexit esp_jazz_remove(struct platform_device *dev)
217 return 0; 217 return 0;
218} 218}
219 219
220/* work with hotplug and coldplug */
221MODULE_ALIAS("platform:jazz_esp");
222
220static struct platform_driver esp_jazz_driver = { 223static struct platform_driver esp_jazz_driver = {
221 .probe = esp_jazz_probe, 224 .probe = esp_jazz_probe,
222 .remove = __devexit_p(esp_jazz_remove), 225 .remove = __devexit_p(esp_jazz_remove),
223 .driver = { 226 .driver = {
224 .name = "jazz_esp", 227 .name = "jazz_esp",
228 .owner = THIS_MODULE,
225 }, 229 },
226}; 230};
227 231
diff --git a/drivers/scsi/lpfc/lpfc_attr.c b/drivers/scsi/lpfc/lpfc_attr.c
index a9fbb3f88659..960baaf11fb1 100644
--- a/drivers/scsi/lpfc/lpfc_attr.c
+++ b/drivers/scsi/lpfc/lpfc_attr.c
@@ -182,8 +182,8 @@ lpfc_option_rom_version_show(struct device *dev, struct device_attribute *attr,
182 return snprintf(buf, PAGE_SIZE, "%s\n", phba->OptionROMVersion); 182 return snprintf(buf, PAGE_SIZE, "%s\n", phba->OptionROMVersion);
183} 183}
184static ssize_t 184static ssize_t
185lpfc_state_show(struct device *dev, struct device_attribute *attr, 185lpfc_link_state_show(struct device *dev, struct device_attribute *attr,
186 char *buf) 186 char *buf)
187{ 187{
188 struct Scsi_Host *shost = class_to_shost(dev); 188 struct Scsi_Host *shost = class_to_shost(dev);
189 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata; 189 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
@@ -936,7 +936,7 @@ static DEVICE_ATTR(programtype, S_IRUGO, lpfc_programtype_show, NULL);
936static DEVICE_ATTR(portnum, S_IRUGO, lpfc_vportnum_show, NULL); 936static DEVICE_ATTR(portnum, S_IRUGO, lpfc_vportnum_show, NULL);
937static DEVICE_ATTR(fwrev, S_IRUGO, lpfc_fwrev_show, NULL); 937static DEVICE_ATTR(fwrev, S_IRUGO, lpfc_fwrev_show, NULL);
938static DEVICE_ATTR(hdw, S_IRUGO, lpfc_hdw_show, NULL); 938static DEVICE_ATTR(hdw, S_IRUGO, lpfc_hdw_show, NULL);
939static DEVICE_ATTR(state, S_IRUGO, lpfc_state_show, NULL); 939static DEVICE_ATTR(link_state, S_IRUGO, lpfc_link_state_show, NULL);
940static DEVICE_ATTR(option_rom_version, S_IRUGO, 940static DEVICE_ATTR(option_rom_version, S_IRUGO,
941 lpfc_option_rom_version_show, NULL); 941 lpfc_option_rom_version_show, NULL);
942static DEVICE_ATTR(num_discovered_ports, S_IRUGO, 942static DEVICE_ATTR(num_discovered_ports, S_IRUGO,
@@ -1666,7 +1666,7 @@ struct device_attribute *lpfc_hba_attrs[] = {
1666 &dev_attr_fwrev, 1666 &dev_attr_fwrev,
1667 &dev_attr_hdw, 1667 &dev_attr_hdw,
1668 &dev_attr_option_rom_version, 1668 &dev_attr_option_rom_version,
1669 &dev_attr_state, 1669 &dev_attr_link_state,
1670 &dev_attr_num_discovered_ports, 1670 &dev_attr_num_discovered_ports,
1671 &dev_attr_lpfc_drvr_version, 1671 &dev_attr_lpfc_drvr_version,
1672 &dev_attr_lpfc_temp_sensor, 1672 &dev_attr_lpfc_temp_sensor,
@@ -1714,7 +1714,7 @@ struct device_attribute *lpfc_hba_attrs[] = {
1714 1714
1715struct device_attribute *lpfc_vport_attrs[] = { 1715struct device_attribute *lpfc_vport_attrs[] = {
1716 &dev_attr_info, 1716 &dev_attr_info,
1717 &dev_attr_state, 1717 &dev_attr_link_state,
1718 &dev_attr_num_discovered_ports, 1718 &dev_attr_num_discovered_ports,
1719 &dev_attr_lpfc_drvr_version, 1719 &dev_attr_lpfc_drvr_version,
1720 &dev_attr_lpfc_log_verbose, 1720 &dev_attr_lpfc_log_verbose,
diff --git a/drivers/scsi/mac_esp.c b/drivers/scsi/mac_esp.c
new file mode 100644
index 000000000000..cd37bd69a115
--- /dev/null
+++ b/drivers/scsi/mac_esp.c
@@ -0,0 +1,657 @@
1/* mac_esp.c: ESP front-end for Macintosh Quadra systems.
2 *
3 * Adapted from jazz_esp.c and the old mac_esp.c.
4 *
5 * The pseudo DMA algorithm is based on the one used in NetBSD.
6 * See sys/arch/mac68k/obio/esp.c for some background information.
7 *
8 * Copyright (C) 2007-2008 Finn Thain
9 */
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/dma-mapping.h>
18#include <linux/scatterlist.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/nubus.h>
22
23#include <asm/irq.h>
24#include <asm/dma.h>
25
26#include <asm/macints.h>
27#include <asm/macintosh.h>
28
29#include <scsi/scsi_host.h>
30
31#include "esp_scsi.h"
32
33#define DRV_MODULE_NAME "mac_esp"
34#define PFX DRV_MODULE_NAME ": "
35#define DRV_VERSION "1.000"
36#define DRV_MODULE_RELDATE "Sept 15, 2007"
37
38#define MAC_ESP_IO_BASE 0x50F00000
39#define MAC_ESP_REGS_QUADRA (MAC_ESP_IO_BASE + 0x10000)
40#define MAC_ESP_REGS_QUADRA2 (MAC_ESP_IO_BASE + 0xF000)
41#define MAC_ESP_REGS_QUADRA3 (MAC_ESP_IO_BASE + 0x18000)
42#define MAC_ESP_REGS_SPACING 0x402
43#define MAC_ESP_PDMA_REG 0xF9800024
44#define MAC_ESP_PDMA_REG_SPACING 0x4
45#define MAC_ESP_PDMA_IO_OFFSET 0x100
46
47#define esp_read8(REG) mac_esp_read8(esp, REG)
48#define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)
49
50struct mac_esp_priv {
51 struct esp *esp;
52 void __iomem *pdma_regs;
53 void __iomem *pdma_io;
54 int error;
55};
56static struct platform_device *internal_esp, *external_esp;
57
58#define MAC_ESP_GET_PRIV(esp) ((struct mac_esp_priv *) \
59 platform_get_drvdata((struct platform_device *) \
60 (esp->dev)))
61
62static inline void mac_esp_write8(struct esp *esp, u8 val, unsigned long reg)
63{
64 nubus_writeb(val, esp->regs + reg * 16);
65}
66
67static inline u8 mac_esp_read8(struct esp *esp, unsigned long reg)
68{
69 return nubus_readb(esp->regs + reg * 16);
70}
71
72/* For pseudo DMA and PIO we need the virtual address
73 * so this address mapping is the identity mapping.
74 */
75
76static dma_addr_t mac_esp_map_single(struct esp *esp, void *buf,
77 size_t sz, int dir)
78{
79 return (dma_addr_t)buf;
80}
81
82static int mac_esp_map_sg(struct esp *esp, struct scatterlist *sg,
83 int num_sg, int dir)
84{
85 int i;
86
87 for (i = 0; i < num_sg; i++)
88 sg[i].dma_address = (u32)sg_virt(&sg[i]);
89 return num_sg;
90}
91
92static void mac_esp_unmap_single(struct esp *esp, dma_addr_t addr,
93 size_t sz, int dir)
94{
95 /* Nothing to do. */
96}
97
98static void mac_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
99 int num_sg, int dir)
100{
101 /* Nothing to do. */
102}
103
104static void mac_esp_reset_dma(struct esp *esp)
105{
106 /* Nothing to do. */
107}
108
109static void mac_esp_dma_drain(struct esp *esp)
110{
111 /* Nothing to do. */
112}
113
114static void mac_esp_dma_invalidate(struct esp *esp)
115{
116 /* Nothing to do. */
117}
118
119static int mac_esp_dma_error(struct esp *esp)
120{
121 return MAC_ESP_GET_PRIV(esp)->error;
122}
123
124static inline int mac_esp_wait_for_empty_fifo(struct esp *esp)
125{
126 struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
127 int i = 500000;
128
129 do {
130 if (!(esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES))
131 return 0;
132
133 if (esp_read8(ESP_STATUS) & ESP_STAT_INTR)
134 return 1;
135
136 udelay(2);
137 } while (--i);
138
139 printk(KERN_ERR PFX "FIFO is not empty (sreg %02x)\n",
140 esp_read8(ESP_STATUS));
141 mep->error = 1;
142 return 1;
143}
144
145static inline int mac_esp_wait_for_dreq(struct esp *esp)
146{
147 struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
148 int i = 500000;
149
150 do {
151 if (mep->pdma_regs == NULL) {
152 if (mac_irq_pending(IRQ_MAC_SCSIDRQ))
153 return 0;
154 } else {
155 if (nubus_readl(mep->pdma_regs) & 0x200)
156 return 0;
157 }
158
159 if (esp_read8(ESP_STATUS) & ESP_STAT_INTR)
160 return 1;
161
162 udelay(2);
163 } while (--i);
164
165 printk(KERN_ERR PFX "PDMA timeout (sreg %02x)\n",
166 esp_read8(ESP_STATUS));
167 mep->error = 1;
168 return 1;
169}
170
171#define MAC_ESP_PDMA_LOOP(operands) \
172 asm volatile ( \
173 " tstw %2 \n" \
174 " jbeq 20f \n" \
175 "1: movew " operands " \n" \
176 "2: movew " operands " \n" \
177 "3: movew " operands " \n" \
178 "4: movew " operands " \n" \
179 "5: movew " operands " \n" \
180 "6: movew " operands " \n" \
181 "7: movew " operands " \n" \
182 "8: movew " operands " \n" \
183 "9: movew " operands " \n" \
184 "10: movew " operands " \n" \
185 "11: movew " operands " \n" \
186 "12: movew " operands " \n" \
187 "13: movew " operands " \n" \
188 "14: movew " operands " \n" \
189 "15: movew " operands " \n" \
190 "16: movew " operands " \n" \
191 " subqw #1,%2 \n" \
192 " jbne 1b \n" \
193 "20: tstw %3 \n" \
194 " jbeq 30f \n" \
195 "21: movew " operands " \n" \
196 " subqw #1,%3 \n" \
197 " jbne 21b \n" \
198 "30: tstw %4 \n" \
199 " jbeq 40f \n" \
200 "31: moveb " operands " \n" \
201 "32: nop \n" \
202 "40: \n" \
203 " \n" \
204 " .section __ex_table,\"a\" \n" \
205 " .align 4 \n" \
206 " .long 1b,40b \n" \
207 " .long 2b,40b \n" \
208 " .long 3b,40b \n" \
209 " .long 4b,40b \n" \
210 " .long 5b,40b \n" \
211 " .long 6b,40b \n" \
212 " .long 7b,40b \n" \
213 " .long 8b,40b \n" \
214 " .long 9b,40b \n" \
215 " .long 10b,40b \n" \
216 " .long 11b,40b \n" \
217 " .long 12b,40b \n" \
218 " .long 13b,40b \n" \
219 " .long 14b,40b \n" \
220 " .long 15b,40b \n" \
221 " .long 16b,40b \n" \
222 " .long 21b,40b \n" \
223 " .long 31b,40b \n" \
224 " .long 32b,40b \n" \
225 " .previous \n" \
226 : "+a" (addr) \
227 : "a" (mep->pdma_io), "r" (count32), "r" (count2), "g" (esp_count))
228
229static void mac_esp_send_pdma_cmd(struct esp *esp, u32 addr, u32 esp_count,
230 u32 dma_count, int write, u8 cmd)
231{
232 struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
233 unsigned long flags;
234
235 local_irq_save(flags);
236
237 mep->error = 0;
238
239 if (!write)
240 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
241
242 esp_write8((esp_count >> 0) & 0xFF, ESP_TCLOW);
243 esp_write8((esp_count >> 8) & 0xFF, ESP_TCMED);
244
245 scsi_esp_cmd(esp, cmd);
246
247 do {
248 unsigned int count32 = esp_count >> 5;
249 unsigned int count2 = (esp_count & 0x1F) >> 1;
250 unsigned int start_addr = addr;
251
252 if (mac_esp_wait_for_dreq(esp))
253 break;
254
255 if (write) {
256 MAC_ESP_PDMA_LOOP("%1@,%0@+");
257
258 esp_count -= addr - start_addr;
259 } else {
260 unsigned int n;
261
262 MAC_ESP_PDMA_LOOP("%0@+,%1@");
263
264 if (mac_esp_wait_for_empty_fifo(esp))
265 break;
266
267 n = (esp_read8(ESP_TCMED) << 8) + esp_read8(ESP_TCLOW);
268 addr = start_addr + esp_count - n;
269 esp_count = n;
270 }
271 } while (esp_count);
272
273 local_irq_restore(flags);
274}
275
276/*
277 * Programmed IO routines follow.
278 */
279
280static inline int mac_esp_wait_for_fifo(struct esp *esp)
281{
282 int i = 500000;
283
284 do {
285 if (esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES)
286 return 0;
287
288 udelay(2);
289 } while (--i);
290
291 printk(KERN_ERR PFX "FIFO is empty (sreg %02x)\n",
292 esp_read8(ESP_STATUS));
293 return 1;
294}
295
296static inline int mac_esp_wait_for_intr(struct esp *esp)
297{
298 int i = 500000;
299
300 do {
301 esp->sreg = esp_read8(ESP_STATUS);
302 if (esp->sreg & ESP_STAT_INTR)
303 return 0;
304
305 udelay(2);
306 } while (--i);
307
308 printk(KERN_ERR PFX "IRQ timeout (sreg %02x)\n", esp->sreg);
309 return 1;
310}
311
312#define MAC_ESP_PIO_LOOP(operands, reg1) \
313 asm volatile ( \
314 "1: moveb " operands " \n" \
315 " subqw #1,%1 \n" \
316 " jbne 1b \n" \
317 : "+a" (addr), "+r" (reg1) \
318 : "a" (fifo))
319
320#define MAC_ESP_PIO_FILL(operands, reg1) \
321 asm volatile ( \
322 " moveb " operands " \n" \
323 " moveb " operands " \n" \
324 " moveb " operands " \n" \
325 " moveb " operands " \n" \
326 " moveb " operands " \n" \
327 " moveb " operands " \n" \
328 " moveb " operands " \n" \
329 " moveb " operands " \n" \
330 " moveb " operands " \n" \
331 " moveb " operands " \n" \
332 " moveb " operands " \n" \
333 " moveb " operands " \n" \
334 " moveb " operands " \n" \
335 " moveb " operands " \n" \
336 " moveb " operands " \n" \
337 " moveb " operands " \n" \
338 " subqw #8,%1 \n" \
339 " subqw #8,%1 \n" \
340 : "+a" (addr), "+r" (reg1) \
341 : "a" (fifo))
342
343#define MAC_ESP_FIFO_SIZE 16
344
345static void mac_esp_send_pio_cmd(struct esp *esp, u32 addr, u32 esp_count,
346 u32 dma_count, int write, u8 cmd)
347{
348 unsigned long flags;
349 struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
350 u8 *fifo = esp->regs + ESP_FDATA * 16;
351
352 local_irq_save(flags);
353
354 cmd &= ~ESP_CMD_DMA;
355 mep->error = 0;
356
357 if (write) {
358 scsi_esp_cmd(esp, cmd);
359
360 if (!mac_esp_wait_for_intr(esp)) {
361 if (mac_esp_wait_for_fifo(esp))
362 esp_count = 0;
363 } else {
364 esp_count = 0;
365 }
366 } else {
367 scsi_esp_cmd(esp, ESP_CMD_FLUSH);
368
369 if (esp_count >= MAC_ESP_FIFO_SIZE)
370 MAC_ESP_PIO_FILL("%0@+,%2@", esp_count);
371 else
372 MAC_ESP_PIO_LOOP("%0@+,%2@", esp_count);
373
374 scsi_esp_cmd(esp, cmd);
375 }
376
377 while (esp_count) {
378 unsigned int n;
379
380 if (mac_esp_wait_for_intr(esp)) {
381 mep->error = 1;
382 break;
383 }
384
385 if (esp->sreg & ESP_STAT_SPAM) {
386 printk(KERN_ERR PFX "gross error\n");
387 mep->error = 1;
388 break;
389 }
390
391 n = esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES;
392
393 if (write) {
394 if (n > esp_count)
395 n = esp_count;
396 esp_count -= n;
397
398 MAC_ESP_PIO_LOOP("%2@,%0@+", n);
399
400 if ((esp->sreg & ESP_STAT_PMASK) == ESP_STATP)
401 break;
402
403 if (esp_count) {
404 esp->ireg = esp_read8(ESP_INTRPT);
405 if (esp->ireg & ESP_INTR_DC)
406 break;
407
408 scsi_esp_cmd(esp, ESP_CMD_TI);
409 }
410 } else {
411 esp->ireg = esp_read8(ESP_INTRPT);
412 if (esp->ireg & ESP_INTR_DC)
413 break;
414
415 n = MAC_ESP_FIFO_SIZE - n;
416 if (n > esp_count)
417 n = esp_count;
418
419 if (n == MAC_ESP_FIFO_SIZE) {
420 MAC_ESP_PIO_FILL("%0@+,%2@", esp_count);
421 } else {
422 esp_count -= n;
423 MAC_ESP_PIO_LOOP("%0@+,%2@", n);
424 }
425
426 scsi_esp_cmd(esp, ESP_CMD_TI);
427 }
428 }
429
430 local_irq_restore(flags);
431}
432
433static int mac_esp_irq_pending(struct esp *esp)
434{
435 if (esp_read8(ESP_STATUS) & ESP_STAT_INTR)
436 return 1;
437 return 0;
438}
439
440static u32 mac_esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len)
441{
442 return dma_len > 0xFFFF ? 0xFFFF : dma_len;
443}
444
445static struct esp_driver_ops mac_esp_ops = {
446 .esp_write8 = mac_esp_write8,
447 .esp_read8 = mac_esp_read8,
448 .map_single = mac_esp_map_single,
449 .map_sg = mac_esp_map_sg,
450 .unmap_single = mac_esp_unmap_single,
451 .unmap_sg = mac_esp_unmap_sg,
452 .irq_pending = mac_esp_irq_pending,
453 .dma_length_limit = mac_esp_dma_length_limit,
454 .reset_dma = mac_esp_reset_dma,
455 .dma_drain = mac_esp_dma_drain,
456 .dma_invalidate = mac_esp_dma_invalidate,
457 .send_dma_cmd = mac_esp_send_pdma_cmd,
458 .dma_error = mac_esp_dma_error,
459};
460
461static int __devinit esp_mac_probe(struct platform_device *dev)
462{
463 struct scsi_host_template *tpnt = &scsi_esp_template;
464 struct Scsi_Host *host;
465 struct esp *esp;
466 int err;
467 int chips_present;
468 struct mac_esp_priv *mep;
469
470 if (!MACH_IS_MAC)
471 return -ENODEV;
472
473 switch (macintosh_config->scsi_type) {
474 case MAC_SCSI_QUADRA:
475 case MAC_SCSI_QUADRA3:
476 chips_present = 1;
477 break;
478 case MAC_SCSI_QUADRA2:
479 if ((macintosh_config->ident == MAC_MODEL_Q900) ||
480 (macintosh_config->ident == MAC_MODEL_Q950))
481 chips_present = 2;
482 else
483 chips_present = 1;
484 break;
485 default:
486 chips_present = 0;
487 }
488
489 if (dev->id + 1 > chips_present)
490 return -ENODEV;
491
492 host = scsi_host_alloc(tpnt, sizeof(struct esp));
493
494 err = -ENOMEM;
495 if (!host)
496 goto fail;
497
498 host->max_id = 8;
499 host->use_clustering = DISABLE_CLUSTERING;
500 esp = shost_priv(host);
501
502 esp->host = host;
503 esp->dev = dev;
504
505 esp->command_block = kzalloc(16, GFP_KERNEL);
506 if (!esp->command_block)
507 goto fail_unlink;
508 esp->command_block_dma = (dma_addr_t)esp->command_block;
509
510 esp->scsi_id = 7;
511 host->this_id = esp->scsi_id;
512 esp->scsi_id_mask = 1 << esp->scsi_id;
513
514 mep = kzalloc(sizeof(struct mac_esp_priv), GFP_KERNEL);
515 if (!mep)
516 goto fail_free_command_block;
517 mep->esp = esp;
518 platform_set_drvdata(dev, mep);
519
520 switch (macintosh_config->scsi_type) {
521 case MAC_SCSI_QUADRA:
522 esp->cfreq = 16500000;
523 esp->regs = (void __iomem *)MAC_ESP_REGS_QUADRA;
524 mep->pdma_io = esp->regs + MAC_ESP_PDMA_IO_OFFSET;
525 mep->pdma_regs = NULL;
526 break;
527 case MAC_SCSI_QUADRA2:
528 esp->cfreq = 25000000;
529 esp->regs = (void __iomem *)(MAC_ESP_REGS_QUADRA2 +
530 dev->id * MAC_ESP_REGS_SPACING);
531 mep->pdma_io = esp->regs + MAC_ESP_PDMA_IO_OFFSET;
532 mep->pdma_regs = (void __iomem *)(MAC_ESP_PDMA_REG +
533 dev->id * MAC_ESP_PDMA_REG_SPACING);
534 nubus_writel(0x1d1, mep->pdma_regs);
535 break;
536 case MAC_SCSI_QUADRA3:
537 /* These quadras have a real DMA controller (the PSC) but we
538 * don't know how to drive it so we must use PIO instead.
539 */
540 esp->cfreq = 25000000;
541 esp->regs = (void __iomem *)MAC_ESP_REGS_QUADRA3;
542 mep->pdma_io = NULL;
543 mep->pdma_regs = NULL;
544 break;
545 }
546
547 esp->ops = &mac_esp_ops;
548 if (mep->pdma_io == NULL) {
549 printk(KERN_INFO PFX "using PIO for controller %d\n", dev->id);
550 esp_write8(0, ESP_TCLOW);
551 esp_write8(0, ESP_TCMED);
552 esp->flags = ESP_FLAG_DISABLE_SYNC;
553 mac_esp_ops.send_dma_cmd = mac_esp_send_pio_cmd;
554 } else {
555 printk(KERN_INFO PFX "using PDMA for controller %d\n", dev->id);
556 }
557
558 host->irq = IRQ_MAC_SCSI;
559 err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "Mac ESP",
560 esp);
561 if (err < 0)
562 goto fail_free_priv;
563
564 err = scsi_esp_register(esp, &dev->dev);
565 if (err)
566 goto fail_free_irq;
567
568 return 0;
569
570fail_free_irq:
571 free_irq(host->irq, esp);
572fail_free_priv:
573 kfree(mep);
574fail_free_command_block:
575 kfree(esp->command_block);
576fail_unlink:
577 scsi_host_put(host);
578fail:
579 return err;
580}
581
582static int __devexit esp_mac_remove(struct platform_device *dev)
583{
584 struct mac_esp_priv *mep = platform_get_drvdata(dev);
585 struct esp *esp = mep->esp;
586 unsigned int irq = esp->host->irq;
587
588 scsi_esp_unregister(esp);
589
590 free_irq(irq, esp);
591
592 kfree(mep);
593
594 kfree(esp->command_block);
595
596 scsi_host_put(esp->host);
597
598 return 0;
599}
600
601static struct platform_driver esp_mac_driver = {
602 .probe = esp_mac_probe,
603 .remove = __devexit_p(esp_mac_remove),
604 .driver = {
605 .name = DRV_MODULE_NAME,
606 },
607};
608
609static int __init mac_esp_init(void)
610{
611 int err;
612
613 err = platform_driver_register(&esp_mac_driver);
614 if (err)
615 return err;
616
617 internal_esp = platform_device_alloc(DRV_MODULE_NAME, 0);
618 if (internal_esp && platform_device_add(internal_esp)) {
619 platform_device_put(internal_esp);
620 internal_esp = NULL;
621 }
622
623 external_esp = platform_device_alloc(DRV_MODULE_NAME, 1);
624 if (external_esp && platform_device_add(external_esp)) {
625 platform_device_put(external_esp);
626 external_esp = NULL;
627 }
628
629 if (internal_esp || external_esp) {
630 return 0;
631 } else {
632 platform_driver_unregister(&esp_mac_driver);
633 return -ENOMEM;
634 }
635}
636
637static void __exit mac_esp_exit(void)
638{
639 platform_driver_unregister(&esp_mac_driver);
640
641 if (internal_esp) {
642 platform_device_unregister(internal_esp);
643 internal_esp = NULL;
644 }
645 if (external_esp) {
646 platform_device_unregister(external_esp);
647 external_esp = NULL;
648 }
649}
650
651MODULE_DESCRIPTION("Mac ESP SCSI driver");
652MODULE_AUTHOR("Finn Thain <fthain@telegraphics.com.au>");
653MODULE_LICENSE("GPLv2");
654MODULE_VERSION(DRV_VERSION);
655
656module_init(mac_esp_init);
657module_exit(mac_esp_exit);
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index d61df036910c..287690853caf 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -609,8 +609,8 @@ qla2x00_pci_info_show(struct device *dev, struct device_attribute *attr,
609} 609}
610 610
611static ssize_t 611static ssize_t
612qla2x00_state_show(struct device *dev, struct device_attribute *attr, 612qla2x00_link_state_show(struct device *dev, struct device_attribute *attr,
613 char *buf) 613 char *buf)
614{ 614{
615 scsi_qla_host_t *ha = shost_priv(class_to_shost(dev)); 615 scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
616 int len = 0; 616 int len = 0;
@@ -814,7 +814,7 @@ static DEVICE_ATTR(isp_id, S_IRUGO, qla2x00_isp_id_show, NULL);
814static DEVICE_ATTR(model_name, S_IRUGO, qla2x00_model_name_show, NULL); 814static DEVICE_ATTR(model_name, S_IRUGO, qla2x00_model_name_show, NULL);
815static DEVICE_ATTR(model_desc, S_IRUGO, qla2x00_model_desc_show, NULL); 815static DEVICE_ATTR(model_desc, S_IRUGO, qla2x00_model_desc_show, NULL);
816static DEVICE_ATTR(pci_info, S_IRUGO, qla2x00_pci_info_show, NULL); 816static DEVICE_ATTR(pci_info, S_IRUGO, qla2x00_pci_info_show, NULL);
817static DEVICE_ATTR(state, S_IRUGO, qla2x00_state_show, NULL); 817static DEVICE_ATTR(link_state, S_IRUGO, qla2x00_link_state_show, NULL);
818static DEVICE_ATTR(zio, S_IRUGO | S_IWUSR, qla2x00_zio_show, qla2x00_zio_store); 818static DEVICE_ATTR(zio, S_IRUGO | S_IWUSR, qla2x00_zio_show, qla2x00_zio_store);
819static DEVICE_ATTR(zio_timer, S_IRUGO | S_IWUSR, qla2x00_zio_timer_show, 819static DEVICE_ATTR(zio_timer, S_IRUGO | S_IWUSR, qla2x00_zio_timer_show,
820 qla2x00_zio_timer_store); 820 qla2x00_zio_timer_store);
@@ -838,7 +838,7 @@ struct device_attribute *qla2x00_host_attrs[] = {
838 &dev_attr_model_name, 838 &dev_attr_model_name,
839 &dev_attr_model_desc, 839 &dev_attr_model_desc,
840 &dev_attr_pci_info, 840 &dev_attr_pci_info,
841 &dev_attr_state, 841 &dev_attr_link_state,
842 &dev_attr_zio, 842 &dev_attr_zio,
843 &dev_attr_zio_timer, 843 &dev_attr_zio_timer,
844 &dev_attr_beacon, 844 &dev_attr_beacon,
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 9d12d9f26209..cbef785765cf 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -38,78 +38,38 @@ qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
38} 38}
39 39
40static int 40static int
41qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, 41qla24xx_dump_ram(scsi_qla_host_t *ha, uint32_t addr, uint32_t *ram,
42 uint32_t cram_size, uint32_t *ext_mem, void **nxt) 42 uint32_t ram_dwords, void **nxt)
43{ 43{
44 int rval; 44 int rval;
45 uint32_t cnt, stat, timer, risc_address, ext_mem_cnt; 45 uint32_t cnt, stat, timer, dwords, idx;
46 uint16_t mb[4]; 46 uint16_t mb0;
47 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 47 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
48 dma_addr_t dump_dma = ha->gid_list_dma;
49 uint32_t *dump = (uint32_t *)ha->gid_list;
48 50
49 rval = QLA_SUCCESS; 51 rval = QLA_SUCCESS;
50 risc_address = ext_mem_cnt = 0; 52 mb0 = 0;
51 memset(mb, 0, sizeof(mb));
52 53
53 /* Code RAM. */ 54 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
54 risc_address = 0x20000;
55 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
56 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 55 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
57 56
58 for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS; 57 dwords = GID_LIST_SIZE / 4;
59 cnt++, risc_address++) { 58 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
60 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 59 cnt += dwords, addr += dwords) {
61 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 60 if (cnt + dwords > ram_dwords)
62 RD_REG_WORD(&reg->mailbox8); 61 dwords = ram_dwords - cnt;
63 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
64
65 for (timer = 6000000; timer; timer--) {
66 /* Check for pending interrupts. */
67 stat = RD_REG_DWORD(&reg->host_status);
68 if (stat & HSRX_RISC_INT) {
69 stat &= 0xff;
70 62
71 if (stat == 0x1 || stat == 0x2 || 63 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
72 stat == 0x10 || stat == 0x11) { 64 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
73 set_bit(MBX_INTERRUPT,
74 &ha->mbx_cmd_flags);
75 65
76 mb[0] = RD_REG_WORD(&reg->mailbox0); 66 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
77 mb[2] = RD_REG_WORD(&reg->mailbox2); 67 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
78 mb[3] = RD_REG_WORD(&reg->mailbox3); 68 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
69 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
79 70
80 WRT_REG_DWORD(&reg->hccr, 71 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
81 HCCRX_CLR_RISC_INT); 72 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
82 RD_REG_DWORD(&reg->hccr);
83 break;
84 }
85
86 /* Clear this intr; it wasn't a mailbox intr */
87 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
88 RD_REG_DWORD(&reg->hccr);
89 }
90 udelay(5);
91 }
92
93 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
94 rval = mb[0] & MBS_MASK;
95 code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
96 } else {
97 rval = QLA_FUNCTION_FAILED;
98 }
99 }
100
101 if (rval == QLA_SUCCESS) {
102 /* External Memory. */
103 risc_address = 0x100000;
104 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
105 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
106 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
107 }
108 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
109 cnt++, risc_address++) {
110 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
111 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
112 RD_REG_WORD(&reg->mailbox8);
113 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 73 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
114 74
115 for (timer = 6000000; timer; timer--) { 75 for (timer = 6000000; timer; timer--) {
@@ -123,9 +83,7 @@ qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
123 set_bit(MBX_INTERRUPT, 83 set_bit(MBX_INTERRUPT,
124 &ha->mbx_cmd_flags); 84 &ha->mbx_cmd_flags);
125 85
126 mb[0] = RD_REG_WORD(&reg->mailbox0); 86 mb0 = RD_REG_WORD(&reg->mailbox0);
127 mb[2] = RD_REG_WORD(&reg->mailbox2);
128 mb[3] = RD_REG_WORD(&reg->mailbox3);
129 87
130 WRT_REG_DWORD(&reg->hccr, 88 WRT_REG_DWORD(&reg->hccr,
131 HCCRX_CLR_RISC_INT); 89 HCCRX_CLR_RISC_INT);
@@ -141,17 +99,34 @@ qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
141 } 99 }
142 100
143 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 101 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
144 rval = mb[0] & MBS_MASK; 102 rval = mb0 & MBS_MASK;
145 ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 103 for (idx = 0; idx < dwords; idx++)
104 ram[cnt + idx] = swab32(dump[idx]);
146 } else { 105 } else {
147 rval = QLA_FUNCTION_FAILED; 106 rval = QLA_FUNCTION_FAILED;
148 } 107 }
149 } 108 }
150 109
151 *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL; 110 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
152 return rval; 111 return rval;
153} 112}
154 113
114static int
115qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
116 uint32_t cram_size, void **nxt)
117{
118 int rval;
119
120 /* Code RAM. */
121 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
122 if (rval != QLA_SUCCESS)
123 return rval;
124
125 /* External Memory. */
126 return qla24xx_dump_ram(ha, 0x100000, *nxt,
127 ha->fw_memory_size - 0x100000 + 1, nxt);
128}
129
155static uint32_t * 130static uint32_t *
156qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 131qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
157 uint32_t count, uint32_t *buf) 132 uint32_t count, uint32_t *buf)
@@ -239,6 +214,90 @@ qla24xx_soft_reset(scsi_qla_host_t *ha)
239 return rval; 214 return rval;
240} 215}
241 216
217static int
218qla2xxx_dump_ram(scsi_qla_host_t *ha, uint32_t addr, uint16_t *ram,
219 uint16_t ram_words, void **nxt)
220{
221 int rval;
222 uint32_t cnt, stat, timer, words, idx;
223 uint16_t mb0;
224 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
225 dma_addr_t dump_dma = ha->gid_list_dma;
226 uint16_t *dump = (uint16_t *)ha->gid_list;
227
228 rval = QLA_SUCCESS;
229 mb0 = 0;
230
231 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
232 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
233
234 words = GID_LIST_SIZE / 2;
235 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
236 cnt += words, addr += words) {
237 if (cnt + words > ram_words)
238 words = ram_words - cnt;
239
240 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
241 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
242
243 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
244 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
245 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
246 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
247
248 WRT_MAILBOX_REG(ha, reg, 4, words);
249 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
250
251 for (timer = 6000000; timer; timer--) {
252 /* Check for pending interrupts. */
253 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
254 if (stat & HSR_RISC_INT) {
255 stat &= 0xff;
256
257 if (stat == 0x1 || stat == 0x2) {
258 set_bit(MBX_INTERRUPT,
259 &ha->mbx_cmd_flags);
260
261 mb0 = RD_MAILBOX_REG(ha, reg, 0);
262
263 /* Release mailbox registers. */
264 WRT_REG_WORD(&reg->semaphore, 0);
265 WRT_REG_WORD(&reg->hccr,
266 HCCR_CLR_RISC_INT);
267 RD_REG_WORD(&reg->hccr);
268 break;
269 } else if (stat == 0x10 || stat == 0x11) {
270 set_bit(MBX_INTERRUPT,
271 &ha->mbx_cmd_flags);
272
273 mb0 = RD_MAILBOX_REG(ha, reg, 0);
274
275 WRT_REG_WORD(&reg->hccr,
276 HCCR_CLR_RISC_INT);
277 RD_REG_WORD(&reg->hccr);
278 break;
279 }
280
281 /* clear this intr; it wasn't a mailbox intr */
282 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
283 RD_REG_WORD(&reg->hccr);
284 }
285 udelay(5);
286 }
287
288 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
289 rval = mb0 & MBS_MASK;
290 for (idx = 0; idx < words; idx++)
291 ram[cnt + idx] = swab16(dump[idx]);
292 } else {
293 rval = QLA_FUNCTION_FAILED;
294 }
295 }
296
297 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
298 return rval;
299}
300
242static inline void 301static inline void
243qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 302qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
244 uint16_t *buf) 303 uint16_t *buf)
@@ -258,19 +317,14 @@ void
258qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 317qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
259{ 318{
260 int rval; 319 int rval;
261 uint32_t cnt, timer; 320 uint32_t cnt;
262 uint32_t risc_address;
263 uint16_t mb0, mb2;
264 321
265 uint32_t stat;
266 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 322 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
267 uint16_t __iomem *dmp_reg; 323 uint16_t __iomem *dmp_reg;
268 unsigned long flags; 324 unsigned long flags;
269 struct qla2300_fw_dump *fw; 325 struct qla2300_fw_dump *fw;
270 uint32_t data_ram_cnt; 326 void *nxt;
271 327
272 risc_address = data_ram_cnt = 0;
273 mb0 = mb2 = 0;
274 flags = 0; 328 flags = 0;
275 329
276 if (!hardware_locked) 330 if (!hardware_locked)
@@ -388,185 +442,23 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
388 } 442 }
389 } 443 }
390 444
391 if (rval == QLA_SUCCESS) { 445 /* Get RISC SRAM. */
392 /* Get RISC SRAM. */ 446 if (rval == QLA_SUCCESS)
393 risc_address = 0x800; 447 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
394 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 448 sizeof(fw->risc_ram) / 2, &nxt);
395 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
396 }
397 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
398 cnt++, risc_address++) {
399 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
400 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
401
402 for (timer = 6000000; timer; timer--) {
403 /* Check for pending interrupts. */
404 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
405 if (stat & HSR_RISC_INT) {
406 stat &= 0xff;
407
408 if (stat == 0x1 || stat == 0x2) {
409 set_bit(MBX_INTERRUPT,
410 &ha->mbx_cmd_flags);
411
412 mb0 = RD_MAILBOX_REG(ha, reg, 0);
413 mb2 = RD_MAILBOX_REG(ha, reg, 2);
414
415 /* Release mailbox registers. */
416 WRT_REG_WORD(&reg->semaphore, 0);
417 WRT_REG_WORD(&reg->hccr,
418 HCCR_CLR_RISC_INT);
419 RD_REG_WORD(&reg->hccr);
420 break;
421 } else if (stat == 0x10 || stat == 0x11) {
422 set_bit(MBX_INTERRUPT,
423 &ha->mbx_cmd_flags);
424
425 mb0 = RD_MAILBOX_REG(ha, reg, 0);
426 mb2 = RD_MAILBOX_REG(ha, reg, 2);
427
428 WRT_REG_WORD(&reg->hccr,
429 HCCR_CLR_RISC_INT);
430 RD_REG_WORD(&reg->hccr);
431 break;
432 }
433
434 /* clear this intr; it wasn't a mailbox intr */
435 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
436 RD_REG_WORD(&reg->hccr);
437 }
438 udelay(5);
439 }
440
441 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
442 rval = mb0 & MBS_MASK;
443 fw->risc_ram[cnt] = htons(mb2);
444 } else {
445 rval = QLA_FUNCTION_FAILED;
446 }
447 }
448
449 if (rval == QLA_SUCCESS) {
450 /* Get stack SRAM. */
451 risc_address = 0x10000;
452 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
453 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
454 }
455 for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
456 cnt++, risc_address++) {
457 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
458 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
459 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
460
461 for (timer = 6000000; timer; timer--) {
462 /* Check for pending interrupts. */
463 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
464 if (stat & HSR_RISC_INT) {
465 stat &= 0xff;
466
467 if (stat == 0x1 || stat == 0x2) {
468 set_bit(MBX_INTERRUPT,
469 &ha->mbx_cmd_flags);
470
471 mb0 = RD_MAILBOX_REG(ha, reg, 0);
472 mb2 = RD_MAILBOX_REG(ha, reg, 2);
473
474 /* Release mailbox registers. */
475 WRT_REG_WORD(&reg->semaphore, 0);
476 WRT_REG_WORD(&reg->hccr,
477 HCCR_CLR_RISC_INT);
478 RD_REG_WORD(&reg->hccr);
479 break;
480 } else if (stat == 0x10 || stat == 0x11) {
481 set_bit(MBX_INTERRUPT,
482 &ha->mbx_cmd_flags);
483
484 mb0 = RD_MAILBOX_REG(ha, reg, 0);
485 mb2 = RD_MAILBOX_REG(ha, reg, 2);
486
487 WRT_REG_WORD(&reg->hccr,
488 HCCR_CLR_RISC_INT);
489 RD_REG_WORD(&reg->hccr);
490 break;
491 }
492
493 /* clear this intr; it wasn't a mailbox intr */
494 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
495 RD_REG_WORD(&reg->hccr);
496 }
497 udelay(5);
498 }
499
500 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
501 rval = mb0 & MBS_MASK;
502 fw->stack_ram[cnt] = htons(mb2);
503 } else {
504 rval = QLA_FUNCTION_FAILED;
505 }
506 }
507
508 if (rval == QLA_SUCCESS) {
509 /* Get data SRAM. */
510 risc_address = 0x11000;
511 data_ram_cnt = ha->fw_memory_size - risc_address + 1;
512 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
513 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
514 }
515 for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
516 cnt++, risc_address++) {
517 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
518 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
519 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
520
521 for (timer = 6000000; timer; timer--) {
522 /* Check for pending interrupts. */
523 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
524 if (stat & HSR_RISC_INT) {
525 stat &= 0xff;
526
527 if (stat == 0x1 || stat == 0x2) {
528 set_bit(MBX_INTERRUPT,
529 &ha->mbx_cmd_flags);
530
531 mb0 = RD_MAILBOX_REG(ha, reg, 0);
532 mb2 = RD_MAILBOX_REG(ha, reg, 2);
533
534 /* Release mailbox registers. */
535 WRT_REG_WORD(&reg->semaphore, 0);
536 WRT_REG_WORD(&reg->hccr,
537 HCCR_CLR_RISC_INT);
538 RD_REG_WORD(&reg->hccr);
539 break;
540 } else if (stat == 0x10 || stat == 0x11) {
541 set_bit(MBX_INTERRUPT,
542 &ha->mbx_cmd_flags);
543
544 mb0 = RD_MAILBOX_REG(ha, reg, 0);
545 mb2 = RD_MAILBOX_REG(ha, reg, 2);
546
547 WRT_REG_WORD(&reg->hccr,
548 HCCR_CLR_RISC_INT);
549 RD_REG_WORD(&reg->hccr);
550 break;
551 }
552 449
553 /* clear this intr; it wasn't a mailbox intr */ 450 /* Get stack SRAM. */
554 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); 451 if (rval == QLA_SUCCESS)
555 RD_REG_WORD(&reg->hccr); 452 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
556 } 453 sizeof(fw->stack_ram) / 2, &nxt);
557 udelay(5);
558 }
559 454
560 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 455 /* Get data SRAM. */
561 rval = mb0 & MBS_MASK; 456 if (rval == QLA_SUCCESS)
562 fw->data_ram[cnt] = htons(mb2); 457 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
563 } else { 458 ha->fw_memory_size - 0x11000 + 1, &nxt);
564 rval = QLA_FUNCTION_FAILED;
565 }
566 }
567 459
568 if (rval == QLA_SUCCESS) 460 if (rval == QLA_SUCCESS)
569 qla2xxx_copy_queues(ha, &fw->data_ram[cnt]); 461 qla2xxx_copy_queues(ha, nxt);
570 462
571 if (rval != QLA_SUCCESS) { 463 if (rval != QLA_SUCCESS) {
572 qla_printk(KERN_WARNING, ha, 464 qla_printk(KERN_WARNING, ha,
@@ -1010,7 +902,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1010 goto qla24xx_fw_dump_failed_0; 902 goto qla24xx_fw_dump_failed_0;
1011 903
1012 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 904 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1013 fw->ext_mem, &nxt); 905 &nxt);
1014 if (rval != QLA_SUCCESS) 906 if (rval != QLA_SUCCESS)
1015 goto qla24xx_fw_dump_failed_0; 907 goto qla24xx_fw_dump_failed_0;
1016 908
@@ -1318,7 +1210,7 @@ qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1318 goto qla25xx_fw_dump_failed_0; 1210 goto qla25xx_fw_dump_failed_0;
1319 1211
1320 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1212 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1321 fw->ext_mem, &nxt); 1213 &nxt);
1322 if (rval != QLA_SUCCESS) 1214 if (rval != QLA_SUCCESS)
1323 goto qla25xx_fw_dump_failed_0; 1215 goto qla25xx_fw_dump_failed_0;
1324 1216
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
index 078f2a15f40b..cf194517400d 100644
--- a/drivers/scsi/qla2xxx/qla_fw.h
+++ b/drivers/scsi/qla2xxx/qla_fw.h
@@ -1036,22 +1036,6 @@ struct mid_db_entry_24xx {
1036 uint8_t reserved_1; 1036 uint8_t reserved_1;
1037}; 1037};
1038 1038
1039 /*
1040 * Virtual Fabric ID type definition.
1041 */
1042typedef struct vf_id {
1043 uint16_t id : 12;
1044 uint16_t priority : 4;
1045} vf_id_t;
1046
1047/*
1048 * Virtual Fabric HopCt type definition.
1049 */
1050typedef struct vf_hopct {
1051 uint16_t reserved : 8;
1052 uint16_t hopct : 8;
1053} vf_hopct_t;
1054
1055/* 1039/*
1056 * Virtual Port Control IOCB 1040 * Virtual Port Control IOCB
1057 */ 1041 */
@@ -1082,10 +1066,10 @@ struct vp_ctrl_entry_24xx {
1082 1066
1083 uint8_t vp_idx_map[16]; 1067 uint8_t vp_idx_map[16];
1084 uint16_t flags; 1068 uint16_t flags;
1085 struct vf_id id; 1069 uint16_t id;
1086 uint16_t reserved_4; 1070 uint16_t reserved_4;
1087 struct vf_hopct hopct; 1071 uint16_t hopct;
1088 uint8_t reserved_5[8]; 1072 uint8_t reserved_5[24];
1089}; 1073};
1090 1074
1091/* 1075/*
@@ -1132,9 +1116,9 @@ struct vp_config_entry_24xx {
1132 uint16_t reserved_vp2; 1116 uint16_t reserved_vp2;
1133 uint8_t port_name_idx2[WWN_SIZE]; 1117 uint8_t port_name_idx2[WWN_SIZE];
1134 uint8_t node_name_idx2[WWN_SIZE]; 1118 uint8_t node_name_idx2[WWN_SIZE];
1135 struct vf_id id; 1119 uint16_t id;
1136 uint16_t reserved_4; 1120 uint16_t reserved_4;
1137 struct vf_hopct hopct; 1121 uint16_t hopct;
1138 uint8_t reserved_5; 1122 uint8_t reserved_5;
1139}; 1123};
1140 1124
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
index 76eb4fecce65..f8827068d30f 100644
--- a/drivers/scsi/qla2xxx/qla_gbl.h
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
@@ -152,10 +152,6 @@ extern int
152qla2x00_issue_iocb(scsi_qla_host_t *, void *, dma_addr_t, size_t); 152qla2x00_issue_iocb(scsi_qla_host_t *, void *, dma_addr_t, size_t);
153 153
154extern int 154extern int
155qla2x00_issue_iocb_timeout(scsi_qla_host_t *, void *, dma_addr_t, size_t,
156 uint32_t);
157
158extern int
159qla2x00_abort_command(scsi_qla_host_t *, srb_t *); 155qla2x00_abort_command(scsi_qla_host_t *, srb_t *);
160 156
161extern int 157extern int
diff --git a/drivers/scsi/qla2xxx/qla_gs.c b/drivers/scsi/qla2xxx/qla_gs.c
index 750d7ef83aae..4cb80b476c85 100644
--- a/drivers/scsi/qla2xxx/qla_gs.c
+++ b/drivers/scsi/qla2xxx/qla_gs.c
@@ -1583,8 +1583,8 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *ha)
1583 eiter->type = __constant_cpu_to_be16(FDMI_PORT_MAX_FRAME_SIZE); 1583 eiter->type = __constant_cpu_to_be16(FDMI_PORT_MAX_FRAME_SIZE);
1584 eiter->len = __constant_cpu_to_be16(4 + 4); 1584 eiter->len = __constant_cpu_to_be16(4 + 4);
1585 max_frame_size = IS_FWI2_CAPABLE(ha) ? 1585 max_frame_size = IS_FWI2_CAPABLE(ha) ?
1586 (uint32_t) icb24->frame_payload_size: 1586 le16_to_cpu(icb24->frame_payload_size):
1587 (uint32_t) ha->init_cb->frame_payload_size; 1587 le16_to_cpu(ha->init_cb->frame_payload_size);
1588 eiter->a.max_frame_size = cpu_to_be32(max_frame_size); 1588 eiter->a.max_frame_size = cpu_to_be32(max_frame_size);
1589 size += 4 + 4; 1589 size += 4 + 4;
1590 1590
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 01e26087c1dd..bbbc5a632a1d 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -3645,7 +3645,7 @@ qla24xx_nvram_config(scsi_qla_host_t *ha)
3645 if (le16_to_cpu(nv->login_timeout) < 4) 3645 if (le16_to_cpu(nv->login_timeout) < 4)
3646 nv->login_timeout = __constant_cpu_to_le16(4); 3646 nv->login_timeout = __constant_cpu_to_le16(4);
3647 ha->login_timeout = le16_to_cpu(nv->login_timeout); 3647 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3648 icb->login_timeout = cpu_to_le16(nv->login_timeout); 3648 icb->login_timeout = nv->login_timeout;
3649 3649
3650 /* Set minimum RATOV to 100 tenths of a second. */ 3650 /* Set minimum RATOV to 100 tenths of a second. */
3651 ha->r_a_tov = 100; 3651 ha->r_a_tov = 100;
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 285479b62d8f..5d9a64a7879b 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -409,6 +409,7 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
409 } 409 }
410 410
411 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 411 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
412 set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags);
412 413
413 ha->flags.management_server_logged_in = 0; 414 ha->flags.management_server_logged_in = 0;
414 qla2x00_post_aen_work(ha, FCH_EVT_LIP, mb[1]); 415 qla2x00_post_aen_work(ha, FCH_EVT_LIP, mb[1]);
@@ -454,8 +455,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
454 455
455 ha->flags.management_server_logged_in = 0; 456 ha->flags.management_server_logged_in = 0;
456 ha->link_data_rate = PORT_SPEED_UNKNOWN; 457 ha->link_data_rate = PORT_SPEED_UNKNOWN;
457 if (ql2xfdmienable)
458 set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags);
459 qla2x00_post_aen_work(ha, FCH_EVT_LINKDOWN, 0); 458 qla2x00_post_aen_work(ha, FCH_EVT_LINKDOWN, 0);
460 break; 459 break;
461 460
@@ -511,6 +510,7 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
511 set_bit(RESET_MARKER_NEEDED, &ha->dpc_flags); 510 set_bit(RESET_MARKER_NEEDED, &ha->dpc_flags);
512 } 511 }
513 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 512 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
513 set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags);
514 514
515 ha->flags.gpsc_supported = 1; 515 ha->flags.gpsc_supported = 1;
516 ha->flags.management_server_logged_in = 0; 516 ha->flags.management_server_logged_in = 0;
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index 7d0a8a4c7719..210060420809 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -681,7 +681,7 @@ qla2x00_verify_checksum(scsi_qla_host_t *ha, uint32_t risc_addr)
681 * Context: 681 * Context:
682 * Kernel context. 682 * Kernel context.
683 */ 683 */
684int 684static int
685qla2x00_issue_iocb_timeout(scsi_qla_host_t *ha, void *buffer, 685qla2x00_issue_iocb_timeout(scsi_qla_host_t *ha, void *buffer,
686 dma_addr_t phys_addr, size_t size, uint32_t tov) 686 dma_addr_t phys_addr, size_t size, uint32_t tov)
687{ 687{
@@ -784,7 +784,6 @@ qla2x00_abort_command(scsi_qla_host_t *ha, srb_t *sp)
784 DEBUG2_3_11(printk("qla2x00_abort_command(%ld): failed=%x.\n", 784 DEBUG2_3_11(printk("qla2x00_abort_command(%ld): failed=%x.\n",
785 ha->host_no, rval)); 785 ha->host_no, rval));
786 } else { 786 } else {
787 sp->flags |= SRB_ABORT_PENDING;
788 DEBUG11(printk("qla2x00_abort_command(%ld): done.\n", 787 DEBUG11(printk("qla2x00_abort_command(%ld): done.\n",
789 ha->host_no)); 788 ha->host_no));
790 } 789 }
@@ -1469,7 +1468,7 @@ qla24xx_login_fabric(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1469 lg->port_id[0] = al_pa; 1468 lg->port_id[0] = al_pa;
1470 lg->port_id[1] = area; 1469 lg->port_id[1] = area;
1471 lg->port_id[2] = domain; 1470 lg->port_id[2] = domain;
1472 lg->vp_index = cpu_to_le16(ha->vp_idx); 1471 lg->vp_index = ha->vp_idx;
1473 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0); 1472 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0);
1474 if (rval != QLA_SUCCESS) { 1473 if (rval != QLA_SUCCESS) {
1475 DEBUG2_3_11(printk("%s(%ld): failed to issue Login IOCB " 1474 DEBUG2_3_11(printk("%s(%ld): failed to issue Login IOCB "
@@ -1724,7 +1723,7 @@ qla24xx_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1724 lg->port_id[0] = al_pa; 1723 lg->port_id[0] = al_pa;
1725 lg->port_id[1] = area; 1724 lg->port_id[1] = area;
1726 lg->port_id[2] = domain; 1725 lg->port_id[2] = domain;
1727 lg->vp_index = cpu_to_le16(ha->vp_idx); 1726 lg->vp_index = ha->vp_idx;
1728 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0); 1727 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0);
1729 if (rval != QLA_SUCCESS) { 1728 if (rval != QLA_SUCCESS) {
1730 DEBUG2_3_11(printk("%s(%ld): failed to issue Logout IOCB " 1729 DEBUG2_3_11(printk("%s(%ld): failed to issue Logout IOCB "
@@ -2210,7 +2209,6 @@ qla24xx_abort_command(scsi_qla_host_t *ha, srb_t *sp)
2210 rval = QLA_FUNCTION_FAILED; 2209 rval = QLA_FUNCTION_FAILED;
2211 } else { 2210 } else {
2212 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no)); 2211 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
2213 sp->flags |= SRB_ABORT_PENDING;
2214 } 2212 }
2215 2213
2216 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2214 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
@@ -2644,12 +2642,11 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *ha,
2644 struct vp_rpt_id_entry_24xx *rptid_entry) 2642 struct vp_rpt_id_entry_24xx *rptid_entry)
2645{ 2643{
2646 uint8_t vp_idx; 2644 uint8_t vp_idx;
2645 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
2647 scsi_qla_host_t *vha; 2646 scsi_qla_host_t *vha;
2648 2647
2649 if (rptid_entry->entry_status != 0) 2648 if (rptid_entry->entry_status != 0)
2650 return; 2649 return;
2651 if (rptid_entry->entry_status != __constant_cpu_to_le16(CS_COMPLETE))
2652 return;
2653 2650
2654 if (rptid_entry->format == 0) { 2651 if (rptid_entry->format == 0) {
2655 DEBUG15(printk("%s:format 0 : scsi(%ld) number of VPs setup %d," 2652 DEBUG15(printk("%s:format 0 : scsi(%ld) number of VPs setup %d,"
@@ -2659,17 +2656,17 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *ha,
2659 rptid_entry->port_id[2], rptid_entry->port_id[1], 2656 rptid_entry->port_id[2], rptid_entry->port_id[1],
2660 rptid_entry->port_id[0])); 2657 rptid_entry->port_id[0]));
2661 } else if (rptid_entry->format == 1) { 2658 } else if (rptid_entry->format == 1) {
2662 vp_idx = LSB(rptid_entry->vp_idx); 2659 vp_idx = LSB(stat);
2663 DEBUG15(printk("%s:format 1: scsi(%ld): VP[%d] enabled " 2660 DEBUG15(printk("%s:format 1: scsi(%ld): VP[%d] enabled "
2664 "- status %d - " 2661 "- status %d - "
2665 "with port id %02x%02x%02x\n",__func__,ha->host_no, 2662 "with port id %02x%02x%02x\n",__func__,ha->host_no,
2666 vp_idx, MSB(rptid_entry->vp_idx), 2663 vp_idx, MSB(stat),
2667 rptid_entry->port_id[2], rptid_entry->port_id[1], 2664 rptid_entry->port_id[2], rptid_entry->port_id[1],
2668 rptid_entry->port_id[0])); 2665 rptid_entry->port_id[0]));
2669 if (vp_idx == 0) 2666 if (vp_idx == 0)
2670 return; 2667 return;
2671 2668
2672 if (MSB(rptid_entry->vp_idx) == 1) 2669 if (MSB(stat) == 1)
2673 return; 2670 return;
2674 2671
2675 list_for_each_entry(vha, &ha->vp_list, vp_list) 2672 list_for_each_entry(vha, &ha->vp_list, vp_list)
@@ -2982,8 +2979,8 @@ qla84xx_verify_chip(struct scsi_qla_host *ha, uint16_t *status)
2982 /* We update the firmware with only one data sequence. */ 2979 /* We update the firmware with only one data sequence. */
2983 options |= VCO_END_OF_DATA; 2980 options |= VCO_END_OF_DATA;
2984 2981
2985 retry = 0;
2986 do { 2982 do {
2983 retry = 0;
2987 memset(mn, 0, sizeof(*mn)); 2984 memset(mn, 0, sizeof(*mn));
2988 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 2985 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
2989 mn->p.req.entry_count = 1; 2986 mn->p.req.entry_count = 1;
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 8b33b163b1d4..3223fd16bcfe 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -67,7 +67,7 @@ static void qla2x00_free_device(scsi_qla_host_t *);
67 67
68static void qla2x00_config_dma_addressing(scsi_qla_host_t *ha); 68static void qla2x00_config_dma_addressing(scsi_qla_host_t *ha);
69 69
70int ql2xfdmienable; 70int ql2xfdmienable=1;
71module_param(ql2xfdmienable, int, S_IRUGO|S_IRUSR); 71module_param(ql2xfdmienable, int, S_IRUGO|S_IRUSR);
72MODULE_PARM_DESC(ql2xfdmienable, 72MODULE_PARM_DESC(ql2xfdmienable,
73 "Enables FDMI registratons " 73 "Enables FDMI registratons "
@@ -2135,7 +2135,7 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2135 kfree(ha->nvram); 2135 kfree(ha->nvram);
2136} 2136}
2137 2137
2138struct qla_work_evt * 2138static struct qla_work_evt *
2139qla2x00_alloc_work(struct scsi_qla_host *ha, enum qla_work_type type, 2139qla2x00_alloc_work(struct scsi_qla_host *ha, enum qla_work_type type,
2140 int locked) 2140 int locked)
2141{ 2141{
@@ -2152,7 +2152,7 @@ qla2x00_alloc_work(struct scsi_qla_host *ha, enum qla_work_type type,
2152 return e; 2152 return e;
2153} 2153}
2154 2154
2155int 2155static int
2156qla2x00_post_work(struct scsi_qla_host *ha, struct qla_work_evt *e, int locked) 2156qla2x00_post_work(struct scsi_qla_host *ha, struct qla_work_evt *e, int locked)
2157{ 2157{
2158 unsigned long flags; 2158 unsigned long flags;
@@ -2373,7 +2373,7 @@ qla2x00_do_dpc(void *data)
2373 } else { 2373 } else {
2374 fcport->login_retry = 0; 2374 fcport->login_retry = 0;
2375 } 2375 }
2376 if (fcport->login_retry == 0) 2376 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
2377 fcport->loop_id = FC_NO_LOOP_ID; 2377 fcport->loop_id = FC_NO_LOOP_ID;
2378 } 2378 }
2379 if (test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 2379 if (test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
@@ -2599,6 +2599,10 @@ qla2x00_timer(scsi_qla_host_t *ha)
2599 start_dpc++; 2599 start_dpc++;
2600 } 2600 }
2601 2601
2602 /* Process any deferred work. */
2603 if (!list_empty(&ha->work_list))
2604 start_dpc++;
2605
2602 /* Schedule the DPC routine if needed */ 2606 /* Schedule the DPC routine if needed */
2603 if ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || 2607 if ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) ||
2604 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || 2608 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) ||
diff --git a/drivers/scsi/qla2xxx/qla_version.h b/drivers/scsi/qla2xxx/qla_version.h
index f42f17acf2cf..afeae2bfe7eb 100644
--- a/drivers/scsi/qla2xxx/qla_version.h
+++ b/drivers/scsi/qla2xxx/qla_version.h
@@ -7,7 +7,7 @@
7/* 7/*
8 * Driver version 8 * Driver version
9 */ 9 */
10#define QLA2XXX_VERSION "8.02.01-k1" 10#define QLA2XXX_VERSION "8.02.01-k2"
11 11
12#define QLA_DRIVER_MAJOR_VER 8 12#define QLA_DRIVER_MAJOR_VER 8
13#define QLA_DRIVER_MINOR_VER 2 13#define QLA_DRIVER_MINOR_VER 2
diff --git a/drivers/scsi/scsi_priv.h b/drivers/scsi/scsi_priv.h
index 3f34e9376b0a..b33e72516ef8 100644
--- a/drivers/scsi/scsi_priv.h
+++ b/drivers/scsi/scsi_priv.h
@@ -121,6 +121,7 @@ extern struct scsi_transport_template blank_transport_template;
121extern void __scsi_remove_device(struct scsi_device *); 121extern void __scsi_remove_device(struct scsi_device *);
122 122
123extern struct bus_type scsi_bus_type; 123extern struct bus_type scsi_bus_type;
124extern struct attribute_group *scsi_sysfs_shost_attr_groups[];
124 125
125/* scsi_netlink.c */ 126/* scsi_netlink.c */
126#ifdef CONFIG_SCSI_NETLINK 127#ifdef CONFIG_SCSI_NETLINK
diff --git a/drivers/scsi/scsi_proc.c b/drivers/scsi/scsi_proc.c
index ed395154a5b1..3a1c99d5c775 100644
--- a/drivers/scsi/scsi_proc.c
+++ b/drivers/scsi/scsi_proc.c
@@ -190,10 +190,14 @@ void scsi_proc_host_rm(struct Scsi_Host *shost)
190 */ 190 */
191static int proc_print_scsidevice(struct device *dev, void *data) 191static int proc_print_scsidevice(struct device *dev, void *data)
192{ 192{
193 struct scsi_device *sdev = to_scsi_device(dev); 193 struct scsi_device *sdev;
194 struct seq_file *s = data; 194 struct seq_file *s = data;
195 int i; 195 int i;
196 196
197 if (!scsi_is_sdev_device(dev))
198 goto out;
199
200 sdev = to_scsi_device(dev);
197 seq_printf(s, 201 seq_printf(s,
198 "Host: scsi%d Channel: %02d Id: %02d Lun: %02d\n Vendor: ", 202 "Host: scsi%d Channel: %02d Id: %02d Lun: %02d\n Vendor: ",
199 sdev->host->host_no, sdev->channel, sdev->id, sdev->lun); 203 sdev->host->host_no, sdev->channel, sdev->id, sdev->lun);
@@ -230,6 +234,7 @@ static int proc_print_scsidevice(struct device *dev, void *data)
230 else 234 else
231 seq_printf(s, "\n"); 235 seq_printf(s, "\n");
232 236
237out:
233 return 0; 238 return 0;
234} 239}
235 240
diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
index e67c14e31bab..fcd7455ffc39 100644
--- a/drivers/scsi/scsi_scan.c
+++ b/drivers/scsi/scsi_scan.c
@@ -322,6 +322,21 @@ out:
322 return NULL; 322 return NULL;
323} 323}
324 324
325static void scsi_target_destroy(struct scsi_target *starget)
326{
327 struct device *dev = &starget->dev;
328 struct Scsi_Host *shost = dev_to_shost(dev->parent);
329 unsigned long flags;
330
331 transport_destroy_device(dev);
332 spin_lock_irqsave(shost->host_lock, flags);
333 if (shost->hostt->target_destroy)
334 shost->hostt->target_destroy(starget);
335 list_del_init(&starget->siblings);
336 spin_unlock_irqrestore(shost->host_lock, flags);
337 put_device(dev);
338}
339
325static void scsi_target_dev_release(struct device *dev) 340static void scsi_target_dev_release(struct device *dev)
326{ 341{
327 struct device *parent = dev->parent; 342 struct device *parent = dev->parent;
@@ -331,9 +346,14 @@ static void scsi_target_dev_release(struct device *dev)
331 put_device(parent); 346 put_device(parent);
332} 347}
333 348
349struct device_type scsi_target_type = {
350 .name = "scsi_target",
351 .release = scsi_target_dev_release,
352};
353
334int scsi_is_target_device(const struct device *dev) 354int scsi_is_target_device(const struct device *dev)
335{ 355{
336 return dev->release == scsi_target_dev_release; 356 return dev->type == &scsi_target_type;
337} 357}
338EXPORT_SYMBOL(scsi_is_target_device); 358EXPORT_SYMBOL(scsi_is_target_device);
339 359
@@ -391,14 +411,17 @@ static struct scsi_target *scsi_alloc_target(struct device *parent,
391 device_initialize(dev); 411 device_initialize(dev);
392 starget->reap_ref = 1; 412 starget->reap_ref = 1;
393 dev->parent = get_device(parent); 413 dev->parent = get_device(parent);
394 dev->release = scsi_target_dev_release;
395 sprintf(dev->bus_id, "target%d:%d:%d", 414 sprintf(dev->bus_id, "target%d:%d:%d",
396 shost->host_no, channel, id); 415 shost->host_no, channel, id);
416#ifndef CONFIG_SYSFS_DEPRECATED
417 dev->bus = &scsi_bus_type;
418#endif
419 dev->type = &scsi_target_type;
397 starget->id = id; 420 starget->id = id;
398 starget->channel = channel; 421 starget->channel = channel;
399 INIT_LIST_HEAD(&starget->siblings); 422 INIT_LIST_HEAD(&starget->siblings);
400 INIT_LIST_HEAD(&starget->devices); 423 INIT_LIST_HEAD(&starget->devices);
401 starget->state = STARGET_RUNNING; 424 starget->state = STARGET_CREATED;
402 starget->scsi_level = SCSI_2; 425 starget->scsi_level = SCSI_2;
403 retry: 426 retry:
404 spin_lock_irqsave(shost->host_lock, flags); 427 spin_lock_irqsave(shost->host_lock, flags);
@@ -411,18 +434,6 @@ static struct scsi_target *scsi_alloc_target(struct device *parent,
411 spin_unlock_irqrestore(shost->host_lock, flags); 434 spin_unlock_irqrestore(shost->host_lock, flags);
412 /* allocate and add */ 435 /* allocate and add */
413 transport_setup_device(dev); 436 transport_setup_device(dev);
414 error = device_add(dev);
415 if (error) {
416 dev_err(dev, "target device_add failed, error %d\n", error);
417 spin_lock_irqsave(shost->host_lock, flags);
418 list_del_init(&starget->siblings);
419 spin_unlock_irqrestore(shost->host_lock, flags);
420 transport_destroy_device(dev);
421 put_device(parent);
422 kfree(starget);
423 return NULL;
424 }
425 transport_add_device(dev);
426 if (shost->hostt->target_alloc) { 437 if (shost->hostt->target_alloc) {
427 error = shost->hostt->target_alloc(starget); 438 error = shost->hostt->target_alloc(starget);
428 439
@@ -430,9 +441,7 @@ static struct scsi_target *scsi_alloc_target(struct device *parent,
430 dev_printk(KERN_ERR, dev, "target allocation failed, error %d\n", error); 441 dev_printk(KERN_ERR, dev, "target allocation failed, error %d\n", error);
431 /* don't want scsi_target_reap to do the final 442 /* don't want scsi_target_reap to do the final
432 * put because it will be under the host lock */ 443 * put because it will be under the host lock */
433 get_device(dev); 444 scsi_target_destroy(starget);
434 scsi_target_reap(starget);
435 put_device(dev);
436 return NULL; 445 return NULL;
437 } 446 }
438 } 447 }
@@ -459,18 +468,10 @@ static void scsi_target_reap_usercontext(struct work_struct *work)
459{ 468{
460 struct scsi_target *starget = 469 struct scsi_target *starget =
461 container_of(work, struct scsi_target, ew.work); 470 container_of(work, struct scsi_target, ew.work);
462 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
463 unsigned long flags;
464 471
465 transport_remove_device(&starget->dev); 472 transport_remove_device(&starget->dev);
466 device_del(&starget->dev); 473 device_del(&starget->dev);
467 transport_destroy_device(&starget->dev); 474 scsi_target_destroy(starget);
468 spin_lock_irqsave(shost->host_lock, flags);
469 if (shost->hostt->target_destroy)
470 shost->hostt->target_destroy(starget);
471 list_del_init(&starget->siblings);
472 spin_unlock_irqrestore(shost->host_lock, flags);
473 put_device(&starget->dev);
474} 475}
475 476
476/** 477/**
@@ -485,21 +486,25 @@ void scsi_target_reap(struct scsi_target *starget)
485{ 486{
486 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); 487 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
487 unsigned long flags; 488 unsigned long flags;
489 enum scsi_target_state state;
490 int empty;
488 491
489 spin_lock_irqsave(shost->host_lock, flags); 492 spin_lock_irqsave(shost->host_lock, flags);
493 state = starget->state;
494 empty = --starget->reap_ref == 0 &&
495 list_empty(&starget->devices) ? 1 : 0;
496 spin_unlock_irqrestore(shost->host_lock, flags);
490 497
491 if (--starget->reap_ref == 0 && list_empty(&starget->devices)) { 498 if (!empty)
492 BUG_ON(starget->state == STARGET_DEL);
493 starget->state = STARGET_DEL;
494 spin_unlock_irqrestore(shost->host_lock, flags);
495 execute_in_process_context(scsi_target_reap_usercontext,
496 &starget->ew);
497 return; 499 return;
498 500
499 } 501 BUG_ON(state == STARGET_DEL);
500 spin_unlock_irqrestore(shost->host_lock, flags); 502 starget->state = STARGET_DEL;
501 503 if (state == STARGET_CREATED)
502 return; 504 scsi_target_destroy(starget);
505 else
506 execute_in_process_context(scsi_target_reap_usercontext,
507 &starget->ew);
503} 508}
504 509
505/** 510/**
@@ -1048,8 +1053,9 @@ static int scsi_probe_and_add_lun(struct scsi_target *starget,
1048 scsi_inq_str(vend, result, 8, 16), 1053 scsi_inq_str(vend, result, 8, 16),
1049 scsi_inq_str(mod, result, 16, 32)); 1054 scsi_inq_str(mod, result, 16, 32));
1050 }); 1055 });
1056
1051 } 1057 }
1052 1058
1053 res = SCSI_SCAN_TARGET_PRESENT; 1059 res = SCSI_SCAN_TARGET_PRESENT;
1054 goto out_free_result; 1060 goto out_free_result;
1055 } 1061 }
@@ -1489,7 +1495,6 @@ struct scsi_device *__scsi_add_device(struct Scsi_Host *shost, uint channel,
1489 if (scsi_host_scan_allowed(shost)) 1495 if (scsi_host_scan_allowed(shost))
1490 scsi_probe_and_add_lun(starget, lun, NULL, &sdev, 1, hostdata); 1496 scsi_probe_and_add_lun(starget, lun, NULL, &sdev, 1, hostdata);
1491 mutex_unlock(&shost->scan_mutex); 1497 mutex_unlock(&shost->scan_mutex);
1492 transport_configure_device(&starget->dev);
1493 scsi_target_reap(starget); 1498 scsi_target_reap(starget);
1494 put_device(&starget->dev); 1499 put_device(&starget->dev);
1495 1500
@@ -1570,7 +1575,6 @@ static void __scsi_scan_target(struct device *parent, unsigned int channel,
1570 out_reap: 1575 out_reap:
1571 /* now determine if the target has any children at all 1576 /* now determine if the target has any children at all
1572 * and if not, nuke it */ 1577 * and if not, nuke it */
1573 transport_configure_device(&starget->dev);
1574 scsi_target_reap(starget); 1578 scsi_target_reap(starget);
1575 1579
1576 put_device(&starget->dev); 1580 put_device(&starget->dev);
diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c
index 67bb20ed45d2..049103f1d16f 100644
--- a/drivers/scsi/scsi_sysfs.c
+++ b/drivers/scsi/scsi_sysfs.c
@@ -21,6 +21,8 @@
21#include "scsi_priv.h" 21#include "scsi_priv.h"
22#include "scsi_logging.h" 22#include "scsi_logging.h"
23 23
24static struct device_type scsi_dev_type;
25
24static const struct { 26static const struct {
25 enum scsi_device_state value; 27 enum scsi_device_state value;
26 char *name; 28 char *name;
@@ -249,18 +251,27 @@ shost_rd_attr(sg_tablesize, "%hu\n");
249shost_rd_attr(unchecked_isa_dma, "%d\n"); 251shost_rd_attr(unchecked_isa_dma, "%d\n");
250shost_rd_attr2(proc_name, hostt->proc_name, "%s\n"); 252shost_rd_attr2(proc_name, hostt->proc_name, "%s\n");
251 253
252static struct device_attribute *scsi_sysfs_shost_attrs[] = { 254static struct attribute *scsi_sysfs_shost_attrs[] = {
253 &dev_attr_unique_id, 255 &dev_attr_unique_id.attr,
254 &dev_attr_host_busy, 256 &dev_attr_host_busy.attr,
255 &dev_attr_cmd_per_lun, 257 &dev_attr_cmd_per_lun.attr,
256 &dev_attr_can_queue, 258 &dev_attr_can_queue.attr,
257 &dev_attr_sg_tablesize, 259 &dev_attr_sg_tablesize.attr,
258 &dev_attr_unchecked_isa_dma, 260 &dev_attr_unchecked_isa_dma.attr,
259 &dev_attr_proc_name, 261 &dev_attr_proc_name.attr,
260 &dev_attr_scan, 262 &dev_attr_scan.attr,
261 &dev_attr_hstate, 263 &dev_attr_hstate.attr,
262 &dev_attr_supported_mode, 264 &dev_attr_supported_mode.attr,
263 &dev_attr_active_mode, 265 &dev_attr_active_mode.attr,
266 NULL
267};
268
269struct attribute_group scsi_shost_attr_group = {
270 .attrs = scsi_sysfs_shost_attrs,
271};
272
273struct attribute_group *scsi_sysfs_shost_attr_groups[] = {
274 &scsi_shost_attr_group,
264 NULL 275 NULL
265}; 276};
266 277
@@ -335,7 +346,12 @@ static struct class sdev_class = {
335/* all probing is done in the individual ->probe routines */ 346/* all probing is done in the individual ->probe routines */
336static int scsi_bus_match(struct device *dev, struct device_driver *gendrv) 347static int scsi_bus_match(struct device *dev, struct device_driver *gendrv)
337{ 348{
338 struct scsi_device *sdp = to_scsi_device(dev); 349 struct scsi_device *sdp;
350
351 if (dev->type != &scsi_dev_type)
352 return 0;
353
354 sdp = to_scsi_device(dev);
339 if (sdp->no_uld_attach) 355 if (sdp->no_uld_attach)
340 return 0; 356 return 0;
341 return (sdp->inq_periph_qual == SCSI_INQ_PQ_CON)? 1: 0; 357 return (sdp->inq_periph_qual == SCSI_INQ_PQ_CON)? 1: 0;
@@ -351,10 +367,16 @@ static int scsi_bus_uevent(struct device *dev, struct kobj_uevent_env *env)
351 367
352static int scsi_bus_suspend(struct device * dev, pm_message_t state) 368static int scsi_bus_suspend(struct device * dev, pm_message_t state)
353{ 369{
354 struct device_driver *drv = dev->driver; 370 struct device_driver *drv;
355 struct scsi_device *sdev = to_scsi_device(dev); 371 struct scsi_device *sdev;
356 int err; 372 int err;
357 373
374 if (dev->type != &scsi_dev_type)
375 return 0;
376
377 drv = dev->driver;
378 sdev = to_scsi_device(dev);
379
358 err = scsi_device_quiesce(sdev); 380 err = scsi_device_quiesce(sdev);
359 if (err) 381 if (err)
360 return err; 382 return err;
@@ -370,10 +392,16 @@ static int scsi_bus_suspend(struct device * dev, pm_message_t state)
370 392
371static int scsi_bus_resume(struct device * dev) 393static int scsi_bus_resume(struct device * dev)
372{ 394{
373 struct device_driver *drv = dev->driver; 395 struct device_driver *drv;
374 struct scsi_device *sdev = to_scsi_device(dev); 396 struct scsi_device *sdev;
375 int err = 0; 397 int err = 0;
376 398
399 if (dev->type != &scsi_dev_type)
400 return 0;
401
402 drv = dev->driver;
403 sdev = to_scsi_device(dev);
404
377 if (drv && drv->resume) 405 if (drv && drv->resume)
378 err = drv->resume(dev); 406 err = drv->resume(dev);
379 407
@@ -781,6 +809,27 @@ sdev_store_queue_type_rw(struct device *dev, struct device_attribute *attr,
781 return count; 809 return count;
782} 810}
783 811
812static int scsi_target_add(struct scsi_target *starget)
813{
814 int error;
815
816 if (starget->state != STARGET_CREATED)
817 return 0;
818
819 error = device_add(&starget->dev);
820 if (error) {
821 dev_err(&starget->dev, "target device_add failed, error %d\n", error);
822 get_device(&starget->dev);
823 scsi_target_reap(starget);
824 put_device(&starget->dev);
825 return error;
826 }
827 transport_add_device(&starget->dev);
828 starget->state = STARGET_RUNNING;
829
830 return 0;
831}
832
784static struct device_attribute sdev_attr_queue_type_rw = 833static struct device_attribute sdev_attr_queue_type_rw =
785 __ATTR(queue_type, S_IRUGO | S_IWUSR, show_queue_type_field, 834 __ATTR(queue_type, S_IRUGO | S_IWUSR, show_queue_type_field,
786 sdev_store_queue_type_rw); 835 sdev_store_queue_type_rw);
@@ -796,10 +845,16 @@ int scsi_sysfs_add_sdev(struct scsi_device *sdev)
796{ 845{
797 int error, i; 846 int error, i;
798 struct request_queue *rq = sdev->request_queue; 847 struct request_queue *rq = sdev->request_queue;
848 struct scsi_target *starget = sdev->sdev_target;
799 849
800 if ((error = scsi_device_set_state(sdev, SDEV_RUNNING)) != 0) 850 if ((error = scsi_device_set_state(sdev, SDEV_RUNNING)) != 0)
801 return error; 851 return error;
802 852
853 error = scsi_target_add(starget);
854 if (error)
855 return error;
856
857 transport_configure_device(&starget->dev);
803 error = device_add(&sdev->sdev_gendev); 858 error = device_add(&sdev->sdev_gendev);
804 if (error) { 859 if (error) {
805 put_device(sdev->sdev_gendev.parent); 860 put_device(sdev->sdev_gendev.parent);
@@ -834,7 +889,7 @@ int scsi_sysfs_add_sdev(struct scsi_device *sdev)
834 goto out; 889 goto out;
835 } 890 }
836 891
837 error = bsg_register_queue(rq, &sdev->sdev_gendev, NULL); 892 error = bsg_register_queue(rq, &sdev->sdev_gendev, NULL, NULL);
838 893
839 if (error) 894 if (error)
840 sdev_printk(KERN_INFO, sdev, 895 sdev_printk(KERN_INFO, sdev,
@@ -971,44 +1026,6 @@ int scsi_register_interface(struct class_interface *intf)
971} 1026}
972EXPORT_SYMBOL(scsi_register_interface); 1027EXPORT_SYMBOL(scsi_register_interface);
973 1028
974
975static struct device_attribute *class_attr_overridden(
976 struct device_attribute **attrs,
977 struct device_attribute *attr)
978{
979 int i;
980
981 if (!attrs)
982 return NULL;
983 for (i = 0; attrs[i]; i++)
984 if (!strcmp(attrs[i]->attr.name, attr->attr.name))
985 return attrs[i];
986 return NULL;
987}
988
989static int class_attr_add(struct device *classdev,
990 struct device_attribute *attr)
991{
992 struct device_attribute *base_attr;
993
994 /*
995 * Spare the caller from having to copy things it's not interested in.
996 */
997 base_attr = class_attr_overridden(scsi_sysfs_shost_attrs, attr);
998 if (base_attr) {
999 /* extend permissions */
1000 attr->attr.mode |= base_attr->attr.mode;
1001
1002 /* override null show/store with default */
1003 if (!attr->show)
1004 attr->show = base_attr->show;
1005 if (!attr->store)
1006 attr->store = base_attr->store;
1007 }
1008
1009 return device_create_file(classdev, attr);
1010}
1011
1012/** 1029/**
1013 * scsi_sysfs_add_host - add scsi host to subsystem 1030 * scsi_sysfs_add_host - add scsi host to subsystem
1014 * @shost: scsi host struct to add to subsystem 1031 * @shost: scsi host struct to add to subsystem
@@ -1018,20 +1035,11 @@ int scsi_sysfs_add_host(struct Scsi_Host *shost)
1018{ 1035{
1019 int error, i; 1036 int error, i;
1020 1037
1038 /* add host specific attributes */
1021 if (shost->hostt->shost_attrs) { 1039 if (shost->hostt->shost_attrs) {
1022 for (i = 0; shost->hostt->shost_attrs[i]; i++) { 1040 for (i = 0; shost->hostt->shost_attrs[i]; i++) {
1023 error = class_attr_add(&shost->shost_dev,
1024 shost->hostt->shost_attrs[i]);
1025 if (error)
1026 return error;
1027 }
1028 }
1029
1030 for (i = 0; scsi_sysfs_shost_attrs[i]; i++) {
1031 if (!class_attr_overridden(shost->hostt->shost_attrs,
1032 scsi_sysfs_shost_attrs[i])) {
1033 error = device_create_file(&shost->shost_dev, 1041 error = device_create_file(&shost->shost_dev,
1034 scsi_sysfs_shost_attrs[i]); 1042 shost->hostt->shost_attrs[i]);
1035 if (error) 1043 if (error)
1036 return error; 1044 return error;
1037 } 1045 }
diff --git a/drivers/scsi/scsi_transport_fc.c b/drivers/scsi/scsi_transport_fc.c
index 6b092a6c295d..5fd64e70029d 100644
--- a/drivers/scsi/scsi_transport_fc.c
+++ b/drivers/scsi/scsi_transport_fc.c
@@ -1961,12 +1961,17 @@ fc_timed_out(struct scsi_cmnd *scmd)
1961} 1961}
1962 1962
1963/* 1963/*
1964 * Must be called with shost->host_lock held 1964 * Called by fc_user_scan to locate an rport on the shost that
1965 * matches the channel and target id, and invoke scsi_scan_target()
1966 * on the rport.
1965 */ 1967 */
1966static int fc_user_scan(struct Scsi_Host *shost, uint channel, 1968static void
1967 uint id, uint lun) 1969fc_user_scan_tgt(struct Scsi_Host *shost, uint channel, uint id, uint lun)
1968{ 1970{
1969 struct fc_rport *rport; 1971 struct fc_rport *rport;
1972 unsigned long flags;
1973
1974 spin_lock_irqsave(shost->host_lock, flags);
1970 1975
1971 list_for_each_entry(rport, &fc_host_rports(shost), peers) { 1976 list_for_each_entry(rport, &fc_host_rports(shost), peers) {
1972 if (rport->scsi_target_id == -1) 1977 if (rport->scsi_target_id == -1)
@@ -1975,13 +1980,54 @@ static int fc_user_scan(struct Scsi_Host *shost, uint channel,
1975 if (rport->port_state != FC_PORTSTATE_ONLINE) 1980 if (rport->port_state != FC_PORTSTATE_ONLINE)
1976 continue; 1981 continue;
1977 1982
1978 if ((channel == SCAN_WILD_CARD || channel == rport->channel) && 1983 if ((channel == rport->channel) &&
1979 (id == SCAN_WILD_CARD || id == rport->scsi_target_id)) { 1984 (id == rport->scsi_target_id)) {
1980 scsi_scan_target(&rport->dev, rport->channel, 1985 spin_unlock_irqrestore(shost->host_lock, flags);
1981 rport->scsi_target_id, lun, 1); 1986 scsi_scan_target(&rport->dev, channel, id, lun, 1);
1987 return;
1982 } 1988 }
1983 } 1989 }
1984 1990
1991 spin_unlock_irqrestore(shost->host_lock, flags);
1992}
1993
1994/*
1995 * Called via sysfs scan routines. Necessary, as the FC transport
1996 * wants to place all target objects below the rport object. So this
1997 * routine must invoke the scsi_scan_target() routine with the rport
1998 * object as the parent.
1999 */
2000static int
2001fc_user_scan(struct Scsi_Host *shost, uint channel, uint id, uint lun)
2002{
2003 uint chlo, chhi;
2004 uint tgtlo, tgthi;
2005
2006 if (((channel != SCAN_WILD_CARD) && (channel > shost->max_channel)) ||
2007 ((id != SCAN_WILD_CARD) && (id >= shost->max_id)) ||
2008 ((lun != SCAN_WILD_CARD) && (lun > shost->max_lun)))
2009 return -EINVAL;
2010
2011 if (channel == SCAN_WILD_CARD) {
2012 chlo = 0;
2013 chhi = shost->max_channel + 1;
2014 } else {
2015 chlo = channel;
2016 chhi = channel + 1;
2017 }
2018
2019 if (id == SCAN_WILD_CARD) {
2020 tgtlo = 0;
2021 tgthi = shost->max_id;
2022 } else {
2023 tgtlo = id;
2024 tgthi = id + 1;
2025 }
2026
2027 for ( ; chlo < chhi; chlo++)
2028 for ( ; tgtlo < tgthi; tgtlo++)
2029 fc_user_scan_tgt(shost, chlo, tgtlo, lun);
2030
1985 return 0; 2031 return 0;
1986} 2032}
1987 2033
diff --git a/drivers/scsi/scsi_transport_sas.c b/drivers/scsi/scsi_transport_sas.c
index 27ec625ab771..7899e3dda9bf 100644
--- a/drivers/scsi/scsi_transport_sas.c
+++ b/drivers/scsi/scsi_transport_sas.c
@@ -192,6 +192,16 @@ static void sas_non_host_smp_request(struct request_queue *q)
192 sas_smp_request(q, rphy_to_shost(rphy), rphy); 192 sas_smp_request(q, rphy_to_shost(rphy), rphy);
193} 193}
194 194
195static void sas_host_release(struct device *dev)
196{
197 struct Scsi_Host *shost = dev_to_shost(dev);
198 struct sas_host_attrs *sas_host = to_sas_host_attrs(shost);
199 struct request_queue *q = sas_host->q;
200
201 if (q)
202 blk_cleanup_queue(q);
203}
204
195static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy) 205static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy)
196{ 206{
197 struct request_queue *q; 207 struct request_queue *q;
@@ -199,6 +209,7 @@ static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy)
199 struct device *dev; 209 struct device *dev;
200 char namebuf[BUS_ID_SIZE]; 210 char namebuf[BUS_ID_SIZE];
201 const char *name; 211 const char *name;
212 void (*release)(struct device *);
202 213
203 if (!to_sas_internal(shost->transportt)->f->smp_handler) { 214 if (!to_sas_internal(shost->transportt)->f->smp_handler) {
204 printk("%s can't handle SMP requests\n", shost->hostt->name); 215 printk("%s can't handle SMP requests\n", shost->hostt->name);
@@ -209,17 +220,19 @@ static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy)
209 q = blk_init_queue(sas_non_host_smp_request, NULL); 220 q = blk_init_queue(sas_non_host_smp_request, NULL);
210 dev = &rphy->dev; 221 dev = &rphy->dev;
211 name = dev->bus_id; 222 name = dev->bus_id;
223 release = NULL;
212 } else { 224 } else {
213 q = blk_init_queue(sas_host_smp_request, NULL); 225 q = blk_init_queue(sas_host_smp_request, NULL);
214 dev = &shost->shost_gendev; 226 dev = &shost->shost_gendev;
215 snprintf(namebuf, sizeof(namebuf), 227 snprintf(namebuf, sizeof(namebuf),
216 "sas_host%d", shost->host_no); 228 "sas_host%d", shost->host_no);
217 name = namebuf; 229 name = namebuf;
230 release = sas_host_release;
218 } 231 }
219 if (!q) 232 if (!q)
220 return -ENOMEM; 233 return -ENOMEM;
221 234
222 error = bsg_register_queue(q, dev, name); 235 error = bsg_register_queue(q, dev, name, release);
223 if (error) { 236 if (error) {
224 blk_cleanup_queue(q); 237 blk_cleanup_queue(q);
225 return -ENOMEM; 238 return -ENOMEM;
@@ -253,7 +266,6 @@ static void sas_bsg_remove(struct Scsi_Host *shost, struct sas_rphy *rphy)
253 return; 266 return;
254 267
255 bsg_unregister_queue(q); 268 bsg_unregister_queue(q);
256 blk_cleanup_queue(q);
257} 269}
258 270
259/* 271/*
@@ -1301,6 +1313,9 @@ static void sas_expander_release(struct device *dev)
1301 struct sas_rphy *rphy = dev_to_rphy(dev); 1313 struct sas_rphy *rphy = dev_to_rphy(dev);
1302 struct sas_expander_device *edev = rphy_to_expander_device(rphy); 1314 struct sas_expander_device *edev = rphy_to_expander_device(rphy);
1303 1315
1316 if (rphy->q)
1317 blk_cleanup_queue(rphy->q);
1318
1304 put_device(dev->parent); 1319 put_device(dev->parent);
1305 kfree(edev); 1320 kfree(edev);
1306} 1321}
@@ -1310,6 +1325,9 @@ static void sas_end_device_release(struct device *dev)
1310 struct sas_rphy *rphy = dev_to_rphy(dev); 1325 struct sas_rphy *rphy = dev_to_rphy(dev);
1311 struct sas_end_device *edev = rphy_to_end_device(rphy); 1326 struct sas_end_device *edev = rphy_to_end_device(rphy);
1312 1327
1328 if (rphy->q)
1329 blk_cleanup_queue(rphy->q);
1330
1313 put_device(dev->parent); 1331 put_device(dev->parent);
1314 kfree(edev); 1332 kfree(edev);
1315} 1333}
diff --git a/drivers/scsi/scsi_transport_spi.c b/drivers/scsi/scsi_transport_spi.c
index bc12b5d5d676..75a64a6cae8c 100644
--- a/drivers/scsi/scsi_transport_spi.c
+++ b/drivers/scsi/scsi_transport_spi.c
@@ -24,6 +24,7 @@
24#include <linux/workqueue.h> 24#include <linux/workqueue.h>
25#include <linux/blkdev.h> 25#include <linux/blkdev.h>
26#include <linux/mutex.h> 26#include <linux/mutex.h>
27#include <linux/sysfs.h>
27#include <scsi/scsi.h> 28#include <scsi/scsi.h>
28#include "scsi_priv.h" 29#include "scsi_priv.h"
29#include <scsi/scsi_device.h> 30#include <scsi/scsi_device.h>
@@ -1374,11 +1375,11 @@ static int spi_host_configure(struct transport_container *tc,
1374 * overloads the return by setting 1<<1 if the attribute should 1375 * overloads the return by setting 1<<1 if the attribute should
1375 * be writeable */ 1376 * be writeable */
1376#define TARGET_ATTRIBUTE_HELPER(name) \ 1377#define TARGET_ATTRIBUTE_HELPER(name) \
1377 (si->f->show_##name ? 1 : 0) + \ 1378 (si->f->show_##name ? S_IRUGO : 0) | \
1378 (si->f->set_##name ? 2 : 0) 1379 (si->f->set_##name ? S_IWUSR : 0)
1379 1380
1380static int target_attribute_is_visible(struct kobject *kobj, 1381static mode_t target_attribute_is_visible(struct kobject *kobj,
1381 struct attribute *attr, int i) 1382 struct attribute *attr, int i)
1382{ 1383{
1383 struct device *cdev = container_of(kobj, struct device, kobj); 1384 struct device *cdev = container_of(kobj, struct device, kobj);
1384 struct scsi_target *starget = transport_class_to_starget(cdev); 1385 struct scsi_target *starget = transport_class_to_starget(cdev);
@@ -1428,7 +1429,7 @@ static int target_attribute_is_visible(struct kobject *kobj,
1428 spi_support_ius(starget)) 1429 spi_support_ius(starget))
1429 return TARGET_ATTRIBUTE_HELPER(hold_mcs); 1430 return TARGET_ATTRIBUTE_HELPER(hold_mcs);
1430 else if (attr == &dev_attr_revalidate.attr) 1431 else if (attr == &dev_attr_revalidate.attr)
1431 return 1; 1432 return S_IWUSR;
1432 1433
1433 return 0; 1434 return 0;
1434} 1435}
@@ -1462,25 +1463,9 @@ static int spi_target_configure(struct transport_container *tc,
1462 struct device *cdev) 1463 struct device *cdev)
1463{ 1464{
1464 struct kobject *kobj = &cdev->kobj; 1465 struct kobject *kobj = &cdev->kobj;
1465 int i; 1466
1466 struct attribute *attr; 1467 /* force an update based on parameters read from the device */
1467 int rc; 1468 sysfs_update_group(kobj, &target_attribute_group);
1468
1469 for (i = 0; (attr = target_attributes[i]) != NULL; i++) {
1470 int j = target_attribute_group.is_visible(kobj, attr, i);
1471
1472 /* FIXME: as well as returning -EEXIST, which we'd like
1473 * to ignore, sysfs also does a WARN_ON and dumps a trace,
1474 * which is bad, so temporarily, skip attributes that are
1475 * already visible (the revalidate one) */
1476 if (j && attr != &dev_attr_revalidate.attr)
1477 rc = sysfs_add_file_to_group(kobj, attr,
1478 target_attribute_group.name);
1479 /* and make the attribute writeable if we have a set
1480 * function */
1481 if ((j & 1))
1482 rc = sysfs_chmod_file(kobj, attr, attr->mode | S_IWUSR);
1483 }
1484 1469
1485 return 0; 1470 return 0;
1486} 1471}
diff --git a/drivers/scsi/sgiwd93.c b/drivers/scsi/sgiwd93.c
index 03e359670506..31fe6051c799 100644
--- a/drivers/scsi/sgiwd93.c
+++ b/drivers/scsi/sgiwd93.c
@@ -313,7 +313,8 @@ static struct platform_driver sgiwd93_driver = {
313 .probe = sgiwd93_probe, 313 .probe = sgiwd93_probe,
314 .remove = __devexit_p(sgiwd93_remove), 314 .remove = __devexit_p(sgiwd93_remove),
315 .driver = { 315 .driver = {
316 .name = "sgiwd93" 316 .name = "sgiwd93",
317 .owner = THIS_MODULE,
317 } 318 }
318}; 319};
319 320
@@ -333,3 +334,4 @@ module_exit(sgiwd93_module_exit);
333MODULE_DESCRIPTION("SGI WD33C93 driver"); 334MODULE_DESCRIPTION("SGI WD33C93 driver");
334MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 335MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
335MODULE_LICENSE("GPL"); 336MODULE_LICENSE("GPL");
337MODULE_ALIAS("platform:sgiwd93");
diff --git a/drivers/scsi/sni_53c710.c b/drivers/scsi/sni_53c710.c
index 0a6b45b1b003..2bbef4c45a0d 100644
--- a/drivers/scsi/sni_53c710.c
+++ b/drivers/scsi/sni_53c710.c
@@ -53,6 +53,7 @@
53MODULE_AUTHOR("Thomas Bogendörfer"); 53MODULE_AUTHOR("Thomas Bogendörfer");
54MODULE_DESCRIPTION("SNI RM 53c710 SCSI Driver"); 54MODULE_DESCRIPTION("SNI RM 53c710 SCSI Driver");
55MODULE_LICENSE("GPL"); 55MODULE_LICENSE("GPL");
56MODULE_ALIAS("platform:snirm_53c710");
56 57
57#define SNIRM710_CLOCK 32 58#define SNIRM710_CLOCK 32
58 59
@@ -136,6 +137,7 @@ static struct platform_driver snirm710_driver = {
136 .remove = __devexit_p(snirm710_driver_remove), 137 .remove = __devexit_p(snirm710_driver_remove),
137 .driver = { 138 .driver = {
138 .name = "snirm_53c710", 139 .name = "snirm_53c710",
140 .owner = THIS_MODULE,
139 }, 141 },
140}; 142};
141 143
diff --git a/drivers/scsi/st.c b/drivers/scsi/st.c
index a860c3a9ae99..e8db66ad0bde 100644
--- a/drivers/scsi/st.c
+++ b/drivers/scsi/st.c
@@ -4322,7 +4322,7 @@ static void do_remove_sysfs_files(void)
4322static ssize_t 4322static ssize_t
4323st_defined_show(struct device *dev, struct device_attribute *attr, char *buf) 4323st_defined_show(struct device *dev, struct device_attribute *attr, char *buf)
4324{ 4324{
4325 struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev); 4325 struct st_modedef *STm = dev_get_drvdata(dev);
4326 ssize_t l = 0; 4326 ssize_t l = 0;
4327 4327
4328 l = snprintf(buf, PAGE_SIZE, "%d\n", STm->defined); 4328 l = snprintf(buf, PAGE_SIZE, "%d\n", STm->defined);
@@ -4334,7 +4334,7 @@ DEVICE_ATTR(defined, S_IRUGO, st_defined_show, NULL);
4334static ssize_t 4334static ssize_t
4335st_defblk_show(struct device *dev, struct device_attribute *attr, char *buf) 4335st_defblk_show(struct device *dev, struct device_attribute *attr, char *buf)
4336{ 4336{
4337 struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev); 4337 struct st_modedef *STm = dev_get_drvdata(dev);
4338 ssize_t l = 0; 4338 ssize_t l = 0;
4339 4339
4340 l = snprintf(buf, PAGE_SIZE, "%d\n", STm->default_blksize); 4340 l = snprintf(buf, PAGE_SIZE, "%d\n", STm->default_blksize);
@@ -4346,7 +4346,7 @@ DEVICE_ATTR(default_blksize, S_IRUGO, st_defblk_show, NULL);
4346static ssize_t 4346static ssize_t
4347st_defdensity_show(struct device *dev, struct device_attribute *attr, char *buf) 4347st_defdensity_show(struct device *dev, struct device_attribute *attr, char *buf)
4348{ 4348{
4349 struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev); 4349 struct st_modedef *STm = dev_get_drvdata(dev);
4350 ssize_t l = 0; 4350 ssize_t l = 0;
4351 char *fmt; 4351 char *fmt;
4352 4352
@@ -4361,7 +4361,7 @@ static ssize_t
4361st_defcompression_show(struct device *dev, struct device_attribute *attr, 4361st_defcompression_show(struct device *dev, struct device_attribute *attr,
4362 char *buf) 4362 char *buf)
4363{ 4363{
4364 struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev); 4364 struct st_modedef *STm = dev_get_drvdata(dev);
4365 ssize_t l = 0; 4365 ssize_t l = 0;
4366 4366
4367 l = snprintf(buf, PAGE_SIZE, "%d\n", STm->default_compression - 1); 4367 l = snprintf(buf, PAGE_SIZE, "%d\n", STm->default_compression - 1);
@@ -4373,7 +4373,7 @@ DEVICE_ATTR(default_compression, S_IRUGO, st_defcompression_show, NULL);
4373static ssize_t 4373static ssize_t
4374st_options_show(struct device *dev, struct device_attribute *attr, char *buf) 4374st_options_show(struct device *dev, struct device_attribute *attr, char *buf)
4375{ 4375{
4376 struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev); 4376 struct st_modedef *STm = dev_get_drvdata(dev);
4377 struct scsi_tape *STp; 4377 struct scsi_tape *STp;
4378 int i, j, options; 4378 int i, j, options;
4379 ssize_t l = 0; 4379 ssize_t l = 0;
diff --git a/drivers/scsi/sun3x_esp.c b/drivers/scsi/sun3x_esp.c
index 06152c7fa689..7514b3a0390e 100644
--- a/drivers/scsi/sun3x_esp.c
+++ b/drivers/scsi/sun3x_esp.c
@@ -294,6 +294,7 @@ static struct platform_driver esp_sun3x_driver = {
294 .remove = __devexit_p(esp_sun3x_remove), 294 .remove = __devexit_p(esp_sun3x_remove),
295 .driver = { 295 .driver = {
296 .name = "sun3x_esp", 296 .name = "sun3x_esp",
297 .owner = THIS_MODULE,
297 }, 298 },
298}; 299};
299 300
@@ -314,3 +315,4 @@ MODULE_VERSION(DRV_VERSION);
314 315
315module_init(sun3x_esp_init); 316module_init(sun3x_esp_init);
316module_exit(sun3x_esp_exit); 317module_exit(sun3x_esp_exit);
318MODULE_ALIAS("platform:sun3x_esp");
diff --git a/drivers/scsi/u14-34f.c b/drivers/scsi/u14-34f.c
index 58d7eee4fe81..640333b1e75c 100644
--- a/drivers/scsi/u14-34f.c
+++ b/drivers/scsi/u14-34f.c
@@ -1715,13 +1715,12 @@ static void flush_dev(struct scsi_device *dev, unsigned long cursec, unsigned in
1715 1715
1716} 1716}
1717 1717
1718static irqreturn_t ihdlr(int irq, unsigned int j) { 1718static irqreturn_t ihdlr(unsigned int j)
1719{
1719 struct scsi_cmnd *SCpnt; 1720 struct scsi_cmnd *SCpnt;
1720 unsigned int i, k, c, status, tstatus, reg, ret; 1721 unsigned int i, k, c, status, tstatus, reg, ret;
1721 struct mscp *spp, *cpp; 1722 struct mscp *spp, *cpp;
1722 1723 int irq = sh[j]->irq;
1723 if (sh[j]->irq != irq)
1724 panic("%s: ihdlr, irq %d, sh[j]->irq %d.\n", BN(j), irq, sh[j]->irq);
1725 1724
1726 /* Check if this board need to be serviced */ 1725 /* Check if this board need to be serviced */
1727 if (!((reg = inb(sh[j]->io_port + REG_SYS_INTR)) & IRQ_ASSERTED)) goto none; 1726 if (!((reg = inb(sh[j]->io_port + REG_SYS_INTR)) & IRQ_ASSERTED)) goto none;
@@ -1935,7 +1934,7 @@ static irqreturn_t do_interrupt_handler(int irq, void *shap) {
1935 if ((j = (unsigned int)((char *)shap - sha)) >= num_boards) return IRQ_NONE; 1934 if ((j = (unsigned int)((char *)shap - sha)) >= num_boards) return IRQ_NONE;
1936 1935
1937 spin_lock_irqsave(sh[j]->host_lock, spin_flags); 1936 spin_lock_irqsave(sh[j]->host_lock, spin_flags);
1938 ret = ihdlr(irq, j); 1937 ret = ihdlr(j);
1939 spin_unlock_irqrestore(sh[j]->host_lock, spin_flags); 1938 spin_unlock_irqrestore(sh[j]->host_lock, spin_flags);
1940 return ret; 1939 return ret;
1941} 1940}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 01:41:19 -0500