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authorJeff Garzik <jgarzik@pobox.com>2005-10-18 18:30:58 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-18 18:30:58 -0400
commit77501f3cb648e18733509a951ed31eddd7ef2c0b (patch)
tree82624caa354394df2422562bf6dda56a2c088704 /drivers/scsi
parent422fa08e538b649a9b80258950d2f8a202f45f19 (diff)
parent59a10b172fccaea793352c00fd9065f0a5b4ef70 (diff)
Merge branch 'upstream'
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/Kconfig27
-rw-r--r--drivers/scsi/Makefile2
-rw-r--r--drivers/scsi/aacraid/linit.c2
-rw-r--r--drivers/scsi/libata-core.c177
-rw-r--r--drivers/scsi/libata-scsi.c55
-rw-r--r--drivers/scsi/libata.h1
-rw-r--r--drivers/scsi/pdc_adma.c739
-rw-r--r--drivers/scsi/qlogicpti.c39
-rw-r--r--drivers/scsi/sata_sil24.c875
9 files changed, 1809 insertions, 108 deletions
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 20019b82b4a8..9c9f162bd6ed 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -489,11 +489,11 @@ config SCSI_SATA_NV
489 489
490 If unsure, say N. 490 If unsure, say N.
491 491
492config SCSI_SATA_PROMISE 492config SCSI_PDC_ADMA
493 tristate "Promise SATA TX2/TX4 support" 493 tristate "Pacific Digital ADMA support"
494 depends on SCSI_SATA && PCI 494 depends on SCSI_SATA && PCI
495 help 495 help
496 This option enables support for Promise Serial ATA TX2/TX4. 496 This option enables support for Pacific Digital ADMA controllers
497 497
498 If unsure, say N. 498 If unsure, say N.
499 499
@@ -505,6 +505,14 @@ config SCSI_SATA_QSTOR
505 505
506 If unsure, say N. 506 If unsure, say N.
507 507
508config SCSI_SATA_PROMISE
509 tristate "Promise SATA TX2/TX4 support"
510 depends on SCSI_SATA && PCI
511 help
512 This option enables support for Promise Serial ATA TX2/TX4.
513
514 If unsure, say N.
515
508config SCSI_SATA_SX4 516config SCSI_SATA_SX4
509 tristate "Promise SATA SX4 support" 517 tristate "Promise SATA SX4 support"
510 depends on SCSI_SATA && PCI && EXPERIMENTAL 518 depends on SCSI_SATA && PCI && EXPERIMENTAL
@@ -521,6 +529,14 @@ config SCSI_SATA_SIL
521 529
522 If unsure, say N. 530 If unsure, say N.
523 531
532config SCSI_SATA_SIL24
533 tristate "Silicon Image 3124/3132 SATA support"
534 depends on SCSI_SATA && PCI && EXPERIMENTAL
535 help
536 This option enables support for Silicon Image 3124/3132 Serial ATA.
537
538 If unsure, say N.
539
524config SCSI_SATA_SIS 540config SCSI_SATA_SIS
525 tristate "SiS 964/180 SATA support" 541 tristate "SiS 964/180 SATA support"
526 depends on SCSI_SATA && PCI && EXPERIMENTAL 542 depends on SCSI_SATA && PCI && EXPERIMENTAL
@@ -553,6 +569,11 @@ config SCSI_SATA_VITESSE
553 569
554 If unsure, say N. 570 If unsure, say N.
555 571
572config SCSI_SATA_INTEL_COMBINED
573 bool
574 depends on IDE=y && !BLK_DEV_IDE_SATA && (SCSI_SATA_AHCI || SCSI_ATA_PIIX)
575 default y
576
556config SCSI_BUSLOGIC 577config SCSI_BUSLOGIC
557 tristate "BusLogic SCSI support" 578 tristate "BusLogic SCSI support"
558 depends on (PCI || ISA || MCA) && SCSI && ISA_DMA_API 579 depends on (PCI || ISA || MCA) && SCSI && ISA_DMA_API
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 48529d180ca8..2d4439826c08 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_SCSI_ATA_PIIX) += libata.o ata_piix.o
130obj-$(CONFIG_SCSI_SATA_PROMISE) += libata.o sata_promise.o 130obj-$(CONFIG_SCSI_SATA_PROMISE) += libata.o sata_promise.o
131obj-$(CONFIG_SCSI_SATA_QSTOR) += libata.o sata_qstor.o 131obj-$(CONFIG_SCSI_SATA_QSTOR) += libata.o sata_qstor.o
132obj-$(CONFIG_SCSI_SATA_SIL) += libata.o sata_sil.o 132obj-$(CONFIG_SCSI_SATA_SIL) += libata.o sata_sil.o
133obj-$(CONFIG_SCSI_SATA_SIL24) += libata.o sata_sil24.o
133obj-$(CONFIG_SCSI_SATA_VIA) += libata.o sata_via.o 134obj-$(CONFIG_SCSI_SATA_VIA) += libata.o sata_via.o
134obj-$(CONFIG_SCSI_SATA_VITESSE) += libata.o sata_vsc.o 135obj-$(CONFIG_SCSI_SATA_VITESSE) += libata.o sata_vsc.o
135obj-$(CONFIG_SCSI_SATA_SIS) += libata.o sata_sis.o 136obj-$(CONFIG_SCSI_SATA_SIS) += libata.o sata_sis.o
@@ -137,6 +138,7 @@ obj-$(CONFIG_SCSI_SATA_SX4) += libata.o sata_sx4.o
137obj-$(CONFIG_SCSI_SATA_NV) += libata.o sata_nv.o 138obj-$(CONFIG_SCSI_SATA_NV) += libata.o sata_nv.o
138obj-$(CONFIG_SCSI_SATA_ULI) += libata.o sata_uli.o 139obj-$(CONFIG_SCSI_SATA_ULI) += libata.o sata_uli.o
139obj-$(CONFIG_SCSI_SATA_MV) += libata.o sata_mv.o 140obj-$(CONFIG_SCSI_SATA_MV) += libata.o sata_mv.o
141obj-$(CONFIG_SCSI_PDC_ADMA) += libata.o pdc_adma.o
140 142
141obj-$(CONFIG_ARM) += arm/ 143obj-$(CONFIG_ARM) += arm/
142 144
diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c
index de8490a92831..a1f9ceef0ac9 100644
--- a/drivers/scsi/aacraid/linit.c
+++ b/drivers/scsi/aacraid/linit.c
@@ -453,9 +453,9 @@ static int aac_eh_reset(struct scsi_cmnd* cmd)
453 /* 453 /*
454 * We can exit If all the commands are complete 454 * We can exit If all the commands are complete
455 */ 455 */
456 spin_unlock_irq(host->host_lock);
456 if (active == 0) 457 if (active == 0)
457 return SUCCESS; 458 return SUCCESS;
458 spin_unlock_irq(host->host_lock);
459 ssleep(1); 459 ssleep(1);
460 spin_lock_irq(host->host_lock); 460 spin_lock_irq(host->host_lock);
461 } 461 }
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c
index d568914c4344..175d4646333d 100644
--- a/drivers/scsi/libata-core.c
+++ b/drivers/scsi/libata-core.c
@@ -63,6 +63,7 @@
63static unsigned int ata_busy_sleep (struct ata_port *ap, 63static unsigned int ata_busy_sleep (struct ata_port *ap,
64 unsigned long tmout_pat, 64 unsigned long tmout_pat,
65 unsigned long tmout); 65 unsigned long tmout);
66static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
66static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev); 67static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
67static void ata_set_mode(struct ata_port *ap); 68static void ata_set_mode(struct ata_port *ap);
68static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev); 69static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
@@ -616,79 +617,53 @@ void ata_tf_from_fis(u8 *fis, struct ata_taskfile *tf)
616 tf->hob_nsect = fis[13]; 617 tf->hob_nsect = fis[13];
617} 618}
618 619
619/** 620static const u8 ata_rw_cmds[] = {
620 * ata_prot_to_cmd - determine which read/write opcodes to use 621 /* pio multi */
621 * @protocol: ATA_PROT_xxx taskfile protocol 622 ATA_CMD_READ_MULTI,
622 * @lba48: true is lba48 is present 623 ATA_CMD_WRITE_MULTI,
623 * 624 ATA_CMD_READ_MULTI_EXT,
624 * Given necessary input, determine which read/write commands 625 ATA_CMD_WRITE_MULTI_EXT,
625 * to use to transfer data. 626 /* pio */
626 * 627 ATA_CMD_PIO_READ,
627 * LOCKING: 628 ATA_CMD_PIO_WRITE,
628 * None. 629 ATA_CMD_PIO_READ_EXT,
629 */ 630 ATA_CMD_PIO_WRITE_EXT,
630static int ata_prot_to_cmd(int protocol, int lba48) 631 /* dma */
631{ 632 ATA_CMD_READ,
632 int rcmd = 0, wcmd = 0; 633 ATA_CMD_WRITE,
633 634 ATA_CMD_READ_EXT,
634 switch (protocol) { 635 ATA_CMD_WRITE_EXT
635 case ATA_PROT_PIO: 636};
636 if (lba48) {
637 rcmd = ATA_CMD_PIO_READ_EXT;
638 wcmd = ATA_CMD_PIO_WRITE_EXT;
639 } else {
640 rcmd = ATA_CMD_PIO_READ;
641 wcmd = ATA_CMD_PIO_WRITE;
642 }
643 break;
644
645 case ATA_PROT_DMA:
646 if (lba48) {
647 rcmd = ATA_CMD_READ_EXT;
648 wcmd = ATA_CMD_WRITE_EXT;
649 } else {
650 rcmd = ATA_CMD_READ;
651 wcmd = ATA_CMD_WRITE;
652 }
653 break;
654
655 default:
656 return -1;
657 }
658
659 return rcmd | (wcmd << 8);
660}
661 637
662/** 638/**
663 * ata_dev_set_protocol - set taskfile protocol and r/w commands 639 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
664 * @dev: device to examine and configure 640 * @qc: command to examine and configure
665 * 641 *
666 * Examine the device configuration, after we have 642 * Examine the device configuration and tf->flags to calculate
667 * read the identify-device page and configured the 643 * the proper read/write commands and protocol to use.
668 * data transfer mode. Set internal state related to
669 * the ATA taskfile protocol (pio, pio mult, dma, etc.)
670 * and calculate the proper read/write commands to use.
671 * 644 *
672 * LOCKING: 645 * LOCKING:
673 * caller. 646 * caller.
674 */ 647 */
675static void ata_dev_set_protocol(struct ata_device *dev) 648void ata_rwcmd_protocol(struct ata_queued_cmd *qc)
676{ 649{
677 int pio = (dev->flags & ATA_DFLAG_PIO); 650 struct ata_taskfile *tf = &qc->tf;
678 int lba48 = (dev->flags & ATA_DFLAG_LBA48); 651 struct ata_device *dev = qc->dev;
679 int proto, cmd;
680 652
681 if (pio) 653 int index, lba48, write;
682 proto = dev->xfer_protocol = ATA_PROT_PIO; 654
683 else 655 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
684 proto = dev->xfer_protocol = ATA_PROT_DMA; 656 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
685 657
686 cmd = ata_prot_to_cmd(proto, lba48); 658 if (dev->flags & ATA_DFLAG_PIO) {
687 if (cmd < 0) 659 tf->protocol = ATA_PROT_PIO;
688 BUG(); 660 index = dev->multi_count ? 0 : 4;
661 } else {
662 tf->protocol = ATA_PROT_DMA;
663 index = 8;
664 }
689 665
690 dev->read_cmd = cmd & 0xff; 666 tf->command = ata_rw_cmds[index + lba48 + write];
691 dev->write_cmd = (cmd >> 8) & 0xff;
692} 667}
693 668
694static const char * xfer_mode_str[] = { 669static const char * xfer_mode_str[] = {
@@ -1266,9 +1241,15 @@ retry:
1266 * anything else.. 1241 * anything else..
1267 * Some drives were very specific about that exact sequence. 1242 * Some drives were very specific about that exact sequence.
1268 */ 1243 */
1269 if (major_version < 4 || (!ata_id_has_lba(dev->id))) 1244 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
1270 ata_dev_init_params(ap, dev); 1245 ata_dev_init_params(ap, dev);
1271 1246
1247 /* current CHS translation info (id[53-58]) might be
1248 * changed. reread the identify device info.
1249 */
1250 ata_dev_reread_id(ap, dev);
1251 }
1252
1272 if (ata_id_has_lba(dev->id)) { 1253 if (ata_id_has_lba(dev->id)) {
1273 dev->flags |= ATA_DFLAG_LBA; 1254 dev->flags |= ATA_DFLAG_LBA;
1274 1255
@@ -1641,7 +1622,7 @@ static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1641 */ 1622 */
1642static void ata_set_mode(struct ata_port *ap) 1623static void ata_set_mode(struct ata_port *ap)
1643{ 1624{
1644 unsigned int i, xfer_shift; 1625 unsigned int xfer_shift;
1645 u8 xfer_mode; 1626 u8 xfer_mode;
1646 int rc; 1627 int rc;
1647 1628
@@ -1670,11 +1651,6 @@ static void ata_set_mode(struct ata_port *ap)
1670 if (ap->ops->post_set_mode) 1651 if (ap->ops->post_set_mode)
1671 ap->ops->post_set_mode(ap); 1652 ap->ops->post_set_mode(ap);
1672 1653
1673 for (i = 0; i < 2; i++) {
1674 struct ata_device *dev = &ap->device[i];
1675 ata_dev_set_protocol(dev);
1676 }
1677
1678 return; 1654 return;
1679 1655
1680err_out: 1656err_out:
@@ -2182,6 +2158,62 @@ static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2182} 2158}
2183 2159
2184/** 2160/**
2161 * ata_dev_reread_id - Reread the device identify device info
2162 * @ap: port where the device is
2163 * @dev: device to reread the identify device info
2164 *
2165 * LOCKING:
2166 */
2167
2168static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2169{
2170 DECLARE_COMPLETION(wait);
2171 struct ata_queued_cmd *qc;
2172 unsigned long flags;
2173 int rc;
2174
2175 qc = ata_qc_new_init(ap, dev);
2176 BUG_ON(qc == NULL);
2177
2178 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
2179 qc->dma_dir = DMA_FROM_DEVICE;
2180
2181 if (dev->class == ATA_DEV_ATA) {
2182 qc->tf.command = ATA_CMD_ID_ATA;
2183 DPRINTK("do ATA identify\n");
2184 } else {
2185 qc->tf.command = ATA_CMD_ID_ATAPI;
2186 DPRINTK("do ATAPI identify\n");
2187 }
2188
2189 qc->tf.flags |= ATA_TFLAG_DEVICE;
2190 qc->tf.protocol = ATA_PROT_PIO;
2191 qc->nsect = 1;
2192
2193 qc->waiting = &wait;
2194 qc->complete_fn = ata_qc_complete_noop;
2195
2196 spin_lock_irqsave(&ap->host_set->lock, flags);
2197 rc = ata_qc_issue(qc);
2198 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2199
2200 if (rc)
2201 goto err_out;
2202
2203 wait_for_completion(&wait);
2204
2205 swap_buf_le16(dev->id, ATA_ID_WORDS);
2206
2207 ata_dump_id(dev);
2208
2209 DPRINTK("EXIT\n");
2210
2211 return;
2212err_out:
2213 ata_port_disable(ap);
2214}
2215
2216/**
2185 * ata_dev_init_params - Issue INIT DEV PARAMS command 2217 * ata_dev_init_params - Issue INIT DEV PARAMS command
2186 * @ap: Port associated with device @dev 2218 * @ap: Port associated with device @dev
2187 * @dev: Device to which command will be sent 2219 * @dev: Device to which command will be sent
@@ -3195,13 +3227,6 @@ struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3195 qc->nbytes = qc->curbytes = 0; 3227 qc->nbytes = qc->curbytes = 0;
3196 3228
3197 ata_tf_init(ap, &qc->tf, dev->devno); 3229 ata_tf_init(ap, &qc->tf, dev->devno);
3198
3199 if (dev->flags & ATA_DFLAG_LBA) {
3200 qc->tf.flags |= ATA_TFLAG_LBA;
3201
3202 if (dev->flags & ATA_DFLAG_LBA48)
3203 qc->tf.flags |= ATA_TFLAG_LBA48;
3204 }
3205 } 3230 }
3206 3231
3207 return qc; 3232 return qc;
diff --git a/drivers/scsi/libata-scsi.c b/drivers/scsi/libata-scsi.c
index 617534b7a25e..1ad75d58c30c 100644
--- a/drivers/scsi/libata-scsi.c
+++ b/drivers/scsi/libata-scsi.c
@@ -784,7 +784,7 @@ static unsigned int ata_scsi_flush_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
784 tf->flags |= ATA_TFLAG_DEVICE; 784 tf->flags |= ATA_TFLAG_DEVICE;
785 tf->protocol = ATA_PROT_NODATA; 785 tf->protocol = ATA_PROT_NODATA;
786 786
787 if ((tf->flags & ATA_TFLAG_LBA48) && 787 if ((qc->dev->flags & ATA_DFLAG_LBA48) &&
788 (ata_id_has_flush_ext(qc->dev->id))) 788 (ata_id_has_flush_ext(qc->dev->id)))
789 tf->command = ATA_CMD_FLUSH_EXT; 789 tf->command = ATA_CMD_FLUSH_EXT;
790 else 790 else
@@ -904,8 +904,6 @@ static unsigned int ata_scsi_verify_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
904{ 904{
905 struct ata_taskfile *tf = &qc->tf; 905 struct ata_taskfile *tf = &qc->tf;
906 struct ata_device *dev = qc->dev; 906 struct ata_device *dev = qc->dev;
907 unsigned int lba = tf->flags & ATA_TFLAG_LBA;
908 unsigned int lba48 = tf->flags & ATA_TFLAG_LBA48;
909 u64 dev_sectors = qc->dev->n_sectors; 907 u64 dev_sectors = qc->dev->n_sectors;
910 u64 block; 908 u64 block;
911 u32 n_block; 909 u32 n_block;
@@ -926,16 +924,16 @@ static unsigned int ata_scsi_verify_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
926 goto out_of_range; 924 goto out_of_range;
927 if ((block + n_block) > dev_sectors) 925 if ((block + n_block) > dev_sectors)
928 goto out_of_range; 926 goto out_of_range;
929 if (lba48) {
930 if (n_block > (64 * 1024))
931 goto invalid_fld;
932 } else {
933 if (n_block > 256)
934 goto invalid_fld;
935 }
936 927
937 if (lba) { 928 if (dev->flags & ATA_DFLAG_LBA) {
938 if (lba48) { 929 tf->flags |= ATA_TFLAG_LBA;
930
931 if (dev->flags & ATA_DFLAG_LBA48) {
932 if (n_block > (64 * 1024))
933 goto invalid_fld;
934
935 /* use LBA48 */
936 tf->flags |= ATA_TFLAG_LBA48;
939 tf->command = ATA_CMD_VERIFY_EXT; 937 tf->command = ATA_CMD_VERIFY_EXT;
940 938
941 tf->hob_nsect = (n_block >> 8) & 0xff; 939 tf->hob_nsect = (n_block >> 8) & 0xff;
@@ -944,6 +942,10 @@ static unsigned int ata_scsi_verify_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
944 tf->hob_lbam = (block >> 32) & 0xff; 942 tf->hob_lbam = (block >> 32) & 0xff;
945 tf->hob_lbal = (block >> 24) & 0xff; 943 tf->hob_lbal = (block >> 24) & 0xff;
946 } else { 944 } else {
945 if (n_block > 256)
946 goto invalid_fld;
947
948 /* use LBA28 */
947 tf->command = ATA_CMD_VERIFY; 949 tf->command = ATA_CMD_VERIFY;
948 950
949 tf->device |= (block >> 24) & 0xf; 951 tf->device |= (block >> 24) & 0xf;
@@ -960,6 +962,9 @@ static unsigned int ata_scsi_verify_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
960 /* CHS */ 962 /* CHS */
961 u32 sect, head, cyl, track; 963 u32 sect, head, cyl, track;
962 964
965 if (n_block > 256)
966 goto invalid_fld;
967
963 /* Convert LBA to CHS */ 968 /* Convert LBA to CHS */
964 track = (u32)block / dev->sectors; 969 track = (u32)block / dev->sectors;
965 cyl = track / dev->heads; 970 cyl = track / dev->heads;
@@ -1025,21 +1030,14 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
1025{ 1030{
1026 struct ata_taskfile *tf = &qc->tf; 1031 struct ata_taskfile *tf = &qc->tf;
1027 struct ata_device *dev = qc->dev; 1032 struct ata_device *dev = qc->dev;
1028 unsigned int lba = tf->flags & ATA_TFLAG_LBA;
1029 unsigned int lba48 = tf->flags & ATA_TFLAG_LBA48;
1030 u64 block; 1033 u64 block;
1031 u32 n_block; 1034 u32 n_block;
1032 1035
1033 tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; 1036 tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
1034 tf->protocol = qc->dev->xfer_protocol;
1035 1037
1036 if (scsicmd[0] == READ_10 || scsicmd[0] == READ_6 || 1038 if (scsicmd[0] == WRITE_10 || scsicmd[0] == WRITE_6 ||
1037 scsicmd[0] == READ_16) { 1039 scsicmd[0] == WRITE_16)
1038 tf->command = qc->dev->read_cmd;
1039 } else {
1040 tf->command = qc->dev->write_cmd;
1041 tf->flags |= ATA_TFLAG_WRITE; 1040 tf->flags |= ATA_TFLAG_WRITE;
1042 }
1043 1041
1044 /* Calculate the SCSI LBA and transfer length. */ 1042 /* Calculate the SCSI LBA and transfer length. */
1045 switch (scsicmd[0]) { 1043 switch (scsicmd[0]) {
@@ -1075,19 +1073,24 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
1075 */ 1073 */
1076 goto nothing_to_do; 1074 goto nothing_to_do;
1077 1075
1078 if (lba) { 1076 if (dev->flags & ATA_DFLAG_LBA) {
1079 if (lba48) { 1077 tf->flags |= ATA_TFLAG_LBA;
1078
1079 if (dev->flags & ATA_DFLAG_LBA48) {
1080 /* The request -may- be too large for LBA48. */ 1080 /* The request -may- be too large for LBA48. */
1081 if ((block >> 48) || (n_block > 65536)) 1081 if ((block >> 48) || (n_block > 65536))
1082 goto out_of_range; 1082 goto out_of_range;
1083 1083
1084 /* use LBA48 */
1085 tf->flags |= ATA_TFLAG_LBA48;
1086
1084 tf->hob_nsect = (n_block >> 8) & 0xff; 1087 tf->hob_nsect = (n_block >> 8) & 0xff;
1085 1088
1086 tf->hob_lbah = (block >> 40) & 0xff; 1089 tf->hob_lbah = (block >> 40) & 0xff;
1087 tf->hob_lbam = (block >> 32) & 0xff; 1090 tf->hob_lbam = (block >> 32) & 0xff;
1088 tf->hob_lbal = (block >> 24) & 0xff; 1091 tf->hob_lbal = (block >> 24) & 0xff;
1089 } else { 1092 } else {
1090 /* LBA28 */ 1093 /* use LBA28 */
1091 1094
1092 /* The request -may- be too large for LBA28. */ 1095 /* The request -may- be too large for LBA28. */
1093 if ((block >> 28) || (n_block > 256)) 1096 if ((block >> 28) || (n_block > 256))
@@ -1096,6 +1099,8 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
1096 tf->device |= (block >> 24) & 0xf; 1099 tf->device |= (block >> 24) & 0xf;
1097 } 1100 }
1098 1101
1102 ata_rwcmd_protocol(qc);
1103
1099 qc->nsect = n_block; 1104 qc->nsect = n_block;
1100 tf->nsect = n_block & 0xff; 1105 tf->nsect = n_block & 0xff;
1101 1106
@@ -1112,6 +1117,8 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc, u8 *scsicmd)
1112 if ((block >> 28) || (n_block > 256)) 1117 if ((block >> 28) || (n_block > 256))
1113 goto out_of_range; 1118 goto out_of_range;
1114 1119
1120 ata_rwcmd_protocol(qc);
1121
1115 /* Convert LBA to CHS */ 1122 /* Convert LBA to CHS */
1116 track = (u32)block / dev->sectors; 1123 track = (u32)block / dev->sectors;
1117 cyl = track / dev->heads; 1124 cyl = track / dev->heads;
diff --git a/drivers/scsi/libata.h b/drivers/scsi/libata.h
index 9d951a2909ce..39cce63dc45d 100644
--- a/drivers/scsi/libata.h
+++ b/drivers/scsi/libata.h
@@ -42,6 +42,7 @@ extern int atapi_enabled;
42extern int ata_qc_complete_noop(struct ata_queued_cmd *qc, u8 drv_stat); 42extern int ata_qc_complete_noop(struct ata_queued_cmd *qc, u8 drv_stat);
43extern struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap, 43extern struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
44 struct ata_device *dev); 44 struct ata_device *dev);
45extern void ata_rwcmd_protocol(struct ata_queued_cmd *qc);
45extern void ata_qc_free(struct ata_queued_cmd *qc); 46extern void ata_qc_free(struct ata_queued_cmd *qc);
46extern int ata_qc_issue(struct ata_queued_cmd *qc); 47extern int ata_qc_issue(struct ata_queued_cmd *qc);
47extern int ata_check_atapi_dma(struct ata_queued_cmd *qc); 48extern int ata_check_atapi_dma(struct ata_queued_cmd *qc);
diff --git a/drivers/scsi/pdc_adma.c b/drivers/scsi/pdc_adma.c
new file mode 100644
index 000000000000..53b8db4be1a9
--- /dev/null
+++ b/drivers/scsi/pdc_adma.c
@@ -0,0 +1,739 @@
1/*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
43#include "scsi.h"
44#include <scsi/scsi_host.h>
45#include <asm/io.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "pdc_adma"
49#define DRV_VERSION "0.01"
50
51/* macro to calculate base address for ATA regs */
52#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
53
54/* macro to calculate base address for ADMA regs */
55#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
56
57enum {
58 ADMA_PORTS = 2,
59 ADMA_CPB_BYTES = 40,
60 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
61 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
62
63 ADMA_DMA_BOUNDARY = 0xffffffff,
64
65 /* global register offsets */
66 ADMA_MODE_LOCK = 0x00c7,
67
68 /* per-channel register offsets */
69 ADMA_CONTROL = 0x0000, /* ADMA control */
70 ADMA_STATUS = 0x0002, /* ADMA status */
71 ADMA_CPB_COUNT = 0x0004, /* CPB count */
72 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
73 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
74 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
75 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
76 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
77
78 /* ADMA_CONTROL register bits */
79 aNIEN = (1 << 8), /* irq mask: 1==masked */
80 aGO = (1 << 7), /* packet trigger ("Go!") */
81 aRSTADM = (1 << 5), /* ADMA logic reset */
82 aRSTA = (1 << 2), /* ATA hard reset */
83 aPIOMD4 = 0x0003, /* PIO mode 4 */
84
85 /* ADMA_STATUS register bits */
86 aPSD = (1 << 6),
87 aUIRQ = (1 << 4),
88 aPERR = (1 << 0),
89
90 /* CPB bits */
91 cDONE = (1 << 0),
92 cVLD = (1 << 0),
93 cDAT = (1 << 2),
94 cIEN = (1 << 3),
95
96 /* PRD bits */
97 pORD = (1 << 4),
98 pDIRO = (1 << 5),
99 pEND = (1 << 7),
100
101 /* ATA register flags */
102 rIGN = (1 << 5),
103 rEND = (1 << 7),
104
105 /* ATA register addresses */
106 ADMA_REGS_CONTROL = 0x0e,
107 ADMA_REGS_SECTOR_COUNT = 0x12,
108 ADMA_REGS_LBA_LOW = 0x13,
109 ADMA_REGS_LBA_MID = 0x14,
110 ADMA_REGS_LBA_HIGH = 0x15,
111 ADMA_REGS_DEVICE = 0x16,
112 ADMA_REGS_COMMAND = 0x17,
113
114 /* PCI device IDs */
115 board_1841_idx = 0, /* ADMA 2-port controller */
116};
117
118typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
119
120struct adma_port_priv {
121 u8 *pkt;
122 dma_addr_t pkt_dma;
123 adma_state_t state;
124};
125
126static int adma_ata_init_one (struct pci_dev *pdev,
127 const struct pci_device_id *ent);
128static irqreturn_t adma_intr (int irq, void *dev_instance,
129 struct pt_regs *regs);
130static int adma_port_start(struct ata_port *ap);
131static void adma_host_stop(struct ata_host_set *host_set);
132static void adma_port_stop(struct ata_port *ap);
133static void adma_phy_reset(struct ata_port *ap);
134static void adma_qc_prep(struct ata_queued_cmd *qc);
135static int adma_qc_issue(struct ata_queued_cmd *qc);
136static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
137static void adma_bmdma_stop(struct ata_queued_cmd *qc);
138static u8 adma_bmdma_status(struct ata_port *ap);
139static void adma_irq_clear(struct ata_port *ap);
140static void adma_eng_timeout(struct ata_port *ap);
141
142static Scsi_Host_Template adma_ata_sht = {
143 .module = THIS_MODULE,
144 .name = DRV_NAME,
145 .ioctl = ata_scsi_ioctl,
146 .queuecommand = ata_scsi_queuecmd,
147 .eh_strategy_handler = ata_scsi_error,
148 .can_queue = ATA_DEF_QUEUE,
149 .this_id = ATA_SHT_THIS_ID,
150 .sg_tablesize = LIBATA_MAX_PRD,
151 .max_sectors = ATA_MAX_SECTORS,
152 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
153 .emulated = ATA_SHT_EMULATED,
154 .use_clustering = ENABLE_CLUSTERING,
155 .proc_name = DRV_NAME,
156 .dma_boundary = ADMA_DMA_BOUNDARY,
157 .slave_configure = ata_scsi_slave_config,
158 .bios_param = ata_std_bios_param,
159};
160
161static struct ata_port_operations adma_ata_ops = {
162 .port_disable = ata_port_disable,
163 .tf_load = ata_tf_load,
164 .tf_read = ata_tf_read,
165 .check_status = ata_check_status,
166 .check_atapi_dma = adma_check_atapi_dma,
167 .exec_command = ata_exec_command,
168 .dev_select = ata_std_dev_select,
169 .phy_reset = adma_phy_reset,
170 .qc_prep = adma_qc_prep,
171 .qc_issue = adma_qc_issue,
172 .eng_timeout = adma_eng_timeout,
173 .irq_handler = adma_intr,
174 .irq_clear = adma_irq_clear,
175 .port_start = adma_port_start,
176 .port_stop = adma_port_stop,
177 .host_stop = adma_host_stop,
178 .bmdma_stop = adma_bmdma_stop,
179 .bmdma_status = adma_bmdma_status,
180};
181
182static struct ata_port_info adma_port_info[] = {
183 /* board_1841_idx */
184 {
185 .sht = &adma_ata_sht,
186 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
187 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO,
188 .pio_mask = 0x10, /* pio4 */
189 .udma_mask = 0x1f, /* udma0-4 */
190 .port_ops = &adma_ata_ops,
191 },
192};
193
194static struct pci_device_id adma_ata_pci_tbl[] = {
195 { PCI_VENDOR_ID_PDC, 0x1841, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
196 board_1841_idx },
197
198 { } /* terminate list */
199};
200
201static struct pci_driver adma_ata_pci_driver = {
202 .name = DRV_NAME,
203 .id_table = adma_ata_pci_tbl,
204 .probe = adma_ata_init_one,
205 .remove = ata_pci_remove_one,
206};
207
208static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
209{
210 return 1; /* ATAPI DMA not yet supported */
211}
212
213static void adma_bmdma_stop(struct ata_queued_cmd *qc)
214{
215 /* nothing */
216}
217
218static u8 adma_bmdma_status(struct ata_port *ap)
219{
220 return 0;
221}
222
223static void adma_irq_clear(struct ata_port *ap)
224{
225 /* nothing */
226}
227
228static void adma_reset_engine(void __iomem *chan)
229{
230 /* reset ADMA to idle state */
231 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
232 udelay(2);
233 writew(aPIOMD4, chan + ADMA_CONTROL);
234 udelay(2);
235}
236
237static void adma_reinit_engine(struct ata_port *ap)
238{
239 struct adma_port_priv *pp = ap->private_data;
240 void __iomem *mmio_base = ap->host_set->mmio_base;
241 void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no);
242
243 /* mask/clear ATA interrupts */
244 writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr);
245 ata_check_status(ap);
246
247 /* reset the ADMA engine */
248 adma_reset_engine(chan);
249
250 /* set in-FIFO threshold to 0x100 */
251 writew(0x100, chan + ADMA_FIFO_IN);
252
253 /* set CPB pointer */
254 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
255
256 /* set out-FIFO threshold to 0x100 */
257 writew(0x100, chan + ADMA_FIFO_OUT);
258
259 /* set CPB count */
260 writew(1, chan + ADMA_CPB_COUNT);
261
262 /* read/discard ADMA status */
263 readb(chan + ADMA_STATUS);
264}
265
266static inline void adma_enter_reg_mode(struct ata_port *ap)
267{
268 void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
269
270 writew(aPIOMD4, chan + ADMA_CONTROL);
271 readb(chan + ADMA_STATUS); /* flush */
272}
273
274static void adma_phy_reset(struct ata_port *ap)
275{
276 struct adma_port_priv *pp = ap->private_data;
277
278 pp->state = adma_state_idle;
279 adma_reinit_engine(ap);
280 ata_port_probe(ap);
281 ata_bus_reset(ap);
282}
283
284static void adma_eng_timeout(struct ata_port *ap)
285{
286 struct adma_port_priv *pp = ap->private_data;
287
288 if (pp->state != adma_state_idle) /* healthy paranoia */
289 pp->state = adma_state_mmio;
290 adma_reinit_engine(ap);
291 ata_eng_timeout(ap);
292}
293
294static int adma_fill_sg(struct ata_queued_cmd *qc)
295{
296 struct scatterlist *sg = qc->sg;
297 struct ata_port *ap = qc->ap;
298 struct adma_port_priv *pp = ap->private_data;
299 u8 *buf = pp->pkt;
300 int nelem, i = (2 + buf[3]) * 8;
301 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
302
303 for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
304 u32 addr;
305 u32 len;
306
307 addr = (u32)sg_dma_address(sg);
308 *(__le32 *)(buf + i) = cpu_to_le32(addr);
309 i += 4;
310
311 len = sg_dma_len(sg) >> 3;
312 *(__le32 *)(buf + i) = cpu_to_le32(len);
313 i += 4;
314
315 if ((nelem + 1) == qc->n_elem)
316 pFLAGS |= pEND;
317 buf[i++] = pFLAGS;
318 buf[i++] = qc->dev->dma_mode & 0xf;
319 buf[i++] = 0; /* pPKLW */
320 buf[i++] = 0; /* reserved */
321
322 *(__le32 *)(buf + i)
323 = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
324 i += 4;
325
326 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", nelem,
327 (unsigned long)addr, len);
328 }
329 return i;
330}
331
332static void adma_qc_prep(struct ata_queued_cmd *qc)
333{
334 struct adma_port_priv *pp = qc->ap->private_data;
335 u8 *buf = pp->pkt;
336 u32 pkt_dma = (u32)pp->pkt_dma;
337 int i = 0;
338
339 VPRINTK("ENTER\n");
340
341 adma_enter_reg_mode(qc->ap);
342 if (qc->tf.protocol != ATA_PROT_DMA) {
343 ata_qc_prep(qc);
344 return;
345 }
346
347 buf[i++] = 0; /* Response flags */
348 buf[i++] = 0; /* reserved */
349 buf[i++] = cVLD | cDAT | cIEN;
350 i++; /* cLEN, gets filled in below */
351
352 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
353 i += 4; /* cNCPB */
354 i += 4; /* cPRD, gets filled in below */
355
356 buf[i++] = 0; /* reserved */
357 buf[i++] = 0; /* reserved */
358 buf[i++] = 0; /* reserved */
359 buf[i++] = 0; /* reserved */
360
361 /* ATA registers; must be a multiple of 4 */
362 buf[i++] = qc->tf.device;
363 buf[i++] = ADMA_REGS_DEVICE;
364 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
365 buf[i++] = qc->tf.hob_nsect;
366 buf[i++] = ADMA_REGS_SECTOR_COUNT;
367 buf[i++] = qc->tf.hob_lbal;
368 buf[i++] = ADMA_REGS_LBA_LOW;
369 buf[i++] = qc->tf.hob_lbam;
370 buf[i++] = ADMA_REGS_LBA_MID;
371 buf[i++] = qc->tf.hob_lbah;
372 buf[i++] = ADMA_REGS_LBA_HIGH;
373 }
374 buf[i++] = qc->tf.nsect;
375 buf[i++] = ADMA_REGS_SECTOR_COUNT;
376 buf[i++] = qc->tf.lbal;
377 buf[i++] = ADMA_REGS_LBA_LOW;
378 buf[i++] = qc->tf.lbam;
379 buf[i++] = ADMA_REGS_LBA_MID;
380 buf[i++] = qc->tf.lbah;
381 buf[i++] = ADMA_REGS_LBA_HIGH;
382 buf[i++] = 0;
383 buf[i++] = ADMA_REGS_CONTROL;
384 buf[i++] = rIGN;
385 buf[i++] = 0;
386 buf[i++] = qc->tf.command;
387 buf[i++] = ADMA_REGS_COMMAND | rEND;
388
389 buf[3] = (i >> 3) - 2; /* cLEN */
390 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
391
392 i = adma_fill_sg(qc);
393 wmb(); /* flush PRDs and pkt to memory */
394#if 0
395 /* dump out CPB + PRDs for debug */
396 {
397 int j, len = 0;
398 static char obuf[2048];
399 for (j = 0; j < i; ++j) {
400 len += sprintf(obuf+len, "%02x ", buf[j]);
401 if ((j & 7) == 7) {
402 printk("%s\n", obuf);
403 len = 0;
404 }
405 }
406 if (len)
407 printk("%s\n", obuf);
408 }
409#endif
410}
411
412static inline void adma_packet_start(struct ata_queued_cmd *qc)
413{
414 struct ata_port *ap = qc->ap;
415 void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
416
417 VPRINTK("ENTER, ap %p\n", ap);
418
419 /* fire up the ADMA engine */
420 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
421}
422
423static int adma_qc_issue(struct ata_queued_cmd *qc)
424{
425 struct adma_port_priv *pp = qc->ap->private_data;
426
427 switch (qc->tf.protocol) {
428 case ATA_PROT_DMA:
429 pp->state = adma_state_pkt;
430 adma_packet_start(qc);
431 return 0;
432
433 case ATA_PROT_ATAPI_DMA:
434 BUG();
435 break;
436
437 default:
438 break;
439 }
440
441 pp->state = adma_state_mmio;
442 return ata_qc_issue_prot(qc);
443}
444
445static inline unsigned int adma_intr_pkt(struct ata_host_set *host_set)
446{
447 unsigned int handled = 0, port_no;
448 u8 __iomem *mmio_base = host_set->mmio_base;
449
450 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
451 struct ata_port *ap = host_set->ports[port_no];
452 struct adma_port_priv *pp;
453 struct ata_queued_cmd *qc;
454 void __iomem *chan = ADMA_REGS(mmio_base, port_no);
455 u8 drv_stat, status = readb(chan + ADMA_STATUS);
456
457 if (status == 0)
458 continue;
459 handled = 1;
460 adma_enter_reg_mode(ap);
461 if ((ap->flags & ATA_FLAG_PORT_DISABLED))
462 continue;
463 pp = ap->private_data;
464 if (!pp || pp->state != adma_state_pkt)
465 continue;
466 qc = ata_qc_from_tag(ap, ap->active_tag);
467 drv_stat = 0;
468 if ((status & (aPERR | aPSD | aUIRQ)))
469 drv_stat = ATA_ERR;
470 else if (pp->pkt[0] != cDONE)
471 drv_stat = ATA_ERR;
472 ata_qc_complete(qc, drv_stat);
473 }
474 return handled;
475}
476
477static inline unsigned int adma_intr_mmio(struct ata_host_set *host_set)
478{
479 unsigned int handled = 0, port_no;
480
481 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
482 struct ata_port *ap;
483 ap = host_set->ports[port_no];
484 if (ap && (!(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))) {
485 struct ata_queued_cmd *qc;
486 struct adma_port_priv *pp = ap->private_data;
487 if (!pp || pp->state != adma_state_mmio)
488 continue;
489 qc = ata_qc_from_tag(ap, ap->active_tag);
490 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
491
492 /* check main status, clearing INTRQ */
493 u8 status = ata_chk_status(ap);
494 if ((status & ATA_BUSY))
495 continue;
496 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
497 ap->id, qc->tf.protocol, status);
498
499 /* complete taskfile transaction */
500 pp->state = adma_state_idle;
501 ata_qc_complete(qc, status);
502 handled = 1;
503 }
504 }
505 }
506 return handled;
507}
508
509static irqreturn_t adma_intr(int irq, void *dev_instance, struct pt_regs *regs)
510{
511 struct ata_host_set *host_set = dev_instance;
512 unsigned int handled = 0;
513
514 VPRINTK("ENTER\n");
515
516 spin_lock(&host_set->lock);
517 handled = adma_intr_pkt(host_set) | adma_intr_mmio(host_set);
518 spin_unlock(&host_set->lock);
519
520 VPRINTK("EXIT\n");
521
522 return IRQ_RETVAL(handled);
523}
524
525static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base)
526{
527 port->cmd_addr =
528 port->data_addr = base + 0x000;
529 port->error_addr =
530 port->feature_addr = base + 0x004;
531 port->nsect_addr = base + 0x008;
532 port->lbal_addr = base + 0x00c;
533 port->lbam_addr = base + 0x010;
534 port->lbah_addr = base + 0x014;
535 port->device_addr = base + 0x018;
536 port->status_addr =
537 port->command_addr = base + 0x01c;
538 port->altstatus_addr =
539 port->ctl_addr = base + 0x038;
540}
541
542static int adma_port_start(struct ata_port *ap)
543{
544 struct device *dev = ap->host_set->dev;
545 struct adma_port_priv *pp;
546 int rc;
547
548 rc = ata_port_start(ap);
549 if (rc)
550 return rc;
551 adma_enter_reg_mode(ap);
552 rc = -ENOMEM;
553 pp = kcalloc(1, sizeof(*pp), GFP_KERNEL);
554 if (!pp)
555 goto err_out;
556 pp->pkt = dma_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
557 GFP_KERNEL);
558 if (!pp->pkt)
559 goto err_out_kfree;
560 /* paranoia? */
561 if ((pp->pkt_dma & 7) != 0) {
562 printk("bad alignment for pp->pkt_dma: %08x\n",
563 (u32)pp->pkt_dma);
564 goto err_out_kfree2;
565 }
566 memset(pp->pkt, 0, ADMA_PKT_BYTES);
567 ap->private_data = pp;
568 adma_reinit_engine(ap);
569 return 0;
570
571err_out_kfree2:
572 kfree(pp);
573err_out_kfree:
574 kfree(pp);
575err_out:
576 ata_port_stop(ap);
577 return rc;
578}
579
580static void adma_port_stop(struct ata_port *ap)
581{
582 struct device *dev = ap->host_set->dev;
583 struct adma_port_priv *pp = ap->private_data;
584
585 adma_reset_engine(ADMA_REGS(ap->host_set->mmio_base, ap->port_no));
586 if (pp != NULL) {
587 ap->private_data = NULL;
588 if (pp->pkt != NULL)
589 dma_free_coherent(dev, ADMA_PKT_BYTES,
590 pp->pkt, pp->pkt_dma);
591 kfree(pp);
592 }
593 ata_port_stop(ap);
594}
595
596static void adma_host_stop(struct ata_host_set *host_set)
597{
598 unsigned int port_no;
599
600 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
601 adma_reset_engine(ADMA_REGS(host_set->mmio_base, port_no));
602
603 ata_pci_host_stop(host_set);
604}
605
606static void adma_host_init(unsigned int chip_id,
607 struct ata_probe_ent *probe_ent)
608{
609 unsigned int port_no;
610 void __iomem *mmio_base = probe_ent->mmio_base;
611
612 /* enable/lock aGO operation */
613 writeb(7, mmio_base + ADMA_MODE_LOCK);
614
615 /* reset the ADMA logic */
616 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
617 adma_reset_engine(ADMA_REGS(mmio_base, port_no));
618}
619
620static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
621{
622 int rc;
623
624 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
625 if (rc) {
626 printk(KERN_ERR DRV_NAME
627 "(%s): 32-bit DMA enable failed\n",
628 pci_name(pdev));
629 return rc;
630 }
631 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
632 if (rc) {
633 printk(KERN_ERR DRV_NAME
634 "(%s): 32-bit consistent DMA enable failed\n",
635 pci_name(pdev));
636 return rc;
637 }
638 return 0;
639}
640
641static int adma_ata_init_one(struct pci_dev *pdev,
642 const struct pci_device_id *ent)
643{
644 static int printed_version;
645 struct ata_probe_ent *probe_ent = NULL;
646 void __iomem *mmio_base;
647 unsigned int board_idx = (unsigned int) ent->driver_data;
648 int rc, port_no;
649
650 if (!printed_version++)
651 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
652
653 rc = pci_enable_device(pdev);
654 if (rc)
655 return rc;
656
657 rc = pci_request_regions(pdev, DRV_NAME);
658 if (rc)
659 goto err_out;
660
661 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
662 rc = -ENODEV;
663 goto err_out_regions;
664 }
665
666 mmio_base = pci_iomap(pdev, 4, 0);
667 if (mmio_base == NULL) {
668 rc = -ENOMEM;
669 goto err_out_regions;
670 }
671
672 rc = adma_set_dma_masks(pdev, mmio_base);
673 if (rc)
674 goto err_out_iounmap;
675
676 probe_ent = kcalloc(1, sizeof(*probe_ent), GFP_KERNEL);
677 if (probe_ent == NULL) {
678 rc = -ENOMEM;
679 goto err_out_iounmap;
680 }
681
682 probe_ent->dev = pci_dev_to_dev(pdev);
683 INIT_LIST_HEAD(&probe_ent->node);
684
685 probe_ent->sht = adma_port_info[board_idx].sht;
686 probe_ent->host_flags = adma_port_info[board_idx].host_flags;
687 probe_ent->pio_mask = adma_port_info[board_idx].pio_mask;
688 probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask;
689 probe_ent->udma_mask = adma_port_info[board_idx].udma_mask;
690 probe_ent->port_ops = adma_port_info[board_idx].port_ops;
691
692 probe_ent->irq = pdev->irq;
693 probe_ent->irq_flags = SA_SHIRQ;
694 probe_ent->mmio_base = mmio_base;
695 probe_ent->n_ports = ADMA_PORTS;
696
697 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
698 adma_ata_setup_port(&probe_ent->port[port_no],
699 ADMA_ATA_REGS((unsigned long)mmio_base, port_no));
700 }
701
702 pci_set_master(pdev);
703
704 /* initialize adapter */
705 adma_host_init(board_idx, probe_ent);
706
707 rc = ata_device_add(probe_ent);
708 kfree(probe_ent);
709 if (rc != ADMA_PORTS)
710 goto err_out_iounmap;
711 return 0;
712
713err_out_iounmap:
714 pci_iounmap(pdev, mmio_base);
715err_out_regions:
716 pci_release_regions(pdev);
717err_out:
718 pci_disable_device(pdev);
719 return rc;
720}
721
722static int __init adma_ata_init(void)
723{
724 return pci_module_init(&adma_ata_pci_driver);
725}
726
727static void __exit adma_ata_exit(void)
728{
729 pci_unregister_driver(&adma_ata_pci_driver);
730}
731
732MODULE_AUTHOR("Mark Lord");
733MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
734MODULE_LICENSE("GPL");
735MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
736MODULE_VERSION(DRV_VERSION);
737
738module_init(adma_ata_init);
739module_exit(adma_ata_exit);
diff --git a/drivers/scsi/qlogicpti.c b/drivers/scsi/qlogicpti.c
index a917ab7475ac..1fd5fc6d0fe3 100644
--- a/drivers/scsi/qlogicpti.c
+++ b/drivers/scsi/qlogicpti.c
@@ -1119,6 +1119,36 @@ static inline void update_can_queue(struct Scsi_Host *host, u_int in_ptr, u_int
1119 host->sg_tablesize = QLOGICPTI_MAX_SG(num_free); 1119 host->sg_tablesize = QLOGICPTI_MAX_SG(num_free);
1120} 1120}
1121 1121
1122static unsigned int scsi_rbuf_get(struct scsi_cmnd *cmd, unsigned char **buf_out)
1123{
1124 unsigned char *buf;
1125 unsigned int buflen;
1126
1127 if (cmd->use_sg) {
1128 struct scatterlist *sg;
1129
1130 sg = (struct scatterlist *) cmd->request_buffer;
1131 buf = kmap_atomic(sg->page, KM_IRQ0) + sg->offset;
1132 buflen = sg->length;
1133 } else {
1134 buf = cmd->request_buffer;
1135 buflen = cmd->request_bufflen;
1136 }
1137
1138 *buf_out = buf;
1139 return buflen;
1140}
1141
1142static void scsi_rbuf_put(struct scsi_cmnd *cmd, unsigned char *buf)
1143{
1144 if (cmd->use_sg) {
1145 struct scatterlist *sg;
1146
1147 sg = (struct scatterlist *) cmd->request_buffer;
1148 kunmap_atomic(buf - sg->offset, KM_IRQ0);
1149 }
1150}
1151
1122/* 1152/*
1123 * Until we scan the entire bus with inquiries, go throught this fella... 1153 * Until we scan the entire bus with inquiries, go throught this fella...
1124 */ 1154 */
@@ -1145,11 +1175,9 @@ static void ourdone(struct scsi_cmnd *Cmnd)
1145 int ok = host_byte(Cmnd->result) == DID_OK; 1175 int ok = host_byte(Cmnd->result) == DID_OK;
1146 if (Cmnd->cmnd[0] == 0x12 && ok) { 1176 if (Cmnd->cmnd[0] == 0x12 && ok) {
1147 unsigned char *iqd; 1177 unsigned char *iqd;
1178 unsigned int iqd_len;
1148 1179
1149 if (Cmnd->use_sg != 0) 1180 iqd_len = scsi_rbuf_get(Cmnd, &iqd);
1150 BUG();
1151
1152 iqd = ((unsigned char *)Cmnd->buffer);
1153 1181
1154 /* tags handled in midlayer */ 1182 /* tags handled in midlayer */
1155 /* enable sync mode? */ 1183 /* enable sync mode? */
@@ -1163,6 +1191,9 @@ static void ourdone(struct scsi_cmnd *Cmnd)
1163 if (iqd[7] & 0x20) { 1191 if (iqd[7] & 0x20) {
1164 qpti->dev_param[tgt].device_flags |= 0x20; 1192 qpti->dev_param[tgt].device_flags |= 0x20;
1165 } 1193 }
1194
1195 scsi_rbuf_put(Cmnd, iqd);
1196
1166 qpti->sbits |= (1 << tgt); 1197 qpti->sbits |= (1 << tgt);
1167 } else if (!ok) { 1198 } else if (!ok) {
1168 qpti->sbits |= (1 << tgt); 1199 qpti->sbits |= (1 << tgt);
diff --git a/drivers/scsi/sata_sil24.c b/drivers/scsi/sata_sil24.c
new file mode 100644
index 000000000000..19857814d69f
--- /dev/null
+++ b/drivers/scsi/sata_sil24.c
@@ -0,0 +1,875 @@
1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/blkdev.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/dma-mapping.h>
38#include <scsi/scsi_host.h>
39#include "scsi.h"
40#include <linux/libata.h>
41#include <asm/io.h>
42
43#define DRV_NAME "sata_sil24"
44#define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
45
46/*
47 * Port request block (PRB) 32 bytes
48 */
49struct sil24_prb {
50 u16 ctrl;
51 u16 prot;
52 u32 rx_cnt;
53 u8 fis[6 * 4];
54};
55
56/*
57 * Scatter gather entry (SGE) 16 bytes
58 */
59struct sil24_sge {
60 u64 addr;
61 u32 cnt;
62 u32 flags;
63};
64
65/*
66 * Port multiplier
67 */
68struct sil24_port_multiplier {
69 u32 diag;
70 u32 sactive;
71};
72
73enum {
74 /*
75 * Global controller registers (128 bytes @ BAR0)
76 */
77 /* 32 bit regs */
78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
79 HOST_CTRL = 0x40,
80 HOST_IRQ_STAT = 0x44,
81 HOST_PHY_CFG = 0x48,
82 HOST_BIST_CTRL = 0x50,
83 HOST_BIST_PTRN = 0x54,
84 HOST_BIST_STAT = 0x58,
85 HOST_MEM_BIST_STAT = 0x5c,
86 HOST_FLASH_CMD = 0x70,
87 /* 8 bit regs */
88 HOST_FLASH_DATA = 0x74,
89 HOST_TRANSITION_DETECT = 0x75,
90 HOST_GPIO_CTRL = 0x76,
91 HOST_I2C_ADDR = 0x78, /* 32 bit */
92 HOST_I2C_DATA = 0x7c,
93 HOST_I2C_XFER_CNT = 0x7e,
94 HOST_I2C_CTRL = 0x7f,
95
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN = (1 << 31),
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
105
106 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
107 /* 32 bit regs */
108 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
113 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
114 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
115 PORT_CMD_ERR = 0x1024, /* command error number */
116 PORT_FIS_CFG = 0x1028,
117 PORT_FIFO_THRES = 0x102c,
118 /* 16 bit regs */
119 PORT_DECODE_ERR_CNT = 0x1040,
120 PORT_DECODE_ERR_THRESH = 0x1042,
121 PORT_CRC_ERR_CNT = 0x1044,
122 PORT_CRC_ERR_THRESH = 0x1046,
123 PORT_HSHK_ERR_CNT = 0x1048,
124 PORT_HSHK_ERR_THRESH = 0x104a,
125 /* 32 bit regs */
126 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL = 0x1f00,
132 PORT_SSTATUS = 0x1f04,
133 PORT_SERROR = 0x1f08,
134 PORT_SACTIVE = 0x1f0c,
135
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST = (1 << 0), /* port reset */
138 PORT_CS_DEV_RST = (1 << 1), /* device reset */
139 PORT_CS_INIT = (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
145
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
155 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
156
157 /* bits[27:16] are unmasked (raw) */
158 PORT_IRQ_RAW_SHIFT = 16,
159 PORT_IRQ_MASKED_MASK = 0x7ff,
160 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
161
162 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
163 PORT_IRQ_STEER_SHIFT = 30,
164 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
165
166 /* PORT_CMD_ERR constants */
167 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
168 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
169 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
170 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
171 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
172 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
173 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
174 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
175 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
176 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
177 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
178 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
179 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
180 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
181 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
182 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
183 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
184 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
185 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
186 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
187 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
188 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
189
190 /*
191 * Other constants
192 */
193 SGE_TRM = (1 << 31), /* Last SGE in chain */
194 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
195
196 /* board id */
197 BID_SIL3124 = 0,
198 BID_SIL3132 = 1,
199 BID_SIL3131 = 2,
200
201 IRQ_STAT_4PORTS = 0xf,
202};
203
204struct sil24_cmd_block {
205 struct sil24_prb prb;
206 struct sil24_sge sge[LIBATA_MAX_PRD];
207};
208
209/*
210 * ap->private_data
211 *
212 * The preview driver always returned 0 for status. We emulate it
213 * here from the previous interrupt.
214 */
215struct sil24_port_priv {
216 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
217 dma_addr_t cmd_block_dma; /* DMA base addr for them */
218 struct ata_taskfile tf; /* Cached taskfile registers */
219};
220
221/* ap->host_set->private_data */
222struct sil24_host_priv {
223 void *host_base; /* global controller control (128 bytes @BAR0) */
224 void *port_base; /* port registers (4 * 8192 bytes @BAR2) */
225};
226
227static u8 sil24_check_status(struct ata_port *ap);
228static u8 sil24_check_err(struct ata_port *ap);
229static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
230static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
231static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
232static void sil24_phy_reset(struct ata_port *ap);
233static void sil24_qc_prep(struct ata_queued_cmd *qc);
234static int sil24_qc_issue(struct ata_queued_cmd *qc);
235static void sil24_irq_clear(struct ata_port *ap);
236static void sil24_eng_timeout(struct ata_port *ap);
237static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
238static int sil24_port_start(struct ata_port *ap);
239static void sil24_port_stop(struct ata_port *ap);
240static void sil24_host_stop(struct ata_host_set *host_set);
241static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
242
243static struct pci_device_id sil24_pci_tbl[] = {
244 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
245 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
246 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
247 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
248 { } /* terminate list */
249};
250
251static struct pci_driver sil24_pci_driver = {
252 .name = DRV_NAME,
253 .id_table = sil24_pci_tbl,
254 .probe = sil24_init_one,
255 .remove = ata_pci_remove_one, /* safe? */
256};
257
258static Scsi_Host_Template sil24_sht = {
259 .module = THIS_MODULE,
260 .name = DRV_NAME,
261 .ioctl = ata_scsi_ioctl,
262 .queuecommand = ata_scsi_queuecmd,
263 .eh_strategy_handler = ata_scsi_error,
264 .can_queue = ATA_DEF_QUEUE,
265 .this_id = ATA_SHT_THIS_ID,
266 .sg_tablesize = LIBATA_MAX_PRD,
267 .max_sectors = ATA_MAX_SECTORS,
268 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
269 .emulated = ATA_SHT_EMULATED,
270 .use_clustering = ATA_SHT_USE_CLUSTERING,
271 .proc_name = DRV_NAME,
272 .dma_boundary = ATA_DMA_BOUNDARY,
273 .slave_configure = ata_scsi_slave_config,
274 .bios_param = ata_std_bios_param,
275 .ordered_flush = 1, /* NCQ not supported yet */
276};
277
278static struct ata_port_operations sil24_ops = {
279 .port_disable = ata_port_disable,
280
281 .check_status = sil24_check_status,
282 .check_altstatus = sil24_check_status,
283 .check_err = sil24_check_err,
284 .dev_select = ata_noop_dev_select,
285
286 .tf_read = sil24_tf_read,
287
288 .phy_reset = sil24_phy_reset,
289
290 .qc_prep = sil24_qc_prep,
291 .qc_issue = sil24_qc_issue,
292
293 .eng_timeout = sil24_eng_timeout,
294
295 .irq_handler = sil24_interrupt,
296 .irq_clear = sil24_irq_clear,
297
298 .scr_read = sil24_scr_read,
299 .scr_write = sil24_scr_write,
300
301 .port_start = sil24_port_start,
302 .port_stop = sil24_port_stop,
303 .host_stop = sil24_host_stop,
304};
305
306/*
307 * Use bits 30-31 of host_flags to encode available port numbers.
308 * Current maxium is 4.
309 */
310#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
311#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
312
313static struct ata_port_info sil24_port_info[] = {
314 /* sil_3124 */
315 {
316 .sht = &sil24_sht,
317 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
318 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
319 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
320 .pio_mask = 0x1f, /* pio0-4 */
321 .mwdma_mask = 0x07, /* mwdma0-2 */
322 .udma_mask = 0x3f, /* udma0-5 */
323 .port_ops = &sil24_ops,
324 },
325 /* sil_3132 */
326 {
327 .sht = &sil24_sht,
328 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
329 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
330 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
331 .pio_mask = 0x1f, /* pio0-4 */
332 .mwdma_mask = 0x07, /* mwdma0-2 */
333 .udma_mask = 0x3f, /* udma0-5 */
334 .port_ops = &sil24_ops,
335 },
336 /* sil_3131/sil_3531 */
337 {
338 .sht = &sil24_sht,
339 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
340 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
341 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
342 .pio_mask = 0x1f, /* pio0-4 */
343 .mwdma_mask = 0x07, /* mwdma0-2 */
344 .udma_mask = 0x3f, /* udma0-5 */
345 .port_ops = &sil24_ops,
346 },
347};
348
349static inline void sil24_update_tf(struct ata_port *ap)
350{
351 struct sil24_port_priv *pp = ap->private_data;
352 void *port = (void *)ap->ioaddr.cmd_addr;
353 struct sil24_prb *prb = port;
354
355 ata_tf_from_fis(prb->fis, &pp->tf);
356}
357
358static u8 sil24_check_status(struct ata_port *ap)
359{
360 struct sil24_port_priv *pp = ap->private_data;
361 return pp->tf.command;
362}
363
364static u8 sil24_check_err(struct ata_port *ap)
365{
366 struct sil24_port_priv *pp = ap->private_data;
367 return pp->tf.feature;
368}
369
370static int sil24_scr_map[] = {
371 [SCR_CONTROL] = 0,
372 [SCR_STATUS] = 1,
373 [SCR_ERROR] = 2,
374 [SCR_ACTIVE] = 3,
375};
376
377static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
378{
379 void *scr_addr = (void *)ap->ioaddr.scr_addr;
380 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
381 void *addr;
382 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
383 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
384 }
385 return 0xffffffffU;
386}
387
388static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
389{
390 void *scr_addr = (void *)ap->ioaddr.scr_addr;
391 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
392 void *addr;
393 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
394 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
395 }
396}
397
398static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
399{
400 struct sil24_port_priv *pp = ap->private_data;
401 *tf = pp->tf;
402}
403
404static void sil24_phy_reset(struct ata_port *ap)
405{
406 __sata_phy_reset(ap);
407 /*
408 * No ATAPI yet. Just unconditionally indicate ATA device.
409 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
410 * and libata core will ignore the device.
411 */
412 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
413 ap->device[0].class = ATA_DEV_ATA;
414}
415
416static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
417 struct sil24_cmd_block *cb)
418{
419 struct scatterlist *sg = qc->sg;
420 struct sil24_sge *sge = cb->sge;
421 unsigned i;
422
423 for (i = 0; i < qc->n_elem; i++, sg++, sge++) {
424 sge->addr = cpu_to_le64(sg_dma_address(sg));
425 sge->cnt = cpu_to_le32(sg_dma_len(sg));
426 sge->flags = 0;
427 sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM);
428 }
429}
430
431static void sil24_qc_prep(struct ata_queued_cmd *qc)
432{
433 struct ata_port *ap = qc->ap;
434 struct sil24_port_priv *pp = ap->private_data;
435 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
436 struct sil24_prb *prb = &cb->prb;
437
438 switch (qc->tf.protocol) {
439 case ATA_PROT_PIO:
440 case ATA_PROT_DMA:
441 case ATA_PROT_NODATA:
442 break;
443 default:
444 /* ATAPI isn't supported yet */
445 BUG();
446 }
447
448 ata_tf_to_fis(&qc->tf, prb->fis, 0);
449
450 if (qc->flags & ATA_QCFLAG_DMAMAP)
451 sil24_fill_sg(qc, cb);
452}
453
454static int sil24_qc_issue(struct ata_queued_cmd *qc)
455{
456 struct ata_port *ap = qc->ap;
457 void *port = (void *)ap->ioaddr.cmd_addr;
458 struct sil24_port_priv *pp = ap->private_data;
459 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
460
461 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
462 return 0;
463}
464
465static void sil24_irq_clear(struct ata_port *ap)
466{
467 /* unused */
468}
469
470static int __sil24_reset_controller(void *port)
471{
472 int cnt;
473 u32 tmp;
474
475 /* Reset controller state. Is this correct? */
476 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
477 readl(port + PORT_CTRL_STAT); /* sync */
478
479 /* Max ~100ms */
480 for (cnt = 0; cnt < 1000; cnt++) {
481 udelay(100);
482 tmp = readl(port + PORT_CTRL_STAT);
483 if (!(tmp & PORT_CS_DEV_RST))
484 break;
485 }
486
487 if (tmp & PORT_CS_DEV_RST)
488 return -1;
489 return 0;
490}
491
492static void sil24_reset_controller(struct ata_port *ap)
493{
494 printk(KERN_NOTICE DRV_NAME
495 " ata%u: resetting controller...\n", ap->id);
496 if (__sil24_reset_controller((void *)ap->ioaddr.cmd_addr))
497 printk(KERN_ERR DRV_NAME
498 " ata%u: failed to reset controller\n", ap->id);
499}
500
501static void sil24_eng_timeout(struct ata_port *ap)
502{
503 struct ata_queued_cmd *qc;
504
505 qc = ata_qc_from_tag(ap, ap->active_tag);
506 if (!qc) {
507 printk(KERN_ERR "ata%u: BUG: tiemout without command\n",
508 ap->id);
509 return;
510 }
511
512 /*
513 * hack alert! We cannot use the supplied completion
514 * function from inside the ->eh_strategy_handler() thread.
515 * libata is the only user of ->eh_strategy_handler() in
516 * any kernel, so the default scsi_done() assumes it is
517 * not being called from the SCSI EH.
518 */
519 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
520 qc->scsidone = scsi_finish_command;
521 ata_qc_complete(qc, ATA_ERR);
522
523 sil24_reset_controller(ap);
524}
525
526static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
527{
528 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
529 struct sil24_port_priv *pp = ap->private_data;
530 void *port = (void *)ap->ioaddr.cmd_addr;
531 u32 irq_stat, cmd_err, sstatus, serror;
532
533 irq_stat = readl(port + PORT_IRQ_STAT);
534 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
535
536 if (!(irq_stat & PORT_IRQ_ERROR)) {
537 /* ignore non-completion, non-error irqs for now */
538 printk(KERN_WARNING DRV_NAME
539 "ata%u: non-error exception irq (irq_stat %x)\n",
540 ap->id, irq_stat);
541 return;
542 }
543
544 cmd_err = readl(port + PORT_CMD_ERR);
545 sstatus = readl(port + PORT_SSTATUS);
546 serror = readl(port + PORT_SERROR);
547 if (serror)
548 writel(serror, port + PORT_SERROR);
549
550 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
551 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
552 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
553
554 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
555 /*
556 * Device is reporting error, tf registers are valid.
557 */
558 sil24_update_tf(ap);
559 } else {
560 /*
561 * Other errors. libata currently doesn't have any
562 * mechanism to report these errors. Just turn on
563 * ATA_ERR.
564 */
565 pp->tf.command = ATA_ERR;
566 }
567
568 if (qc)
569 ata_qc_complete(qc, pp->tf.command);
570
571 sil24_reset_controller(ap);
572}
573
574static inline void sil24_host_intr(struct ata_port *ap)
575{
576 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
577 void *port = (void *)ap->ioaddr.cmd_addr;
578 u32 slot_stat;
579
580 slot_stat = readl(port + PORT_SLOT_STAT);
581 if (!(slot_stat & HOST_SSTAT_ATTN)) {
582 struct sil24_port_priv *pp = ap->private_data;
583 /*
584 * !HOST_SSAT_ATTN guarantees successful completion,
585 * so reading back tf registers is unnecessary for
586 * most commands. TODO: read tf registers for
587 * commands which require these values on successful
588 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
589 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
590 */
591 sil24_update_tf(ap);
592
593 if (qc)
594 ata_qc_complete(qc, pp->tf.command);
595 } else
596 sil24_error_intr(ap, slot_stat);
597}
598
599static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
600{
601 struct ata_host_set *host_set = dev_instance;
602 struct sil24_host_priv *hpriv = host_set->private_data;
603 unsigned handled = 0;
604 u32 status;
605 int i;
606
607 status = readl(hpriv->host_base + HOST_IRQ_STAT);
608
609 if (status == 0xffffffff) {
610 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
611 "PCI fault or device removal?\n");
612 goto out;
613 }
614
615 if (!(status & IRQ_STAT_4PORTS))
616 goto out;
617
618 spin_lock(&host_set->lock);
619
620 for (i = 0; i < host_set->n_ports; i++)
621 if (status & (1 << i)) {
622 struct ata_port *ap = host_set->ports[i];
623 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
624 sil24_host_intr(host_set->ports[i]);
625 handled++;
626 } else
627 printk(KERN_ERR DRV_NAME
628 ": interrupt from disabled port %d\n", i);
629 }
630
631 spin_unlock(&host_set->lock);
632 out:
633 return IRQ_RETVAL(handled);
634}
635
636static int sil24_port_start(struct ata_port *ap)
637{
638 struct device *dev = ap->host_set->dev;
639 struct sil24_port_priv *pp;
640 struct sil24_cmd_block *cb;
641 size_t cb_size = sizeof(*cb);
642 dma_addr_t cb_dma;
643
644 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
645 if (!pp)
646 return -ENOMEM;
647 memset(pp, 0, sizeof(*pp));
648
649 pp->tf.command = ATA_DRDY;
650
651 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
652 if (!cb) {
653 kfree(pp);
654 return -ENOMEM;
655 }
656 memset(cb, 0, cb_size);
657
658 pp->cmd_block = cb;
659 pp->cmd_block_dma = cb_dma;
660
661 ap->private_data = pp;
662
663 return 0;
664}
665
666static void sil24_port_stop(struct ata_port *ap)
667{
668 struct device *dev = ap->host_set->dev;
669 struct sil24_port_priv *pp = ap->private_data;
670 size_t cb_size = sizeof(*pp->cmd_block);
671
672 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
673 kfree(pp);
674}
675
676static void sil24_host_stop(struct ata_host_set *host_set)
677{
678 struct sil24_host_priv *hpriv = host_set->private_data;
679
680 iounmap(hpriv->host_base);
681 iounmap(hpriv->port_base);
682 kfree(hpriv);
683}
684
685static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
686{
687 static int printed_version = 0;
688 unsigned int board_id = (unsigned int)ent->driver_data;
689 struct ata_port_info *pinfo = &sil24_port_info[board_id];
690 struct ata_probe_ent *probe_ent = NULL;
691 struct sil24_host_priv *hpriv = NULL;
692 void *host_base = NULL, *port_base = NULL;
693 int i, rc;
694
695 if (!printed_version++)
696 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
697
698 rc = pci_enable_device(pdev);
699 if (rc)
700 return rc;
701
702 rc = pci_request_regions(pdev, DRV_NAME);
703 if (rc)
704 goto out_disable;
705
706 rc = -ENOMEM;
707 /* ioremap mmio registers */
708 host_base = ioremap(pci_resource_start(pdev, 0),
709 pci_resource_len(pdev, 0));
710 if (!host_base)
711 goto out_free;
712 port_base = ioremap(pci_resource_start(pdev, 2),
713 pci_resource_len(pdev, 2));
714 if (!port_base)
715 goto out_free;
716
717 /* allocate & init probe_ent and hpriv */
718 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
719 if (!probe_ent)
720 goto out_free;
721
722 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
723 if (!hpriv)
724 goto out_free;
725
726 memset(probe_ent, 0, sizeof(*probe_ent));
727 probe_ent->dev = pci_dev_to_dev(pdev);
728 INIT_LIST_HEAD(&probe_ent->node);
729
730 probe_ent->sht = pinfo->sht;
731 probe_ent->host_flags = pinfo->host_flags;
732 probe_ent->pio_mask = pinfo->pio_mask;
733 probe_ent->udma_mask = pinfo->udma_mask;
734 probe_ent->port_ops = pinfo->port_ops;
735 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
736
737 probe_ent->irq = pdev->irq;
738 probe_ent->irq_flags = SA_SHIRQ;
739 probe_ent->mmio_base = port_base;
740 probe_ent->private_data = hpriv;
741
742 memset(hpriv, 0, sizeof(*hpriv));
743 hpriv->host_base = host_base;
744 hpriv->port_base = port_base;
745
746 /*
747 * Configure the device
748 */
749 /*
750 * FIXME: This device is certainly 64-bit capable. We just
751 * don't know how to use it. After fixing 32bit activation in
752 * this function, enable 64bit masks here.
753 */
754 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
755 if (rc) {
756 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
757 pci_name(pdev));
758 goto out_free;
759 }
760 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
761 if (rc) {
762 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
763 pci_name(pdev));
764 goto out_free;
765 }
766
767 /* GPIO off */
768 writel(0, host_base + HOST_FLASH_CMD);
769
770 /* Mask interrupts during initialization */
771 writel(0, host_base + HOST_CTRL);
772
773 for (i = 0; i < probe_ent->n_ports; i++) {
774 void *port = port_base + i * PORT_REGS_SIZE;
775 unsigned long portu = (unsigned long)port;
776 u32 tmp;
777 int cnt;
778
779 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
780 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
781
782 ata_std_ports(&probe_ent->port[i]);
783
784 /* Initial PHY setting */
785 writel(0x20c, port + PORT_PHY_CFG);
786
787 /* Clear port RST */
788 tmp = readl(port + PORT_CTRL_STAT);
789 if (tmp & PORT_CS_PORT_RST) {
790 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
791 readl(port + PORT_CTRL_STAT); /* sync */
792 for (cnt = 0; cnt < 10; cnt++) {
793 msleep(10);
794 tmp = readl(port + PORT_CTRL_STAT);
795 if (!(tmp & PORT_CS_PORT_RST))
796 break;
797 }
798 if (tmp & PORT_CS_PORT_RST)
799 printk(KERN_ERR DRV_NAME
800 "(%s): failed to clear port RST\n",
801 pci_name(pdev));
802 }
803
804 /* Zero error counters. */
805 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
806 writel(0x8000, port + PORT_CRC_ERR_THRESH);
807 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
808 writel(0x0000, port + PORT_DECODE_ERR_CNT);
809 writel(0x0000, port + PORT_CRC_ERR_CNT);
810 writel(0x0000, port + PORT_HSHK_ERR_CNT);
811
812 /* FIXME: 32bit activation? */
813 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
814 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
815
816 /* Configure interrupts */
817 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
818 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
819 port + PORT_IRQ_ENABLE_SET);
820
821 /* Clear interrupts */
822 writel(0x0fff0fff, port + PORT_IRQ_STAT);
823 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
824
825 /* Clear port multiplier enable and resume bits */
826 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
827
828 /* Reset itself */
829 if (__sil24_reset_controller(port))
830 printk(KERN_ERR DRV_NAME
831 "(%s): failed to reset controller\n",
832 pci_name(pdev));
833 }
834
835 /* Turn on interrupts */
836 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
837
838 pci_set_master(pdev);
839
840 /* FIXME: check ata_device_add return value */
841 ata_device_add(probe_ent);
842
843 kfree(probe_ent);
844 return 0;
845
846 out_free:
847 if (host_base)
848 iounmap(host_base);
849 if (port_base)
850 iounmap(port_base);
851 kfree(probe_ent);
852 kfree(hpriv);
853 pci_release_regions(pdev);
854 out_disable:
855 pci_disable_device(pdev);
856 return rc;
857}
858
859static int __init sil24_init(void)
860{
861 return pci_module_init(&sil24_pci_driver);
862}
863
864static void __exit sil24_exit(void)
865{
866 pci_unregister_driver(&sil24_pci_driver);
867}
868
869MODULE_AUTHOR("Tejun Heo");
870MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
871MODULE_LICENSE("GPL");
872MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
873
874module_init(sil24_init);
875module_exit(sil24_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 00:07:02 -0500