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authorSakthivel K <Sakthivel.SaravananKamalRaju@pmcs.com>2013-04-17 06:56:36 -0400
committerJames Bottomley <JBottomley@Parallels.com>2013-05-10 10:47:45 -0400
commite574210170c4a9a1bf1d3afd158d06edd3a840de (patch)
tree00423e7125d999bef9b9aff810e7f673cc89f3ed /drivers/scsi
parent6a7252fdb0c3259d123c39c365ea4a7740885279 (diff)
[SCSI] pm80xx: Added SPCv/ve specific ids, variables and modify for SPC
Updated pci id table with device, vendor, subdevice and subvendor ids for 8081, 8088, 8089 SAS/SATA controllers. Added SPCv/ve related macros. Updated macros, hba info structure and other structures for SPCv/ve. Update of structure and variable names for SPC hardware functionalities. Signed-off-by: Sakthivel K <Sakthivel.SaravananKamalRaju@pmcs.com> Signed-off-by: Anand Kumar S <AnandKumar.Santhanam@pmcs.com> Acked-by: Jack Wang <jack_wang@usish.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/pm8001/pm8001_ctl.c69
-rw-r--r--drivers/scsi/pm8001/pm8001_defs.h19
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.c213
-rw-r--r--drivers/scsi/pm8001/pm8001_init.c48
-rw-r--r--drivers/scsi/pm8001/pm8001_sas.h92
5 files changed, 320 insertions, 121 deletions
diff --git a/drivers/scsi/pm8001/pm8001_ctl.c b/drivers/scsi/pm8001/pm8001_ctl.c
index 45bc197bc22f..ae2b1242d0ac 100644
--- a/drivers/scsi/pm8001/pm8001_ctl.c
+++ b/drivers/scsi/pm8001/pm8001_ctl.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver
3 * 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd. 4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved. 5 * All rights reserved.
@@ -58,8 +58,13 @@ static ssize_t pm8001_ctl_mpi_interface_rev_show(struct device *cdev,
58 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 58 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
59 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 59 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
60 60
61 return snprintf(buf, PAGE_SIZE, "%d\n", 61 if (pm8001_ha->chip_id == chip_8001) {
62 pm8001_ha->main_cfg_tbl.interface_rev); 62 return snprintf(buf, PAGE_SIZE, "%d\n",
63 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev);
64 } else {
65 return snprintf(buf, PAGE_SIZE, "%d\n",
66 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev);
67 }
63} 68}
64static 69static
65DEVICE_ATTR(interface_rev, S_IRUGO, pm8001_ctl_mpi_interface_rev_show, NULL); 70DEVICE_ATTR(interface_rev, S_IRUGO, pm8001_ctl_mpi_interface_rev_show, NULL);
@@ -78,11 +83,19 @@ static ssize_t pm8001_ctl_fw_version_show(struct device *cdev,
78 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 83 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
79 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 84 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
80 85
81 return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n", 86 if (pm8001_ha->chip_id == chip_8001) {
82 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 24), 87 return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n",
83 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 16), 88 (u8)(pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev >> 24),
84 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 8), 89 (u8)(pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev >> 16),
85 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev)); 90 (u8)(pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev >> 8),
91 (u8)(pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev));
92 } else {
93 return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n",
94 (u8)(pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev >> 24),
95 (u8)(pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev >> 16),
96 (u8)(pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev >> 8),
97 (u8)(pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
98 }
86} 99}
87static DEVICE_ATTR(fw_version, S_IRUGO, pm8001_ctl_fw_version_show, NULL); 100static DEVICE_ATTR(fw_version, S_IRUGO, pm8001_ctl_fw_version_show, NULL);
88/** 101/**
@@ -99,8 +112,13 @@ static ssize_t pm8001_ctl_max_out_io_show(struct device *cdev,
99 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 112 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
100 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 113 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
101 114
102 return snprintf(buf, PAGE_SIZE, "%d\n", 115 if (pm8001_ha->chip_id == chip_8001) {
103 pm8001_ha->main_cfg_tbl.max_out_io); 116 return snprintf(buf, PAGE_SIZE, "%d\n",
117 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io);
118 } else {
119 return snprintf(buf, PAGE_SIZE, "%d\n",
120 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io);
121 }
104} 122}
105static DEVICE_ATTR(max_out_io, S_IRUGO, pm8001_ctl_max_out_io_show, NULL); 123static DEVICE_ATTR(max_out_io, S_IRUGO, pm8001_ctl_max_out_io_show, NULL);
106/** 124/**
@@ -117,8 +135,15 @@ static ssize_t pm8001_ctl_max_devices_show(struct device *cdev,
117 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 135 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
118 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 136 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
119 137
120 return snprintf(buf, PAGE_SIZE, "%04d\n", 138 if (pm8001_ha->chip_id == chip_8001) {
121 (u16)(pm8001_ha->main_cfg_tbl.max_sgl >> 16)); 139 return snprintf(buf, PAGE_SIZE, "%04d\n",
140 (u16)(pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl >> 16)
141 );
142 } else {
143 return snprintf(buf, PAGE_SIZE, "%04d\n",
144 (u16)(pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl >> 16)
145 );
146 }
122} 147}
123static DEVICE_ATTR(max_devices, S_IRUGO, pm8001_ctl_max_devices_show, NULL); 148static DEVICE_ATTR(max_devices, S_IRUGO, pm8001_ctl_max_devices_show, NULL);
124/** 149/**
@@ -136,8 +161,15 @@ static ssize_t pm8001_ctl_max_sg_list_show(struct device *cdev,
136 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 161 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
137 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 162 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
138 163
139 return snprintf(buf, PAGE_SIZE, "%04d\n", 164 if (pm8001_ha->chip_id == chip_8001) {
140 pm8001_ha->main_cfg_tbl.max_sgl & 0x0000FFFF); 165 return snprintf(buf, PAGE_SIZE, "%04d\n",
166 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl & 0x0000FFFF
167 );
168 } else {
169 return snprintf(buf, PAGE_SIZE, "%04d\n",
170 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl & 0x0000FFFF
171 );
172 }
141} 173}
142static DEVICE_ATTR(max_sg_list, S_IRUGO, pm8001_ctl_max_sg_list_show, NULL); 174static DEVICE_ATTR(max_sg_list, S_IRUGO, pm8001_ctl_max_sg_list_show, NULL);
143 175
@@ -173,7 +205,14 @@ static ssize_t pm8001_ctl_sas_spec_support_show(struct device *cdev,
173 struct Scsi_Host *shost = class_to_shost(cdev); 205 struct Scsi_Host *shost = class_to_shost(cdev);
174 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 206 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
175 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 207 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
176 mode = (pm8001_ha->main_cfg_tbl.ctrl_cap_flag & 0xfe000000)>>25; 208 /* fe000000 means supports SAS2.1 */
209 if (pm8001_ha->chip_id == chip_8001)
210 mode = (pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag &
211 0xfe000000)>>25;
212 else
213 /* fe000000 means supports SAS2.1 */
214 mode = (pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag &
215 0xfe000000)>>25;
177 return show_sas_spec_support_status(mode, buf); 216 return show_sas_spec_support_status(mode, buf);
178} 217}
179static DEVICE_ATTR(sas_spec_support, S_IRUGO, 218static DEVICE_ATTR(sas_spec_support, S_IRUGO,
diff --git a/drivers/scsi/pm8001/pm8001_defs.h b/drivers/scsi/pm8001/pm8001_defs.h
index c3d20c8d4abe..b25f87c8f469 100644
--- a/drivers/scsi/pm8001/pm8001_defs.h
+++ b/drivers/scsi/pm8001/pm8001_defs.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver
3 * 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd. 4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved. 5 * All rights reserved.
@@ -43,6 +43,10 @@
43 43
44enum chip_flavors { 44enum chip_flavors {
45 chip_8001, 45 chip_8001,
46 chip_8008,
47 chip_8009,
48 chip_8018,
49 chip_8019
46}; 50};
47#define USI_MAX_MEMCNT 9 51#define USI_MAX_MEMCNT 9
48#define PM8001_MAX_DMA_SG SG_ALL 52#define PM8001_MAX_DMA_SG SG_ALL
@@ -69,12 +73,19 @@ enum port_type {
69#define PM8001_MPI_QUEUE 1024 /* maximum mpi queue entries */ 73#define PM8001_MPI_QUEUE 1024 /* maximum mpi queue entries */
70#define PM8001_MAX_INB_NUM 1 74#define PM8001_MAX_INB_NUM 1
71#define PM8001_MAX_OUTB_NUM 1 75#define PM8001_MAX_OUTB_NUM 1
76#define PM8001_MAX_SPCV_INB_NUM 1
77#define PM8001_MAX_SPCV_OUTB_NUM 4
72#define PM8001_CAN_QUEUE 508 /* SCSI Queue depth */ 78#define PM8001_CAN_QUEUE 508 /* SCSI Queue depth */
73 79
80/* Inbound/Outbound queue size */
81#define IOMB_SIZE_SPC 64
82#define IOMB_SIZE_SPCV 128
83
74/* unchangeable hardware details */ 84/* unchangeable hardware details */
75#define PM8001_MAX_PHYS 8 /* max. possible phys */ 85#define PM8001_MAX_PHYS 16 /* max. possible phys */
76#define PM8001_MAX_PORTS 8 /* max. possible ports */ 86#define PM8001_MAX_PORTS 16 /* max. possible ports */
77#define PM8001_MAX_DEVICES 1024 /* max supported device */ 87#define PM8001_MAX_DEVICES 2048 /* max supported device */
88#define PM8001_MAX_MSIX_VEC 64 /* max msi-x int for spcv/ve */
78 89
79enum memory_region_num { 90enum memory_region_num {
80 AAP1 = 0x0, /* application acceleration processor */ 91 AAP1 = 0x0, /* application acceleration processor */
diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c
index b8dd05074abb..9846ee648384 100644
--- a/drivers/scsi/pm8001/pm8001_hwi.c
+++ b/drivers/scsi/pm8001/pm8001_hwi.c
@@ -50,32 +50,39 @@
50static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 50static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51{ 51{
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00); 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04); 54 pm8001_mr32(address, 0x00);
55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08); 55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C); 56 pm8001_mr32(address, 0x04);
57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10); 57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14); 58 pm8001_mr32(address, 0x08);
59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18); 59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
60 pm8001_ha->main_cfg_tbl.inbound_queue_offset = 60 pm8001_mr32(address, 0x0C);
61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
62 pm8001_mr32(address, 0x10);
63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
64 pm8001_mr32(address, 0x14);
65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
66 pm8001_mr32(address, 0x18);
67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
61 pm8001_mr32(address, MAIN_IBQ_OFFSET); 68 pm8001_mr32(address, MAIN_IBQ_OFFSET);
62 pm8001_ha->main_cfg_tbl.outbound_queue_offset = 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
63 pm8001_mr32(address, MAIN_OBQ_OFFSET); 70 pm8001_mr32(address, MAIN_OBQ_OFFSET);
64 pm8001_ha->main_cfg_tbl.hda_mode_flag = 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
66 73
67 /* read analog Setting offset from the configuration table */ 74 /* read analog Setting offset from the configuration table */
68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset = 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
70 77
71 /* read Error Dump Offset and Length */ 78 /* read Error Dump Offset and Length */
72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 = 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 = 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 = 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 = 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
80} 87}
81 88
@@ -86,31 +93,56 @@ static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
86static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 93static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
87{ 94{
88 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 95 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
89 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00); 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
90 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04); 97 pm8001_mr32(address, 0x00);
91 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08); 98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
92 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C); 99 pm8001_mr32(address, 0x04);
93 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10); 100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
94 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14); 101 pm8001_mr32(address, 0x08);
95 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18); 102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
96 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C); 103 pm8001_mr32(address, 0x0C);
97 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20); 104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
98 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24); 105 pm8001_mr32(address, 0x10);
99 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28); 106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
100 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C); 107 pm8001_mr32(address, 0x14);
101 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30); 108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
102 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34); 109 pm8001_mr32(address, 0x18);
103 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38); 110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
104 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C); 111 pm8001_mr32(address, 0x1C);
105 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40); 112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
106 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44); 113 pm8001_mr32(address, 0x20);
107 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48); 114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
108 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C); 115 pm8001_mr32(address, 0x24);
109 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50); 116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
110 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54); 117 pm8001_mr32(address, 0x28);
111 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58); 118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
112 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C); 119 pm8001_mr32(address, 0x2C);
113 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60); 120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
121 pm8001_mr32(address, 0x30);
122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
123 pm8001_mr32(address, 0x34);
124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
125 pm8001_mr32(address, 0x38);
126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
127 pm8001_mr32(address, 0x3C);
128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
129 pm8001_mr32(address, 0x40);
130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
131 pm8001_mr32(address, 0x44);
132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
133 pm8001_mr32(address, 0x48);
134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
135 pm8001_mr32(address, 0x4C);
136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
137 pm8001_mr32(address, 0x50);
138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
139 pm8001_mr32(address, 0x54);
140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
141 pm8001_mr32(address, 0x58);
142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
143 pm8001_mr32(address, 0x5C);
144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
145 pm8001_mr32(address, 0x60);
114} 146}
115 147
116/** 148/**
@@ -155,38 +187,41 @@ static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
155 */ 187 */
156static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 188static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
157{ 189{
158 int qn = 1;
159 int i; 190 int i;
160 u32 offsetib, offsetob; 191 u32 offsetib, offsetob;
161 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 192 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
162 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 193 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
163 194
164 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0; 195 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
165 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0; 196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
166 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0; 197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
167 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0; 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
168 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0; 199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
169 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
170 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0; 201 0;
171 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
172 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 203 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0; 204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0; 205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
175 206 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
176 pm8001_ha->main_cfg_tbl.upper_event_log_addr = 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
208
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
177 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 210 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
178 pm8001_ha->main_cfg_tbl.lower_event_log_addr = 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
179 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 212 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
180 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE; 213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
181 pm8001_ha->main_cfg_tbl.event_log_option = 0x01; 214 PM8001_EVENT_LOG_SIZE;
182 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr = 215 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
216 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
183 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 217 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
184 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr = 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
185 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 219 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
186 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE; 220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
187 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01; 221 PM8001_EVENT_LOG_SIZE;
188 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01; 222 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
189 for (i = 0; i < qn; i++) { 223 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
224 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
190 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 225 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
191 PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30); 226 PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
192 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 227 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
@@ -212,7 +247,7 @@ static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
212 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 247 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
213 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 248 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
214 } 249 }
215 for (i = 0; i < qn; i++) { 250 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
216 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 251 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
217 PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30); 252 PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
218 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 253 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
@@ -250,42 +285,51 @@ static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
250{ 285{
251 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 286 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
252 pm8001_mw32(address, 0x24, 287 pm8001_mw32(address, 0x24,
253 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd); 288 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
254 pm8001_mw32(address, 0x28, 289 pm8001_mw32(address, 0x28,
255 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3); 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
256 pm8001_mw32(address, 0x2C, 291 pm8001_mw32(address, 0x2C,
257 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7); 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
258 pm8001_mw32(address, 0x30, 293 pm8001_mw32(address, 0x30,
259 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3); 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
260 pm8001_mw32(address, 0x34, 295 pm8001_mw32(address, 0x34,
261 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7); 296 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
262 pm8001_mw32(address, 0x38, 297 pm8001_mw32(address, 0x38,
263 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3); 298 pm8001_ha->main_cfg_tbl.pm8001_tbl.
299 outbound_tgt_ITNexus_event_pid0_3);
264 pm8001_mw32(address, 0x3C, 300 pm8001_mw32(address, 0x3C,
265 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7); 301 pm8001_ha->main_cfg_tbl.pm8001_tbl.
302 outbound_tgt_ITNexus_event_pid4_7);
266 pm8001_mw32(address, 0x40, 303 pm8001_mw32(address, 0x40,
267 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3); 304 pm8001_ha->main_cfg_tbl.pm8001_tbl.
305 outbound_tgt_ssp_event_pid0_3);
268 pm8001_mw32(address, 0x44, 306 pm8001_mw32(address, 0x44,
269 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7); 307 pm8001_ha->main_cfg_tbl.pm8001_tbl.
308 outbound_tgt_ssp_event_pid4_7);
270 pm8001_mw32(address, 0x48, 309 pm8001_mw32(address, 0x48,
271 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3); 310 pm8001_ha->main_cfg_tbl.pm8001_tbl.
311 outbound_tgt_smp_event_pid0_3);
272 pm8001_mw32(address, 0x4C, 312 pm8001_mw32(address, 0x4C,
273 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7); 313 pm8001_ha->main_cfg_tbl.pm8001_tbl.
314 outbound_tgt_smp_event_pid4_7);
274 pm8001_mw32(address, 0x50, 315 pm8001_mw32(address, 0x50,
275 pm8001_ha->main_cfg_tbl.upper_event_log_addr); 316 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
276 pm8001_mw32(address, 0x54, 317 pm8001_mw32(address, 0x54,
277 pm8001_ha->main_cfg_tbl.lower_event_log_addr); 318 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
278 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size); 319 pm8001_mw32(address, 0x58,
279 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option); 320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
321 pm8001_mw32(address, 0x5C,
322 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
280 pm8001_mw32(address, 0x60, 323 pm8001_mw32(address, 0x60,
281 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr); 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
282 pm8001_mw32(address, 0x64, 325 pm8001_mw32(address, 0x64,
283 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr); 326 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
284 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size); 327 pm8001_mw32(address, 0x68,
328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
285 pm8001_mw32(address, 0x6C, 329 pm8001_mw32(address, 0x6C,
286 pm8001_ha->main_cfg_tbl.iop_event_log_option); 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
287 pm8001_mw32(address, 0x70, 331 pm8001_mw32(address, 0x70,
288 pm8001_ha->main_cfg_tbl.fatal_err_interrupt); 332 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
289} 333}
290 334
291/** 335/**
@@ -4706,4 +4750,3 @@ const struct pm8001_dispatch pm8001_8001_dispatch = {
4706 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4750 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4707 .sas_re_init_req = pm8001_chip_sas_re_initialization, 4751 .sas_re_init_req = pm8001_chip_sas_re_initialization,
4708}; 4752};
4709
diff --git a/drivers/scsi/pm8001/pm8001_init.c b/drivers/scsi/pm8001/pm8001_init.c
index 3d5e522e00fc..f3234b2a0d79 100644
--- a/drivers/scsi/pm8001/pm8001_init.c
+++ b/drivers/scsi/pm8001/pm8001_init.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 * 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd. 4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved. 5 * All rights reserved.
@@ -44,8 +44,12 @@
44 44
45static struct scsi_transport_template *pm8001_stt; 45static struct scsi_transport_template *pm8001_stt;
46 46
47/**
48 * chip info structure to identify chip key functionality as
49 * encryption available/not, no of ports, hw specific function ref
50 */
47static const struct pm8001_chip_info pm8001_chips[] = { 51static const struct pm8001_chip_info pm8001_chips[] = {
48 [chip_8001] = { 8, &pm8001_8001_dispatch,}, 52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
49}; 53};
50static int pm8001_id; 54static int pm8001_id;
51 55
@@ -843,14 +847,45 @@ err_out_enable:
843 return rc; 847 return rc;
844} 848}
845 849
850/* update of pci device, vendor id and driver data with
851 * unique value for each of the controller
852 */
846static struct pci_device_id pm8001_pci_table[] = { 853static struct pci_device_id pm8001_pci_table[] = {
847 { 854 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
848 PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001
849 },
850 { 855 {
851 PCI_DEVICE(0x117c, 0x0042), 856 PCI_DEVICE(0x117c, 0x0042),
852 .driver_data = chip_8001 857 .driver_data = chip_8001
853 }, 858 },
859 /* Support for SPC/SPCv/SPCve controllers */
860 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
861 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
862 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
863 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
864 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
865 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
866 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
867 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
868 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
869 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
870 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
871 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
872 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
873 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
874 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
875 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
876 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
877 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
878 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
879 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
880 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
881 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
882 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
883 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
884 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
885 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
886 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
887 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
888 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
854 {} /* terminate list */ 889 {} /* terminate list */
855}; 890};
856 891
@@ -902,7 +937,8 @@ module_init(pm8001_init);
902module_exit(pm8001_exit); 937module_exit(pm8001_exit);
903 938
904MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 939MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
905MODULE_DESCRIPTION("PMC-Sierra PM8001 SAS/SATA controller driver"); 940MODULE_DESCRIPTION(
941 "PMC-Sierra PM8001/8081/8088/8089 SAS/SATA controller driver");
906MODULE_VERSION(DRV_VERSION); 942MODULE_VERSION(DRV_VERSION);
907MODULE_LICENSE("GPL"); 943MODULE_LICENSE("GPL");
908MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 944MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
diff --git a/drivers/scsi/pm8001/pm8001_sas.h b/drivers/scsi/pm8001/pm8001_sas.h
index 11008205aeb3..37a339e6a3a4 100644
--- a/drivers/scsi/pm8001/pm8001_sas.h
+++ b/drivers/scsi/pm8001/pm8001_sas.h
@@ -173,6 +173,7 @@ struct pm8001_dispatch {
173}; 173};
174 174
175struct pm8001_chip_info { 175struct pm8001_chip_info {
176 u32 encrypt;
176 u32 n_phy; 177 u32 n_phy;
177 const struct pm8001_dispatch *dispatch; 178 const struct pm8001_dispatch *dispatch;
178}; 179};
@@ -256,7 +257,20 @@ struct mpi_mem_req {
256 struct mpi_mem region[USI_MAX_MEMCNT]; 257 struct mpi_mem region[USI_MAX_MEMCNT];
257}; 258};
258 259
259struct main_cfg_table { 260struct encrypt {
261 u32 cipher_mode;
262 u32 sec_mode;
263 u32 status;
264 u32 flag;
265};
266
267struct sas_phy_attribute_table {
268 u32 phystart1_16[16];
269 u32 outbound_hw_event_pid1_16[16];
270};
271
272union main_cfg_table {
273 struct {
260 u32 signature; 274 u32 signature;
261 u32 interface_rev; 275 u32 interface_rev;
262 u32 firmware_rev; 276 u32 firmware_rev;
@@ -292,19 +306,67 @@ struct main_cfg_table {
292 u32 fatal_err_dump_length1; 306 u32 fatal_err_dump_length1;
293 u32 hda_mode_flag; 307 u32 hda_mode_flag;
294 u32 anolog_setup_table_offset; 308 u32 anolog_setup_table_offset;
309 u32 rsvd[4];
310 } pm8001_tbl;
311
312 struct {
313 u32 signature;
314 u32 interface_rev;
315 u32 firmware_rev;
316 u32 max_out_io;
317 u32 max_sgl;
318 u32 ctrl_cap_flag;
319 u32 gst_offset;
320 u32 inbound_queue_offset;
321 u32 outbound_queue_offset;
322 u32 inbound_q_nppd_hppd;
323 u32 rsvd[10];
324 u32 upper_event_log_addr;
325 u32 lower_event_log_addr;
326 u32 event_log_size;
327 u32 event_log_severity;
328 u32 upper_pcs_event_log_addr;
329 u32 lower_pcs_event_log_addr;
330 u32 pcs_event_log_size;
331 u32 pcs_event_log_severity;
332 u32 fatal_err_interrupt;
333 u32 fatal_err_dump_offset0;
334 u32 fatal_err_dump_length0;
335 u32 fatal_err_dump_offset1;
336 u32 fatal_err_dump_length1;
337 u32 gpio_led_mapping;
338 u32 analog_setup_table_offset;
339 u32 int_vec_table_offset;
340 u32 phy_attr_table_offset;
341 u32 port_recovery_timer;
342 u32 interrupt_reassertion_delay;
343 } pm80xx_tbl;
295}; 344};
296struct general_status_table { 345
346union general_status_table {
347 struct {
297 u32 gst_len_mpistate; 348 u32 gst_len_mpistate;
298 u32 iq_freeze_state0; 349 u32 iq_freeze_state0;
299 u32 iq_freeze_state1; 350 u32 iq_freeze_state1;
300 u32 msgu_tcnt; 351 u32 msgu_tcnt;
301 u32 iop_tcnt; 352 u32 iop_tcnt;
302 u32 reserved; 353 u32 rsvd;
303 u32 phy_state[8]; 354 u32 phy_state[8];
304 u32 reserved1; 355 u32 gpio_input_val;
305 u32 reserved2; 356 u32 rsvd1[2];
306 u32 reserved3; 357 u32 recover_err_info[8];
358 } pm8001_tbl;
359 struct {
360 u32 gst_len_mpistate;
361 u32 iq_freeze_state0;
362 u32 iq_freeze_state1;
363 u32 msgu_tcnt;
364 u32 iop_tcnt;
365 u32 rsvd[9];
366 u32 gpio_input_val;
367 u32 rsvd1[2];
307 u32 recover_err_info[8]; 368 u32 recover_err_info[8];
369 } pm80xx_tbl;
308}; 370};
309struct inbound_queue_table { 371struct inbound_queue_table {
310 u32 element_pri_size_cnt; 372 u32 element_pri_size_cnt;
@@ -351,15 +413,21 @@ struct pm8001_hba_info {
351 struct device *dev; 413 struct device *dev;
352 struct pm8001_hba_memspace io_mem[6]; 414 struct pm8001_hba_memspace io_mem[6];
353 struct mpi_mem_req memoryMap; 415 struct mpi_mem_req memoryMap;
416 struct encrypt encrypt_info; /* support encryption */
354 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/ 417 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
355 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/ 418 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
356 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/ 419 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
357 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/ 420 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
358 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/ 421 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
359 struct main_cfg_table main_cfg_tbl; 422 void __iomem *pspa_q_tbl_addr;
360 struct general_status_table gs_tbl; 423 /*MPI SAS PHY attributes Queue Config Table Addr*/
361 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM]; 424 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
362 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM]; 425 union main_cfg_table main_cfg_tbl;
426 union general_status_table gs_tbl;
427 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
428 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM];
429 struct sas_phy_attribute_table phy_attr_table;
430 /* MPI SAS PHY attributes */
363 u8 sas_addr[SAS_ADDR_SIZE]; 431 u8 sas_addr[SAS_ADDR_SIZE];
364 struct sas_ha_struct *sas;/* SCSI/SAS glue */ 432 struct sas_ha_struct *sas;/* SCSI/SAS glue */
365 struct Scsi_Host *shost; 433 struct Scsi_Host *shost;
@@ -372,10 +440,12 @@ struct pm8001_hba_info {
372 struct pm8001_port port[PM8001_MAX_PHYS]; 440 struct pm8001_port port[PM8001_MAX_PHYS];
373 u32 id; 441 u32 id;
374 u32 irq; 442 u32 irq;
443 u32 iomb_size; /* SPC and SPCV IOMB size */
375 struct pm8001_device *devices; 444 struct pm8001_device *devices;
376 struct pm8001_ccb_info *ccb_info; 445 struct pm8001_ccb_info *ccb_info;
377#ifdef PM8001_USE_MSIX 446#ifdef PM8001_USE_MSIX
378 struct msix_entry msix_entries[16];/*for msi-x interrupt*/ 447 struct msix_entry msix_entries[PM8001_MAX_MSIX_VEC];
448 /*for msi-x interrupt*/
379 int number_of_intr;/*will be used in remove()*/ 449 int number_of_intr;/*will be used in remove()*/
380#endif 450#endif
381#ifdef PM8001_USE_TASKLET 451#ifdef PM8001_USE_TASKLET
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 18:36:45 -0500