diff options
author | Alexey Dobriyan <adobriyan@gmail.com> | 2006-03-08 03:14:22 -0500 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-03-12 10:12:11 -0500 |
commit | 85ae97d816da3f8af9dcfbc4197a2950b55c3b0d (patch) | |
tree | 033848609c70a5cb5311f7f3d269f582c74ec5b5 /drivers/scsi | |
parent | f018fa552c52642a6b9db2bda90477762e42163f (diff) |
[SCSI] drivers/scsi/FlashPoint.c: remove unused things
* Remove unused #define's
* Remove unused typedefs.
* Remove prototypes for non-existing functions.
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r-- | drivers/scsi/FlashPoint.c | 345 |
1 files changed, 1 insertions, 344 deletions
diff --git a/drivers/scsi/FlashPoint.c b/drivers/scsi/FlashPoint.c index 8d64f0bed628..38e6b71484b7 100644 --- a/drivers/scsi/FlashPoint.c +++ b/drivers/scsi/FlashPoint.c | |||
@@ -47,15 +47,10 @@ | |||
47 | #define SccbMgr_isr FlashPoint_HandleInterrupt | 47 | #define SccbMgr_isr FlashPoint_HandleInterrupt |
48 | 48 | ||
49 | 49 | ||
50 | #define MAX_CDBLEN 12 | ||
51 | 50 | ||
52 | #define SCAM_LEV_2 1 | ||
53 | 51 | ||
54 | #define CRCMASK 0xA001 | 52 | #define CRCMASK 0xA001 |
55 | 53 | ||
56 | #define BL_VENDOR_ID 0x104B | ||
57 | #define FP_DEVICE_ID 0x8130 | ||
58 | #define MM_DEVICE_ID 0x1040 | ||
59 | 54 | ||
60 | 55 | ||
61 | #define FAILURE 0xFFFFFFFFL | 56 | #define FAILURE 0xFFFFFFFFL |
@@ -65,15 +60,9 @@ typedef unsigned char UCHAR; | |||
65 | typedef unsigned short USHORT; | 60 | typedef unsigned short USHORT; |
66 | typedef unsigned int UINT; | 61 | typedef unsigned int UINT; |
67 | typedef unsigned long ULONG; | 62 | typedef unsigned long ULONG; |
68 | typedef unsigned char * PUCHAR; | ||
69 | typedef unsigned short* PUSHORT; | ||
70 | typedef unsigned long * PULONG; | ||
71 | typedef void * PVOID; | ||
72 | 63 | ||
73 | 64 | ||
74 | typedef unsigned char * uchar_ptr; | ||
75 | typedef unsigned short * ushort_ptr; | 65 | typedef unsigned short * ushort_ptr; |
76 | typedef unsigned long * ulong_ptr; | ||
77 | 66 | ||
78 | 67 | ||
79 | #define s08bits char | 68 | #define s08bits char |
@@ -84,9 +73,6 @@ typedef unsigned long * ulong_ptr; | |||
84 | #define u16bits unsigned s16bits | 73 | #define u16bits unsigned s16bits |
85 | #define u32bits unsigned s32bits | 74 | #define u32bits unsigned s32bits |
86 | 75 | ||
87 | typedef u08bits * pu08bits; | ||
88 | typedef u16bits * pu16bits; | ||
89 | typedef u32bits * pu32bits; | ||
90 | 76 | ||
91 | 77 | ||
92 | #define BIT(x) ((UCHAR)(1<<(x))) /* single-bit mask in bit position x */ | 78 | #define BIT(x) ((UCHAR)(1<<(x))) /* single-bit mask in bit position x */ |
@@ -144,10 +130,6 @@ typedef SCCBMGR_INFO * PSCCBMGR_INFO; | |||
144 | #define HARPOON_FAMILY 0x02 | 130 | #define HARPOON_FAMILY 0x02 |
145 | 131 | ||
146 | 132 | ||
147 | #define ISA_BUS_CARD 0x01 | ||
148 | #define EISA_BUS_CARD 0x02 | ||
149 | #define PCI_BUS_CARD 0x03 | ||
150 | #define VESA_BUS_CARD 0x04 | ||
151 | 133 | ||
152 | /* SCCB struct used for both SCCB and UCB manager compiles! | 134 | /* SCCB struct used for both SCCB and UCB manager compiles! |
153 | * The UCB Manager treats the SCCB as it's 'native hardware structure' | 135 | * The UCB Manager treats the SCCB as it's 'native hardware structure' |
@@ -200,14 +182,11 @@ typedef struct _SCCB { | |||
200 | ULONG Sccb_SGoffset; | 182 | ULONG Sccb_SGoffset; |
201 | } SCCB; | 183 | } SCCB; |
202 | 184 | ||
203 | #define SCCB_SIZE sizeof(SCCB) | ||
204 | 185 | ||
205 | #pragma pack() | 186 | #pragma pack() |
206 | 187 | ||
207 | 188 | ||
208 | 189 | ||
209 | #define SCSI_INITIATOR_COMMAND 0x00 | ||
210 | #define TARGET_MODE_COMMAND 0x01 | ||
211 | #define SCATTER_GATHER_COMMAND 0x02 | 190 | #define SCATTER_GATHER_COMMAND 0x02 |
212 | #define RESIDUAL_COMMAND 0x03 | 191 | #define RESIDUAL_COMMAND 0x03 |
213 | #define RESIDUAL_SG_COMMAND 0x04 | 192 | #define RESIDUAL_SG_COMMAND 0x04 |
@@ -216,12 +195,10 @@ typedef struct _SCCB { | |||
216 | 195 | ||
217 | #define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */ | 196 | #define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */ |
218 | #define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */ | 197 | #define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */ |
219 | #define TAG_Q_MASK 0xE0 | ||
220 | #define SCCB_DATA_XFER_OUT 0x10 /* Write */ | 198 | #define SCCB_DATA_XFER_OUT 0x10 /* Write */ |
221 | #define SCCB_DATA_XFER_IN 0x08 /* Read */ | 199 | #define SCCB_DATA_XFER_IN 0x08 /* Read */ |
222 | 200 | ||
223 | 201 | ||
224 | #define FOURTEEN_BYTES 0x00 /* Request Sense Buffer size */ | ||
225 | #define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */ | 202 | #define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */ |
226 | 203 | ||
227 | 204 | ||
@@ -235,9 +212,7 @@ typedef struct _SCCB { | |||
235 | #define DATA_OUT_ST 7 | 212 | #define DATA_OUT_ST 7 |
236 | #define DATA_IN_ST 8 | 213 | #define DATA_IN_ST 8 |
237 | #define DISCONNECT_ST 9 | 214 | #define DISCONNECT_ST 9 |
238 | #define STATUS_ST 10 | ||
239 | #define ABORT_ST 11 | 215 | #define ABORT_ST 11 |
240 | #define MESSAGE_ST 12 | ||
241 | 216 | ||
242 | 217 | ||
243 | #define F_HOST_XFER_DIR 0x01 | 218 | #define F_HOST_XFER_DIR 0x01 |
@@ -249,7 +224,6 @@ typedef struct _SCCB { | |||
249 | 224 | ||
250 | 225 | ||
251 | #define F_STATUSLOADED 0x01 | 226 | #define F_STATUSLOADED 0x01 |
252 | #define F_MSGLOADED 0x02 | ||
253 | #define F_DEV_SELECTED 0x04 | 227 | #define F_DEV_SELECTED 0x04 |
254 | 228 | ||
255 | 229 | ||
@@ -257,56 +231,39 @@ typedef struct _SCCB { | |||
257 | #define SCCB_DATA_UNDER_RUN 0x0C | 231 | #define SCCB_DATA_UNDER_RUN 0x0C |
258 | #define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */ | 232 | #define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */ |
259 | #define SCCB_DATA_OVER_RUN 0x12 | 233 | #define SCCB_DATA_OVER_RUN 0x12 |
260 | #define SCCB_UNEXPECTED_BUS_FREE 0x13 /* Target dropped SCSI BSY */ | ||
261 | #define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */ | 234 | #define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */ |
262 | 235 | ||
263 | #define SCCB_INVALID_OP_CODE 0x16 /* SCCB invalid operation code */ | ||
264 | #define SCCB_INVALID_SCCB 0x1A /* Invalid SCCB - bad parameter */ | ||
265 | #define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */ | 236 | #define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */ |
266 | #define SCCB_BM_ERR 0x30 /* BusMaster error. */ | 237 | #define SCCB_BM_ERR 0x30 /* BusMaster error. */ |
267 | #define SCCB_PARITY_ERR 0x34 /* SCSI parity error */ | 238 | #define SCCB_PARITY_ERR 0x34 /* SCSI parity error */ |
268 | 239 | ||
269 | 240 | ||
270 | 241 | ||
271 | #define SCCB_INVALID_DIRECTION 0x18 /* Invalid target direction */ | ||
272 | #define SCCB_DUPLICATE_SCCB 0x19 /* Duplicate SCCB */ | ||
273 | #define SCCB_SCSI_RST 0x35 /* SCSI RESET detected. */ | ||
274 | 242 | ||
275 | 243 | ||
276 | #define SCCB_IN_PROCESS 0x00 | 244 | #define SCCB_IN_PROCESS 0x00 |
277 | #define SCCB_SUCCESS 0x01 | 245 | #define SCCB_SUCCESS 0x01 |
278 | #define SCCB_ABORT 0x02 | 246 | #define SCCB_ABORT 0x02 |
279 | #define SCCB_NOT_FOUND 0x03 | ||
280 | #define SCCB_ERROR 0x04 | 247 | #define SCCB_ERROR 0x04 |
281 | #define SCCB_INVALID 0x05 | ||
282 | 248 | ||
283 | #define SCCB_SIZE sizeof(SCCB) | ||
284 | 249 | ||
285 | 250 | ||
286 | #define ORION_FW_REV 3110 | 251 | #define ORION_FW_REV 3110 |
287 | 252 | ||
288 | #define HARP_REVD 1 | ||
289 | 253 | ||
290 | 254 | ||
291 | #define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */ | 255 | #define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */ |
292 | 256 | ||
293 | #define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */ | 257 | #define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */ |
294 | 258 | ||
295 | #define WIDE_SCSI 1 | ||
296 | 259 | ||
297 | #define MAX_SCSI_TAR 16 | 260 | #define MAX_SCSI_TAR 16 |
298 | #define MAX_LUN 32 | 261 | #define MAX_LUN 32 |
299 | #define LUN_MASK 0x1f | 262 | #define LUN_MASK 0x1f |
300 | 263 | ||
301 | #if defined(HARP_REVA) | ||
302 | #define SG_BUF_CNT 15 /*Number of prefetched elements. */ | ||
303 | #else | ||
304 | #define SG_BUF_CNT 16 /*Number of prefetched elements. */ | 264 | #define SG_BUF_CNT 16 /*Number of prefetched elements. */ |
305 | #endif | ||
306 | 265 | ||
307 | #define SG_ELEMENT_SIZE 8 /*Eight byte per element. */ | 266 | #define SG_ELEMENT_SIZE 8 /*Eight byte per element. */ |
308 | #define SG_LOCAL_MASK 0x00000000L | ||
309 | #define SG_ELEMENT_MASK 0xFFFFFFFFL | ||
310 | 267 | ||
311 | 268 | ||
312 | #define RD_HARPOON(ioport) OS_InPortByte((u32bits)ioport) | 269 | #define RD_HARPOON(ioport) OS_InPortByte((u32bits)ioport) |
@@ -318,31 +275,25 @@ typedef struct _SCCB { | |||
318 | 275 | ||
319 | 276 | ||
320 | #define TAR_SYNC_MASK (BIT(7)+BIT(6)) | 277 | #define TAR_SYNC_MASK (BIT(7)+BIT(6)) |
321 | #define SYNC_UNKNOWN 0x00 | ||
322 | #define SYNC_TRYING BIT(6) | 278 | #define SYNC_TRYING BIT(6) |
323 | #define SYNC_SUPPORTED (BIT(7)+BIT(6)) | 279 | #define SYNC_SUPPORTED (BIT(7)+BIT(6)) |
324 | 280 | ||
325 | #define TAR_WIDE_MASK (BIT(5)+BIT(4)) | 281 | #define TAR_WIDE_MASK (BIT(5)+BIT(4)) |
326 | #define WIDE_DISABLED 0x00 | ||
327 | #define WIDE_ENABLED BIT(4) | 282 | #define WIDE_ENABLED BIT(4) |
328 | #define WIDE_NEGOCIATED BIT(5) | 283 | #define WIDE_NEGOCIATED BIT(5) |
329 | 284 | ||
330 | #define TAR_TAG_Q_MASK (BIT(3)+BIT(2)) | 285 | #define TAR_TAG_Q_MASK (BIT(3)+BIT(2)) |
331 | #define TAG_Q_UNKNOWN 0x00 | ||
332 | #define TAG_Q_TRYING BIT(2) | 286 | #define TAG_Q_TRYING BIT(2) |
333 | #define TAG_Q_REJECT BIT(3) | 287 | #define TAG_Q_REJECT BIT(3) |
334 | #define TAG_Q_SUPPORTED (BIT(3)+BIT(2)) | ||
335 | 288 | ||
336 | #define TAR_ALLOW_DISC BIT(0) | 289 | #define TAR_ALLOW_DISC BIT(0) |
337 | 290 | ||
338 | 291 | ||
339 | #define EE_SYNC_MASK (BIT(0)+BIT(1)) | 292 | #define EE_SYNC_MASK (BIT(0)+BIT(1)) |
340 | #define EE_SYNC_ASYNC 0x00 | ||
341 | #define EE_SYNC_5MB BIT(0) | 293 | #define EE_SYNC_5MB BIT(0) |
342 | #define EE_SYNC_10MB BIT(1) | 294 | #define EE_SYNC_10MB BIT(1) |
343 | #define EE_SYNC_20MB (BIT(0)+BIT(1)) | 295 | #define EE_SYNC_20MB (BIT(0)+BIT(1)) |
344 | 296 | ||
345 | #define EE_ALLOW_DISC BIT(6) | ||
346 | #define EE_WIDE_SCSI BIT(7) | 297 | #define EE_WIDE_SCSI BIT(7) |
347 | 298 | ||
348 | 299 | ||
@@ -418,7 +369,6 @@ typedef struct SCCBcard *PSCCBcard; | |||
418 | #define ID_STRING_LENGTH 32 | 369 | #define ID_STRING_LENGTH 32 |
419 | #define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */ | 370 | #define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */ |
420 | 371 | ||
421 | #define TYPE_CODE1 00 /*No ID yet */ | ||
422 | 372 | ||
423 | #define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */ | 373 | #define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */ |
424 | 374 | ||
@@ -430,16 +380,9 @@ typedef struct SCCBcard *PSCCBcard; | |||
430 | 380 | ||
431 | #define ID_0_7 0x18 | 381 | #define ID_0_7 0x18 |
432 | #define ID_8_F 0x11 | 382 | #define ID_8_F 0x11 |
433 | #define ID_10_17 0x12 | ||
434 | #define ID_18_1F 0x0B | ||
435 | #define MISC_CODE 0x14 | 383 | #define MISC_CODE 0x14 |
436 | #define CLR_P_FLAG 0x18 | 384 | #define CLR_P_FLAG 0x18 |
437 | #define LOCATE_ON 0x12 | ||
438 | #define LOCATE_OFF 0x0B | ||
439 | 385 | ||
440 | #define LVL_1_MST 0x00 | ||
441 | #define LVL_2_MST 0x40 | ||
442 | #define DOM_LVL_2 0xC0 | ||
443 | 386 | ||
444 | 387 | ||
445 | #define INIT_SELTD 0x01 | 388 | #define INIT_SELTD 0x01 |
@@ -455,64 +398,24 @@ typedef struct SCCBscam_info { | |||
455 | UCHAR id_string[ID_STRING_LENGTH]; | 398 | UCHAR id_string[ID_STRING_LENGTH]; |
456 | enum scam_id_st state; | 399 | enum scam_id_st state; |
457 | 400 | ||
458 | } SCCBSCAM_INFO, *PSCCBSCAM_INFO; | 401 | } SCCBSCAM_INFO; |
459 | 402 | ||
460 | 403 | ||
461 | #define SCSI_TEST_UNIT_READY 0x00 | ||
462 | #define SCSI_REZERO_UNIT 0x01 | ||
463 | #define SCSI_REQUEST_SENSE 0x03 | 404 | #define SCSI_REQUEST_SENSE 0x03 |
464 | #define SCSI_FORMAT_UNIT 0x04 | ||
465 | #define SCSI_REASSIGN 0x07 | ||
466 | #define SCSI_READ 0x08 | 405 | #define SCSI_READ 0x08 |
467 | #define SCSI_WRITE 0x0A | 406 | #define SCSI_WRITE 0x0A |
468 | #define SCSI_SEEK 0x0B | ||
469 | #define SCSI_INQUIRY 0x12 | ||
470 | #define SCSI_MODE_SELECT 0x15 | ||
471 | #define SCSI_RESERVE_UNIT 0x16 | ||
472 | #define SCSI_RELEASE_UNIT 0x17 | ||
473 | #define SCSI_MODE_SENSE 0x1A | ||
474 | #define SCSI_START_STOP_UNIT 0x1B | 407 | #define SCSI_START_STOP_UNIT 0x1B |
475 | #define SCSI_SEND_DIAGNOSTIC 0x1D | ||
476 | #define SCSI_READ_CAPACITY 0x25 | ||
477 | #define SCSI_READ_EXTENDED 0x28 | 408 | #define SCSI_READ_EXTENDED 0x28 |
478 | #define SCSI_WRITE_EXTENDED 0x2A | 409 | #define SCSI_WRITE_EXTENDED 0x2A |
479 | #define SCSI_SEEK_EXTENDED 0x2B | ||
480 | #define SCSI_WRITE_AND_VERIFY 0x2E | 410 | #define SCSI_WRITE_AND_VERIFY 0x2E |
481 | #define SCSI_VERIFY 0x2F | ||
482 | #define SCSI_READ_DEFECT_DATA 0x37 | ||
483 | #define SCSI_WRITE_BUFFER 0x3B | ||
484 | #define SCSI_READ_BUFFER 0x3C | ||
485 | #define SCSI_RECV_DIAGNOSTIC 0x1C | ||
486 | #define SCSI_READ_LONG 0x3E | ||
487 | #define SCSI_WRITE_LONG 0x3F | ||
488 | #define SCSI_LAST_SCSI_CMND SCSI_WRITE_LONG | ||
489 | #define SCSI_INVALID_CMND 0xFF | ||
490 | 411 | ||
491 | 412 | ||
492 | 413 | ||
493 | #define SSGOOD 0x00 | 414 | #define SSGOOD 0x00 |
494 | #define SSCHECK 0x02 | 415 | #define SSCHECK 0x02 |
495 | #define SSCOND_MET 0x04 | ||
496 | #define SSBUSY 0x08 | ||
497 | #define SSRESERVATION_CONFLICT 0x18 | ||
498 | #define SSCMD_TERM 0x22 | ||
499 | #define SSQ_FULL 0x28 | 416 | #define SSQ_FULL 0x28 |
500 | 417 | ||
501 | 418 | ||
502 | #define SKNO_SEN 0x00 | ||
503 | #define SKRECOV_ERR 0x01 | ||
504 | #define SKNOT_RDY 0x02 | ||
505 | #define SKMED_ERR 0x03 | ||
506 | #define SKHW_ERR 0x04 | ||
507 | #define SKILL_REQ 0x05 | ||
508 | #define SKUNIT_ATTN 0x06 | ||
509 | #define SKDATA_PROTECT 0x07 | ||
510 | #define SKBLNK_CHK 0x08 | ||
511 | #define SKCPY_ABORT 0x0A | ||
512 | #define SKABORT_CMD 0x0B | ||
513 | #define SKEQUAL 0x0C | ||
514 | #define SKVOL_OVF 0x0D | ||
515 | #define SKMIS_CMP 0x0E | ||
516 | 419 | ||
517 | 420 | ||
518 | #define SMCMD_COMP 0x00 | 421 | #define SMCMD_COMP 0x00 |
@@ -520,7 +423,6 @@ typedef struct SCCBscam_info { | |||
520 | #define SMSAVE_DATA_PTR 0x02 | 423 | #define SMSAVE_DATA_PTR 0x02 |
521 | #define SMREST_DATA_PTR 0x03 | 424 | #define SMREST_DATA_PTR 0x03 |
522 | #define SMDISC 0x04 | 425 | #define SMDISC 0x04 |
523 | #define SMINIT_DETEC_ERR 0x05 | ||
524 | #define SMABORT 0x06 | 426 | #define SMABORT 0x06 |
525 | #define SMREJECT 0x07 | 427 | #define SMREJECT 0x07 |
526 | #define SMNO_OP 0x08 | 428 | #define SMNO_OP 0x08 |
@@ -535,35 +437,22 @@ typedef struct SCCBscam_info { | |||
535 | 437 | ||
536 | 438 | ||
537 | #define SMSYNC 0x01 | 439 | #define SMSYNC 0x01 |
538 | #define SM10MBS 0x19 /* 100ns */ | ||
539 | #define SM5MBS 0x32 /* 200ns */ | ||
540 | #define SMOFFSET 0x0F /* Maxoffset value */ | ||
541 | #define SMWDTR 0x03 | 440 | #define SMWDTR 0x03 |
542 | #define SM8BIT 0x00 | 441 | #define SM8BIT 0x00 |
543 | #define SM16BIT 0x01 | 442 | #define SM16BIT 0x01 |
544 | #define SM32BIT 0x02 | ||
545 | #define SMIGNORWR 0x23 /* Ignore Wide Residue */ | 443 | #define SMIGNORWR 0x23 /* Ignore Wide Residue */ |
546 | 444 | ||
547 | 445 | ||
548 | #define ARBITRATION_DELAY 0x01 /* 2.4us using a 40Mhz clock */ | ||
549 | #define BUS_SETTLE_DELAY 0x01 /* 400ns */ | ||
550 | #define BUS_CLEAR_DELAY 0x01 /* 800ns */ | ||
551 | 446 | ||
552 | 447 | ||
553 | 448 | ||
554 | #define SPHASE_TO 0x0A /* 10 second timeout waiting for */ | ||
555 | #define SCMD_TO 0x0F /* Overall command timeout */ | ||
556 | 449 | ||
557 | 450 | ||
558 | 451 | ||
559 | #define SIX_BYTE_CMD 0x06 | 452 | #define SIX_BYTE_CMD 0x06 |
560 | #define TEN_BYTE_CMD 0x0A | ||
561 | #define TWELVE_BYTE_CMD 0x0C | 453 | #define TWELVE_BYTE_CMD 0x0C |
562 | 454 | ||
563 | #define ASYNC 0x00 | 455 | #define ASYNC 0x00 |
564 | #define PERI25NS 0x06 /* 25/4ns to next clock for xbow. */ | ||
565 | #define SYNC10MBS 0x19 | ||
566 | #define SYNC5MBS 0x32 | ||
567 | #define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */ | 456 | #define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */ |
568 | 457 | ||
569 | 458 | ||
@@ -572,19 +461,11 @@ typedef struct SCCBscam_info { | |||
572 | #define EEPROM_CHECK_SUM 0 | 461 | #define EEPROM_CHECK_SUM 0 |
573 | #define FW_SIGNATURE 2 | 462 | #define FW_SIGNATURE 2 |
574 | #define MODEL_NUMB_0 4 | 463 | #define MODEL_NUMB_0 4 |
575 | #define MODEL_NUMB_1 5 | ||
576 | #define MODEL_NUMB_2 6 | 464 | #define MODEL_NUMB_2 6 |
577 | #define MODEL_NUMB_3 7 | ||
578 | #define MODEL_NUMB_4 8 | 465 | #define MODEL_NUMB_4 8 |
579 | #define MODEL_NUMB_5 9 | ||
580 | #define IO_BASE_ADDR 10 | ||
581 | #define IRQ_NUMBER 12 | ||
582 | #define PCI_INT_PIN 13 | ||
583 | #define BUS_DELAY 14 /*On time in byte 14 off delay in 15 */ | ||
584 | #define SYSTEM_CONFIG 16 | 466 | #define SYSTEM_CONFIG 16 |
585 | #define SCSI_CONFIG 17 | 467 | #define SCSI_CONFIG 17 |
586 | #define BIOS_CONFIG 18 | 468 | #define BIOS_CONFIG 18 |
587 | #define SPIN_UP_DELAY 19 | ||
588 | #define SCAM_CONFIG 20 | 469 | #define SCAM_CONFIG 20 |
589 | #define ADAPTER_SCSI_ID 24 | 470 | #define ADAPTER_SCSI_ID 24 |
590 | 471 | ||
@@ -609,7 +490,6 @@ typedef struct SCCBscam_info { | |||
609 | 490 | ||
610 | 491 | ||
611 | 492 | ||
612 | #define DOM_MASTER (BIT(0) + BIT(1)) | ||
613 | #define SCAM_ENABLED BIT(2) | 493 | #define SCAM_ENABLED BIT(2) |
614 | #define SCAM_LEVEL2 BIT(3) | 494 | #define SCAM_LEVEL2 BIT(3) |
615 | 495 | ||
@@ -644,16 +524,9 @@ typedef struct SCCBscam_info { | |||
644 | /* Sub Vendor ID and Sub Device ID only available in | 524 | /* Sub Vendor ID and Sub Device ID only available in |
645 | Harpoon Version 2 and higher */ | 525 | Harpoon Version 2 and higher */ |
646 | 526 | ||
647 | #define hp_sub_vendor_id_0 0x04 /* LSB */ | ||
648 | #define hp_sub_vendor_id_1 0x05 /* MSB */ | ||
649 | #define hp_sub_device_id_0 0x06 /* LSB */ | 527 | #define hp_sub_device_id_0 0x06 /* LSB */ |
650 | #define hp_sub_device_id_1 0x07 /* MSB */ | ||
651 | 528 | ||
652 | 529 | ||
653 | #define hp_dual_addr_lo 0x08 | ||
654 | #define hp_dual_addr_lmi 0x09 | ||
655 | #define hp_dual_addr_hmi 0x0A | ||
656 | #define hp_dual_addr_hi 0x0B | ||
657 | 530 | ||
658 | #define hp_semaphore 0x0C | 531 | #define hp_semaphore 0x0C |
659 | #define SCCB_MGR_ACTIVE BIT(0) | 532 | #define SCCB_MGR_ACTIVE BIT(0) |
@@ -661,9 +534,7 @@ typedef struct SCCBscam_info { | |||
661 | #define SCCB_MGR_PRESENT BIT(3) | 534 | #define SCCB_MGR_PRESENT BIT(3) |
662 | #define BIOS_IN_USE BIT(4) | 535 | #define BIOS_IN_USE BIT(4) |
663 | 536 | ||
664 | #define hp_user_defined_D 0x0D | ||
665 | 537 | ||
666 | #define hp_reserved_E 0x0E | ||
667 | 538 | ||
668 | #define hp_sys_ctrl 0x0F | 539 | #define hp_sys_ctrl 0x0F |
669 | 540 | ||
@@ -671,95 +542,49 @@ typedef struct SCCBscam_info { | |||
671 | #define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */ | 542 | #define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */ |
672 | #define HALT_MACH BIT(3) /*Halt State Machine */ | 543 | #define HALT_MACH BIT(3) /*Halt State Machine */ |
673 | #define HARD_ABORT BIT(4) /*Hard Abort */ | 544 | #define HARD_ABORT BIT(4) /*Hard Abort */ |
674 | #define DIAG_MODE BIT(5) /*Diagnostic Mode */ | ||
675 | 545 | ||
676 | #define BM_ABORT_TMOUT 0x50 /*Halt State machine time out */ | ||
677 | 546 | ||
678 | #define hp_sys_cfg 0x10 | ||
679 | 547 | ||
680 | #define DONT_RST_FIFO BIT(7) /*Don't reset FIFO */ | ||
681 | 548 | ||
682 | 549 | ||
683 | #define hp_host_ctrl0 0x11 | ||
684 | 550 | ||
685 | #define DUAL_ADDR_MODE BIT(0) /*Enable 64-bit addresses */ | ||
686 | #define IO_MEM_SPACE BIT(1) /*I/O Memory Space */ | ||
687 | #define RESOURCE_LOCK BIT(2) /*Enable Resource Lock */ | ||
688 | #define IGNOR_ACCESS_ERR BIT(3) /*Ignore Access Error */ | ||
689 | #define HOST_INT_EDGE BIT(4) /*Host interrupt level/edge mode sel */ | ||
690 | #define SIX_CLOCKS BIT(5) /*6 Clocks between Strobe */ | ||
691 | #define DMA_EVEN_PARITY BIT(6) /*Enable DMA Enen Parity */ | ||
692 | 551 | ||
693 | /* | ||
694 | #define BURST_MODE BIT(0) | ||
695 | */ | ||
696 | 552 | ||
697 | #define hp_reserved_12 0x12 | ||
698 | 553 | ||
699 | #define hp_host_blk_cnt 0x13 | 554 | #define hp_host_blk_cnt 0x13 |
700 | 555 | ||
701 | #define XFER_BLK1 0x00 /* 0 0 0 1 byte per block*/ | ||
702 | #define XFER_BLK2 0x01 /* 0 0 1 2 byte per block*/ | ||
703 | #define XFER_BLK4 0x02 /* 0 1 0 4 byte per block*/ | ||
704 | #define XFER_BLK8 0x03 /* 0 1 1 8 byte per block*/ | ||
705 | #define XFER_BLK16 0x04 /* 1 0 0 16 byte per block*/ | ||
706 | #define XFER_BLK32 0x05 /* 1 0 1 32 byte per block*/ | ||
707 | #define XFER_BLK64 0x06 /* 1 1 0 64 byte per block*/ | 556 | #define XFER_BLK64 0x06 /* 1 1 0 64 byte per block*/ |
708 | 557 | ||
709 | #define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes*/ | 558 | #define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes*/ |
710 | 559 | ||
711 | 560 | ||
712 | #define hp_reserved_14 0x14 | ||
713 | #define hp_reserved_15 0x15 | ||
714 | #define hp_reserved_16 0x16 | ||
715 | 561 | ||
716 | #define hp_int_mask 0x17 | 562 | #define hp_int_mask 0x17 |
717 | 563 | ||
718 | #define INT_CMD_COMPL BIT(0) /* DMA command complete */ | 564 | #define INT_CMD_COMPL BIT(0) /* DMA command complete */ |
719 | #define INT_EXT_STATUS BIT(1) /* Extended Status Set */ | 565 | #define INT_EXT_STATUS BIT(1) /* Extended Status Set */ |
720 | #define INT_SCSI BIT(2) /* Scsi block interrupt */ | ||
721 | #define INT_FIFO_RDY BIT(4) /* FIFO data ready */ | ||
722 | 566 | ||
723 | 567 | ||
724 | #define hp_xfer_cnt_lo 0x18 | 568 | #define hp_xfer_cnt_lo 0x18 |
725 | #define hp_xfer_cnt_mi 0x19 | ||
726 | #define hp_xfer_cnt_hi 0x1A | 569 | #define hp_xfer_cnt_hi 0x1A |
727 | #define hp_xfer_cmd 0x1B | 570 | #define hp_xfer_cmd 0x1B |
728 | 571 | ||
729 | #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */ | 572 | #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */ |
730 | #define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */ | 573 | #define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */ |
731 | #define XFER_HOST_MPU 0x02 /* 0 1 0 Transfer Host -> MPU */ | ||
732 | #define XFER_MPU_HOST 0x03 /* 0 1 1 Transfer MPU -> Host */ | ||
733 | #define XFER_DMA_MPU 0x04 /* 1 0 0 Transfer DMA -> MPU */ | ||
734 | #define XFER_MPU_DMA 0x05 /* 1 0 1 Transfer MPU -> DMA */ | ||
735 | #define SET_SEMAPHORE 0x06 /* 1 1 0 Set Semaphore */ | ||
736 | #define XFER_NOP 0x07 /* 1 1 1 Transfer NOP */ | ||
737 | #define XFER_MB_MPU 0x06 /* 1 1 0 Transfer MB -> MPU */ | ||
738 | #define XFER_MB_DMA 0x07 /* 1 1 1 Transfer MB -> DMA */ | ||
739 | 574 | ||
740 | 575 | ||
741 | #define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */ | 576 | #define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */ |
742 | #define XFER_HOST_8BIT 0x08 /* 0 1 8 BIT Transfer Size */ | ||
743 | #define XFER_HOST_16BIT 0x10 /* 1 0 16 BIT Transfer Size */ | ||
744 | #define XFER_HOST_32BIT 0x18 /* 1 1 32 BIT Transfer Size */ | ||
745 | 577 | ||
746 | #define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */ | 578 | #define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */ |
747 | #define XFER_DMA_16BIT 0x40 /* 1 0 16 BIT Transfer Size */ | ||
748 | 579 | ||
749 | #define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */ | 580 | #define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */ |
750 | 581 | ||
751 | #define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT)) | 582 | #define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT)) |
752 | #define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT)) | 583 | #define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT)) |
753 | #define WIDE_HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_16BIT)) | ||
754 | #define WIDE_HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_16BIT)) | ||
755 | 584 | ||
756 | #define hp_host_addr_lo 0x1C | 585 | #define hp_host_addr_lo 0x1C |
757 | #define hp_host_addr_lmi 0x1D | ||
758 | #define hp_host_addr_hmi 0x1E | 586 | #define hp_host_addr_hmi 0x1E |
759 | #define hp_host_addr_hi 0x1F | ||
760 | 587 | ||
761 | #define hp_pio_data 0x20 | ||
762 | #define hp_reserved_21 0x21 | ||
763 | #define hp_ee_ctrl 0x22 | 588 | #define hp_ee_ctrl 0x22 |
764 | 589 | ||
765 | #define EXT_ARB_ACK BIT(7) | 590 | #define EXT_ARB_ACK BIT(7) |
@@ -777,17 +602,8 @@ typedef struct SCCBscam_info { | |||
777 | #define EWDS 0x04 | 602 | #define EWDS 0x04 |
778 | #define EWDS_ADDR 0x0000 | 603 | #define EWDS_ADDR 0x0000 |
779 | 604 | ||
780 | #define hp_brdctl 0x23 | ||
781 | 605 | ||
782 | #define DAT_7 BIT(7) | ||
783 | #define DAT_6 BIT(6) | ||
784 | #define DAT_5 BIT(5) | ||
785 | #define BRD_STB BIT(4) | ||
786 | #define BRD_CS BIT(3) | ||
787 | #define BRD_WR BIT(2) | ||
788 | 606 | ||
789 | #define hp_reserved_24 0x24 | ||
790 | #define hp_reserved_25 0x25 | ||
791 | 607 | ||
792 | 608 | ||
793 | 609 | ||
@@ -796,70 +612,36 @@ typedef struct SCCBscam_info { | |||
796 | 612 | ||
797 | #define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */ | 613 | #define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */ |
798 | #define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */ | 614 | #define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */ |
799 | #define BM_XFER_MIN_8 BIT(2) /*Enable bus master transfer of 9 */ | ||
800 | #define BIOS_ENA BIT(3) /*Enable BIOS/FLASH Enable */ | ||
801 | #define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */ | 615 | #define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */ |
802 | #define FAST_SINGLE BIT(6) /*?? */ | 616 | #define FAST_SINGLE BIT(6) /*?? */ |
803 | 617 | ||
804 | #define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L) | 618 | #define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L) |
805 | 619 | ||
806 | #define hp_reserved_27 0x27 | ||
807 | 620 | ||
808 | #define hp_sg_addr 0x28 | 621 | #define hp_sg_addr 0x28 |
809 | #define hp_page_ctrl 0x29 | 622 | #define hp_page_ctrl 0x29 |
810 | 623 | ||
811 | #define SCATTER_EN BIT(0) | 624 | #define SCATTER_EN BIT(0) |
812 | #define SGRAM_ARAM BIT(1) | 625 | #define SGRAM_ARAM BIT(1) |
813 | #define BIOS_SHADOW BIT(2) | ||
814 | #define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */ | 626 | #define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */ |
815 | #define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */ | 627 | #define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */ |
816 | 628 | ||
817 | #define hp_reserved_2A 0x2A | ||
818 | #define hp_pci_cmd_cfg 0x2B | ||
819 | 629 | ||
820 | #define IO_SPACE_ENA BIT(0) /*enable I/O space */ | ||
821 | #define MEM_SPACE_ENA BIT(1) /*enable memory space */ | ||
822 | #define BUS_MSTR_ENA BIT(2) /*enable bus master operation */ | ||
823 | #define MEM_WI_ENA BIT(4) /*enable Write and Invalidate */ | ||
824 | #define PAR_ERR_RESP BIT(6) /*enable parity error responce. */ | ||
825 | 630 | ||
826 | #define hp_reserved_2C 0x2C | ||
827 | 631 | ||
828 | #define hp_pci_stat_cfg 0x2D | 632 | #define hp_pci_stat_cfg 0x2D |
829 | 633 | ||
830 | #define DATA_PARITY_ERR BIT(0) | ||
831 | #define REC_TARGET_ABORT BIT(4) /*received Target abort */ | ||
832 | #define REC_MASTER_ABORT BIT(5) /*received Master abort */ | 634 | #define REC_MASTER_ABORT BIT(5) /*received Master abort */ |
833 | #define SIG_SYSTEM_ERR BIT(6) | ||
834 | #define DETECTED_PAR_ERR BIT(7) | ||
835 | 635 | ||
836 | #define hp_reserved_2E 0x2E | ||
837 | 636 | ||
838 | #define hp_sys_status 0x2F | ||
839 | 637 | ||
840 | #define SLV_DATA_RDY BIT(0) /*Slave data ready */ | ||
841 | #define XFER_CNT_ZERO BIT(1) /*Transfer counter = 0 */ | ||
842 | #define BM_FIFO_EMPTY BIT(2) /*FIFO empty */ | ||
843 | #define BM_FIFO_FULL BIT(3) /*FIFO full */ | ||
844 | #define HOST_OP_DONE BIT(4) /*host operation done */ | ||
845 | #define DMA_OP_DONE BIT(5) /*DMA operation done */ | ||
846 | #define SLV_OP_DONE BIT(6) /*Slave operation done */ | ||
847 | #define PWR_ON_FLAG BIT(7) /*Power on flag */ | ||
848 | 638 | ||
849 | #define hp_reserved_30 0x30 | ||
850 | 639 | ||
851 | #define hp_host_status0 0x31 | ||
852 | 640 | ||
853 | #define HOST_TERM BIT(5) /*Host Terminal Count */ | ||
854 | #define HOST_TRSHLD BIT(6) /*Host Threshold */ | ||
855 | #define CONNECTED_2_HOST BIT(7) /*Connected to Host */ | ||
856 | 641 | ||
857 | #define hp_reserved_32 0x32 | ||
858 | 642 | ||
859 | #define hp_rev_num 0x33 | 643 | #define hp_rev_num 0x33 |
860 | 644 | ||
861 | #define REV_A_CONST 0x0E | ||
862 | #define REV_B_CONST 0x0E | ||
863 | 645 | ||
864 | #define hp_stack_data 0x34 | 646 | #define hp_stack_data 0x34 |
865 | #define hp_stack_addr 0x35 | 647 | #define hp_stack_addr 0x35 |
@@ -869,8 +651,6 @@ typedef struct SCCBscam_info { | |||
869 | #define BM_FORCE_OFF BIT(0) /*Bus Master is forced to get off */ | 651 | #define BM_FORCE_OFF BIT(0) /*Bus Master is forced to get off */ |
870 | #define PCI_TGT_ABORT BIT(0) /*PCI bus master transaction aborted */ | 652 | #define PCI_TGT_ABORT BIT(0) /*PCI bus master transaction aborted */ |
871 | #define PCI_DEV_TMOUT BIT(1) /*PCI Device Time out */ | 653 | #define PCI_DEV_TMOUT BIT(1) /*PCI Device Time out */ |
872 | #define FIFO_TC_NOT_ZERO BIT(2) /*FIFO or transfer counter not zero */ | ||
873 | #define CHIP_RST_OCCUR BIT(3) /*Chip reset occurs */ | ||
874 | #define CMD_ABORTED BIT(4) /*Command aborted */ | 654 | #define CMD_ABORTED BIT(4) /*Command aborted */ |
875 | #define BM_PARITY_ERR BIT(5) /*parity error on data received */ | 655 | #define BM_PARITY_ERR BIT(5) /*parity error on data received */ |
876 | #define PIO_OVERRUN BIT(6) /*Slave data overrun */ | 656 | #define PIO_OVERRUN BIT(6) /*Slave data overrun */ |
@@ -880,24 +660,13 @@ typedef struct SCCBscam_info { | |||
880 | 660 | ||
881 | #define hp_int_status 0x37 | 661 | #define hp_int_status 0x37 |
882 | 662 | ||
883 | #define BM_CMD_CMPL BIT(0) /*Bus Master command complete */ | ||
884 | #define EXT_STATUS_ON BIT(1) /*Extended status is valid */ | 663 | #define EXT_STATUS_ON BIT(1) /*Extended status is valid */ |
885 | #define SCSI_INTERRUPT BIT(2) /*Global indication of a SCSI int. */ | 664 | #define SCSI_INTERRUPT BIT(2) /*Global indication of a SCSI int. */ |
886 | #define BM_FIFO_RDY BIT(4) | ||
887 | #define INT_ASSERTED BIT(5) /* */ | 665 | #define INT_ASSERTED BIT(5) /* */ |
888 | #define SRAM_BUSY BIT(6) /*Scatter/Gather RAM busy */ | ||
889 | #define CMD_REG_BUSY BIT(7) | ||
890 | 666 | ||
891 | 667 | ||
892 | #define hp_fifo_cnt 0x38 | 668 | #define hp_fifo_cnt 0x38 |
893 | #define hp_curr_host_cnt 0x39 | ||
894 | #define hp_reserved_3A 0x3A | ||
895 | #define hp_fifo_in_addr 0x3B | ||
896 | 669 | ||
897 | #define hp_fifo_out_addr 0x3C | ||
898 | #define hp_reserved_3D 0x3D | ||
899 | #define hp_reserved_3E 0x3E | ||
900 | #define hp_reserved_3F 0x3F | ||
901 | 670 | ||
902 | 671 | ||
903 | 672 | ||
@@ -937,9 +706,7 @@ typedef struct SCCBscam_info { | |||
937 | #define SCSI_IOBIT BIT(0) | 706 | #define SCSI_IOBIT BIT(0) |
938 | 707 | ||
939 | #define S_SCSI_PHZ (BIT(2)+BIT(1)+BIT(0)) | 708 | #define S_SCSI_PHZ (BIT(2)+BIT(1)+BIT(0)) |
940 | #define S_CMD_PH (BIT(2) ) | ||
941 | #define S_MSGO_PH (BIT(2)+BIT(1) ) | 709 | #define S_MSGO_PH (BIT(2)+BIT(1) ) |
942 | #define S_STAT_PH (BIT(2) +BIT(0)) | ||
943 | #define S_MSGI_PH (BIT(2)+BIT(1)+BIT(0)) | 710 | #define S_MSGI_PH (BIT(2)+BIT(1)+BIT(0)) |
944 | #define S_DATAI_PH ( BIT(0)) | 711 | #define S_DATAI_PH ( BIT(0)) |
945 | #define S_DATAO_PH 0x00 | 712 | #define S_DATAO_PH 0x00 |
@@ -947,7 +714,6 @@ typedef struct SCCBscam_info { | |||
947 | 714 | ||
948 | #define hp_scsictrl_0 0x45 | 715 | #define hp_scsictrl_0 0x45 |
949 | 716 | ||
950 | #define NO_ARB BIT(7) | ||
951 | #define SEL_TAR BIT(6) | 717 | #define SEL_TAR BIT(6) |
952 | #define ENA_ATN BIT(4) | 718 | #define ENA_ATN BIT(4) |
953 | #define ENA_RESEL BIT(2) | 719 | #define ENA_RESEL BIT(2) |
@@ -969,44 +735,33 @@ typedef struct SCCBscam_info { | |||
969 | 735 | ||
970 | #define hp_scsireset 0x47 | 736 | #define hp_scsireset 0x47 |
971 | 737 | ||
972 | #define SCSI_TAR BIT(7) | ||
973 | #define SCSI_INI BIT(6) | 738 | #define SCSI_INI BIT(6) |
974 | #define SCAM_EN BIT(5) | 739 | #define SCAM_EN BIT(5) |
975 | #define ACK_HOLD BIT(4) | ||
976 | #define DMA_RESET BIT(3) | 740 | #define DMA_RESET BIT(3) |
977 | #define HPSCSI_RESET BIT(2) | 741 | #define HPSCSI_RESET BIT(2) |
978 | #define PROG_RESET BIT(1) | 742 | #define PROG_RESET BIT(1) |
979 | #define FIFO_CLR BIT(0) | 743 | #define FIFO_CLR BIT(0) |
980 | 744 | ||
981 | #define hp_xfercnt_0 0x48 | 745 | #define hp_xfercnt_0 0x48 |
982 | #define hp_xfercnt_1 0x49 | ||
983 | #define hp_xfercnt_2 0x4A | 746 | #define hp_xfercnt_2 0x4A |
984 | #define hp_xfercnt_3 0x4B | ||
985 | 747 | ||
986 | #define hp_fifodata_0 0x4C | 748 | #define hp_fifodata_0 0x4C |
987 | #define hp_fifodata_1 0x4D | ||
988 | #define hp_addstat 0x4E | 749 | #define hp_addstat 0x4E |
989 | 750 | ||
990 | #define SCAM_TIMER BIT(7) | 751 | #define SCAM_TIMER BIT(7) |
991 | #define AUTO_RUNNING BIT(6) | ||
992 | #define FAST_SYNC BIT(5) | ||
993 | #define SCSI_MODE8 BIT(3) | 752 | #define SCSI_MODE8 BIT(3) |
994 | #define SCSI_PAR_ERR BIT(0) | 753 | #define SCSI_PAR_ERR BIT(0) |
995 | 754 | ||
996 | #define hp_prgmcnt_0 0x4F | 755 | #define hp_prgmcnt_0 0x4F |
997 | 756 | ||
998 | #define AUTO_PC_MASK 0x3F | ||
999 | 757 | ||
1000 | #define hp_selfid_0 0x50 | 758 | #define hp_selfid_0 0x50 |
1001 | #define hp_selfid_1 0x51 | 759 | #define hp_selfid_1 0x51 |
1002 | #define hp_arb_id 0x52 | 760 | #define hp_arb_id 0x52 |
1003 | 761 | ||
1004 | #define ARB_ID (BIT(3) + BIT(2) + BIT(1) + BIT(0)) | ||
1005 | 762 | ||
1006 | #define hp_select_id 0x53 | 763 | #define hp_select_id 0x53 |
1007 | 764 | ||
1008 | #define RESEL_ID (BIT(7) + BIT(6) + BIT(5) + BIT(4)) | ||
1009 | #define SELECT_ID (BIT(3) + BIT(2) + BIT(1) + BIT(0)) | ||
1010 | 765 | ||
1011 | #define hp_synctarg_base 0x54 | 766 | #define hp_synctarg_base 0x54 |
1012 | #define hp_synctarg_12 0x54 | 767 | #define hp_synctarg_12 0x54 |
@@ -1029,63 +784,38 @@ typedef struct SCCBscam_info { | |||
1029 | #define hp_synctarg_2 0x62 | 784 | #define hp_synctarg_2 0x62 |
1030 | #define hp_synctarg_3 0x63 | 785 | #define hp_synctarg_3 0x63 |
1031 | 786 | ||
1032 | #define RATE_20MB 0x00 | ||
1033 | #define RATE_10MB ( BIT(5)) | ||
1034 | #define RATE_6_6MB ( BIT(6) ) | ||
1035 | #define RATE_5MB ( BIT(6)+BIT(5)) | ||
1036 | #define RATE_4MB (BIT(7) ) | ||
1037 | #define RATE_3_33MB (BIT(7) +BIT(5)) | ||
1038 | #define RATE_2_85MB (BIT(7)+BIT(6) ) | ||
1039 | #define RATE_2_5MB (BIT(7)+BIT(5)+BIT(6)) | ||
1040 | #define NEXT_CLK BIT(5) | ||
1041 | #define SLOWEST_SYNC (BIT(7)+BIT(6)+BIT(5)) | ||
1042 | #define NARROW_SCSI BIT(4) | 787 | #define NARROW_SCSI BIT(4) |
1043 | #define SYNC_OFFSET (BIT(3) + BIT(2) + BIT(1) + BIT(0)) | ||
1044 | #define DEFAULT_ASYNC 0x00 | ||
1045 | #define DEFAULT_OFFSET 0x0F | 788 | #define DEFAULT_OFFSET 0x0F |
1046 | 789 | ||
1047 | #define hp_autostart_0 0x64 | 790 | #define hp_autostart_0 0x64 |
1048 | #define hp_autostart_1 0x65 | 791 | #define hp_autostart_1 0x65 |
1049 | #define hp_autostart_2 0x66 | ||
1050 | #define hp_autostart_3 0x67 | 792 | #define hp_autostart_3 0x67 |
1051 | 793 | ||
1052 | 794 | ||
1053 | 795 | ||
1054 | #define DISABLE 0x00 | ||
1055 | #define AUTO_IMMED BIT(5) | 796 | #define AUTO_IMMED BIT(5) |
1056 | #define SELECT BIT(6) | 797 | #define SELECT BIT(6) |
1057 | #define RESELECT (BIT(6)+BIT(5)) | ||
1058 | #define BUSFREE BIT(7) | ||
1059 | #define XFER_0 (BIT(7)+BIT(5)) | ||
1060 | #define END_DATA (BIT(7)+BIT(6)) | 798 | #define END_DATA (BIT(7)+BIT(6)) |
1061 | #define MSG_PHZ (BIT(7)+BIT(6)+BIT(5)) | ||
1062 | 799 | ||
1063 | #define hp_gp_reg_0 0x68 | 800 | #define hp_gp_reg_0 0x68 |
1064 | #define hp_gp_reg_1 0x69 | 801 | #define hp_gp_reg_1 0x69 |
1065 | #define hp_gp_reg_2 0x6A | ||
1066 | #define hp_gp_reg_3 0x6B | 802 | #define hp_gp_reg_3 0x6B |
1067 | 803 | ||
1068 | #define hp_seltimeout 0x6C | 804 | #define hp_seltimeout 0x6C |
1069 | 805 | ||
1070 | 806 | ||
1071 | #define TO_2ms 0x54 /* 2.0503ms */ | ||
1072 | #define TO_4ms 0x67 /* 3.9959ms */ | 807 | #define TO_4ms 0x67 /* 3.9959ms */ |
1073 | 808 | ||
1074 | #define TO_5ms 0x03 /* 4.9152ms */ | 809 | #define TO_5ms 0x03 /* 4.9152ms */ |
1075 | #define TO_10ms 0x07 /* 11.xxxms */ | 810 | #define TO_10ms 0x07 /* 11.xxxms */ |
1076 | #define TO_250ms 0x99 /* 250.68ms */ | 811 | #define TO_250ms 0x99 /* 250.68ms */ |
1077 | #define TO_290ms 0xB1 /* 289.99ms */ | 812 | #define TO_290ms 0xB1 /* 289.99ms */ |
1078 | #define TO_350ms 0xD6 /* 350.62ms */ | ||
1079 | #define TO_417ms 0xFF /* 417.79ms */ | ||
1080 | 813 | ||
1081 | #define hp_clkctrl_0 0x6D | 814 | #define hp_clkctrl_0 0x6D |
1082 | 815 | ||
1083 | #define PWR_DWN BIT(6) | 816 | #define PWR_DWN BIT(6) |
1084 | #define ACTdeassert BIT(4) | 817 | #define ACTdeassert BIT(4) |
1085 | #define ATNonErr BIT(3) | ||
1086 | #define CLK_30MHZ BIT(1) | ||
1087 | #define CLK_40MHZ (BIT(1) + BIT(0)) | 818 | #define CLK_40MHZ (BIT(1) + BIT(0)) |
1088 | #define CLK_50MHZ BIT(2) | ||
1089 | 819 | ||
1090 | #define CLKCTRL_DEFAULT (ACTdeassert | CLK_40MHZ) | 820 | #define CLKCTRL_DEFAULT (ACTdeassert | CLK_40MHZ) |
1091 | 821 | ||
@@ -1095,38 +825,21 @@ typedef struct SCCBscam_info { | |||
1095 | #define hp_offsetctr 0x70 | 825 | #define hp_offsetctr 0x70 |
1096 | #define hp_xferstat 0x71 | 826 | #define hp_xferstat 0x71 |
1097 | 827 | ||
1098 | #define FIFO_FULL BIT(7) | ||
1099 | #define FIFO_EMPTY BIT(6) | 828 | #define FIFO_EMPTY BIT(6) |
1100 | #define FIFO_MASK 0x3F /* Mask for the FIFO count value. */ | ||
1101 | #define FIFO_LEN 0x20 | ||
1102 | 829 | ||
1103 | #define hp_portctrl_1 0x72 | 830 | #define hp_portctrl_1 0x72 |
1104 | 831 | ||
1105 | #define EVEN_HOST_P BIT(5) | ||
1106 | #define INVT_SCSI BIT(4) | ||
1107 | #define CHK_SCSI_P BIT(3) | 832 | #define CHK_SCSI_P BIT(3) |
1108 | #define HOST_MODE8 BIT(0) | 833 | #define HOST_MODE8 BIT(0) |
1109 | #define HOST_MODE16 0x00 | ||
1110 | 834 | ||
1111 | #define hp_xfer_pad 0x73 | 835 | #define hp_xfer_pad 0x73 |
1112 | 836 | ||
1113 | #define ID_UNLOCK BIT(3) | 837 | #define ID_UNLOCK BIT(3) |
1114 | #define XFER_PAD BIT(2) | ||
1115 | 838 | ||
1116 | #define hp_scsidata_0 0x74 | 839 | #define hp_scsidata_0 0x74 |
1117 | #define hp_scsidata_1 0x75 | 840 | #define hp_scsidata_1 0x75 |
1118 | #define hp_timer_0 0x76 | ||
1119 | #define hp_timer_1 0x77 | ||
1120 | 841 | ||
1121 | #define hp_reserved_78 0x78 | ||
1122 | #define hp_reserved_79 0x79 | ||
1123 | #define hp_reserved_7A 0x7A | ||
1124 | #define hp_reserved_7B 0x7B | ||
1125 | 842 | ||
1126 | #define hp_reserved_7C 0x7C | ||
1127 | #define hp_reserved_7D 0x7D | ||
1128 | #define hp_reserved_7E 0x7E | ||
1129 | #define hp_reserved_7F 0x7F | ||
1130 | 843 | ||
1131 | #define hp_aramBase 0x80 | 844 | #define hp_aramBase 0x80 |
1132 | #define BIOS_DATA_OFFSET 0x60 | 845 | #define BIOS_DATA_OFFSET 0x60 |
@@ -1135,22 +848,15 @@ typedef struct SCCBscam_info { | |||
1135 | 848 | ||
1136 | 849 | ||
1137 | 850 | ||
1138 | #define AUTO_LEN 0x80 | ||
1139 | #define AR0 0x00 | ||
1140 | #define AR1 BITW(8) | ||
1141 | #define AR2 BITW(9) | ||
1142 | #define AR3 (BITW(9) + BITW(8)) | 851 | #define AR3 (BITW(9) + BITW(8)) |
1143 | #define SDATA BITW(10) | 852 | #define SDATA BITW(10) |
1144 | 853 | ||
1145 | #define NOP_OP 0x00 /* Nop command */ | ||
1146 | 854 | ||
1147 | #define CRD_OP BITW(11) /* Cmp Reg. w/ Data */ | 855 | #define CRD_OP BITW(11) /* Cmp Reg. w/ Data */ |
1148 | 856 | ||
1149 | #define CRR_OP BITW(12) /* Cmp Reg. w. Reg. */ | 857 | #define CRR_OP BITW(12) /* Cmp Reg. w. Reg. */ |
1150 | 858 | ||
1151 | #define CBE_OP (BITW(14)+BITW(12)+BITW(11)) /* Cmp SCSI cmd class & Branch EQ */ | ||
1152 | 859 | ||
1153 | #define CBN_OP (BITW(14)+BITW(13)) /* Cmp SCSI cmd class & Branch NOT EQ */ | ||
1154 | 860 | ||
1155 | #define CPE_OP (BITW(14)+BITW(11)) /* Cmp SCSI phs & Branch EQ */ | 861 | #define CPE_OP (BITW(14)+BITW(11)) /* Cmp SCSI phs & Branch EQ */ |
1156 | 862 | ||
@@ -1163,7 +869,6 @@ typedef struct SCCBscam_info { | |||
1163 | #define ASTATUS (BITW(10)+BITW(8)) | 869 | #define ASTATUS (BITW(10)+BITW(8)) |
1164 | #define AMSG_OUT (BITW(10)+BITW(9)) | 870 | #define AMSG_OUT (BITW(10)+BITW(9)) |
1165 | #define AMSG_IN (BITW(10)+BITW(9)+BITW(8)) | 871 | #define AMSG_IN (BITW(10)+BITW(9)+BITW(8)) |
1166 | #define AILLEGAL (BITW(9)+BITW(8)) | ||
1167 | 872 | ||
1168 | 873 | ||
1169 | #define BRH_OP BITW(13) /* Branch */ | 874 | #define BRH_OP BITW(13) /* Branch */ |
@@ -1176,17 +881,11 @@ typedef struct SCCBscam_info { | |||
1176 | #define TCB_OP (BITW(13)+BITW(11)) /* Test condition & branch */ | 881 | #define TCB_OP (BITW(13)+BITW(11)) /* Test condition & branch */ |
1177 | 882 | ||
1178 | 883 | ||
1179 | #define ATN_SET BITW(8) | ||
1180 | #define ATN_RESET BITW(9) | ||
1181 | #define XFER_CNT (BITW(9)+BITW(8)) | ||
1182 | #define FIFO_0 BITW(10) | 884 | #define FIFO_0 BITW(10) |
1183 | #define FIFO_NOT0 (BITW(10)+BITW(8)) | ||
1184 | #define T_USE_SYNC0 (BITW(10)+BITW(9)) | ||
1185 | 885 | ||
1186 | 886 | ||
1187 | #define MPM_OP BITW(15) /* Match phase and move data */ | 887 | #define MPM_OP BITW(15) /* Match phase and move data */ |
1188 | 888 | ||
1189 | #define MDR_OP (BITW(12)+BITW(11)) /* Move data to Reg. */ | ||
1190 | 889 | ||
1191 | #define MRR_OP BITW(14) /* Move DReg. to Reg. */ | 890 | #define MRR_OP BITW(14) /* Move DReg. to Reg. */ |
1192 | 891 | ||
@@ -1196,34 +895,14 @@ typedef struct SCCBscam_info { | |||
1196 | 895 | ||
1197 | #define D_AR0 0x00 | 896 | #define D_AR0 0x00 |
1198 | #define D_AR1 BIT(0) | 897 | #define D_AR1 BIT(0) |
1199 | #define D_AR2 BIT(1) | ||
1200 | #define D_AR3 (BIT(1) + BIT(0)) | ||
1201 | #define D_SDATA BIT(2) | ||
1202 | #define D_BUCKET (BIT(2) + BIT(1) + BIT(0)) | 898 | #define D_BUCKET (BIT(2) + BIT(1) + BIT(0)) |
1203 | 899 | ||
1204 | 900 | ||
1205 | #define ADR_OP (BITW(13)+BITW(12)) /* Logical AND Reg. w. Data */ | ||
1206 | 901 | ||
1207 | #define ADS_OP (BITW(14)+BITW(13)+BITW(12)) | ||
1208 | 902 | ||
1209 | #define ODR_OP (BITW(13)+BITW(12)+BITW(11)) | ||
1210 | 903 | ||
1211 | #define ODS_OP (BITW(14)+BITW(13)+BITW(12)+BITW(11)) | ||
1212 | 904 | ||
1213 | #define STR_OP (BITW(15)+BITW(14)) /* Store to A_Reg. */ | ||
1214 | 905 | ||
1215 | #define AINT_ENA1 0x00 | ||
1216 | #define AINT_STAT1 BITW(8) | ||
1217 | #define ASCSI_SIG BITW(9) | ||
1218 | #define ASCSI_CNTL (BITW(9)+BITW(8)) | ||
1219 | #define APORT_CNTL BITW(10) | ||
1220 | #define ARST_CNTL (BITW(10)+BITW(8)) | ||
1221 | #define AXFERCNT0 (BITW(10)+BITW(9)) | ||
1222 | #define AXFERCNT1 (BITW(10)+BITW(9)+BITW(8)) | ||
1223 | #define AXFERCNT2 BITW(11) | ||
1224 | #define AFIFO_DATA (BITW(11)+BITW(8)) | ||
1225 | #define ASCSISELID (BITW(11)+BITW(9)) | ||
1226 | #define ASCSISYNC0 (BITW(11)+BITW(9)+BITW(8)) | ||
1227 | 906 | ||
1228 | 907 | ||
1229 | #define RAT_OP (BITW(14)+BITW(13)+BITW(11)) | 908 | #define RAT_OP (BITW(14)+BITW(13)+BITW(11)) |
@@ -1233,7 +912,6 @@ typedef struct SCCBscam_info { | |||
1233 | 912 | ||
1234 | #define SSI_ITAR_DISC (ITAR_DISC >> 8) | 913 | #define SSI_ITAR_DISC (ITAR_DISC >> 8) |
1235 | #define SSI_IDO_STRT (IDO_STRT >> 8) | 914 | #define SSI_IDO_STRT (IDO_STRT >> 8) |
1236 | #define SSI_IDI_STRT (IDO_STRT >> 8) | ||
1237 | 915 | ||
1238 | #define SSI_ICMD_COMP (ICMD_COMP >> 8) | 916 | #define SSI_ICMD_COMP (ICMD_COMP >> 8) |
1239 | #define SSI_ITICKLE (ITICKLE >> 8) | 917 | #define SSI_ITICKLE (ITICKLE >> 8) |
@@ -1248,13 +926,11 @@ typedef struct SCCBscam_info { | |||
1248 | #define CMDPZ 0x04 /*Command phase */ | 926 | #define CMDPZ 0x04 /*Command phase */ |
1249 | #define DINT 0x12 /*Data Out/In interrupt */ | 927 | #define DINT 0x12 /*Data Out/In interrupt */ |
1250 | #define DI 0x13 /*Data Out */ | 928 | #define DI 0x13 /*Data Out */ |
1251 | #define MI 0x14 /*Message In */ | ||
1252 | #define DC 0x19 /*Disconnect Message */ | 929 | #define DC 0x19 /*Disconnect Message */ |
1253 | #define ST 0x1D /*Status Phase */ | 930 | #define ST 0x1D /*Status Phase */ |
1254 | #define UNKNWN 0x24 /*Unknown bus action */ | 931 | #define UNKNWN 0x24 /*Unknown bus action */ |
1255 | #define CC 0x25 /*Command Completion failure */ | 932 | #define CC 0x25 /*Command Completion failure */ |
1256 | #define TICK 0x26 /*New target reselected us. */ | 933 | #define TICK 0x26 /*New target reselected us. */ |
1257 | #define RFAIL 0x27 /*Reselection failed */ | ||
1258 | #define SELCHK 0x28 /*Select & Check SCSI ID latch reg */ | 934 | #define SELCHK 0x28 /*Select & Check SCSI ID latch reg */ |
1259 | 935 | ||
1260 | 936 | ||
@@ -1268,25 +944,18 @@ typedef struct SCCBscam_info { | |||
1268 | 944 | ||
1269 | 945 | ||
1270 | #define TAG_STRT 0x00 | 946 | #define TAG_STRT 0x00 |
1271 | #define SELECTION_START 0x00 | ||
1272 | #define DISCONNECT_START 0x10/2 | 947 | #define DISCONNECT_START 0x10/2 |
1273 | #define END_DATA_START 0x14/2 | 948 | #define END_DATA_START 0x14/2 |
1274 | #define NONTAG_STRT 0x02/2 | ||
1275 | #define CMD_ONLY_STRT CMDPZ/2 | 949 | #define CMD_ONLY_STRT CMDPZ/2 |
1276 | #define TICKLE_STRT TICK/2 | ||
1277 | #define SELCHK_STRT SELCHK/2 | 950 | #define SELCHK_STRT SELCHK/2 |
1278 | 951 | ||
1279 | 952 | ||
1280 | 953 | ||
1281 | 954 | ||
1282 | #define mEEPROM_CLK_DELAY(port) (RD_HARPOON(port+hp_intstat_1)) | ||
1283 | 955 | ||
1284 | #define mWAIT_10MS(port) (RD_HARPOON(port+hp_intstat_1)) | ||
1285 | 956 | ||
1286 | 957 | ||
1287 | #define CLR_XFER_CNT(port) (WR_HARPOON(port+hp_xfercnt_0, 0x00)) | ||
1288 | 958 | ||
1289 | #define SET_XFER_CNT(port, data) (WR_HARP32(port,hp_xfercnt_0,data)) | ||
1290 | 959 | ||
1291 | #define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;} | 960 | #define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;} |
1292 | /* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2), \ | 961 | /* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2), \ |
@@ -1308,11 +977,7 @@ typedef struct SCCBscam_info { | |||
1308 | #define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\ | 977 | #define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\ |
1309 | WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));} | 978 | WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));} |
1310 | 979 | ||
1311 | #define ACCEPT_STAT(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\ | ||
1312 | WR_HARPOON(port+hp_scsisig, S_ILL_PH);} | ||
1313 | 980 | ||
1314 | #define ACCEPT_STAT_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\ | ||
1315 | WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));} | ||
1316 | 981 | ||
1317 | #define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),\ | 982 | #define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),\ |
1318 | WR_HARPOON(port+hp_scsireset, 0x00)) | 983 | WR_HARPOON(port+hp_scsireset, 0x00)) |
@@ -1332,7 +997,6 @@ typedef struct SCCBscam_info { | |||
1332 | 997 | ||
1333 | 998 | ||
1334 | 999 | ||
1335 | void scsiStartAuto(ULONG port); | ||
1336 | static UCHAR FPT_sisyncn(ULONG port, UCHAR p_card, UCHAR syncFlag); | 1000 | static UCHAR FPT_sisyncn(ULONG port, UCHAR p_card, UCHAR syncFlag); |
1337 | static void FPT_ssel(ULONG port, UCHAR p_card); | 1001 | static void FPT_ssel(ULONG port, UCHAR p_card); |
1338 | static void FPT_sres(ULONG port, UCHAR p_card, PSCCBcard pCurrCard); | 1002 | static void FPT_sres(ULONG port, UCHAR p_card, PSCCBcard pCurrCard); |
@@ -1405,7 +1069,6 @@ static void FPT_DiagEEPROM(ULONG p_port); | |||
1405 | 1069 | ||
1406 | 1070 | ||
1407 | 1071 | ||
1408 | void busMstrAbort(ULONG port); | ||
1409 | static void FPT_dataXferProcessor(ULONG port, PSCCBcard pCurrCard); | 1072 | static void FPT_dataXferProcessor(ULONG port, PSCCBcard pCurrCard); |
1410 | static void FPT_busMstrSGDataXferStart(ULONG port, PSCCB pCurrSCCB); | 1073 | static void FPT_busMstrSGDataXferStart(ULONG port, PSCCB pCurrSCCB); |
1411 | static void FPT_busMstrDataXferStart(ULONG port, PSCCB pCurrSCCB); | 1074 | static void FPT_busMstrDataXferStart(ULONG port, PSCCB pCurrSCCB); |
@@ -1446,12 +1109,6 @@ static void FPT_autoLoadDefaultMap(ULONG p_port); | |||
1446 | 1109 | ||
1447 | 1110 | ||
1448 | 1111 | ||
1449 | void OS_start_timer(unsigned long ioport, unsigned long timeout); | ||
1450 | void OS_stop_timer(unsigned long ioport, unsigned long timeout); | ||
1451 | void OS_disable_int(unsigned char intvec); | ||
1452 | void OS_enable_int(unsigned char intvec); | ||
1453 | void OS_delay(unsigned long count); | ||
1454 | int OS_VirtToPhys(u32bits CardHandle, u32bits *physaddr, u32bits *virtaddr); | ||
1455 | 1112 | ||
1456 | static SCCBMGR_TAR_INFO FPT_sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR] = { { { 0 } } }; | 1113 | static SCCBMGR_TAR_INFO FPT_sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR] = { { { 0 } } }; |
1457 | static SCCBCARD FPT_BL_Card[MAX_CARDS] = { { 0 } }; | 1114 | static SCCBCARD FPT_BL_Card[MAX_CARDS] = { { 0 } }; |